Transmitting module and method for transmitting differential signal in serial bus system

Abstract

A transmission module and a method for transmitting a differential signal in a serial bus system are provided. The transmission module has first to fourth transmission stages connected in a full bridge, in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series; and a current limiting circuit for measuring and evaluating the current through the first and second leakage resistors connected to the full bridge, wherein the first to fourth transmission stages for generating a differential bus signal for a bus of a bus system in response to two different values of a digital transmission signal are designed in such a way that a transmission module generates a first or second bus state on the bus in a first operating mode thereof and generates a third or fourth bus state in a second operating mode thereof a state in which the bus signal on the bus forms a voltage difference, the voltage value of which is different for the first to fourth bus states.

Description

Technical Field

[0001] The present invention relates to a transmission module and a method for transmitting a differential signal in a serial bus system. The transmission module and the method are particularly applicable to CAN XL. Background Art

[0002] Serial bus systems are used for the transmission of messages or data in technical installations. For example, serial bus systems can enable communication between sensors and control devices in vehicles or technical production facilities, etc. There are various standards or data transmission protocols for data transmission. In particular, the CAN bus system, the LVDS bus system (LVDS=Low Voltage Differential Signaling), the MSC bus system (MSC=Micro-Second Channel) and the 10BASE-T1S Ethernet are known.

[0003] In the case of a CAN bus system, messages are transmitted by means of the CAN and / or CAN FD protocol, as described in the standard ISO-11898-1:2015 as the CAN protocol specification with CAN FD. In the case of CAN FD, when transmitting on the bus, switching back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase) is performed. In the case of a CAN FD bus system, data transmission rates of more than 1 megabit per second (1 Mbps) are possible in the second communication phase. CAN FD is used in vehicles by most manufacturers, for example, with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s.

[0004] In order to be able to achieve even higher data rates in the second communication phase, there are successor bus systems for CAN FD, such as CAN-SIC and CAN XL. In the case of CAN-SIC in accordance with the standard CiA601-4, a data rate of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. In the case of CAN XL, a data rate of >10 Mbit / s is required in the second communication phase. The requirements for this are specified in the standard CiA610-3 of the organization CAN in Automation (CiA). In addition to pure data transmission via the CAN bus, CAN XL should also support other functions, such as functional safety (Safety), data security (Security) and quality of service (QoS = Quality of Service). These are basic characteristics required in autonomous vehicles.

[0005] In the case of all the above-mentioned CAN-based bus systems, for the transmit signal TxD, the bus signal CAN_H is driven to the bus separately and the bus signal CAN_L is driven to the bus ideally at the same time. In this case, at least in the first communication phase, a bus state is actively driven in the bus signals CAN_H and CAN_L. The other bus state is not driven and occurs due to the terminal resistance of the bus line or bus core of the bus. Due to the different driven states, in a real bus system, the signal shape of the bus signals CAN_H and CAN_L may deviate from the ideal signal shape. The reason for this is especially the bus system design, such as the branch lines for the bus signals CAN_H and CAN_L, the switching delay of the switching stage, etc. This mismatch of the two bus signals CAN_H and CAN_L may cause errors when evaluating the bus signals received from the bus.

[0006] In order to send and receive bus signals, a transmitting / receiving device is usually used for each communication user in a CAN bus system, which is also called a CAN transceiver or a CAN FD transceiver or the like. A CAN transceiver or a CAN FD transceiver must not exceed the limit values ​​for operation in a vehicle with regard to wired radiation or emission. Transceivers for CAN XL must also comply with the more stringent limit values ​​specified in the IEC 62228-3 guideline. As a result, the bus system can only be operated at a higher predetermined bit rate than in the case of CAN FD and CAN SIC. Complying with these strict limit values ​​is a major challenge depending on the available semiconductor technology.

[0007] Even in the case of transceivers for CAN-XL, the states recessive (rec) and dominant (dom) must be generated in the arbitration phase. In order to meet the emission requirements of the standard IEC62228-3, the temporal variation of the common mode voltage of the bus lines for the signals CAN_H, CAN_L in the mentioned transmission states, i.e. recessive, dominant, must be kept within narrow limits, since this temporal variation is the decisive cause of electromagnetic emissions in differential systems. The differential signal components cause no or negligible emissions, since the electromagnetic fields cancel each other out, whereas they add in the case of common mode signal components.

[0008] In order to suppress the common-mode signal changes generated by non-ideal transceivers, common-mode chokes are used at their output ends, which are used to verify compliance with the IEC62228-3 standard, especially during certification measurements. Common-mode chokes are also called common-mode inductors (Common-Mode-Choke, CMC). The task of the common-mode choke is to allow the differential signal (DM=differential mode) to pass as little as possible without any influence, and to suppress the common-mode signal (CM=common mode) as completely as possible. However, in actual operation, the common-mode choke and other slightly asymmetrical components convert part of the differential signal into a common-mode signal (DCMR=Differential-to-Common-Mode Conversion). Therefore, it is also important to make the spectral characteristics of the differential signal generated by the transceiver as optimal as possible. Summary of the invention

[0009] The object of the present invention is therefore to provide a transmission module and a method for transmitting differential signals in a serial bus system, which solve the above-mentioned problems. In particular, the transmission module and the method for transmitting differential signals in a serial bus system should make it possible to compensate for interference variables that influence the transmission behavior of the transmission module in an efficient and yet cost-effective manner.

[0010] This object is achieved by a transmission module for transmitting differential signals in a serial bus system having the features of claim 1. The transmission module has first to fourth transmission stages connected in a full bridge, wherein the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, and has a current limiting circuit for measuring and evaluating the current through a first and a second leakage resistor connected to the full bridge, wherein the first to fourth transmission stages are designed for generating a differential bus signal for a bus of the bus system in response to two different values ​​of a digital transmission signal such that the transmission module generates a first or second bus state on the bus in its first operating mode and a third or fourth bus state in its second operating mode, wherein the bus signal on the bus forms a voltage difference, the voltage value of which is different for the first to fourth bus states, and wherein the current limiting circuit is designed to limit the current through the second leakage resistor based on its evaluation of the current and as a function of the value of the digital transmission signal and the operating mode of the transmission module and a predetermined limit value.

[0011] The described transmission module has a relatively uncomplicated current limiting device which requires little space on the semiconductor chip and is designed in an inexpensive manner. As a result, the described transmission module is very cost-effective to manufacture. However, the described transmission module can very well and safely comply with the limit values ​​required for the transmission module.

[0012] In particular, the described transmission module can be used to implement the limit values ​​required for the transmission of a transmission / receiving device for a CAN XL. The transmission module in particular meets the CiA610-3 guideline, which prescribes a certain maximum transmission current for the transmission module, namely a maximum of 115 mA. In particular, the circuit of the described transmission module ensures that the elements of the full bridge limit the transmission current of the transmission module to a maximum of 115 mA. Furthermore, the transmission module can in particular meet the IEC62228-3 guideline, which specifies limit values ​​to be observed for the bus states dom, sic and rec.

[0013] The design of the transmission module described has a particularly advantageous effect on minimizing interference emissions. The reason for this is that, in the case of a transmission module for representing a corresponding internal resistance of a full bridge, more resistor parts and fewer semiconductor parts (pn junctions, transistors) are provided, compared to the solution in which transistors arranged at the terminals for voltage supply (CAN-Supply) and for grounding (CAN_GND) are used instead of resistors of the transmission module. In the case of the transmission module described, this results in a better matching of the voltage levels at the terminals for the bus. This leads to smaller common mode amplitudes and thus smaller emissions.

[0014] The interference emission of the full bridge circuit of the described transmission module is therefore further minimized compared to other transmission modules having a full bridge circuit. This applies in particular when taking into account process fluctuations and changes in the barrier temperature Tj of the semiconductors of other transmission modules.

[0015] The described transmission module allows a time-staggered and controlled switching process by dividing its four transmission stages into n parts. Switching in accordance with a Gaussian error function can be achieved. This allows a soft behavior to be set during the switching process. In addition, the possible variation of the time stages prevents the occurrence of narrowband frequency lines in the radiation spectrum during switching.

[0016] Alternatively, it is possible to carry out staggered and controlled switching processes with the described transmission module in fixed time steps and varying voltage steps. This also makes it possible to influence the transmission behavior of the transmission module so that predefined limit values ​​are observed.

[0017] Advantageous further embodiments of the transmission module are described in the dependent claims.

[0018] According to one embodiment, the current limiting circuit is designed to control the first to fourth transmitting stages in a first operating mode of the transmitting module to generate a third bus state if an evaluation of the current through the first and / or second leakage resistor shows that the value of at least one of the currents exceeds a predetermined limit value.

[0019] According to one embodiment, the current limiting circuit is designed to control the first to fourth transmitting stages in a first operating mode of the transmitting module to generate a first bus state in a modified manner if an evaluation of the current through the first and / or second leakage resistor shows that the value of at least one of the currents exceeds a predetermined limit value.

[0020] According to one design, the first bus state is a dominant bus state, and the second bus state is a recessive bus state that can be overwritten by the dominant bus state, wherein the current limiting circuit is designed so that each falling edge at the transmit signal activates the current limiting circuit, and wherein the current limiting circuit is designed to switch the transmit module to a transmit state for generating a recessive bus state on the bus at each rising edge at the transmit signal.

[0021] Optionally, the current limiting circuit has a filter with a filter duration, wherein the current limiting circuit is designed to actuate the first to fourth transmitting stages for current limiting in a first operating mode of the transmitting module only after the filter duration has expired.

[0022] The current limiting circuit can have a first and a second comparator, wherein a first leakage resistor is connected between a terminal for bus voltage supply and the full bridge and between inputs of the first comparator, and wherein a second leakage resistor is connected between a terminal for ground and the full bridge and between inputs of the second comparator.

[0023] The current limiting circuit may also have an operating mode control block which is designed to evaluate the output of the comparator.

[0024] According to at least one embodiment, the current limiting circuit further has an adaptation module for adapting the current limiting according to at least one information and / or parameter, wherein the at least one information and / or parameter includes: a holding time, during which the third bus state switched due to the current limiting can be fixed, independently of the output signal of the comparator; current identification, which indicates during the third bus state switched due to the current limiting whether the current has dropped below a value common to the third bus state; and identification of transient interference, for which the current limiting circuit is not activated, independently of the output signal of the comparator.

[0025] The current limiting circuit may be designed to generate a digital signal indicating that the current limiting is active, wherein in the first operating mode of the transmit module the first to fourth transmit stages can be controlled to generate the third bus state, or inactive.

[0026] The output terminals of the full bridge may be provided for connection to a terminating resistor of the bus.

[0027] The sending module can be switched to a first operating mode in a first communication phase of a frame, the frame being generated for a message to at least one other user station of the bus system, wherein the sending module is switched to a second operating mode or a third operating mode in a second communication phase of the frame, and wherein in the first communication phase, a negotiation is carried out between the user stations of the bus system as to which user station has exclusive access to the bus of the bus system in a second communication phase immediately following the first communication phase.

[0028] It is conceivable that the first transmitting stage is designed to generate a transmitting current for a first signal which can be sent to a bus of the bus system, wherein the second transmitting stage is designed to generate a transmitting current for a second signal which can be sent to the bus as a differential signal relative to the first signal, wherein the third transmitting stage is designed to generate a transmitting current for the first signal, and wherein the fourth transmitting stage is designed to generate a transmitting current for the second signal.

[0029] According to one embodiment, each of the first to fourth transmission stages has at least two current stages connected in parallel to each other, wherein each of the at least two current stages has a switchable resistor, and wherein the switchable resistor of the transmission stage has different resistance values, wherein for each of the first to fourth transmission stages, the number n of the at least two current stages is the same, wherein n is a natural number greater than 1. In this case, each of the at least two current stages may have a CMOS transistor for switching the resistance of the current stage, wherein the CMOS transistor of the current stage of the first transmission stage is a PMOS transistor, wherein the CMOS transistor of the current stage of the second transmission stage is an NMOS transistor, wherein the CMOS transistor of the current stage of the third transmission stage is a PMOS transistor, and wherein the CMOS transistor of the current stage of the fourth transmission stage is an NMOS transistor.

[0030] In one design, each of the first to fourth transmitting stages further has a reverse polarity diode for protecting against positive feedback into a terminal for bus voltage supply and negative feedback from a terminal for grounding, and at least one common source and gate for protecting the CMOS transistor, wherein at least two common sources and gates are connected in parallel to each other, wherein for each of the first to fourth transmitting stages, the number of common sources and gates y is the same, wherein y is a natural number greater than 1, and wherein the on-resistance of at least two common sources and gates is different.

[0031] The transmission module may further comprise a control circuit for controlling switchable components of the first to fourth transmission stages as a function of the digital transmission signal and an operating mode provided for the transmission module, wherein the control circuit is designed for time-staggered and controlled switching of resistance values ​​of at least two current stages.

[0032] The previously described transmission module can be part of a transmission / reception device for a subscriber station of a serial bus system, which subscriber station also has a reception module for receiving signals from the bus.

[0033] The transmitting / receiving device can be part of a subscriber station for a serial bus system, which also has a communication control device for controlling the communication in the bus system and for generating digital transmission signals for actuating the first to fourth transmitting stages.

[0034] The aforementioned object is also achieved by a method for transmitting a differential signal in a serial bus system having the features of claim 19. The method is performed with a transmission module having a current limiting circuit and first to fourth transmission stages connected in a full bridge, wherein the method comprises the following steps: measuring and evaluating a current through a first and a second leakage resistor connected to the full bridge with the current limiting circuit, wherein the first and the fourth transmission stages are connected in series and the third and the second transmission stages are connected in series, and in response to two different values ​​of a digital transmission signal, generating a differential bus signal for a bus of the bus system with the first to the fourth transmission stage, so that the transmission module generates a first or a second bus state on the bus in its first operating mode and a third or a fourth bus state in its second operating mode, wherein the bus signal on the bus forms a voltage difference, the voltage value of which is different for the first to the fourth bus state, wherein the current limiting circuit limits the current through the second leakage resistor in the first operating mode of the transmission module based on its evaluation of the current and depending on the value of the digital transmission signal and the operating mode of the transmission module and a predetermined limit value.

[0035] This approach offers the same advantages as mentioned previously with respect to the sending module.

[0036] Other possible implementations of the present invention also include combinations not explicitly mentioned of features or implementations described above or below with respect to the embodiments. Here, those skilled in the art will also add individual aspects as improvements or supplements to the corresponding basic forms of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention will be described in more detail below with reference to the accompanying drawings and according to embodiments.

[0038] Figure 1 shows a simplified block diagram of a bus system according to a first embodiment;

[0039] Figure 2 A circuit diagram is shown for illustrating the structure of a message which can be sent by a subscriber station of a bus system according to a first exemplary embodiment;

[0040] Figure 3 Show Figure 1 An example of the ideal time variation of bus signals CAN_H and CAN_L in a bus system;

[0041] Figure 4 Shown due to Figure 4 The time variation process of the voltage difference VDIFF formed on the bus of the bus system due to the bus signal;

[0042] Figure 5 An example of the time course of a digital transmission signal which should be converted into a signal for arbitration in the arbitration phase (SIC operating mode) is shown. Figure 1 The bus signals CAN_H and CAN_L of the bus of the bus system;

[0043] Figure 6 FIG. 1 shows the time course of the bus signals CAN_H, CAN_L when changing from the recessive bus state to the dominant bus state and back to the recessive bus state, which are based on the arbitration phase (SIC operating mode) Figure 5 The send signal is sent to the bus;

[0044] Figure 7 Indicates that in the data stage it should be converted to Figure 1 An example of a time variation process of a digital transmission signal of bus signals CAN_H and CAN_L of a bus of a bus system;

[0045] Figure 8 Shown based on Figure 7 The time variation process of the bus signals CAN_H and CAN_L sent to the bus in the data phase;

[0046] Fig. 9 A circuit diagram showing a transmission module having a current limiting circuit for a subscriber station of a bus system according to a first embodiment;

[0047] Fig.10 Shown for depicting the use of Fig. 9 A timing diagram of various current levels of a transmitting stage of a first specific example of a transmitting module of FIG.

[0048] Fig.11 Show Fig. 9 details of a transmit stage of a second specific example of a transmit module;

[0049] Fig.12 An example of the time course of a digital transmission signal in the arbitration phase, which should be converted into a Figure 1 The bus signals CAN_H and CAN_L of the bus of the bus system;

[0050] Fig.13 Shown by Fig. 9 The sending module is based on Fig.12 The time variation process of the sending signal being sent to the bus signals CAN_H and CAN_L on the bus;

[0051] Fig.14 Shown based on Fig.12 and Fig.13 The signal is Fig. 9 a time variation of a current flowing to ground in a portion of a current limiting circuit; and

[0052] Fig.15 Show Fig. 9 The current limiting circuit is based on Figure 12 to Figure 14 The time variation process of the current limiting signal generated by the signal; and

[0053] Fig.16 A circuit diagram of a transmitting module having a current-limiting circuit for a subscriber station of a bus system according to a second exemplary embodiment is shown.

[0054] In the figures, identical or functionally identical elements are provided with the same reference symbols unless otherwise indicated. DETAILED DESCRIPTION

[0055] Figure 1 A bus system 1 is shown which may be, for example, at least in sections a CAN bus system, a CAN FD bus system, etc. The bus system 1 may be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

[0056] Although the bus system 1 is described below based on a CAN bus system, the bus system 1 is not limited to the CAN bus system. Alternatively, the bus system 1 may be a 10BASE-T1S bus system or another serial bus system 1 which uses differential signals.

[0057] exist Figure 1In the embodiment, the bus system 1 has a plurality of subscriber stations 10, 20, 30, which are each connected to a bus 40 or bus line having a first bus core 41 and a second bus core 42. For signals on the bus 40, the bus cores 41, 42 may also be referred to as CAN_H and CAN_L. Messages 45, 46, 47 may be transmitted in the form of signals via the bus 40 between the individual subscriber stations 10, 20, 30. The subscriber stations 10, 20, 30 may be, for example, control devices or display devices of a motor vehicle.

[0058] like Figure 1 As shown in FIG. 1 , the user stations 10 and 30 each include a communication control device 11 and a transmitting / receiving device 12 . The transmitting / receiving device 12 includes a transmitting module 121 and a receiving module 122 .

[0059] The user station 20 has a communication control device 21 and a transmitting / receiving device 22 . The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222 .

[0060] The transmitting / receiving devices 12 of the subscriber stations 10, 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if this Figure 1 Not shown.

[0061] The communication control devices 11 , 21 are respectively used to control the communication between the corresponding user station 10 , 20 , 30 and at least one other user station among the user stations 10 , 20 , 30 connected to the bus 40 via the bus 40 .

[0062] The communication control device 11 creates and reads a first message 45, 47, which is, for example, a modified CAN message 45, 47. In this case, the modified CAN message 45, 47 is constructed, for example, based on the CAN SIC format or the CAN XL format. The sending / receiving device 12 is used to send and receive messages 45, 47 from the bus. The sending module 121 receives a digital transmission signal TxD created by the communication control device 11 for one of the messages 45, 47, and converts the digital transmission signal into a signal on the bus 40. The receiving module 121 receives a signal corresponding to the message 45 to 47 sent on the bus 40, and generates a digital reception signal RxD therefrom. The receiving module 122 sends the reception signal RxD to the communication control device 11.

[0063] The communication control device 21 can be implemented as a conventional CAN controller according to ISO 11898-1:2015, i.e. as a CAN FD-tolerant classic CAN controller or a CAN FD controller. The communication control device 21 creates and reads a second message 46, for example a CAN FD message 46. The transmitting / receiving device 22 is used to send and receive the message 46 from the bus 40. The transmitting module 221 receives the digital transmission signal TxD created by the communication control device 21 and converts the digital transmission signal into a signal for the message 46 on the bus 40. The receiving module 221 receives the signals corresponding to the messages 45 to 47 sent on the bus 40 and generates a digital receiving signal RxD therefrom. Otherwise, the transmitting / receiving device 22 can be implemented as a conventional CAN transceiver.

[0064] For sending messages 45 , 47 using CAN XL or CAN SIC, proven properties are ensured which are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifiers and arbitration according to the known CSMA / CR method.

[0065] With the two subscriber stations 10 , 30 , it is possible to form and then transmit messages 45 in different CAN formats, in particular a CAN FD format or a CAN SIC format or a CAN XL format, and to receive such messages 45 , as described in more detail below.

[0066] Figure 2 For message 45, it is shown that a frame 450, in particular a CAN XL frame, is provided by communication control device 11 for transmitting / receiving device 12 for transmission on bus 40. In this case, communication control device 11 creates frame 450 in the present exemplary embodiment to be compatible with CAN FD. Alternatively, frame 450 is compatible with CAN SIC.

[0067] according to Figure 2 , a frame 450 for CAN communication on bus 40 is divided into different communication phases 451, 452, namely arbitration phase 451 (first communication phase) and data phase 452 (second communication phase). Frame 450 has an arbitration field 453, a control field 454, a data field 455, a checksum field 456 and a frame termination field 457 after the start bit SOF.

[0068] In the arbitration phase 451, by means of an identifier (ID) in the arbitration field 453, for example with bits ID28 to ID18, it is negotiated in a bit-wise manner between the subscriber stations 10, 20, 30 which subscriber station 10, 20, 30 wants to send a message 45, 46 with the highest priority and thus obtains exclusive access to the bus 40 of the bus system 1 for the next time for sending in the subsequent data phase 452. In the arbitration phase 451, the physical layer is used as in the case of CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0069] An important point during phase 451 is the use of the known CSMA / CR method, which allows user stations 10, 20, 30 to access bus 40 simultaneously without destroying higher priority messages 45, 46. This makes it relatively easy to add further bus user stations 10, 20, 30 to bus system 1, which is very advantageous.

[0070] The CSMA / CR method requires that a so-called recessive state must be present on the bus 40, which can be overwritten by other subscriber stations 10, 20, 30 with a dominant level or dominant state on the bus 40. In the recessive state, high-ohmic conditions exist at the individual subscriber stations 10, 20, 30, which, combined with the parasitics of the bus circuit, result in long time constants. This results in the maximum bit rate of the current CAN FD physical layer being limited to approximately 2 Mbits per second in real vehicle use.

[0071] In the data phase 452, in addition to part of the control field 454, the useful data of the CAN-XL frame 450 or message 45 from the data field 455 and the checksum field 456 are also sent. The checksum field 456 can contain a checksum for the data of the data phase 452 including the stuffing bits that are inserted as inverted bits by the sender of the message 45 after a predetermined number of identical bits, in particular 10 identical bits. At the end of the data phase 452, the switch is back to the arbitration phase 451.

[0072] At least one acknowledgement bit may be contained in the end field, in particular the acknowledgement field, in the end of frame field 457. Furthermore, there may be a sequence of 11 identical bits that indicates the end of the CAN XL frame 450. The at least one acknowledgement bit may be used to inform the receiver whether an error has been detected in the received CAN XL frame 450 or message 45.

[0073] Only when the sending subscriber station 10 has won the arbitration and thus has exclusive access to the bus 40 of the bus system for sending does the sender of the message 45 begin to send the bits of the data phase 452 onto the bus 40 .

[0074] Therefore, in the arbitration phase 451 as the first communication phase, the user stations 10, 30 partially, in particular up to (including) the FDF bit, use the format known from CAN / CAN-FD according to ISO11898-1:2015. However, compared to CAN or CAN FD, it is possible to increase the net data transmission rate in the data phase 452 as the second communication phase, in particular to more than 10 megabits per second. In addition, it is possible to increase the size of the useful data per frame, in particular to approximately 2 kbytes or any other value. In particular, this value is equal to the value specified for CAN XL in ISO11898-1.

[0075] Figure 3 On the left side, it is shown that the user stations 10, 20, 30 send signals CAN_H, CAN_L to the bus 40 in the arbitration phase 451, which alternately have at least one dominant state 401 or at least one recessive state 402. After the arbitration in the arbitration phase 451, one of the user stations 10, 20, 30 is determined as the winner. It is assumed that the user station 10 wins the arbitration. Then, at the end of the arbitration phase 451, the transmitting / receiving device 12 of the user station 10 switches its physical layer from the first operating mode (SLOW) to the second operating mode (FAST_TX), because the user station 10 is the sender of the message 45 in the data phase 452. Then, the transmitting module 121 generates the state L0 or L1 for the signals CAN_H, CAN_L on the bus 40 in the data phase 452 or in the second operating mode (FAST_TX) in sequence and thus serially according to the transmit signal TxD. The frequency of the signals CAN_H, CAN_L can be increased in the data phase 452, such as in Figure 3 As shown on the right side of the figure. Therefore, the net data transmission rate in the data phase 452 is increased compared to the arbitration phase 451. However, the transmitting / receiving device 12 of the user station 30 switches its physical layer from the first operating mode (SLOW) to the third operating mode (FAST_RX) at the end of the arbitration phase 451, because the user station 30 is only the receiver of the frame 450 in the data phase 452, that is, not the transmitter. After the arbitration phase 451 is completed, all the transmitting / receiving devices 12 of the user stations 10 and 30 switch their operating modes to the first operating mode (SLOW). Therefore, all the transmitting / receiving devices 12 also switch their physical layers.

[0076] according to Figure 4In the arbitration phase 451, ideally, a signal difference VDIFF=CAN_H-CAN_L is formed on the bus 40, with a value of VDIFF=2V for the dominant state 401 and a value of VDIFF=0V for the recessive state 402. Figure 4 In the data phase 452, a signal difference VDIFF=CAN_H-CAN_L with states L0 and L1 is formed on the bus 40, as shown in Figure 4 . State L0 has a value of VDIFF=1V. State L1 has a value of VDIFF=-1V. The receiving module 122 can distinguish between the states 401, 402 and L0, L1 using receiving thresholds in the regions TH_T1, TH_T2, TH_T3, respectively. In this case, the receiving module 122 uses at least a receiving threshold T1 of, for example, 0.7V in the arbitration phase 451. The receiving module 122 uses a receiving threshold T2 of, for example, -0.35V in the arbitration phase 451, but if necessary also in the data phase 452. A receiving threshold T3 of, for example, 0.0V is used in the data phase 452. When in the previous reference Figure 3 When switching between the first to third operating modes (SLOW, FAST_TX, FAST_RX) described above, the receiving module 122 switches the receiving threshold value respectively.

[0077] Figure 5 An example of a portion of a digital transmit signal TxD is shown, which the transmit module 121 receives from the communication control device 11 in the arbitration phase 451 and generates therefrom the signals CAN_H, CAN_L for the bus 40. Figure 5 In the example, the transmission signal TxD changes from the state LW (low=Low) to the state HI (high=High) and returns to the state LW (low=Low) again.

[0078] As in Figure 6 As shown in more detail in FIG. 1 , the sending module 121 may be Figure 5 The transmit signal TxD generates the signals CAN_H, CAN_L for the bus cores 41, 42, so that the state 403 (sic) is additionally present. The state 403 (sic) can have different lengths, as shown by the state 403_0 (sic) when transitioning from the state 402 (rec) to the state 401 (dom) and by the state 403_1 (sic) when transitioning from the state 401 (dom) to the state 402 (rec). The state 403_0 (sic) is shorter in time than the state 403_1 (sic). In order to generate the state 403 (sic) according to Figure 6 signal, the sending module 121 is switched to the SIC operation mode (SIC mode).

[0079] In CiA610-3, the short sic state 403_0 does not need to be traversed and the state depends on the type of implementation. For CAN-SIC and for the SIC operating mode in the case of CAN-XL, the duration of the "long" state 403_1 (sic) is specified as t_sic < 530ns, from Figure 5 The transmission starts at the rising edge of the transmission signal TxD.

[0080] In the "long" state 403_1 (sic), the transmission module 121 should adapt the impedance between the bus cores 41 (CANH) and 42 (CANL) as well as possible to the characteristic wave impedance Zw of the bus line used. In this case, Zw=100 ohms or 120 ohms is suitable. This adaptation prevents reflections and thus allows operation at higher bit rates. For simplicity, state 403 (sic) or sic state 403 is always mentioned below.

[0081] The transmission module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC, and CAN-XL.

[0082]

[0083] Table 1: CAN types for transmitter module 121

[0084] Thus, the transmission status or the transmission module status sic may not only be generated in the case of CAN-SIC or CAN-XL (xl_sic). The transmission status or the transmission module status sic may also be generated in the case of CAN-FD. However, in CAN-FD, the time for the transmission status or the transmission module status sic may be shorter than in the case of CAN-SIC or CAN-XL.

[0085] Figure 7 An example of another part of the digital transmission signal TxD is shown, which the transmission module 121 receives from the communication control device 11 in the data phase 452 and generates therefrom the signals CAN_H, CAN_L for the bus 40. Figure 7 In the example, the transmission signal TxD switches multiple times from the state HI (high = High) to the state LW (low = Low) and switches again to the state HI (high = High) and so on.

[0086] As in Figure 8 As shown in more detail in FIG. 1 , the sending module 121 is for Figure 7The transmit signal TxD generates the signals CAN_H, CAN_L for the bus cores 41, 42, so that the state L0 is formed for the state LW (low=Low). In addition, the state L1 is formed for the state HI (high=High).

[0087] Fig. 9 The basic structure of a transmission module 121 for one of the subscriber stations 10, 30 is shown. The transmission module 121 has a current limiting circuit 1210 and can generate a signal having states 401, 402, 403 according to Figure 6 The signals CAN_H, CAN_L and the states L0, L1 are based on Figure 8 In addition, due to the current limiting circuit 1210, it is possible to generate signals CAN_H and CAN_L according to Fig.13 The signal change process of the signals CAN_H and CAN_L is as follows: Fig.12 , Fig.14 and Fig.15 obtained from the signal.

[0088] The sending module 121 has four sending stages, namely, a first sending stage 121A, a second sending stage 121B, a third sending stage 121C and a fourth sending stage 121D. Fig. 9 As shown in , the transmission stages 121A to 121D are wired as a full bridge.

[0089] The current limiting circuit 1210 of the transmission module 121 has leakage resistors 1211, 1212, comparators 1213, 1214 at which input filters 1213A, 1214A and / or output filters 1213C, 1214C are arranged, and an operating mode control block 1215. The operating mode control block 1215 has a storage module 1215A for storing information and / or parameters 1215P, an evaluation and switching module 1215B, and optionally a filter 1215C.

[0090] The components of the transmission stages 121A to 121D, which are described in more detail below, are controlled via the operating mode control block 1215 and / or the at least one control device 124. In this case, the operating mode control block 1215 and / or the at least one control device 124 send at least one signal to a control terminal 125, to which the components of the transmission stages 121A to 121D are connected. For the sake of clarity, Fig. 9 Not all line connections for this are shown.

[0091] Transmitter module 121 is connected to bus 40 , more precisely to its first bus core 41 for CAN_H or CAN-XL_H and to its second bus core 42 for CAN_L or CAN-XL_L. Each of transmitter stages 121A to 121D is connected to bus 40 .

[0092] A voltage supply is provided via at least one terminal 43 for supplying electrical energy, in particular a voltage CAN-Supply of typically 5 V, to the first and second bus cores 41, 42. A connection to ground or CAN_GND is achieved via a terminal 44. The first and second bus cores 41, 42 are terminated with a terminal resistor 49. The terminal resistor 49 is connected as an external load resistor in a full bridge connection. The resistor 49 is connected in a bridge branch between the terminals for the bus cores 41, 42.

[0093] On the one hand, the leakage resistors 1211 and 1212 are used to protect the transmission module 121 and external devices, especially the user station 10 and / or other devices of the bus 40. The leakage resistors 1211 and 1212 are arranged in the circuit of the transmission stage 121 and are suitable for Figure 6 DOM state 401 and SIC state 403. According to the design and specification, in DOM state 401, twice the current flows in SIC state, but in DOM state 401, the current flows only in one path of the transmitting module 121. In SIC state, the current flows in two paths of the transmitting module 121. The two paths are designed or configured in the same way. Therefore, the same voltage drop occurs at the leakage resistors 1211 and 1212.

[0094] For the current limiting circuit 1210, the leakage resistors 1211, 1212 are used on the other hand for voltage measurement and / or current measurement at the transmission stage 121. The leakage resistors 1211, 1212 can also be called shunt resistors. The resistors 1211, 1212 typically have a resistance value of <1 ohm. According to the following description of the transmission stages 121A, 121B, 121C, 121D, the current limiting circuit 1210 is described in more detail below.

[0095] Fig. 9The first transmission stage 121A has a reverse polarity diode D_A, first to yth transistors HVP_A1 to HVP_Ay (where y is a natural number >1) and a parallel circuit 121A1, in which the first to nth current stages are connected in parallel, where n is a natural number >1. In addition, there is a control circuit T_A. The first current stage has a series circuit consisting of a resistor R_A1 and a transistor P_A1. The nth current stage has a series circuit consisting of a resistor R_An and a transistor P_An. Each of the first to yth transistors HVP_A1 to HVP_Ay is a CMOS transistor, in particular a PMOS transistor. Transistors P_A1 to P_An are CMOS transistors, in particular PMOS transistors. The abbreviation "CMOS" denotes a semiconductor element in which not only p-channel MOSFETs but also n-channel MOSFETs are used on a common substrate. The abbreviation CMOS stands for the English name "Complementary metal-Oxide-Semiconductor", which means "complementary / complementary metal oxide semiconductor" after translation. The abbreviation "MOSFET" stands for metal oxide field effect transistor. The control circuit T_A controls the transistors P_A1 to P_An of the first to nth current stages according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121 . The control circuit T_A can be controlled by the operating mode control block 1215 .

[0096] Fig. 9 The second transmission stage 121B has a reverse polarity diode D_B, first to yth transistors HVN_B1 to HVN_By (where y is a natural number >1) and a parallel circuit 121B1, wherein the first to nth current stages are connected in parallel, where n is a natural number >1. In addition, there is a control circuit T_B. The first current stage S1 has a series circuit consisting of a resistor R_B1 and a transistor N_B1. The nth current stage has a series circuit consisting of a resistor R_Bn and a transistor N_Bn. Each of the first to yth transistors HVN_B1 to HVN_By is a CMOS transistor, in particular an NMOS transistor. Transistors N_B1 to N_Bn are CMOS transistors, in particular NMOS transistors. The control circuit T_B controls the transistors N_B1 to N_Bn of the first to nth current stages according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121. The control circuit T_B can be controlled by the operating mode control block 1215.

[0097] Fig. 9The third transmission stage 121C has a reverse polarity diode D_C, first to yth transistors HVP_C1 to HVP_Cy (where y is a natural number >1) and a parallel circuit 121C1, wherein the first to nth current stages are connected in parallel, where n is a natural number >1. In addition, there is a control circuit T_C. The first current stage has a series circuit consisting of a resistor R_C1 and a transistor P_C1. The nth current stage has a series circuit consisting of a resistor R_An and a transistor P_An. Each of the first to yth transistors HVP_C1 to HVP_Cy is a CMOS transistor, in particular a PMOS transistor. Transistors P_C1 to P_Cn are CMOS transistors, in particular PMOS transistors. The control circuit T_C controls the transistors P_C1 to P_Cn of the first to nth current stages according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121. The control circuit T_C can be controlled by the operating mode control block 1215.

[0098] Fig. 9 The fourth transmission stage 121D has a reverse polarity diode D_D, first to yth transistors HVN_D1 to HVN_Dy (where y is a natural number >1) and a parallel circuit 121D1, wherein the first to nth current stages are connected in parallel, wherein n is a natural number >1. In addition, there is a control circuit T_D. The first current stage has a series circuit consisting of a resistor R_D1 and a transistor N_D1. The nth current stage has a series circuit consisting of a resistor R_Dn and a transistor P_Dn. Each of the first to yth transistors HVN_D1 to HVN_Dy is a CMOS transistor, in particular an NMOS transistor. Transistors N_D1 to N_Dn are CMOS transistors, in particular NMOS transistors. The control circuit T_D controls the transistors N_D1 to N_Dn of the first to nth current stages according to the transmission signal TxD and the set operating modes SIC and FAST_TX of the transmission module 121. The control circuit T_D can be controlled by the operating mode control block 1215.

[0099] Therefore, the current levels S1 to Sn of the transmission stages 121A to 121D are designed as resistance levels. The resistance levels are set by selecting the resistance values ​​of the corresponding current levels, for example by selecting the resistors R_A1 to R_An for the transmission stage 121A, etc. The current levels appear as a result of the setting of the resistance values ​​of the resistors. The number n can be selected arbitrarily. In particular, the number n and thus the number or number of resistance levels or current levels can be selected between 1 and 60. However, alternatively, a number greater than 60 can be selected for n.

[0100] Each of the reverse polarity diodes D_A, D_B, D_C, D_D protects the associated transmission stage from positive feedback to terminal 44 (CAN-Supply) and negative feedback to terminal 43 (CAN_GND). Each of the reverse polarity diodes D_A, D_B, D_C, D_D can also be referred to as a blocking diode.

[0101] Each of the parallel circuits 121A1, 121B1, 121C1, 121D1, more precisely the corresponding control circuits T_A, T_B, T_C, T_D and / or the operating mode control block 1215 sets the resistance value of the corresponding transmission stage 121A, 121B, 121C, 121D according to the operating mode (SLOW or SIC, FAST_TX) of the transmission module 121 and the transmission signal TxD. Therefore, the resistance value of each transmission stage 121A, 121B, 121C, 121D can be set according to the operating mode (SLOW or SIC, FAST_TX) of the transmission module 121 and the transmission signal TxD. Fig.10 and Fig.11 And Table 2 and Table 3 describe this.

[0102] Each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy is an HV cascode and can also be referred to as an HV support device. The transistors HVP_A1 to HVP_Ay protect the assigned CMOS transistors P_A1 to P_An of the assigned parallel circuit 121A1 in such a way that one / a plurality of corresponding transistors HVP_A1 to HVP_Ay absorb high voltage drops. Each of the transistors HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy has the same function as the CMOS transistors of the respectively assigned parallel circuits 121B1, 121C1, 121D1. Each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy is connected at its control terminal to the terminal 125. Therefore, each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy can be controlled by at least one control device 124 and / or an operation mode control block 1215.

[0103] In the case of the transmission module 121, the transmission stage 121A is connected between the terminal 43 for voltage supply and the terminal 41 (CANH) for the signal CAN_H. The transmission stage 121C is connected between the terminal 43 for voltage supply and the terminal 42 (CANL) and the terminal 43 or the terminal 44 (CAN_GND) for grounding. The transmission stage 121D is connected between the terminal 41 (CANH) for the signal CAN_H and the terminal 43 or the terminal 44 (CAN_GND) for grounding. The transmission stage 121B is connected between the terminal 42 (CANL) for the signal CAN_L and the terminal 43 or the terminal 44 (CAN_GND) for grounding. Therefore, in the case of the transmission module 121, on the one hand, the transmission stage 121A is connected to the CANH path. On the other hand, the transmission stage 121D is connected to the CANH path. On the one hand, the transmission stage 121C is connected to the CANL path. On the other hand, the transmission stage 121B is connected to the CANL path.

[0104] Therefore, the sending module 121 in the CANH path and the CANL path is composed of a certain number of parallel circuits 121A1, 121B1, 121C1, and 121D1 of current levels. As previously described, a single current level is realized by a series circuit composed of a CMOS switch and a resistor. The parallel circuits of all current levels are connected in series with HV common source and common gate HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy, and reverse polarity diodes D_A, D_B, D_C, and D_D in the CANH path and the CANL path, as previously described. The HV cascodes HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy enable compliance with limit values ​​(maximum rated parameters), such as -27V to +40V for the voltage at CANH and CANL.

[0105] According to the operation mode of the sending module 121 and the bus states 401 (dom), 403 (sic), 402 (rec) in the SIC operation mode (arbitration phase 451) and L0, L1 in the data phase 452 Fig. 9The basic functioning of the circuit is explained with the help of the following Table 2. Table 2 shows the required impedance as a function of the state of the transmit module 121 and the operating mode of the phases 451, 452, as well as the impedance of the transmit stage 121A / 121B and the impedance of the transmit stage 121C / 121D. The values ​​for the impedance of the transmit stages 121A / 121B and 121C / 121D shown in the following Table 2 lead to an impedance-adapted transmit state, in which the following applies: R_diff_transmit_module=wave impedance Zw on the bus 40. This minimizes reflections in the bus system 1.

[0106]

[0107] Table 2: Impedance required according to the transmit state

[0108] If the impedance is “infinite”, the transmission module 121 or the corresponding transmission stage 121A, 121B, 121C, 121D is switched off or made non-conductive.

[0109] However, alternatively, for bus states L0, L1, different impedances than those in Table 2 are possible for the transmission stages 121A / 121B and 121C / 121D. For example, for the transmission stage 121A / 121B, an impedance of 65||0 can be generated for the bus states L0, L1 instead of an impedance of 55||600 for the bus states L0, L1. As a result, the correct voltage for L0, L1 will also appear on the bus 40, but a resistance difference of R_diff=2*65=130 ohms will appear. As a result, the reflection coefficient will be Gamma=(R_diff-Zw) / (Rdiff+Zw)=30 / 230=0.13, which can be acceptable depending on the implementation. The same applies to the transmission stage 121C / 121D, where an impedance of 0||65 can be generated for the bus states L0, L1 instead of an impedance of 600||55 for the bus states L0, L1.

[0110] Will Fig. 9 The division of each parallel circuit 121A1, 121B1, 121C1, 121D1 into n parts or n current levels allows a time-staggered and controlled switching process between bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or bus states L0, L1 in the data phase 452. For this purpose, the resistance values ​​of the resistors of the n current levels are set, for example, using Fig.10 illustrated in specific examples.

[0111] Fig.10An example of current levels for each switching stage or current stage S1 to S12 is shown. Thus, in the example shown, twelve current stages S1, S2 to S6 to S12 are used for each of the parallel circuits 121A1, 121B1, 121C1, 121D1. Thus n=12 applies.

[0112] Current I( Fig.10 The values ​​of I1, I2, I6, I12, etc. are set by selecting the series resistance values ​​of the corresponding current levels S1 to S12. Fig.10 The horizontal axis in the figure has different resistance values.

[0113] In order to generate bus states 401, 402, 403 in arbitration phase (SIC operating mode) 451 or bus states L0, L1 in data phase 452, the respective current stages S1 to S12 are switched on or off in a time-staggered manner by means of the CMOS transistors of the current stages S1 to S12. As a result, the corresponding current I flows in the CANH path or CANL path to which the upper-stage transmission stages 121A, 121B, 121C, 121D are connected.

[0114] Generally speaking, it is advantageous to design the staggering (interleaved stages) and the resistors for each switching stage or current stage S1 to S12 so that the shape of the signal difference VDIFF follows a Gaussian error function, thereby analytically producing the lowest emissions.

[0115] To transition from state 402 (implicit) to state 401 (explicit), this corresponds to Figure 4 At the rising edge of the voltage difference VDIFF, the current in the CANH and CANL paths is gradually increased by connecting the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1 at a time staggered manner to generate a dominant level at the bus 40. Accordingly, the transition from state 401 (dominant) to state 402 (recessive) is made by disconnecting the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1 at a time staggered manner, which corresponds to Figure 4 The falling edge of the voltage difference VDIFF of the parallel circuit 121A1, 121B1, 121C1, 121D1 is connected, and the total current for generating the dominant level of the nominal VDIFF=2V flows through the bus resistor or the terminal resistor 49.

[0116] As described above, by setting the current levels of the individual current levels S1 to S12 in time and by setting the resistance values ​​of the resistors of the individual current levels S1 to S12, it is possible to balance the bus signals CAN_H, CAN_L with each other when transitioning between the states 401, 402, so that the current level according to Figure 6 The structure of the transmitting module 121 enables the current levels of the parallel circuits 121A1, 121B1, 121C1, 121D1 to be switched on at different times. This time control makes it possible to equalize the signal shapes of CAN_H and CAN_L, such as according to Figure 6 As required. It is possible to shape the signal course for CAN_H and CAN_L in a targeted manner. In general, the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452 can be shaped according to the preset.

[0117] The resistances of the individual current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 and thus their respective contributions to the total current can be selected in different ways in order to achieve the lowest possible emission, in particular low emission of the transmitting module 121. For low emission, it is advantageous to switch on or off a small current I (high resistance value) at the beginning and end of the switching process between the bus states 401, 402 and to switch on or off a large current (low resistance value) indirectly during the switching process. Fig.10 The setting of the currents of the current stages S1 to S12 shown in FIG. 1 is very advantageous.

[0118] Compared with the implementation method in which the current levels S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, and 121D1 have the same resistance, Fig.10 The configuration avoids current increase during the turn-off, transition from state 401 (dominant) to state 402 (recessive).

[0119] The granularity of the time staggering (interleaving) for switching the individual current stages S1 to S12 on or off is in the range of about 2 ns. Such small steps or steps for the time staggering cause small common-mode interferences and have a small negative effect on the emission. In this case, the voltage steps set by the resistors or resistor stages of the current stages S1, S2 to S6 to S12 are kept fixed and the time staggering is varied so that a behavior that is as soft as possible (according to the Gaussian error function) occurs during the switching process. The variation of the time step or the time stage also prevents the appearance of narrow-band frequency lines in the radiation spectrum.

[0120] Alternatively, staggered steps may be performed at fixed time steps and varying voltage steps.

[0121] The illustrated structure of the transmission module 121 enables symmetrical switching of the bus signals CAN_H and CAN_L at steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452. Figure 6 ).

[0122] On the one hand, the illustrated structure of the transmission module 121 using fast CMOS switches or CMOS transistors enables much steeper switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 in the data phase 452. On the other hand, the symmetry of the time profile of the bus signals CAN_H and CAN_L required for compliance with the transmission limit values ​​is achieved during the switching process. The matching of the characteristic curve is achieved by selecting or using the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1. The matching of the characteristic curve is thus less dependent on the parameters of the transistors used in the parallel circuits 121A1, 121B1, 121C1, 121D1.

[0123] The CMOS transistors of the transmission stages 121A1, 121B1, 121C1, 121D1 are operated as switches, i.e., they have a maximum voltage between the gate terminal and the source terminal. Thus, the matching of the individual transmission stages 121A1, 121B1, 121C1, 121D1 is decisively dependent on the matching of the resistors R_A1 to R_An, R_B1 to R_Bn, R_C1 to R_Cn, R_D1 to R_Dn, and no longer on the transistors R_A1 to R_An, R_B1 to R_Bn, R_C1 to R_Cn, R_D1 to R_Dn (PMOS) at the bus core 41 (CANH) and the transistors N_D1 to N_Dn and N_B1 to N_Bn (NMOS) at the bus core 42 (CANL).

[0124] The dominant state 401 (dom) is determined by matching the resistors R_A1 to R_An (transmitting stage 121A) with the resistors R_B1 to R_Bn (transmitting stage 121B). In this case and also below, the term "matching" means an active fine-tuning step according to one possibility. According to another possibility, the term "matching" means that the resistor values ​​are matched to each other as well as possible, which is performed as standard without a matching step or a fine-tuning step.

[0125] The Sic state (sic) is determined by matching (Matching) the resistors R_A1 to R_An (transmission stage 121A) with the resistors R_C1 to R_Cn (transmission stage 121C) and matching (Matching) the resistors R_D1 to R_Dn (transmission stage 121D) with the resistors R_B1 to R_Bn (transmission stage 121B).

[0126] In the operating mode XL-Fast, the state L0 is determined by matching the resistors R_A1 to R_An (transmitting stage 121A) with the resistors R_B1 to R_Bn (transmitting stage 121B). The state L1 is determined by matching the resistors R_C1 to R_Cn (transmitting stage 121C) with the resistors R_D1 to R_Dn (transmitting stage 121D).

[0127] The on-resistance Ron of the corresponding transistors of the transmission stages 121A1 , 121B1 , 121C1 , 121D1 should be significantly smaller than the respective series-connected resistances of the individual current stages of the transmission stages 121A1 , 121B1 , 121C1 , 121D1 .

[0128] Fig.11 Show Fig. 9 Specific example of the structure of the transmitting stage 121B of the embodiment. Therefore, the transmitting stage 121B in the parallel circuit 121B1 has three current stages S_I, S_II, and S_III. The first current stage S_I has a resistor R_B1_I and a transistor N_B1_I connected in series. The second current stage S_II has a resistor R_B1_II and a transistor N_B1_II connected in series. The third current stage S_III has a resistor R_B1_III and a transistor N_B1_III connected in series.

[0129] For those with basis Fig.11 Configuration Fig. 9 The following description of the circuit of the transmission stage 121A, 121C, 121D should assume that each of the transmission stages 121A1, 121C1, 121D1 also has a corresponding Fig.11 The three current levels S_I, S_II, S_III of the example.

[0130] Table 3 below shows Fig.11 The three transistors N_B1_I, N_B1_II, N_B1_III and Fig. 9 The corresponding transistors of the transmitting stages 121A, 121C, and 121D are controlled according to the transmitting stages 121A / 121B and the transmitting stages 121C and 121D, respectively.

[0131]

[0132] Table 3: Required impedance according to the transmission state

[0133] In this way, the required steeper edges can be generated at the bus signals CAN_H and CAN_L using transmit module 121 and transmit limit values ​​can be adhered to.

[0134] Alternatively, as previously described, more than three current stages may be used in the respective transmission stages 121A, 121B, 121C, 121D.

[0135] The described transmission module 121 can reduce the effects caused by the asymmetric behavior of the transmission stages 121A, 121B, 121C, 121D, which may appear in the transmission states dom, sic, rec or 401, 403, 402 and degrade the transmission. The transmission module 121 prevents the unequal behavior of the components in the transmission stages 121A, 121B of the full bridge (effect 1), so that in the dominant state 401, the change of the common mode voltage is minimized or prevented compared to the rec state 402. In addition, the transmission module 121 can prevent the unequal behavior of the components in the transmission stages 121A / D and 121C / B of the full bridge (effect 2), so that in the sic state 403, the change of the common mode voltage is minimized or prevented compared to the rec state 402. This is particularly advantageous since adequate transmission results can only be achieved if, starting from the common mode levels of the rec state 402, the common mode levels in the dom state 401 and the sic state 403 match those of the rec state 402, however, the causes leading to the behavior of effect 1 may be different from those leading to effect 2.

[0136] The transmission module 121 is further able to reduce the effects caused by the asymmetric behavior of the transmission stage, which may appear in the transmission states dom (401), sic (403), rec (402), L0, L1 and increase overshoot and thus degrade the transmission. The transmission module 121 prevents Fig.12 The unequal behavior of the components in the transmitting stages 121A0 , 121B0 of the full bridge (effect 1 ) causes a change in the common mode voltage to be minimized or prevented in the dom state 401 compared to the rec state 402 .

[0137] In order to prevent effect 1, the resistance Ron (on-resistance) of the common source and common gate in the transmission stage 121A, 121B can be changed, in particular by controlling it with the control circuit T_A, T_B respectively belonging to it. This is done by changing up to y transistors HVP_A1 to HVP_Ay connected in parallel and / or up to y transistors HVN_B1 to HVN_By connected in parallel. In order not to change the symmetry of the two series circuits of the transmission stage 121A0, 121D0 and the transmission stage 121C0, 121B0 in the sic state 403, the common source and common gate of the transmission stage 121D0, 121C0 must also undergo the same change. Therefore, up to y transistors HVN_D1 to HVP_Dy connected in parallel and / or up to y transistors HVP_C1 to HVP_Cy connected in parallel are also changed accordingly. To this end, each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVP_Dy is connected at its control terminal (gate terminal) to the terminal 125. Each of these transistors can therefore be controlled by at least one control device 124. Interventions for correcting the common mode level in the dom state 401 are carried out by similar or identical changes of HVP_A1 to HVP_Ay and HVP_C1 to HVP_Cy or by similar or identical changes of HVP_D1 to HVN_Dy and HVP_B1 to HVN_By.

[0138] In addition, by designing the transmission module 121, it is possible to prevent, in particular, substrate current losses in the reverse polarity diodes D_A and D_B from causing the common mode levels in the dom state 401 to no longer match. In the sic state, the reverse polarity diodes D_A and D_B are not too strongly energized, and in addition all the reverse polarity diodes D_A, D_B, D_C, D_D of the four transmission stages 121A, 121B, 121C, 121D are activated. The transmission module 121 can prevent different common mode levels in the dom state and the sic state. In addition, it is possible to prevent qualitatively identical effects from being produced by unequal behavior in the common source and common gate.

[0139] Therefore, the transmission module 121 can positively influence the effect on the transmission value of the transmitting / receiving device 12 , which is decisively influenced by the transmission module 121 .

[0140] In order to comply with the limit values ​​for interference emissions specified in the CiA610-3 specification / guideline, Fig. 9 The current limiting circuit 1210 uses Fig. 9 The sending module 121 has the following characteristics.

[0141] In order to achieve a voltage difference VDIFF=CAN_H-CAN_L of approximately 1V for bus state L0 in data phase 452, which can also be referred to as VDIFF_L0=approximately 1V, transmission stages 121A, 121B are operated with an impedance of approximately or approximately 65 ohms, respectively. In this case, transmission stages 121C, 121D are blocked or at least significantly higher than transmission stages 121A, 121B. In connection with an external bus load resistor 49 having a resistance value RL=50 ohms, a current of approximately 20 mA flows in bus state L0, and the voltage difference VDIFF_L0 is approximately or approximately 1V.

[0142] The current limiting circuit 1210 uses this property not only for the data phase 452, but also for the arbitration phase 451 in order to limit the current of the transmitting module 121 in the dominant bus state 401. This is necessary because for the dom state 401 of the transmitting module 121 with the bus load resistor 49 having a resistance value RL=50 ohms, the following applies to the current of the transmitting module 121:

[0143] A) Voltage difference VDIFF_dom=CAN_H_dom-CAN_L_dom=2V,

[0144] B) Dominant state transmission current: I_dom = VDIFF_dom / RL = 2V / 50 ohms = 40mA,

[0145] C) the resistance of the transmission stage 121B in the dominant state: R_PartB_dom=(U_CANL_dom-U_CANL_dio) / I_dom=(1.5V-0.7V) / 40mA=20 ohms, which is the sum of the equivalent resistance of the circuit composed of switches N_B1 to N_B1n and the resistances R_B1 to R_B1n,

[0146] D) Current in the dominant state 401 during short circuit: I_dom_KS=U_Source_HVN_B_max / R_PartB_dom=4V / 20 ohm=200mA=>exceeds the specified limit value GW of a maximum of 115mA ( Fig.14 ).

[0147] In order to avoid or eliminate the maximum limit value GW of 115mA ( Fig.14 ) exceeds, the current limiting circuit 1210 operates as follows.

[0148] Fig. 9The comparator 1213 in the embodiment detects the voltage drop or voltage U_S1 or current I_S1 across the resistor 1211. The comparator 1214 detects the voltage drop or voltage U_GND or current I_GND across the resistor 1212. If the voltage U_S1 at the resistor 1211 exceeds the predetermined limit value GW( Fig.14 ), the comparator 1213 signals this to the operating mode control block 1215. If the voltage U_GND at the resistor 1212 exceeds a predetermined limit value, the comparator 1214 signals this to the operating mode control block 1215. The predetermined limit value GW( Fig.14 ) is specified in particular as not exceeding a current limit of 115 mA, which corresponds to the maximum value from the specification / guideline CiA610-3.

[0149] In the operation mode control block 1215, information and / or parameters 1215P about the transmission module 121 exist in the memory module 1215A. The information and / or parameters 1215P include the level of the transmission signal TxD, the operation mode of the transmission module 121, the state of the transmission module 121, etc. The state of the transmission module 121 can also be referred to as a transmitter state.

[0150] Fig. 9 The operating mode control block 1215 is designed to evaluate the signals at the outputs of the comparators 1213, 1214 with respect to the overcurrent and to set the state of the transmission module 121 accordingly. In addition, the operating mode control block 1215 is designed to evaluate the transmission signal TxD ( Figure 5 , Figure 7 , Fig.12 ), that is, which state HI, LW the transmit signal TxD has. The operating mode control block 1215 is designed to combine the two evaluations mentioned as follows.

[0151] If the evaluation of the operating mode control block 1215 shows that a dominant state 401 is currently present in the transmit signal TxD, wherein the condition TxD=LW( Figure 5 , Figure 7 , Fig.12 ) and comparators 1213, 1214 signal a persistent overcurrent at their outputs, the operating mode control block 1215 sets state L0 for the transmitting module 121, which Figure 8 In this case, as mentioned above, the typical voltage VDIFF_L0_typ of the voltage difference Vdiff for the L0 state is generally VDIFF_L0_typ=CAN_H-CAN_L=1V.

[0152] use Fig. 9 The current limiting circuit 1210 obtains the following current limiting value I_L0_KS:

[0153] A) L0 sending current I_L0 = VDIFF_L0 / RL = 1V / 50 ohms = 20mA

[0154] B) Resistance of the transmitting stage 121B in the L0 state: R_PartB_L0=(U_CANL_L0-U_CANL_dio) / I_L0=(2V-0.7V) / 50 ohms=65 ohms

[0155] D) Current in the L0 state during short circuit: I_Level0_KS=U_Source_HVN_B_max / R_PartB_L0=4V / 65 ohms=61 mA.

[0156] therefore, Fig. 9 The current limiting circuit 1210 causes the specified limit value GW (115 mA) to not exceed the maximum value. Fig.14 ).therefore, Fig. 9 The current limiting circuit 1210 can achieve compliance with limit values ​​for interference emission according to applicable guidelines.

[0157] Figures 12 to 15 A specific example signal is shown for a more detailed explanation. Fig. 9 The current limiting circuit 1210 is used to comply with the function of the limit value of the interference emission.

[0158] This example is based on the fact that, for example, in the case of a transmission stage 121B, in the case of a short circuit, for example, U_CANL_KS=18V (CiA610-3, -3V ... +18V), a voltage of approximately 4V is present at the source of the switches HVN_B1 to HVN_Bn. This results in the case where the cascode HVN_B is driven with a switch threshold voltage, in particular a MOS threshold voltage, of approximately 1V minus 5V. Therefore, in the case of a short circuit greater than or equal to 5V, a voltage of approximately 4V is always present at the source of the switch HVN_B.

[0159] exist Figures 12 to 15 In the case of the example, assuming Fig. 9 The current limiting circuit 1210 has either filters 1213A and 1214A with a filter duration T_F1 or filters 1213C and 1214C with a filter duration T_F1 or a filter 1215C with a filter duration T_F1. Fig. 9 The current limiting circuit 1210 uses the filtering duration T_F0 generated by at least one of the previously mentioned filters.

[0160] In principle, Fig. 9 The current limiting circuit 1210, especially the operation mode control block 1215 thereof, is designed so that Fig.12Each falling edge of the transmit signal TxD activates Fig. 9 The current limiting circuit 1210 is designed so that Fig.12 Each rising edge of the transmit signal TxD causes the operating mode of the transmit module 121 to be changed to generate the bus state recessive 402. Fig.12 In the case of the example, Fig. 9 The current limiting circuit 1210 can be activated in particular at the time t_A. The activation can be performed by the operating mode control block 1215.

[0161] According to Figures 12 to 15 Signal, observe the example: In the arbitration stage 451, first use Fig. 9 The sending module 121 communicates as previously described and as in Figures 12 to 15 Therefore, according to Fig.12 The state HI, LW of the transmit signal TxD generates a dominant state 401 or a recessive state 402 with a voltage U on the bus 40, as described previously and as in Fig.13 Based on this, according to Fig.14 , a ground current I_GND between 0 mA and 40 mA appears, and the ground current flows into the terminal 44 via the resistor 1212. In addition, the current limiting circuit 1210 generates a digital current limiting signal I_L having a value LW (low = Low), as shown in Fig.15 as shown on the left.

[0162] However, in Figures 12 to 15 At the time t_K in , a short circuit occurs after a positive voltage of, for example, U_KS=18 V. In particular, U_CAN_L=18 V applies.

[0163] Therefore, the ground current I_GND jumps to a value of 200mA, such as Fig.14 As shown in . Since the value of the ground current I_GND therefore exceeds the limit value GW of 115 mA set in the comparators 1213, 1214, the filtering duration T_F1 starts to run. After the filtering duration T_F1 expires, the current limiting circuit 1210 changes its digital current limiting signal I_L from the previous value LW (low=low) to the value HI (high=high), as shown in Fig.15 as shown on the right.

[0164] therefore, Fig.14 The ground current I_GND in is limited to below the predetermined limit value GW. Fig.14 In the example of , the limit value has a value of 115 mA. This complies with the specifications of the CiA 610-3 standard.

[0165] exist Figures 12 to 15At the time point t_KS in the figure, the short circuit on the bus 40 is terminated or eliminated. At this time point, the digital current limiting signal I_L is still at the value HI (high = high), as shown in Fig.15 Therefore, the operating mode control block 1215 controls the transmission stages 121A, 121B, 121C, 121D as described above, so that the voltages for CAN_H and CAN_L are generated to set or generate the bus state L0 on the bus 40.

[0166] Therefore, the ground current I_GND is pulled to the value for bus state L0. Fig.14 In the example of , this ground current I_GND(L0) has a value of approximately 20 mA. This also complies with the specifications of the CiA610-3 standard.

[0167] In addition, the filter duration T_F0 is Figures 12 to 15 After the filter duration T_F0 expires, the current limiting circuit 1210 changes its digital current limiting signal I_L from the previous value HI (high = high) to the value LW (low = Low), as shown in Fig.15 Therefore, the operating mode control block 1215 controls the transmission stages 121A, 121B, 121C, 121D as described above, so that the voltages for CAN_H and CAN_L are generated in order to set or generate the dominant bus state 401 on the bus 40.

[0168] Therefore, the ground current I_GND is pulled from the value for bus state L0 to the value for bus state 401. Fig.14 In the example case, the ground current I_GND has a value of approximately 40 mA.

[0169] The specifications of the CiA610-3 standard / guideline are thereby complied with.

[0170] The filtering duration T_F1, T_F0 produced by at least one of the previously mentioned filters 1213A, 1214A or 1213C, 1214C or 1215C provides a certain inertia for the circuit 1210. Thus, the current limiting circuit 1210 has a high robustness against interfering voltages / currents, such as the previously considered short circuit.

[0171] The following boundary conditions apply to the determination of the size of the filter durations T_F1, T_F0 for activating or changing the value of the signal I_GND:

[0172] a) From a coupled input frequency of 1 MHz, common-mode interference occurs with a decisive amplitude; this amplitude can trigger current overshoot or limitation. From this criterion, it follows that t_filt_DPI>=1μs,

[0173] b) Pulse-like interference according to the international standard ISO 7637 occurs in less than 1 μs, which means that t_filt_pulse>=1 μs.

[0174] The design of the filter duration T_F1=1 μs therefore results in the current limiting not being effective for at least approximately 1 μs after the short-circuit condition has been applied. This should not cause problems, since only a maximum static current limit of 115 mA is specified in the specification. If the static current limit is exceeded during the duration T_F1, there are no problems or damage to the common mode choke (CMC) or to the integrated circuit (transceiver IC) of the transmitting and receiving device 12, neither thermally nor electrically.

[0175] In this way, current limiting circuit 1210 limits the current of transmission module 121 according to the upper limit of specification / guideline CiA610-3. This also applies to arbitration phase 451 even though state L0 is provided only for communication in the data phase according to the CAN-XL specification.

[0176] Therefore, even in the slow phase of communication, that is, the arbitration phase 451, the operation mode control block 1215 uses the Figure 8 or Fig.13 bus state L0 in order to limit the short-circuit current through resistor 1212.

[0177] Fig.16 A transmission module 121_0 with a current limiting circuit 1210_0 according to the second embodiment is shown. The transmission module 121_0 is constructed in many parts in the same way as the transmission module 121 according to the first embodiment. Therefore, only the differences from the first embodiment are described below.

[0178] Different from the first embodiment, the current limiting circuit 1210_0 according to this embodiment has an adaptation module 1215D. The adaptation module 1215D uses the holding time to adapt the current limiting time. The holding time is stored in the storage module 1215A as information and / or parameter 1215P.

[0179] If the current limiting circuit 1210_0 has triggered the current limiting once, regardless of the output signals of the comparators 1213 , 1214 , the state L0 is controlled or activated for the transmitting module 121_0 and fixed within the holding time by the adaptation module 1215D.

[0180] In this way, the interference emission of the sending module 121_0 can be further reduced.

[0181] According to a third exemplary embodiment, the adaptation module 1215D is designed to perform an additional current detection, in particular with a circuit, which checks during the transmission state L0 of the transmission module 121_0 whether the current I_GND has dropped below a predetermined limit value. If the current I_GND has dropped below the predetermined limit value, the adaptation module 1215D can cause the operating mode control block 1215 to switch the transmission module 121_0 back to the dominant state 401 again as long as the state 401 is still requested via the transmission signal TxD=LW. In this case, it is also avoided that the upper limit of the current limit is exceeded.

[0182] In this way, the interference emission of the sending module 121_0 can be further reduced.

[0183] According to a fourth embodiment, the adaptation module 1215D is designed to identify transient disturbances. If such disturbances are identified, the aforementioned current limiting is not activated by the current limiting circuit 1210_0 even if the comparators 1213, 1214 will signal activation. Instead, the adaptation module 1215D activates the current limiting only when there is an overcurrent and no transient disturbance is detected.

[0184] In this way, the interference emission of the sending module 121_0 can be further reduced.

[0185] According to the fifth embodiment, the adaptation module 1215D is designed to prevent the operating mode control block 1215 from switching the transmission module 121_0 to the state L0 when the transmission signal TxD=LW is present and an overcurrent is detected. Instead, the currently existing dominant state 401 of the transmission module 121_0 is modified by increasing the impedance of the transmission stages 121A and 121B. This is done by gradually or suddenly switching off the transistors of the parallel circuits P_A1 to _An and N_A1 to _An of the transmission stage 121A.

[0186] In this way, the interference emission of the sending module 121_0 can be further reduced.

[0187] All previously described embodiments of the bus system 1 and the method performed therein, the transmission module 121, 121_0, the current limiting circuit 1210, 1210_0, the transmission / reception device 12, 22, the user station 10, 20, 30 according to the first and second exemplary embodiments and their modifications or options can be used individually or in all possible combinations. In addition, in particular, the following modifications are conceivable.

[0188] In all described embodiments and their modifications or options, the transmission module 121, 121_0 does not have to have a transmission stage 121A, 121B, 121C, 121D forming a full bridge with connected resistors. Instead, the transmission module 121, 121_0 of any embodiment can have a transmission stage forming a full bridge with connected currents, in particular current sources and / or current sinks.

[0189] The previously described bus system 1 according to the first and second exemplary embodiments is described according to a bus system based on the CAN protocol. However, the bus system 1 according to the first and / or second exemplary embodiment can alternatively be another type of communication network in which signals are transmitted as differential signals. An advantageous, but not necessary prerequisite is that in the case of the bus system 1, exclusive, conflict-free access to the bus 40 for the user stations 10, 20, 30 is guaranteed at least for a certain period of time.

[0190] The bus system 1 according to the first and / or second embodiment and its modifications is in particular a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 may be another communication network in which signals are transmitted serially as differential signals through the bus.

[0191] Thus, the functionality of the previously described exemplary embodiments can be used, for example, in the case of transceiver devices 12 , 22 which can be operated in a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CANSIC bus system or a CAN XL bus system.

[0192] It is possible that for both bus states 401 , 402 , at least temporarily, instead of using dominant and recessive bus states, a first bus state and a second bus state are used, both of which are driven. An example of such a bus system is the CANXL bus system.

[0193] The number and arrangement of subscriber stations 10, 20, 30 in the bus system 1 according to the embodiment and its modifications are arbitrary. In particular, only subscriber station 10 or only subscriber station 30 may be present in the bus system 1 of the first or second embodiment.

Claims

1. A sending module (121; 121_0) for sending a differential signal in a serial bus system (1), comprising: first to fourth transmission stages (121A, 121B, 121C, 121D), the transmission stages being connected in a full bridge, wherein the first and fourth transmission stages (121A, 121D) are connected in series, and the third and second transmission stages (121C, 121B) are connected in series, and a current limiting circuit (1210; 1210_0) for measuring and evaluating the current (I_S1, I_GND) through the first and second leakage resistors (1211, 1212) connected to the full bridge, The first to fourth transmission stages (121A, 121B, 121C, 121D) are designed to generate a differential bus signal (CAN_L, CAN_H) for a bus (40) of a bus system (1) in response to two different values ​​of a digital transmission signal (TxD) so that the transmission module (121; 121_0) generates a first or second bus state (401, 402) on the bus (40) in its first operating mode (SLOW; SIC) and generates a third or fourth bus state (L0, L1) in its second operating mode (FAST_TX), wherein bus signals (CAN_L, CAN_H) on the bus (40) form a voltage difference (VDIFF), the voltage value of the voltage difference being different for the first to fourth bus states (401, 402, L0, L1), and The current limiting circuit (1210; 1210_0) is designed to limit the current (I_GND) through the second leakage resistor (1211, 1212) based on its evaluation of the current (I_S1, I_GND) and depending on the value of the digital transmission signal (TxD) and the operating mode of the transmission module (121; 121_0) and a predetermined limit value (GW).

2. A transmitting module (121; 121_0) according to claim 1, wherein the current limiting circuit (1210; 1210_0) is designed to control the first to fourth transmitting stages (121A, 121B, 121C, 121D) in a first operating mode (SLOW; SIC) of the transmitting module (121; 121_0) to generate a third state (L0) if an evaluation of the current (I_S1, I_GND) through the first and / or second leakage resistor (1211, 1212) shows that the value of at least one of the currents (I_S1, I_GND) exceeds a predetermined limit value (GW).

3. A transmitting module (121; 121_0) according to claim 1, wherein the current limiting circuit (1210; 1210_0) is designed to control the first to fourth transmitting stages (121A, 121B, 121C, 121D) in a first operating mode (SLOW; SIC) of the transmitting module (121; 121_0) to generate a first bus state (401) in a modified manner if an evaluation of the current (I_S1, I_GND) through the first and / or second leakage resistor (1211, 1212) shows that the value of at least one of the currents (I_S1, I_GND) exceeds a predetermined limit value (GW).

4. The sending module (121; 121_0) according to claim 1 or 2, Wherein the first bus state is a dominant bus state (401), The second bus state is a recessive bus state (402) that can be overwritten by the dominant bus state (401), wherein the current limiting circuit (1210; 1210_0) is designed so that each falling edge at the transmit signal (TxD) activates the current limiting circuit (1210; 1210_0), and The current limiting circuit (1210; 1210_0) is designed to switch the transmitting module (121; 121_0) to a transmitting state for generating a recessive bus state (402) on the bus (40) at each rising edge of the transmitting signal (TxD).

5. The sending module (121; 121_0) according to any one of the preceding claims, wherein the current limiting circuit (1210; 1210_0) has a filter (1213A; 1213C; 1214A; 1214C; 1215C) having a filtering duration (T_F1), and The current limiting circuit (1210; 1210_0) is designed to control the first to fourth transmission stages (121A, 121B, 121C, 121D) for current limiting only after the filter duration (T_F1) has expired in a first operating mode (SLOW; SIC) of the transmission module (121; 121_0).

6. The sending module (121; 121_0) according to any one of the preceding claims, The current limiting circuit (1210; 1210_0) has a first and a second comparator (1213, 1214), wherein a first leakage resistor (1211) is connected between a terminal (43) for bus voltage supply and the full bridge and between input terminals of a first comparator (1213), and The second leakage resistor (1212) is connected between the terminal (44) for grounding and the full bridge and between the input terminals of the second comparator (1214).

7. The transmission module (121; 121_0) according to claim 6, wherein the current limiting circuit (1210; 1210_0) has an operating mode control block (1215) which is designed to evaluate the output of the comparator (1213, 1214).

8. The transmitting module (121; 121_0) according to any one of claims 6 or 7, wherein the current limiting circuit (1210; 1210_0) further comprises an adaptation module (1215D) for adapting the current limiting according to at least one information and / or parameter (1215P), wherein the at least one information and / or parameter (1215P) comprises A holding time, during which the third bus state (L0) switched due to current limiting can be fixed, regardless of the output signal of the comparator (1213, 1214), a current detection which indicates during the third bus state (L0) switched due to current limiting whether the current has dropped below a value which is typical for the third bus state (L0), The transient disturbance is detected, regardless of the output signal of the comparator (1213, 1214), and the current limiting circuit (1210; 1210_0) is not activated for the detection of the transient disturbance.

9. A sending module (121; 121_0) according to any of the preceding claims, wherein the current limiting circuit (1210; 1210_0) is designed to generate a digital signal (I_L), which indicates that the current limiting is activated, wherein in a first operating mode (SLOW; SIC) of the sending module (121; 121_0) the first to fourth sending stages (121A, 121B, 121C, 121D) can be controlled to generate a third bus state (L0), or are inactive.

10. The transmission module (121; 121_0) according to any one of the preceding claims, wherein the output terminals (41, 42) of the full bridge are provided for connection to a terminating resistor (49) of the bus (40).

11. The sending module (121; 121_0) according to any one of the preceding claims, wherein the sending module (121; 121_0) is switched to a first operating mode (SLOW; SIC) in a first communication phase (451) of a frame (450) which generates the frame for a message to at least one other user station (10, 20, 30) of the bus system (1), and wherein the transmitting module (121; 121_0) is switched to the second operating mode (FAST_TX) or the third operating mode (FAST_RX) in the second communication phase (452) of the frame (450), and In a first communication phase (451), a negotiation is carried out between user stations (10, 20, 30) of a bus system (1): which user station (10, 20, 30) has exclusive access to a bus (40) of the bus system (1) in a second communication phase (452) immediately following the first communication phase (451).

12. The sending module (121; 121_0) according to any one of the preceding claims, wherein the first transmission stage (121A) is designed to generate a transmission current (I1 to In) for a first signal (CAN_H) which can be transmitted to a bus (40) of the bus system (1), wherein the second transmission stage (121B) is designed to generate a transmission current (I1 to In) for a second signal (CAN_L), which can be transmitted to the bus (40) as a differential signal with respect to the first signal (CAN_H), wherein the third transmission stage (121C) is designed to generate a transmission current (I1 to In) for a first signal (CAN_H), and The fourth transmission stage (121D) is designed to generate a transmission current (I1 to In) for the second signal (CAN_L).

13. The sending module (121; 121_0) according to any one of the preceding claims, wherein each of the first to fourth transmission stages (121A to 121D) has at least two current stages (S1 to Sn) connected in parallel to each other, wherein each of at least two current stages (S1 to Sn) has a switchable resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and The switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the transmission stage (121A to 121D) have different resistance values. For each of the first to fourth transmitting stages (121A to 121D), the number n of at least two current stages (S1 to Sn) is the same, where n is a natural number greater than 1.

14. The sending module (121; 121_0) according to claim 13, wherein each of at least two current stages (S1 to Sn) has a CMOS transistor for switching the resistance (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the current stage (S1 to Sn), wherein the CMOS transistors of the current stage (S1 to Sn) of the first transmission stage (121A) are PMOS transistors, wherein the CMOS transistors of the current stage (S1 to Sn) of the second transmission stage (121B) are NMOS transistors, wherein the CMOS transistors of the current stage (S1 to Sn) of the third transmission stage (121C) are PMOS transistors, and Among them, the CMOS transistors of the current stage (S1 to Sn) of the fourth transmission stage (121D) are NMOS transistors.

15. The transmission module (121; 121_0) according to claim 1, wherein each of the first to fourth transmission stages (121A to 121D) further comprises Reverse polarity diodes (D_A; D_B; D_C; D_D) for protection against positive feedback into the terminal (43) for bus voltage supply and negative feedback from the terminal (44) for ground, and At least one common source and common gate (HVP_A; HVN_B; HVP_C; HVN_D) is used to protect the CMOS transistor. At least two common source and common gate (HVP_A; HVN_B; HVP_C; HVN_D) are connected in parallel with each other. wherein for each of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0), the number y of cascodes (HVP_A; HVN_B; HVP_C; HVN_D) is the same, where y is a natural number greater than 1, and At least two of the common-source and common-gate devices (HVP_A; HVN_B; HVP_C; HVN_D) have different on-resistances.

16. The sending module (121; 121_0) according to any one of the preceding claims, Furthermore, a control circuit (T_A; T_B; T_C; T_D) is provided for controlling the switchable components of the first to fourth transmission stages (121A to 121D) as a function of the digital transmission signal (TxD) and the operating mode (SLOW; SIC; FAST_TX) set for the transmission module (121; 121_0), The control circuit (T_A; T_B; T_C; T_D) is designed for time-staggered and controlled switching of the resistance values ​​of at least two current stages (S1 to Sn).

17. A transmitting / receiving device (12; 22) for a user station (20) of a serial bus system (1), comprising A transmitting module (121; 121_0) according to any one of the preceding claims, and The receiving module (122) is used for receiving a signal from the bus (40).

18. A subscriber station (10; 20; 30) for a serial bus system (1), having a transmitting / receiving device (12; 22) according to claim 17, and A communication control device (11; 21) is used to control communication in a bus system (1) and to generate a digital transmission signal (TxD) for actuating a first to a fourth transmission stage (121A, 121B, 121C, 121D).

19. A method for transmitting a differential signal in a serial bus system (1), wherein the method is performed using a transmission module (121; 121_0), the transmission module having a current limiting circuit (1210; 1210_0) and first to fourth transmission stages (121A, 121B, 121C, 121D) connected in a full bridge, and wherein the method has the following steps, The current (I_S1, I_GND) through the first and second leakage resistors (1211, 1212) connected to the full bridge is measured and evaluated by means of a current limiting circuit (1210; 1210_0), wherein the first and fourth transmission stages (121A, 121D) are connected in series and the third and second transmission stages (121C, 121B) are connected in series, and In response to two different values ​​of a digital transmit signal (TxD), a differential bus signal (CAN_L, CAN_H) for a bus (40) of a bus system (1) is generated using first to fourth transmit stages (121A, 121B, 121C, 121D), so that the transmit module (121; 121_0) generates a first or second bus state (401, 402) on the bus (40) in its first operating mode (SLOW; SIC) and generates a third or fourth bus state (L0, L1) in its second operating mode (FAST_TX), wherein the bus signal (CAN_L, CAN_H) on the bus (40) forms a voltage difference (VDIFF), the voltage value of which is different for the first to fourth bus states (401, 402, L0, L1), and The current limiting circuit (1210; 1210_0) limits the current (I_GND) through the second leakage resistor (1211, 1212) in a first operating mode (SLOW; SIC) of the transmitting module (121; 121_0) based on its evaluation of the current (I_S1, I_GND) and depending on the value of the digital transmission signal (TxD) and the operating mode of the transmitting module (121; 121_0) and a predetermined limit value (GW).

Images