Request message processing method and device, equipment and medium

Abstract

The invention discloses a request message processing method and device, equipment and a medium, and relates to the field of request processing, and the method comprises the steps: obtaining a currently received new request message; performing shifting operation on a message address pre-stored in a preset address memory to generate a target message address storage area; the position sequence of each message address storage area in the preset address memory represents the receiving sequence of each request message corresponding to each corresponding message address; storing non-message address information of the new request message to a preset message memory, and storing a message address of the new request message to a target message address storage area in the preset address memory; according to the method, the message addresses stored in the message address storage areas and the non-message address information of the corresponding request messages in the preset message storage are sequentially acquired based on the position sequence of the message address storage areas in the preset address storage, and the acquired message information is processed, so that the message information is output in a low-delay order-preserving manner.

Description

Technical Field

[0001] The present invention relates to the field of request processing, and in particular to a request message processing method, device, equipment and medium. Background Art

[0002] With the advent of the big data era, high-performance computing, intelligent multimedia and many other fields have put forward higher requirements on the performance of computer systems. In order to meet the performance requirements, computer systems have gradually developed from single-core to multi-core, and from multi-core to multi-chip. The transmission efficiency of the inter-chip interconnection interface has also become increasingly prominent in terms of the impact on system performance. When multiple processors initiate requests, the requests received by the inter-chip interconnection processing module may be requests with the same address that cannot be processed simultaneously and will cause monitoring, that is, conflicting requests, or requests that can be processed simultaneously. In some related technologies, a piece of information is specially opened to save the sequence information corresponding to each message, and the sequence information is updated after each new message is received. The sequence information is compared each time a message is sent. In this way, when a multi-processor request arrives, additional sequence information needs to be opened and resources need to be increased; a comparison algorithm needs to be implemented, and different comparison algorithms have different delays.

[0003] It can be seen that how to ensure that the message information that meets the requirements is output in order with shorter latency and lower power consumption is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a request message processing method, device, equipment and medium, which can ensure that the message information that meets the requirements is output in order with shorter latency and lower power consumption. The specific scheme is as follows:

[0005] In a first aspect, the present invention provides a request message processing method, comprising:

[0006] Get the new request message currently received;

[0007] Performing a shift operation on the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each corresponding message address;

[0008] The non-message address information of the new request message is stored in the preset message memory, and the message address of the new request message is stored in the target message address storage area in the preset address memory;

[0009] Based on the position order of each message address storage area in the preset address memory, the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence, and the obtained message information is processed.

[0010] Optionally, after obtaining the currently received new request message, the following is also included:

[0011] Determining whether the new request message is valid according to the storage state of the preset message memory;

[0012] If the new request message is valid, the step of performing a shift operation on the message address pre-stored in the preset address memory is executed.

[0013] Optionally, before performing a shift operation on the message address pre-stored in the preset address memory, the method further includes:

[0014] Determining whether there is available space in the preset address memory for storing the message address;

[0015] If there is no available space in the preset address memory, a first signal indicating that there is no available space in the preset address memory is output to the back end, and the new request message is stored in a preset first-in-first-out queue until there is available space in the preset address memory for storing the message address;

[0016] If there is available space in the preset address memory, determining whether there is a pre-saved message address in the preset address memory;

[0017] If there are pre-saved message addresses, the position of the available space is determined according to the position of each pre-saved message address;

[0018] If there is no pre-saved message address, directly storing the message address of the new request message in the preset address memory, and outputting a second signal indication to the back end indicating that there is no pre-saved message address in the preset address memory;

[0019] Accordingly, a shift operation is performed on the message address pre-stored in the preset address memory, including:

[0020] The message address pre-stored in the preset address memory is shifted according to the position of the available space.

[0021] Optionally, after the non-message address information of the new request message is saved in the preset message storage, the method further includes:

[0022] Determine the storage location of the non-message address information of the new request message in the preset message memory;

[0023] The storage location is saved to the target message address storage area in the preset address memory.

[0024] Optionally, after the message address of the new request message is saved in the target message address storage area in the preset address storage, the method further includes:

[0025] Obtaining the message address of the request message being processed by the protocol from the preset request address buffer area;

[0026] Compare the message address of the new request message with the message address of the request message being processed by the protocol;

[0027] If the message address of the new request message is the same as the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to invalid;

[0028] If the message address of the new request message is different from the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to valid.

[0029] Optionally, based on the position order of each message address storage area in the preset address storage area, sequentially acquiring the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage area, including:

[0030] Determining whether each message address stored in the message address storage area can be processed by the protocol according to the address mark corresponding to each message address stored in the message address storage area;

[0031] If the address mark is valid, it is determined that the message address stored in the message address storage area can be processed by the protocol;

[0032] If the address is marked as invalid, it is determined that the message address stored in the message address storage area cannot be processed by the protocol;

[0033] Based on the address mark and the position order of each message address storage area in the preset address memory, the message address capable of protocol processing stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence.

[0034] Optionally, after processing the acquired message information, the following steps are further included:

[0035] Determine whether the backend can receive and process the acquired message information to obtain the corresponding judgment result;

[0036] A corresponding third signal indication sent by the back end is received according to the judgment result, so as to determine the processing status of the acquired message information based on the third signal indication.

[0037] In a second aspect, the present invention provides a request message processing device, comprising:

[0038] A message acquisition module is used to acquire the new request message currently received;

[0039] A shift module, used for performing a shift operation on the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each corresponding message address;

[0040] A saving module, used for saving the non-message address information of the new request message to a preset message memory, and saving the message address of the new request message to a target message address storage area in the preset address memory;

[0041] The message information processing module is used to sequentially obtain the message addresses stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory based on the position order of each message address storage area in the preset address memory, and process the obtained message information.

[0042] In a third aspect, the present invention provides an electronic device, comprising:

[0043] Memory for storing computer programs;

[0044] A processor is used to execute a computer program to implement the aforementioned request message processing method.

[0045] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the aforementioned request message processing method when executed by a processor.

[0046] In the present invention, a newly received request message is obtained; a shift operation is performed on a message address pre-stored in a preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each message address; the non-message address information of the new request message is saved in the preset message memory, and the message address of the new request message is saved in the target message address storage area in the preset address memory; based on the position sequence of each message address storage area in the preset address memory, the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are sequentially obtained, and the obtained message information is processed.

[0047] Beneficial effect: The present invention obtains an address storage area for storing a new request message address by performing a shift operation on the message address, and stores non-message address information and address information separately, and finally outputs the message information in sequence according to the position sequence of the address storage area. In this way, the present invention can output message information in a first-in-first-out order by shifting rather than maintaining a sequence information table, thereby reducing latency and outputting message information that meets the requirements in a sequence-preserving manner. At the same time, the address information and non-address information are stored separately, and shifting is performed only according to the address information, thereby reducing logic resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 A flow chart of a request message processing method provided by an embodiment of the present invention.

[0050] Figure 2 A schematic diagram of a request message preprocessing module provided in an embodiment of the present invention;

[0051] Figure 3 A schematic diagram of a multi-processor request processing system provided by an embodiment of the present invention;

[0052] Figure 4 A control flow chart of a shift comparator provided by an embodiment of the present invention;

[0053] Figure 5 A schematic diagram of the structure of a request message processing device provided by an embodiment of the present invention;

[0054] Figure 6 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0057] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0058] In some related technologies, a block of information is specially allocated to store the sequence information corresponding to each message, and the sequence information is updated after each new message is received. The sequence information is compared each time a message is sent. In this way, when multiple processor requests arrive, additional sequence information needs to be allocated, which increases resources; a comparison algorithm needs to be implemented, and different comparison algorithms have different delays. To this end, the present invention provides a request message processing method, device, equipment and medium, which can ensure that the message information that meets the requirements is output in an orderly manner with less latency and lower power consumption.

[0059] See also Figure 1 As shown, an embodiment of the present invention provides a request message processing method, including:

[0060] Step S11: Obtain the currently received new request message.

[0061] In the embodiment of the present invention, the currently received new request message is first obtained. After obtaining the currently received new request message, whether the new request message is valid is determined according to the storage state of the preset message memory; if the new request message is valid, the step of shifting the message address pre-stored in the preset address memory is executed. Specifically, the request message processing of the present invention mainly utilizes the following Figure 2 The request message receiving preprocessing module shown in the figure will also receive a request message valid indication when receiving new request message information. The request message valid indication indicates that the new request message is valid. When there is an external message input and the request message preprocessing module outputs a non-full state (~full), the external logic will set the signal to be valid, otherwise it will be invalid. At the same time, the new request message currently received can be customized according to the specific requirements of the project or the message package format can be determined according to the bus protocol regulations, which includes the request address information.

[0062] Step S12, shifting the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each corresponding message address.

[0063] In an embodiment of the present invention, if the new request message is valid, the step of shifting the message address pre-saved in the preset address memory is executed. However, before shifting the message address pre-saved in the preset address memory, the present invention will first determine whether the message address of the new request message can be stored in the preset address memory, that is, whether the message address pre-saved in the preset address memory needs to be shifted to provide a storage area for the message address of the new request message.

[0064] In this process, the present invention first determines whether there is available space in the preset address memory for storing the message address; if there is no available space in the preset address memory, a first signal indication indicating that there is no available space in the preset address memory is output to the back end, and the new request message is stored in the preset first-in-first-out queue until there is available space in the preset address memory for storing the message address; if there is available space in the preset address memory, it is determined whether there is a pre-saved message address in the preset address memory; if there is a pre-saved message address, the position of the available space is determined according to the position of each pre-saved message address; if there is no pre-saved message address, the message address of the new request message is directly stored in the preset address memory, and a second signal indication indicating that there is no pre-saved message address in the preset address memory is output to the back end. Specifically, if the preset address memory does not have available space for storing the message address, that is, the preset address memory is full, a full signal indication will be output, and at this time, the new request message will first enter the request FIFO (First Input First Output) cache after being read, and then if the request message preprocessing module cache is not full, the message in the request FIFO cache will be read to the request message preprocessing module. However, if the preset address memory of the current request message preprocessing module is full, it will be temporarily stored in the request FIFO cache, and the available space will be obtained after the message address pre-saved in the preset address memory is selected and output. In addition, if the preset address memory has available space for storing the message address, it is necessary to first determine whether the preset address memory is empty and there is no pre-saved message address. If it is empty, an empty signal indication (empty) will be output: indicating that the current message memory is empty. Because the preset address memory is empty at this time, the pre-saved message address does not need to be shifted, and the message address of the new request message can be directly placed in the preset address memory. If it is not empty and there are some pre-saved message addresses, the position of the available space will be determined according to the position of each pre-saved message address. Then, when the pre-saved message addresses in the preset address memory are shifted, the pre-saved message addresses in the preset address memory will be shifted according to the position of the available space.

[0065] Specifically, for example, the shift operation of the pre-saved message address is performed. The preset address memory has a total of 4 rows. The 3rd row has been selected for output. At the next moment, a new message comes in. The 4th row determines that it is the highest row and does not shift. The 3rd row is invalid and does not shift. The message in the 2nd row is shifted to the 3rd row, and the message in the 1st row is shifted to the 2nd row. In this way, the storage area of ​​the 1st row is vacated, and the new message address can be placed in the first row. This ensures that the first input message information is in the storage area with a larger number of rows.

[0066] Step S13: Save the non-message address information of the new request message to the preset message memory, and save the message address of the new request message to the target message address storage area in the preset address memory.

[0067] In the implementation of the present invention, the internal logic of the request message preprocessing module mainly includes a two-dimensional array memory, M shift comparators, and an output information module. Among them, the depth of the two-dimensional array memory is M, and the width is the input request message information bit width. In order to reduce the number of logic, the two-dimensional array memory of the present invention is divided into two parts for storage, namely a preset message memory and a preset address memory. During the shift control, only the message address is shifted, and the remaining information in the message is stored in the message memory. Therefore, after the non-message address information of the new request message is saved in the preset message memory, the storage position of the non-message address information of the new request message in the preset message memory will be determined; the storage position is saved to the target message address storage area in the preset address memory.

[0068] Specifically, when the request message valid indication is valid, the message information in the request message information except the address information is stored in the message memory, and the address memory contains the following two information: 1. The address information of the request message 2. The storage row information of the message memory (that is, the row number of the two-dimensional array in which the current message information is stored). The value of the message storage row information is as follows: when each valid message is input, the current row information is added by 1, and its value range is 0~M-1. That is, the storage information of each row in the address memory is {message address information, storage row information of the message memory}. It should be pointed out that if the message address of the new request message is saved to the target message address storage area in the preset address memory, the address memory valid mark corresponding to the message address of the new request message will be set to valid at the same time. Among them, the address memory valid mark: indicates whether the address in the address memory is valid, that is, whether the message stored in the current row is valid. The bit width is M, and each bit represents a valid indication of a row, 1 is valid, and 0 is invalid. In this way, when the request message valid indication is valid and the address memory valid flag bit x is valid, it means that a valid message has been previously stored in the address memory row x, so as to determine whether the message address stored in the address memory is valid.

[0069] At the same time, the function of the M shift controller modules in the present invention is to select the information in the address memory corresponding to the earliest received message that is different from the address in the protocol processing through logical judgment. Therefore, after the message address of the new request message is saved in the target message address storage area in the preset address memory, the message address of the request message being processed by the protocol is obtained from the preset request address buffer area; the message address of the new request message is compared with the message address of the request message being processed by the protocol; if the message address of the new request message is the same as the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to invalid; if the message address of the new request message is different from the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to valid.

[0070] Specifically, the address information in each shift register needs to be compared with the address comparison information input by the request message preprocessing module. The address comparison information here represents the message address of the request message that is being processed by the protocol, and is combined into {addrn, ... addr1, addr0}. The address comparison information bit width = request address bit width × number of storage table entries; where the number of storage table entries = the maximum number of requests allowed to be initiated by a single processor × the number of processors. At the same time, the address comparison information also corresponds to an address validity flag. The address validity flag indicates that each bit indicates whether the address information corresponding to the above address comparison information is valid (that is, if addr1 in the above address comparison information is invalid, the value is {1 ... 01}). The bit width is M. If it is valid, it indicates that the message entering the request message preprocessing module needs to be compared with the address, otherwise it does not need to be compared with the address. The preset request address buffer stores the message addresses of all request messages that are being processed by the protocol. When the request message is selected from the request message preprocessing module and the protocol processing begins, the request address is recorded in the request address cache module (a two-dimensional array with a bit width of the request message address and a depth of M), and the output is the address comparison information address and a valid flag. If addr0 and addr1 have been stored, the output address comparison information is {00...addr1,addr0}, and the address valid flag is {00...11}. When the entire request processing flow of the corresponding address is completed, the corresponding bit position is invalid. For example, when the addr0 request processing is completed, the address valid flag output becomes {00...10}.

[0071] When comparing the message address of the new request message with the message address of the request message being processed by the protocol, if the message address of the new request message is the same as the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to invalid; if the message address of the new request message is not the same as the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to valid. The address mark here can be named the same address mark, indicating whether there is an address in the address memory that is the same as the address comparison information, the bit width is M, each bit represents a row of the same address indication, and a judgment is required when a new message is input or the address valid flag changes. Setting 1 indicates that there is no same address in the current comparison, and the request message can be processed. M shift comparators are executed sequentially in the same clock to compare the message address of the new request message with the message address of the request message being processed by the protocol. For each shift comparator: if the same address is compared, the corresponding position of the same address mark needs to be 0, otherwise it is set to 1.

[0072] Step S14: based on the position order of each message address storage area in the preset address storage, sequentially obtain the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage, and process the obtained message information.

[0073] In the embodiment of the present invention, when outputting a message request, the present invention will judge whether each message address stored in the message address storage area can be processed by protocol according to the address mark corresponding to each message address stored in the message address storage area; if the address mark is valid, it is determined that the message address stored in the message address storage area can be processed by protocol; if the address mark is invalid, it is determined that the message address stored in the message address storage area cannot be processed by protocol; finally, based on the address mark and the position order of each message address storage area in the preset address memory, the message address stored in the message address storage area that can be processed by protocol and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence. It is also necessary to determine whether this message address can be output for protocol processing according to the address mark.

[0074] In the process of processing the acquired message information, it involves the generation of the processed message flag and the generation of the output message information, wherein the process of generating the processable message flag is as follows: a register optional message indication signal indicator with a signal bit width of M is designed, which is the bitwise OR of the address memory valid mark and the same address mark, indicating the currently selectable message indication signal. Then, the selected message indication signal is subjected to logical judgment processing, and its bit width is M. Each bit represents whether the current row of the address memory can be selected for output. The high bit indicates the earliest arriving message, and the lowest bit indicates the latest arriving message. The principle of high bit effective priority is used to ensure the order-preserving processing of the request message. The final output processable message flag is the bitwise OR result of the optional message indication signal indicator, that is, as long as there are non-same address messages in the address memory, the processable message flag can be output.

[0075] When selecting the message to be output, the shift controller selects the i-th row of the address memory that has no identical address and arrives first during the processing. Since the i-th row contains the message address information and the storage row information of the message memory, the message storage row information j in the i-th row can be obtained. Through the message storage row information j, the selected message can be directly obtained as the j-th row information of the message memory. Then the final output message information is the selected message information and the address information of the i-th row of the address memory. That is, based on the address mark and the position order of each message address storage area in the preset address memory, the message address that can be processed by the protocol stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence, and then the message address and non-message address information are finally output.

[0076] It should also be noted that after processing the acquired message information, it is necessary to determine whether the back end can receive and process the acquired message information to obtain the corresponding judgment result; according to the judgment result, the corresponding third signal indication sent by the back end is received, so as to determine the processing status of the acquired message information based on the third signal indication. The third indication signal here is an external selection message indication, indicating that the back end can process the currently selected message. Its generation logic is: when it is detected that the request message preprocessing module outputs a processable message flag, and determines whether the back end can receive the message processing, if it is satisfied, it is set to 1, otherwise it is set to 0. The minimum delay can be valid at the same clock as the processable message flag, that is, a 0 delay output indication is achieved. In addition, the request message processing of the present invention is not limited to the request message address conflict judgment, and this method can be used when a conflict judgment is required for the input information.

[0077] Since the present invention finally outputs the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage to the back end for protocol processing, in order to prevent data loss and data missing during the output process, the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage can be packaged and encapsulated according to the custom request packet format or the request message packet format specified by the bus protocol, a message packet is obtained, and a hash operation is performed based on the message packet to obtain a hash value, and finally the hash value and the message packet are sent to the back end together, so that the back end can verify the message packet according to the hash value after receiving the message packet to determine whether the message information in the message packet is complete. If not, a signal that cannot be processed is directly returned without other processing. If complete, protocol processing is performed, thereby ensuring the integrity of the message information subjected to protocol processing.

[0078] Beneficial effect: The present invention obtains an address storage area for storing a new request message address by performing a shift operation on the message address, and stores non-message address information and address information separately, and finally outputs the message information in sequence according to the position sequence of the address storage area. In this way, the present invention can output message information in a first-in-first-out order by shifting rather than maintaining a sequence information table, thereby reducing latency and outputting message information that meets the requirements in a sequence-preserving manner. At the same time, the address information and non-address information are stored separately, and shifting is performed only according to the address information, thereby reducing logic resources.

[0079] The process of protocol processing for multiprocessor requests is shown in Figure 3 As shown, when the request of multiple processors arrives, the request message to be processed will first be selected by the request message preprocessing module, and then the request message will start protocol processing. The request processing process mentioned in the present invention, taking CCIX (Cache Coherent Interconnect for Accelerators, a cache consistency interconnect standard for accelerators) protocol as an example, refers to all processes from the beginning of request processing to receiving the request response or ACK (Acknowledgement) response. Next, the processing of the message by the request message preprocessing module will be explained in detail.

[0080] See also Figure 2As shown, the internal logic of the request message preprocessing module mainly includes a two-dimensional array memory, M shift controller modules, and an output information module. The depth of the two-dimensional array memory is M, and the width is the bit width of the input request message information. In order to reduce the number of logic, the two-dimensional array memory of the present invention is divided into two parts for storage, namely, a message memory and an address memory. During the shift control, only the message address is shifted, and the remaining information in the message is stored in the message memory. As shown in the figure, when a new message is input and the request message valid indication is valid, the message information in the request message information except the address information is stored in the message memory, and the address memory contains the following two information: 1. The address information of the request message 2. The storage row information of the message memory (that is, the row number of the two-dimensional array in which the current message information is stored). The value of the message storage row information is: when each valid message is input, the current row information is added by 1, and its value range is 0~M-1. That is, the storage information of each row in the address memory is {message address information, storage row information of the message memory}.

[0081] The function of the M shift controller modules is to select the information in the address memory corresponding to the earliest received message that is different from the current address in the protocol processing through logical judgment. The address information in each shift register needs to be compared with the address comparison information input by the request message preprocessing module, and the M shift comparators are executed sequentially in the same clock. For each shift comparator: if the same address is compared, the corresponding position of the same address mark needs to be set to 0, otherwise it is set to 1. At the same time, when the request message valid indication is valid and the address memory valid mark xth bit is valid, it means that there is a valid message in the address memory before. In this case, the data of the address memory xth row needs to be shifted to the address memory x+1th row, and the address memory valid mark xth bit needs to be moved to the address memory x+1th bit. If the message address information corresponding to the x+th row is selected for output, the address memory valid mark xth bit is set to 0. For example: if there is a valid message in the third row of the address memory and there is a valid message input at present, the shift register 3 will judge the new message input, and will shift the information of the third row of the address memory to the fourth row, and shift the valid mark of the address memory of the third row to the fourth row, and at the same time record the comparison result with the address comparison information input by the module in the same address mark of the fourth row. By analogy, the logic control of each shift comparator is the same. In this way, it is ensured that the message information input first is in the storage area with a larger number of rows. In general, when the address information in the address memory is shifted, the corresponding address valid mark and the same address mark are also shifted at the same time. At the same time, if there is no new message input, it is determined whether the address valid mark changes. If it changes, a new same address mark will be generated. If there is no change, the same address mark remains unchanged.

[0082] For the output information module, the status output and message output are realized. It includes the generation of processable message flag and output message information. The process of generating processable message flag is as follows: the register optional message indication signal indicator with a signal bit width of M is designed, which is the bitwise OR of the address memory valid mark and the same address mark, indicating the currently selectable message indication signal. Then the selected message indication signal is processed by logical judgment. Its bit width is M. Each bit represents whether the current row of the address memory can be selected for output. The high bit indicates the earliest arriving message, and the lowest bit indicates the latest arriving message. The principle of high bit effective priority is used to ensure the order-preserving processing of the request message. The final output processable message flag is the bitwise OR result of the optional message indication signal indicator, that is, as long as there are non-same address messages in the address memory, the processable message flag can be output. Finally, based on the address tag and the position order of each message address storage area in the preset address memory, the message address that can be processed by the protocol stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence, and then the message address and non-message address information are finally output.

[0083] Beneficial effects: The present invention outputs request messages in a first-in-first-out order by shifting rather than maintaining a sequence information table. If there is data in the memory, the selected message can be output without delay at the fastest speed, thereby ensuring low-latency and sequence-preserving output of message information that meets the requirements. At the same time, by splitting the input message, the comparison information and the message information that does not need to be compared are stored separately, reducing logic resources.

[0084] See also Figure 5 As shown, an embodiment of the present invention provides a request message processing device, including:

[0085] The message acquisition module 11 is used to acquire the currently received new request message;

[0086] The shift module 12 is used to perform a shift operation on the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each corresponding message address;

[0087] A storage module 13, used for storing the non-message address information of the new request message into a preset message memory, and storing the message address of the new request message into a target message address storage area in the preset address memory;

[0088] The message information processing module 14 is used to sequentially obtain the message addresses stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory based on the position order of each message address storage area in the preset address memory, and process the obtained message information.

[0089] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0090] Beneficial effect: The present invention obtains an address storage area for storing a new request message address by performing a shift operation on the message address, and stores non-message address information and address information separately, and finally outputs the message information in sequence according to the position sequence of the address storage area. In this way, the present invention can output message information in a first-in-first-out order by shifting rather than maintaining a sequence information table, thereby reducing latency and outputting message information that meets the requirements in a sequence-preserving manner. At the same time, the address information and non-address information are stored separately, and shifting is performed only according to the address information, thereby reducing logic resources.

[0091] Furthermore, an embodiment of the present invention also discloses an electronic device, Figure 6 It is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of the present invention. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the request message processing method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0092] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present invention, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0093] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0094] The operating system 221 is used to manage and control various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the request message processing method executed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0095] Furthermore, the present invention also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed request message processing method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0096] Furthermore, the present invention also discloses a computer program product, including a computer program / instruction; wherein, when the computer program / instruction is executed by a processor, the aforementioned disclosed request message processing method is implemented. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0097] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0098] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0099] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0100] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0101] The technical solution provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A request message processing method, characterized in that: include: Get the new request message currently received; Shifting the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each corresponding message address; Saving the non-message address information of the new request message to a preset message memory, and saving the message address of the new request message to the target message address storage area in the preset address memory; Based on the position order of each message address storage area in the preset address memory, the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence, and the obtained message information is processed.

2. The request message processing method according to claim 1, characterized in that: After obtaining the currently received new request message, the method further includes: Determining whether the new request message is valid according to the storage state of the preset message memory; If the new request message is valid, the step of performing a shift operation on the message address pre-stored in the preset address memory is executed.

3. The request message processing method according to claim 1, characterized in that: Before the shift operation is performed on the message address pre-stored in the preset address memory, the method further includes: Determining whether the preset address memory has available space for storing the message address; If the preset address memory does not have the available space, outputting a first signal indication indicating that the preset address memory does not have the available space to the back end, and storing the new request message in a preset first-in-first-out queue until the preset address memory has available space for storing the message address; If the preset address memory has the available space, determining whether there is a pre-saved message address in the preset address memory; If the pre-saved message address exists, determining the position of the available space according to the position of each pre-saved message address; If the pre-saved message address does not exist, directly storing the message address of the new request message in the preset address memory, and outputting a second signal indication to the back end indicating that the pre-saved message address does not exist in the preset address memory; Correspondingly, the shifting operation on the message address pre-stored in the preset address memory includes: A shift operation is performed on the message address pre-stored in the preset address memory according to the position of the available space.

4. The request message processing method according to claim 1, characterized in that: After the non-message address information of the new request message is saved in the preset message storage, the method further includes: Determining a storage location of the non-message address information of the new request message in the preset message memory; The storage location is saved to the target message address storage area in the preset address memory.

5. The request message processing method according to claim 1, characterized in that: After the message address of the new request message is saved in the target message address storage area in the preset address memory, the method further includes: Obtaining the message address of the request message being processed by the protocol from the preset request address buffer area; Comparing the message address of the new request message with the message address of the request message being processed by the protocol; If the message address of the new request message is the same as the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to invalid; If the message address of the new request message is different from the message address of the request message being processed by the protocol, the address mark corresponding to the message address of the new request message is set to valid.

6. The request message processing method according to claim 5, characterized in that: The step of sequentially acquiring the message addresses stored in the message address storage areas and the non-message address information of the corresponding request message in the preset message storage area based on the position order of each message address storage area in the preset address storage area includes: Determining whether each message address stored in the message address storage area can be processed by protocol according to the address mark corresponding to each message address stored in the message address storage area; If the address mark is valid, it is determined that the message address stored in the message address storage area can be processed by the protocol; If the address is marked as invalid, it is determined that the message address stored in the message address storage area cannot be processed by the protocol; Based on the address mark and the position order of each message address storage area in the preset address memory, the message address capable of protocol processing stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained in sequence.

7. The request message processing method according to any one of claims 1 to 6, characterized in that: After the acquired message information is processed, the method further includes: Determine whether the backend can receive and process the acquired message information to obtain the corresponding judgment result; A corresponding third signal indication sent by the back end is received according to the judgment result, so as to determine a processing status of the acquired message information based on the third signal indication.

8. A request message processing device, characterized in that: include: A message acquisition module is used to acquire the new request message currently received; A shift module, used for performing a shift operation on the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the order of receiving each request message corresponding to each corresponding message address; A saving module, used for saving the non-message address information of the new request message to a preset message memory, and saving the message address of the new request message to the target message address storage area in the preset address memory; A message information processing module is used to sequentially obtain the message addresses stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory based on the position order of each message address storage area in the preset address memory, and process the obtained message information.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the request message processing method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the request message processing method according to any one of claims 1 to 7 are implemented.

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