Multi-system multi-channel video processing transmission method

Abstract

According to the multi-system multi-channel video processing transmission method, the programmable logic gate array is adopted to complete complex processing and switching, and the functions of processing multi-channel different-system videos and converting the multi-channel different-system videos into ARI NC818 optical signals for transmission are achieved. According to the invention, at the front end, video signals are decoded into parallel digital videos through a video decoder, functions of video protocol automatic detection and conversion, video code stream buffering, video scaling, video switching and ARI NC818 protocol coding are completed by adopting an FPGA, logic resources are fully utilized, and special processing and coding and decoding chips are replaced. And at the rear end, an ARI NC818 electric signal is converted into an optical signal through a photoelectric conversion module, so that the transmission of a multi-system multi-channel video is completed.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic component detection, and in particular relates to a multi-standard multi-channel video processing and transmission method. Background Art

[0002] With the rapid development of artificial intelligence and graphics and imaging, visual sensors have become an indispensable component of aviation embedded computers. Graphic images have been widely used in many fields due to their rich information, strong expressiveness, and strong human-computer interaction. In avionics systems, the cockpit display needs to display video data from multiple sources such as visual sensors and radars to provide pilots with comprehensive and accurate decision-making information. However, different sensors are configured with different video interfaces and cannot be matched, and universal video interfaces cannot meet the increasingly complex electromagnetic environment on board. Summary of the invention

[0003] In view of this, the multi-standard multi-channel video processing and transmission method of the present invention solves the problems that the traditional visual sensor interface is not unified, cannot meet the requirements of multi-channel video processing and transmission, and cannot adapt to complex electromagnetic environments.

[0004] A multi-standard multi-channel video processing and transmission method is applicable to video output processing of an airborne cockpit display control system, the method comprising:

[0005] S1: Acquire multiple external video sources on board, perform multi-format video decoding through a video decoder, and form parallel video streams;

[0006] S2: Using FPGA chip to complete the automatic protocol detection and conversion, multi-level cache, video processing, video switching and ARI NC818 encoding functions of the parallel video streams, and output ARI NC818 electrical signals;

[0007] S3: Convert the ARI NC818 electrical signal into an optical signal through an optoelectronic transceiver and output it.

[0008] The technical beneficial effects of the present invention are:

[0009] The video decoding circuit is used to convert multi-standard and multi-channel videos into parallel video signals and transmit them to the FPGA. After receiving the parallel video, the FPGA chip completes protocol detection and conversion, video bitstream caching, video processing, video switching and ARI NC818 encoding functions, and then converts the ARI NC818 electrical signal into an optical signal for transmission through the optoelectronic transceiver, which can realize video transmission over long distances and in complex electromagnetic environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 It is a schematic diagram of the architecture of a multi-standard multi-channel video processing and transmission circuit;

[0012] Figure 2 Schematic diagram of video processing transmission implementation. DETAILED DESCRIPTION

[0013] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0014] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0015] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0016] like Figure 1 to Figure 2 The multi-standard multi-channel video processing and transmission method shown is suitable for video output processing of an airborne cockpit display control system, and the method includes:

[0017] S1: Obtain multiple external video sources on board, perform multi-format video decoding through a video decoder, and form parallel video streams. For example, the video decoder decodes the serial input multi-format video signals into parallel digital signals, and inputs them into the FPGA chip;

[0018] S2: Using FPGA chip to complete the automatic protocol detection and conversion, multi-level cache, video processing, video switching and ARI NC818 encoding functions of the parallel video stream, output ARI NC818 electrical signal, pixel format is RGB888;

[0019] S3: The ARI NC818 electrical signal is converted into an optical signal through an optoelectronic transceiver and output, making full use of the flexibility of FPGA logic, having video processing capabilities, realizing the conversion of multiple video interfaces to the ARI NC818 optical interface, and improving the environmental adaptability of the video output interface.

[0020] The video decoding circuit is used to convert multi-standard and multi-channel videos into parallel video signals and transmit them to the FPGA. After receiving the parallel video, the FPGA chip completes protocol detection and conversion, video bitstream caching, video processing, video switching and ARI NC818 encoding functions, and then converts the ARI NC818 electrical signal into an optical signal for transmission through the optoelectronic transceiver, which can realize video transmission over long distances and in complex electromagnetic environments.

[0021] As a specific implementation method provided in this case, it is suitable for processing multiple videos, each video channel is provided with a first buffer A, a second buffer B and a third buffer C, and the automatic protocol detection and conversion, multi-level caching, video processing and video switching of the parallel video streams using an FPGA chip in S2 include:

[0022] Automatic protocol detection and conversion: using an FPGA chip to receive the parallel video streams, and automatically performing protocol detection and conversion to convert the parallel video streams into a video format that complies with the VESA DMT timing sequence;

[0023] The FPGA chip detects the parameters of the parallel video streams and performs video scaling according to the parameters. The video scaling is adjusted according to the scaling parameters received by the external interface and adjusted to a preset resolution. The scaling parameters are adjusted including:

[0024] That is, multi-level cache---each parallel video stream is stored in the first buffer A and the second buffer B in turn in the form of ping-pong operation. When the buffering in the first buffer A is completed, the parallel video stream is input to the second buffer B for buffering, and the parallel video stream in the first buffer A is read by bilinear interpolation and a scaling operation is performed, or, when the buffering in the second buffer B is completed, the parallel video stream is input to the first buffer A for buffering, and the parallel video stream in the second buffer B is read by bilinear interpolation and a scaling operation is performed, and the scaled parallel video stream is output to the third buffer C, the purpose is to: ensure the transmission efficiency of the parallel video stream and reduce the transmission delay;

[0025] When the external interface receives a switching instruction, the parallel video stream in the third buffer C corresponding to the switching instruction is output. For example, the image in the third buffer C of a certain channel is continuously updated through the first buffer A or the second buffer B. When a switching instruction is sent externally, the updated image data is selectively output to improve the flexibility of video processing and control.

[0026] The multi-standard multi-channel video processing and transmission method uses a programmable logic gate array to complete complex processing and switching, realizes the function of multi-channel video processing of different standards and converting it into ARI NC818 optical signals for transmission. At the front end, the present invention decodes the video signal into parallel digital video through a video decoder, and uses FPGA to complete the functions of automatic video protocol detection and conversion, video code stream buffering, video scaling, video switching, and ARI NC818 protocol encoding, making full use of logic resources to replace special processing and codec chips. At the back end, the ARI NC818 electrical signal is converted into an optical signal through an optoelectronic conversion module to complete the transmission of multi-standard multi-channel video.

[0027] Furthermore, the video code stream processed by the FPGA is encoded into a data stream that complies with the ARI NC818 format protocol Class 3 service, output through the FPGA's SerDes interface, and converted into an optical signal for external output using an optoelectronic transceiver. The maximum rate of the ARINC818 encoding block outputting the video stream is 14.025 Gbps.

[0028] For example: a multi-standard multi-channel video processing and transmission system used in a certain display and control product. This system is based on FPGA and optoelectronic transceivers to implement 4-way video input, processing, switching and encoding output of different standards, as follows:

[0029] The video decoding circuit receives 4 external videos for decoding, obtains parallel video signals, and transmits them to the FPGA through FPGA IO. The FPGA configures the video parameters of the video decoding circuit through the communication interface, obtains and monitors its working status. The FPGA performs protocol detection and conversion on the received parallel video signals to obtain parallel RGB video signals that comply with VESA timing. Parameter detection is then performed, and video streams of different resolutions are uniformly scaled to the specified resolution through bilinear interpolation. The maximum resolution is 3840×2160@60fps. The scaling is based on a multi-level buffer. The input video is stored in buffers A and B in turn using a ping-pong operation, and the scaled video is stored in buffer C. The scaled video selects one output according to the external switching control instruction. The ARI NC818 encoding block outputs the video stream encoded as a data stream that complies with the ARI NC818 protocol Class 3 service, with a maximum rate of 14.025Gbps. The ARI NC818 electrical signal output by the FPGA is converted into an 850nm optical signal through an optoelectronic transceiver, and is output to the cabin display through a standard aviation plug for display. The output optical video signal is resistant to electromagnetic interference, has strong transmission capability, and has greater scalability.

[0030] In order to obtain real-time flight information, the cockpit display needs to receive video information from different sensors. Different types of sensors have different video interfaces. The single-format electrical signal transmission interface can no longer meet the increasingly complex application environment. Using FPGA to implement multi-standard multi-channel video processing and transmission has the following characteristics compared to ordinary video processing and transmission methods:

[0031] First, the flexibility of video input formats is increased. Parallel videos decoded from different video interfaces are automatically detected and converted into digital RGB video signals through FPGA, and then processed and switched inside FPGA for unified output.

[0032] Second, the video processing capability is improved. FPGA has rich logic resources and can realize multi-channel video buffering, scaling, switching and other functions by configuring external memory.

[0033] Third, the environmental adaptability of the video output interface is improved. The ARI NC818 electrical signal output by the FPGA is converted into an optical signal for transmission through an optoelectronic transceiver, and has the ability to resist electromagnetic interference.

[0034] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A multi-standard multi-channel video processing and transmission method, suitable for video output processing of an airborne cockpit display control system, characterized in that: The methods include: S1: Acquire multiple external video sources on board, perform multi-format video decoding through a video decoder, and form parallel video streams; S2: Using FPGA chip to complete the automatic protocol detection and conversion, multi-level cache, video processing, video switching and ARINC818 encoding functions of the parallel video stream, and output ARINC818 electrical signal; S3: Convert the ARINC818 electrical signal into an optical signal through an optoelectronic transceiver and output it.

2. The multi-standard multi-channel video processing and transmission method according to claim 1, characterized in that ,S1 includes decoding the serially input multi-standard video signals into parallel ,digital signals through a video decoder and input them to the FPGA chip.

3. The multi-standard multi-channel video processing and transmission method according to claim 1, characterized in that , suitable for processing multiple channels of video, each channel of video is provided with a first buffer A, a second buffer B and a third buffer C, the automatic protocol detection and conversion, multi-level caching, video processing and video switching of the parallel video streams using the FPGA chip in S2 include, Using an FPGA chip to receive the parallel video streams, and performing automatic protocol detection and conversion, converting the parallel video streams into a video format that complies with the VESA DMT timing; The FPGA chip detects the parameters of the parallel video streams and performs video scaling according to the parameters. The video scaling is adjusted according to the scaling parameters received by the external interface and adjusted to a preset resolution. The scaling parameters are adjusted including: Each parallel video stream is stored in the first buffer A and the second buffer B in turn in the form of a ping-pong operation. When the buffering in the first buffer A is completed and the parallel video stream is input to the second buffer B for buffering, the parallel video stream in the first buffer A is read by a bilinear interpolation method and a scaling operation is performed. Alternatively, when the buffering in the second buffer B is completed and the parallel video stream is input to the first buffer A for buffering, the parallel video stream in the second buffer B is read by a bilinear interpolation method and a scaling operation is performed, and the scaled parallel video stream is output to a third buffer C. When the external interface receives a switching instruction, the parallel video stream in the third buffer C corresponding to the switching instruction is output.

4. The multi-standard multi-channel video processing and transmission method according to claim 1, characterized in that ,The video code stream processed by FPGA is encoded into a data stream that complies with the ARINC818 format protocol, and is output through the SerDes interface of the FPGA chip, and is converted into an optical signal for external output using the optoelectronic transceiver.

5. The multi-standard multi-channel video processing and transmission method according to claim 4, characterized in that ,The maximum rate of the video stream output by the ARINC818 encoding block is 14.025Gbps.

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