SAR-SS type ADC circuit and module with pre-judgment logic

Abstract

The present invention relates to the technical field of image sensor design, and specifically discloses a SAR-SS type ADC circuit and module with pre-judgment logic. Based on digital correlated multi-sampling, the present invention adopts a SAR-SS hybrid architecture to decompose the 12-bit quantization of two columns of pixel signals {V ref,n}, {V sig,n} into coarse quantization by the SAR-ADC part and fine quantization by the SS-ADC part, improving the overall quantization speed of the ADC while achieving low noise and having lower power consumption than the traditional CMS ADC using a single architecture SS type ADC. The circuit of the present invention is provided with a pre-judgment logic part to judge whether it is necessary to perform coarse quantization on the pixel readout signal V sig,2 to reduce the unnecessary time consumption and power consumption of coarse quantization, and further improve the overall speed and power consumption of the ADC.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically, to: 1. A SAR-SS type ADC circuit with pre-judgment logic; 2. A SAR-SS type ADC module with pre-judgment logic. Background Art

[0002] Complementary Metal Oxide Semiconductor Image Sensor (CMOS image sensor), abbreviated as CIS, is widely used in the fields of digital cameras, mobile phone cameras, surveillance cameras, etc. The analog-to-digital converter (ADC), as a key component of CMOS, is responsible for converting the electrical signals generated by the photosensitive elements into digital signals, and its performance directly determines the imaging quality of CMOS.

[0003] Currently, three main types of ADCs are used in CIS: pixel-level ADC, column-level ADC, and chip-level ADC. Among them, the column-level ADC has become the mainstream choice due to its advantages of low power consumption, relatively simple design, and high conversion efficiency. Common column-level ADCs include successive approximation ADC (SAR ADC), cyclic ADC, and single-slope ADC (SS ADC), and each structure has its own characteristics in terms of accuracy, speed, and power consumption, and can be selected according to specific requirements.

[0004] For an ADC operating in a low-light environment, its quantization result is extremely vulnerable to ambient noise, so a low-noise design is required. In recent years, the correlated multi-sampling technique (CMS) has become the mainstream in the design of low-noise ADCs. The single-slope ADC (SS ADC) has become the main type used in CMS ADCs due to its advantages of simple structure, low power consumption, and small area.

[0005] However, traditional CMS ADCs only use a single SS type structure. Although this can achieve a very good noise reduction effect, the quantization time of the ADC is very long, resulting in relatively high power consumption. Moreover, there is an obvious exponential relationship between the conversion speed, power consumption, and number of bits of traditional SS ADCs. To improve the conversion accuracy by 1 bit requires almost doubling the speed and power consumption, and these indicators are particularly important for CIS. Therefore, improving speed and reducing power consumption while ensuring low noise has become an important research point for CMS ADCs. Summary of the Invention

[0006] Based on this, in view of the problem that traditional CMS ADCs need to improve speed and reduce power consumption while ensuring low noise, a SAR-SS type ADC circuit and module with pre-judgment logic are provided.

[0007] The present invention is implemented by the following technical solutions:

[0008] In a first aspect, the present invention provides a SAR-SS type ADC circuit with a pre-judgment logic, which is used to perform 12-bit quantization on two columns of pixel signals {V ref,n}, {V sig,n} to obtain a 12-bit quantization result F ref,n , V sig,n of [V n <11:0>; n ∈ {1, 2}.

[0009] A SAR-SS type ADC circuit with a pre-judgment logic includes: a signal input part, a gain amplification part, a pre-judgment logic part, a SAR-ADC part, an SS-ADC part, and a data processing part.

[0010] 1. The signal input part is used to input V ref,1 , V sig,1 , V ref,2 , V sig,2 in sequence.

[0011] 2. The gain amplification part is used to perform gain amplification on the output of the signal input part.

[0012] 3. The pre-judgment logic part is used to judge whether rough quantization is required after V sig,2 is input.

[0013] 4. The SAR-ADC part is used to: perform rough quantization based on the corresponding output of the gain amplification part to obtain corresponding 6-bit code values D ref,1 , V sig,1 , V ref,2 after V ref,1 <5:0>, D sig,1 <5:0>, D ref,2 <5:0>; perform corresponding operations according to the judgment result of the pre-judgment logic part after V sig,2 is input;

[0014] Among them, if it is judged that rough quantization is not required, then retain D sig,1 <5:0> as the corresponding 6-bit code value D sig,2 of V sig,2 <5:0>; otherwise, perform rough quantization based on the corresponding output of the gain amplification part to obtain the corresponding 6-bit code value D sig,2 <5:0>.

[0015] 5. The SS-ADC part is used to, after the SAR-ADC part completes rough quantization on V ref,n , V sig,n , based on V ref,n , V sig,nPerform digital-related multi-sampling for fine quantization to obtain a 9-bit code value E n <8:0>.

[0016] 6. The data processing unit is used for: for D ref,n <5:0>, D sig,n <5:0> perform digital-related double-sampling to obtain a 6-bit coarse quantization result F n <5:0>, based on D sig,n <5:0> the highest bit D sig,n <0> for E n <8:0> perform conditional multi-sampling selection to obtain a 6-bit fine quantization result F n <11:6>;

[0017] Among them, F n <5:0>, F n <11:6> that is, it constitutes F n <11:0>.

[0018] The implementation of this SAR-SS type ADC circuit with pre-judgment logic is based on the method or process of the embodiment of the present disclosure.

[0019] In a second aspect, the present invention discloses a SAR-SS type ADC module with pre-judgment logic, which adopts the layout of a SAR-SS type ADC circuit with pre-judgment logic as disclosed in the first aspect.

[0020] The implementation of this SAR-SS type ADC module with pre-judgment logic is based on the method or process of the embodiment of the present disclosure.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. On the basis of digital-related multi-sampling, the present invention adopts a SAR-SS hybrid architecture to decompose the 12-bit quantization of two columns of pixel signals {V ref,n}, {V sig,n} into coarse quantization by the SAR-ADC unit and fine quantization by the SS-ADC unit, which improves the overall quantization speed of the ADC while achieving low noise, and has lower power consumption than the traditional CMSADC using a single architecture SS type ADC.

[0023] 2. The circuit of the present invention is provided with a pre-judgment logic unit to judge whether it is necessary to perform coarse quantization on the pixel readout signal V sig,2 to reduce the unnecessary time and power consumption of coarse quantization, and further improve the overall speed and power consumption of the ADC. Description of the Drawings

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 It is a schematic structural diagram of the SAR-SS type ADC circuit with pre-judgment logic provided by the present invention;

[0026] Figure 2 For Figure 1 It is a circuit connection diagram of the signal input part and the gain amplification part in

[0027] Figure 3 For Figure 1 It is a circuit connection diagram of the SAR-ADC part in

[0028] Figure 4 For Figure 1 It is a circuit connection diagram of the SS-ADC part in

[0029] Figure 5 For Figure 4 It is a circuit connection diagram of the ramp generator RAMP_generator in

[0030] Figure 6 For Figure 1 It is a circuit connection diagram of the pre-judgment logic part in

[0031] Figure 7 For Figure 1 It is a schematic diagram of pre-judgment logic selection for the SAR-SS type ADC circuit of

[0032] Figure 8 For Figure 1 It is a circuit diagram of the data processing part in

[0033] Figure 9 For Figure 1 The result of simulating the SAR-SS type ADC circuit of Figure 1 ;

[0034] Figure 10 For Figure 1 The result of simulating the SAR-SS type ADC circuit of Figure 2 ;

[0035] Figure 11 For Figure 1 The result of simulating the SAR-SS type ADC circuit of Figure 3 。 Detailed implementation manners

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] It should be noted that when a component is referred to as being "installed on" another component, it can be directly on the other component or there may also be an intermediate component. When a component is considered to be "disposed on" another component, it can be directly disposed on the other component or there may be an intermediate component at the same time. When a component is considered to be "fixed to" another component, it can be directly fixed to the other component or there may be an intermediate component at the same time.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0039] Embodiment 1

[0040] Embodiment 1 of the present invention provides a SAR-SS type ADC circuit with a pre-judgment logic.

[0041] First of all, it should be noted that the purpose of this SAR-SS type ADC circuit is to perform 12-bit quantization on two columns of pixel signals {V ref,n}, {V sig,n} to obtain a 12-bit quantization result F ref,n , V sig,n with a range of [V n <11:0>.

[0042] Among them, {V ref,n} represents one column of pixel reset signals; {V sig,n} represents one column of pixel readout signals.

[0043] [V ref,n , V sig,n represents a pixel group composed of one pixel reset signal and one pixel readout signal.

[0044] It should be noted that the number of components of the single-column pixel signal can theoretically be increased or decreased. For example, when n is taken as an integer greater than 2, but as the value of n increases, the processing speed of the entire row of pixels (i.e., the CIS frame rate) does not increase significantly. Therefore, in this Embodiment 1, the single-column pixel signal is selected to be composed of 2 signals (i.e., n ∈ {1, 2}, {V ref,n}, which is {V ref,1 , V ref,2}, {V sig,n}, which is {V sig,1 , V sig,2}), which can achieve a better balance between efficiency and area.

[0045] Next, refer to Figure 1 , which shows the structural schematic diagram of this SAR-SS type ADC circuit. According to the function division, this SAR-SS type ADC circuit includes: a signal input part, a gain amplification part, a pre-judgment logic part, a SAR-ADC part, an SS-ADC part, and a data processing part.

[0046] The following is an introduction to each part (considering that the pre-judgment logic part, the SAR-ADC part, and the SS-ADC part are closely related, they will be introduced together):

[0047] 1. The signal input part is used to input V ref,1 , V sig,1 , V ref,2 , V sig,2 in sequence.

[0048] Refer to Figure 2 , the signal input part can be designed to include: 2 input switches S P1 ~ S P2 ;

[0049] The first end of S P1 is connected to {V ref,n}, and the second end is connected to the input end of the gain amplification part;

[0050] The first end of S P2 is connected to {V sig,n}, and the second end is connected to the input end of the gain amplification part.

[0051] In this way, by controlling S P1 , S P2 , they are made to close successively and not simultaneously.

[0052] Specifically, first turn on S P1 , turn off S P2 , and V ref,1 is input through the signal input part and output to the gain amplification part; then turn on S P2 , turn off S P1, V sig,1 That is, it passes through the signal input section and is output to the gain amplification section; V ref,2 and V sig,2 The input control is similar and will not be repeated here.

[0053] Of course, the signal input section can also adopt other circuit designs, but it needs to meet the above-mentioned signal input requirements.

[0054] 2. The gain amplification section is used to amplify the output of the signal input section.

[0055] Refer to Figure 2 , the gain amplification section can be designed to include: 1 high-gain operational amplifier Amp, 1 fixed capacitor C H1 , 1 programmable capacitor C H2 , 1 switch S C .

[0056] The first end of C H2 serves as the input end of the gain amplification section, and the second end is connected to the first end of C H1 , the first end of S C , and the input end of Amp;

[0057] The second end of C H1 , the second end of S C are connected to the output end of Amp;

[0058] The output end of Amp serves as the output end of the gain amplification section, which is used to output the gain signal Vin.

[0059] Specifically, when S C is closed, the signal is reset; when S C is open, the signal is amplified.

[0060] Among them, the gain amplification multiple of the gain amplification section k is positively correlated with C H2 / C H1 . Then, by adjusting C H2 to change its capacitance value, k can be adjusted to reduce the influence of noise on the subsequent signal quantization.

[0061] Then, for Vin, it undergoes four stages of changes:

[0062] After V ref,1 is input, Vin is k *V ref,1 ;

[0063] After V sig,1 is input, Vin is k *V sig,1;

[0064] After the V ref,2 input, Vin is k *V ref,2 ;

[0065] After the V sig,2 input, Vin is k *V sig,2 .

[0066] Of course, the gain amplification unit can also adopt other circuit designs, but it needs to meet the above signal gain requirements.

[0067] 3. For the pre-judgment logic unit, SAR-ADC unit, and SS-ADC unit, generally speaking:

[0068] The pre-judgment logic unit is used to judge whether coarse quantization is needed after the V sig,2 input;

[0069] The SAR-ADC unit is used for: after the V ref,1 , V sig,1 , V ref,2 input, performing coarse quantization based on the corresponding output of the gain amplification unit to obtain the corresponding 6-bit code values D ref,1 <5:0>, D sig,1 <5:0>, D ref,2 <5:0>; after the V sig,2 input, performing corresponding operations according to the judgment result of the pre-judgment logic unit;

[0070] The SS-ADC unit is used to, after the SAR-ADC unit completes coarse quantization of V ref,n , V sig,n , performing digital correlated multi-sampling based on V ref,n , V sig,n to perform fine quantization to obtain the 9-bit code value E n <8:0>.

[0071] Then there is:

[0072] When Vin is k *V ref,1 , coarse quantization will be performed first, and then fine quantization based on digital correlated multi-sampling will be performed;

[0073] When Vin is k *V sig,1 , coarse quantization will be performed first, and then fine quantization based on digital correlated multi-sampling will be performed;

[0074] When Vin is k *V ref,2 , coarse quantization will be performed first, and then fine quantization based on digital correlated multi-sampling will be performed;

[0075] When Vin is k *V sig,2 , it will first determine whether coarse quantization is required, and then perform corresponding operations according to the determination result (if it is determined that coarse quantization is not required, then retain D sig,1 <5:0> as V sig,2 The corresponding 6-bit code value D sig,2 <5:0>; otherwise, perform coarse quantization based on the output of the gain amplification unit to obtain the corresponding 6-bit code value D sig,2 <5:0>), and then perform fine quantization based on digital correlation multiple sampling.

[0076] That is to say, if a quantization period of Vin is divided into stages, it can be divided into: a pre-judgment logic selection stage (which must be performed when Vin is k *V sig,2 ), a coarse quantization stage (which must be performed when Vin is k *V ref,1 , k *V sig,1 , k *V ref,2 ), and whether to perform it is determined according to the result of the pre-judgment logic selection stage when Vin is k *V sig,2 ), a fine quantization stage (which must be performed when Vin is k *V ref,1 , k *V sig,1 , k *V ref,2 , k *V sig,2 ).

[0077] 301. First, introduce the SAR-ADC unit:

[0078] Refer to Figure 3 , the SAR-ADC unit performs 6-bit coarse quantization, and it can be designed to include: a SAR logic unit SAR-logic, a signal gating unit MUX, a capacitor array unit, a switch array unit, one comparator COMP0, one latch Latch, and one switch S1.

[0079] The first end of S1 is connected to the control voltage V CM , and the second end is connected to the output voltage V DAC .

[0080] Among them, when the gain amplification unit performs gain amplification, S1 is closed; when quantization starts, S1 is opened.

[0081] The negative input terminal of COMP0 is connected to VDAC , the positive input terminal is connected to Vin, the output terminal is used to output comparison signals VP and VN, and the control terminal is connected to the timing signal CLK_REAL.

[0082] Among them, COMP0 uses a dynamic comparator, which only adopts a design with a single-stage preamplifier.

[0083] The capacitor array part includes: 7 capacitors C connected in parallel G ~C A ; The upper plates of C G ~C A are connected to V DAC .

[0084] Among them, the capacitance ratio of C G ~C A is 1:1:2:4:8:16:32; C G is a redundant capacitor.

[0085] The switch array part includes: 18 switches S A0 ~S F0 , S A1 ~S F1 , S A2 ~S F2 ;

[0086] Among them, the first end of switch S σ0 , the first end of switch S σ1 , and the first end of switch S σ2 are connected to the lower plate of capacitor C σ ; The second end of S σ0 is connected to V CM ; The second end of S σ1 is connected to the control voltage V H ; The second end of S σ2 is connected to the control voltage V L ; σ ∈ [A, B, C, D, E, F].

[0087] The control terminal of SAR-logic is connected to VP and VN, the first output terminal is used to output the timing signal CLK, and the second output terminal is used to output the control signal Ctrl for the switch array part and MUX.

[0088] It should be noted that SAR-logic adopts asynchronous SAR logic. Since there are 18 switches in the switch array part, Ctrl actually includes 18 corresponding switch control signals (i.e., Ctrl_S A0 ~Ctrl_S F0 , Ctrl_S A1 ~Ctrl_S EF1 , Ctrl_S A2 ~Ctrl_SF2 ), two strobe control signals (i.e., Ctrl_mux2~Ctrl_mux3), to control S A0 ~S F0 , S A1 ~S F1 , S A2 ~S F2 , mux2~mux3 respectively.

[0089] The input end of the Latch is connected to the output end three of the SAR-logic, and the output end is used to output the 6-bit code value obtained by coarse quantization.

[0090] The MUX includes one 2-to-1 multiplexer mux2 and one 3-to-1 multiplexer mux3; one input end of mux2 is connected to V CM , and the other input end is connected to the ramp signal V ramp ; one input end of mux3 is connected to the output end of mux2, another input end is connected to V H , and the third input end is connected to V L , and the output end is connected to the lower board of C G .

[0091] It should be noted that during coarse quantization, mux2 selects V CM ; during fine quantization, mux2 selects V ramp .

[0092] Generally speaking, the capacitor array part cooperates with the switch array part and the MUX to adjust V DAC ; the SAR-logic controls the switch array part based on the comparison result of COMP0.

[0093] 302. Next, introduce the SS-ADC part:

[0094] Refer to Figure 4 , the SS-ADC part performs 6-bit fine quantization, and it can be designed to include: one comparator COMP1, one counter Counter, and one ramp generator RAMP_generator.

[0095] The negative input end of COMP1 is connected to V DAC , the positive input end is connected to Vin, and the output end is used to output the control signal V COM .

[0096] Among them, COMP1 adopts a static comparator, which is designed with a three-stage preamplifier structure, and the offset voltage is reduced by the method of input offset cancellation.

[0097] The input end of Counter is connected to V COM .

[0098] It should be noted that although 6-bit fine quantization is performed by the SS-ADC section, a 3-bit redundant counter is used to compensate for the possible errors between the coarse and fine quantizations. Therefore, Counter is a 9-bit bidirectional counter, which is used to count up and down Vin to obtain E n <8:0>.

[0099] Among them, Counter counts down when Vin is k *V ref,1 and counts up when Vin is k *V sig,1 to obtain E1<8:0>; Counter counts down when Vin is k *V ref,2 and counts up when Vin is k *V sig,2 to obtain E2<8:0>.

[0100] Then, the redundant 3 bits of E n <8:0> include: one sign bit at the highest bit (the 9th bit), one redundant bit at the second highest bit (the 8th bit), and one redundant bit at the third highest bit (the 7th bit).

[0101] That is to say, the SS-ADC section adopts the method of digital correlated multi-sampling, which can reduce the influence of noise.

[0102] RAMP_generator is used to generate V ramp . RAMP_generator is a 6-bit ramp generator, and its design can be as shown in Figure 5 and includes: a conversion circuit section, a current source section, a differential switch section, and an operational amplifier array section.

[0103] Specifically, the conversion circuit section includes: 1 resistor R and 1 resistor R dummy ; the second end of R is connected to the second end of R dummy ; the first end of R is used as the output end of RAMP_generator to output V ramp .

[0104] The current source section includes: 17 current sources I0~I 16 connected in parallel; among them, the current ratio of I0~I 16 is 1:2:4:4:4:4:4:4:4:4:4:4:4:4:4:4:4. In other words, I0 uses an i0 current source (i0 represents the standard current), I1 uses a 2i0 current source, and I2~I 16 all use 4i0 current sources.

[0105] The differential switch section includes: 34 switches S W,0 ~S W,33 ; Among them, I x By S W,x Connect the first end of R through S W,y Connect R dummy The first end of ; x∈{0,2,4,…,32}, y∈{1,3,5,…,33}.

[0106] The operational amplifier array includes: 1 operational amplifier A0, 1 capacitor C x , 1 NMOS tube N1; the negative input terminal of A0 is connected to the reference voltage V th , the positive input terminal is connected to C x The first end of R, the second end of R, the drain of N1, and the output end is connected to C x The second end of N1 and the gate of N1; the source of N1 is grounded.

[0107] The RAMP_generator of the above structure adopts a combination of binary coding and thermometer coding, which can combine the advantages of low complexity and small area of binary coding circuit with high linearity and small burrs of thermometer decoding: the lower 2 bits adopt binary coding to reduce the number of thermometer coding bits, thereby reducing the area of the thermometer coding circuit, and at the same time add an inverter chain to transmit the input signal to ensure delay synchronization; the upper 4 bits adopt thermometer coding to reduce the noise generated by too many flipping bits during the carry process; and A0 and N1 are used to form a negative feedback circuit, and the negative feedback principle of the operational amplifier is used to clamp the initial voltage of the ramp to a fixed value V th , so that V ramp V th As the starting point, gradually rise.

[0108] Of course, RAMP_generator can also use other circuit designs, but it is necessary to ensure that V ramp signal stability.

[0109] 303. Then introduce the pre-judgment logic part:

[0110] See also Figure 6 The pre-judgment logic part can be designed to include: 2 latches LATCH1~LATCH2, 1 inverter INV, 1 exclusive OR gate XOR, 1 AND gate AND, and 1 two-to-one selector mux1.

[0111] The input terminals of LATCH1 and LATCH2 are connected to V COM ;

[0112] The output terminal of LATCH1 is used to output the control signal PRE1. The output terminal of LATCH2 is connected to the input terminal of INV, and the output terminal of INV is used to output the control signal PRE2;

[0113] One input terminal of AND is connected to PRE1, the other input terminal is connected to PRE2, and the output terminal is used to output the selection signal PRE;

[0114] One input terminal of XOR is connected to PRE, and the other input terminal is connected to CLK;

[0115] One input terminal of mux1 is connected to the output terminal of XOR, the other input terminal is connected to CLK, and the output terminal is used to output CLK_REAL.

[0116] Refer to the above description. The pre-judgment logic unit works after the V sig,2 input. LATCH1 latches the C G When the lower substrate is connected to V H the comparison result of COMP1 and serves as PRE1. LATCH2 latches the C G When the lower substrate is connected to V L the comparison result of COMP1 and takes its inverted value through INV as PRE2. PRE1 and PRE2 go through AND to generate PRE.

[0117] If PRE is at a high level, it means PRE1 is at a high level and PRE2 is at a low level. Then, the D sig1 <5:0> is used as D sig2 <5:0>, and the value of V sig,2 is also within the fine quantization range. Therefore, the coarse quantization process can be skipped;

[0118] Since the SAR-logic adopts an asynchronous SAR logic, it relies on the CLK (also known as the asynchronous comparator clock signal) generated by the asynchronous SAR logic. When starting quantization, CLK is at a low level; if the pre-judgment logic unit determines that coarse quantization is not required and PRE is at a high level, PRE is XORed with CLK to obtain a high-level CLK_REAL, which makes COMP0 unable to compare, and the coarse quantization of V sig,2 no longer proceeds. Of course, if the levels of PRE1, PRE2, and PRE are not the cases discussed above, then V sig,2 needs to be coarsely quantized using the SAR-ADC unit.

[0119] It should be noted that the power consumption of the SAR-ADC unit mainly comes from switch switching and DAC charge transfer, and it naturally has a power consumption advantage over the SS-ADC unit. Moreover, after using the pre-judgment logic unit, the power consumption of the SAR-ADC unit can be further saved, and the quantization time of the entire ADC can be shortened.

[0120] In addition, a single-architecture SS-type ADC requires approximately 512 clock cycles for 12-bit quantization, but this SAR-SS type ADC circuit only takes approximately 266 clock cycles, nearly doubling the A / D conversion speed.

[0121] So far, based on the above-mentioned pre-judgment logic unit, SAR-ADC unit, and SS-ADC unit, the quantization period will be specifically described as follows:

[0122] (1) In the coarse quantization stage:

[0123] During the coarse quantization of Vin (i.e., when Vin is k *V ref,1 or k *V sig,1 or k *V ref,2 ), V DAC is connected to COMP0 and compared with Vin, and VP and VN are output to SAR-logic. The pre-judgment logic unit does not work at this time.

[0124] On the one hand, SAR-logic adjusts the switch array unit based on the asynchronous SAR logic according to VP and VN, and then adjusts V DAC .

[0125] The specific method is as follows: The initial state of the switch array unit is that S A0 ~S F0 are closed, and S A1 ~S F1 , S A2 ~S F2 are open; SAR-logic generates Ctrl according to VP and VN, making S A0 open, S A1 or S A2 closed, and the other switches in the switch array unit remain in their previous states unchanged. The value of V DAC changes, and VP and VN also change; SAR-logic will first generate a new Ctrl according to the new VP and VN to control S B0 open, S B1 or S B2 closed, and the other switches in the switch array unit remain in their previous states unchanged; and so on, until S F0 ~S F2 complete the gating; after S F0 ~S F2 complete the gating, SAR-logic will first generate a new Ctrl according to the new VP and VN to control the MUX switch to connect V CM or V H or V L .

[0126] On the other hand, the Latch latches the output signal of the SAR-logic and outputs a 6-bit code value. It should be noted that if the 6-bit code value here is represented as D n <5:0>, then there is:

[0127] When Vin is k *V ref,1 , D n <5:0> is D ref,1 <5:0>;

[0128] When Vin is k *V sig1 , D n <5:0> is D sig,1 <5:0>;

[0129] When Vin is k *V ref,2 , D n <5:0> is D ref,2 <5:0>;

[0130] When Vin is k *V sig,2 , D n <5:0> is D sig,2 <5:0>.

[0131] (2) In the fine quantization stage:

[0132] The lower plate of C0 is connected to V ramp (the initial value of V ramp is V th , and V th is usually set to be equal to V L ), then at the beginning of fine quantization, V DAC is less than Vin; when V ramp is connected, V DAC increases by V ramp / 64 per clock cycle. V DAC is connected to COMP1 and compared with Vin, and then V COM is output to drive the Counter to start counting for digital correlated multi-sampling until V COM reverses, the Counter stops counting, and the count value in it is E n <8:0>.

[0133] (3) In the pre-judgment logic selection stage:

[0134] To more intuitively understand the working mode of this stage, see Figure 7, which shows several situations:

[0135] At time T p0 , S1 is disconnected, and S A1 ~S F1 , S A2 ~S F2 maintain the switched state after coarse quantization of the previous bit unchanged;

[0136] At time T p1 , the lower plate of C G is connected to V H ;

[0137] At time T p2 , the lower plate of C G is connected to V L ;

[0138] At time T p1 , T p2 , V DAC , Vin are compared in COMP1: The comparison result at T p1 is latched and used as PRE1; The comparison result at T p2 is latched and inverted to be used as PRE2; PRE1 and PRE2 go through AND to generate PRE.

[0139] If PRE is 1, corresponding to the situation in the (a) area in Figure 7 , pre-judgment can be performed, and S A1 ~S F1 , S A2 ~S F2 maintain the switched state after coarse quantization of the previous bit and no longer perform coarse quantization on V sig,2 ;

[0140] For other situations such as those shown in the (b) area and (c) area in Figure 7 , coarse quantization of V p3 needs to be performed at time T sig,2 ;

[0141] 4. The data processing unit is used to: perform digital correlated double sampling on D ref,n <5:0>, D sig,n <5:0> to obtain a 6-bit coarse quantization result F n <5:0>, and based on the highest bit D sig,n <5:0> in D sig,n <0> to perform conditional multi-sampling selection on E n <8:0> to obtain a 6-bit fine quantization result F n <11:6>.

[0142] Among them, F n<5:0>, F n <11:6> That is, it forms F n <11:0>.

[0143] That is to say, in the data processing unit, a digital correlation double sampling and conditional multi-sampling combination method is adopted, which can effectively reduce noise.

[0144] See Figure 8 , the data processing unit can be designed to include: 1 subtractor Subtractor, 3 latches LATCH3 to LATCH5, and 1 adaptive multi-sampling unit.

[0145] Among them, LATCH3 is used to latch D sig,n <5:0>; LATCH4 is used to latch D ref,n <5:0>.

[0146] Such as Figure 8 As shown, the input terminal of LATCH3 is connected to the output terminal of Latch, and the first output terminal is used to output D sig,n <5:0>, and the second output terminal is used to output D sig,n <0>. The input terminal of LATCH4 is connected to the output terminal of Latch.

[0147] Subtractor is used to perform subtraction operations on the outputs of LATCH3 and LATCH4, and perform sign correction on the subtraction result according to the highest bit E n <8:0> of E n <8> to obtain F n <5:0>.

[0148] Such as Figure 8 As shown, the first input terminal of Subtractor is connected to the output terminal of LATCH3, the second input terminal is connected to the output terminal of LATCH4, and the third input terminal is connected to the second output terminal of Counter (the first output terminal of Counter is used to output E n <8:0> of the highest bit E n <8>).

[0149] It should be noted that Subtractor first subtracts the output of LATCH3 (i.e., D sig,n <5:0>) from the output of LATCH4 (i.e., D ref,n <5:0>) to obtain the subtraction result. Considering that the subtraction result may be negative, a sign bit E n <8> is introduced: if E n <8> is 0, the subtraction result remains unchanged and is used as F n <5:0>; if E nIf <8> is 1, add 1 to the subtraction result (which is 000001 in binary) and use it as F n <5:0>.

[0150] The adaptive multi-sampling unit is used to generate a selection signal choose according to D sig,n <0> to implement Counter and then perform conditional multi-sampling based on choose.

[0151] As Figure 8 shown, the input end of the adaptive multi-sampling unit is connected to the first output end of LATCH3, and the output end is connected to the control end of Counter. The first output end of Counter is used to output E_6.

[0152] Specifically:

[0153] If D sig,n <0> is 1, Counter performs 1 sampling count and outputs the sampling count result as E_6, that is, it is equivalent to using E n <5:0> (that is, the first bit to the sixth bit of E n <8:0>) as E_6.

[0154] If D sig,n <0> is 0, Counter performs 4 sampling counts and takes the average of the sampling count results as E_6 for output, that is, it is equivalent to using E n <7:2> (that is, the third bit to the eighth bit of E n <8:0>) as E_6.

[0155] LATCH5 is used to latch E_6 and convert it into F n <11:6>.

[0156] As Figure 8 shown, the input end of LATCH5 is connected to the first output end of Counter.

[0157] Specifically, since both E_6 and F n <11:6> are 6 bits, then synchronously shifting E_6 by 6 bits gives F n <11:6>.

[0158] Then, F n <11:6> is the high 6 bits, F n <5:0> is the low 6 bits, and the F n <11:0> composed of both is the 12-bit quantization result of [V ref,n ,V sig,n .

[0159] Simulation verification

[0160] To illustrate the effect of this SAR-SS type ADC circuit, circuit simulation was carried out on it, and the results are as follows Figures 9 - 11 .

[0161] Refer to Figure 9 , which shows the differential non-linearity error (DNL) of this SAR-SS type ADC circuit; refer to Figure 10 , which shows the integral non-linearity error (INL) of this SAR-SS type ADC circuit.

[0162] It can be seen that DNL and INL basically fluctuate within ±0.5 LSB, indicating that the quantization accuracy of this SAR-SS type ADC circuit meets the requirements and no further calibration is required.

[0163] Refer to Figure 11 , which shows the noise situation of this SAR-SS type ADC circuit. It can be seen that the noise of this SAR-SS type ADC circuit is reduced to 122.503 μVrms, indicating that this SAR-SS type ADC circuit achieves the effect of low noise.

[0164] Embodiment 2

[0165] This Embodiment 2 discloses a SAR-SS type ADC module with pre-judgment logic, which adopts the layout of a SAR-SS type ADC circuit with pre-judgment logic disclosed in Embodiment 1. The mode of being packaged into a unit is more conducive to the popularization and application of the above circuit.

[0166] The SAR-SS type ADC module with pre-judgment logic includes: a signal input module (i.e., corresponding to the signal input part), a gain amplification module (i.e., corresponding to the gain amplification part), a pre-judgment logic module (i.e., corresponding to the pre-judgment logic part), a SAR-ADC module (i.e., corresponding to the SAR-ADC part), an SS-ADC module (i.e., corresponding to the SS-ADC), and a data processing module (i.e., corresponding to the data processing part). For the specific circuit distribution, refer to Embodiment 1 and will not be repeated here.

[0167] This Embodiment 2 also synchronously discloses a CMOS image sensor, which adopts the above SAR-SS type ADC module with pre-judgment logic.

[0168] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0169] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A SAR-SS type ADC circuit with a pre-judgment logic, characterized in that, It is used to compare the pixel signals of two columns {V ref,n }、{V sig,n }12bit quantization is performed to obtain [V ref,n ,V sig,n ]'s 12-bit quantization result F n <11:0>; n∈{1,2}; It includes: A signal input unit for sequentially inputting V ref,1 , V sig,1 , V ref,2 , V sig,2 ; A gain amplification unit, which is used to amplify the output of the signal input unit to obtain a gain signal Vin; A pre-judgment logic unit, which is used to judge whether coarse quantization is required after the V sig,2 input; SAR-ADC section, which is used to: ref,1 、V sig,1 、V ref,2 After input, the corresponding output Vin of the gain amplifier is coarsely quantized to obtain the corresponding 6-bit code value D ref,1 <5:0>, D sig,1 <5:0>, D ref,2 <5:0>; at V sig,2 After input, the corresponding operation is performed according to the judgment result of the pre-judgment logic unit; if it is judged that coarse quantization is not necessary, D is retained. sig,1 <5:0> as V sig,2 The corresponding 6-bit code value D sig,2 <5:0>; otherwise, the corresponding 6-bit code value D is obtained by performing coarse quantization based on the output Vin of the gain amplifier. sig,2 <5:0>; The SS-ADC section is used to perform digital correlated multi-sampling based on V ref,n and V sig,n after the SAR-ADC section completes coarse quantization, and to finely quantize to obtain a 9-bit code value E ref,n and V sig,n <8:0>; n <8:0>; Among them, the SS-ADC section includes: 1 comparator COMP1, 1 counter Counter, and 1 ramp generator RAMP_generator; the negative input terminal of COMP1 is connected to the output voltage V of the SAR-ADC section DAC , the positive input terminal is connected to Vin, and the output terminal is used to output the control signal V COM ; the input terminal of Counter is connected to V COM ; among them, Counter is a 9-bit bidirectional counter, which is used to count up and down Vin to obtain E n <8:0>; RAMP_generator is used to generate a ramp signal V ramp ; and A data processing unit, which is configured to: process D ref,n <5:0> and D sig,n <5:0> through digital-related dual sampling to obtain a 6-bit coarse quantization result F n <5:0>, and based on the highest bit D sig,n <0> in D sig,n <0> of E n <8:0> through conditional multi-sampling selection to obtain a 6-bit fine quantization result F n <11:6>; wherein, F n <5:0> and F n <11:6> together constitute F n <11:0>.

2. The SAR-SS type ADC circuit with a pre-judgment logic according to claim 1, characterized in that The signal input section includes: two input switches S P1 ~S P2 ; S P1 The first end of ref,n is connected to {V, and the second end is connected to the input end of the gain amplification unit; S P2 The first end of which is connected to {V sig,n}, and the second end is connected to the input end of the gain amplification unit; Among them, S P1 and S P2 are not closed simultaneously and are closed sequentially.

3. The SAR-SS type ADC circuit with a pre-judgment logic according to claim 1, characterized in that, The gain amplification section includes: one high-gain operational amplifier Amp, one fixed capacitor C H1 , one programmable capacitor C H2 , one switching switch S C ; C H2 The first end of is used as the input end of the gain amplification part, and the second end is connected to C H1 The first end of, S C The first end of, the input end of Amp; C H1 The second end of, S C The second end of is connected to the output end of Amp; The output terminal of Amp serves as the output terminal of the gain amplification unit for outputting the gain signal Vin.

4. A SAR-SS type ADC circuit with a pre-judgment logic according to claim 1, characterized in that, The SAR-ADC unit includes: a SAR logic unit SAR-logic, a signal gating unit MUX, a capacitor array unit, a switch array unit, one comparator COMP0, one latch Latch, and one switching switch S1; The first end of S1 is connected to the control voltage V CM , and the second end is connected to the output voltage V DAC ; The negative input terminal of COMP0 is connected to V DAC , the positive input terminal is connected to Vin, the output terminal is used to output comparison signals VP and VN, and the control terminal is connected to the timing signal CLK_REAL; The capacitor array section includes: seven capacitors C connected in parallel G ~C A ; the upper plates of C G ~C A are connected to V DAC ; The switch array section includes: 18 switches S A0 ~S F0 、S A1 ~S F1 、S A2 ~S F2 ; among them, the first ends of switch S σ0 , switch S σ1 , and switch S σ2 are connected to the lower board of C σ ; the second end of S σ0 is connected to V CM ; the second end of S σ1 is connected to the control voltage V H ; the second end of S σ2 is connected to the control voltage V L ; σ ∈ [A, B, C, D, E, F]; The control terminal of SAR-logic is connected to VP and VN. One output terminal is used to output a timing signal CLK, and the other output terminal is used to output a control signal Ctrl for the switch array unit and MUX; The input terminal of Latch is connected to the third output terminal of SAR-logic, and the output terminal is used to output a 6-bit code value obtained by coarse quantization; The MUX includes a two-to-one multiplexer mux2 and a three-to-one multiplexer mux3; one input terminal of mux2 is connected to V CM , and the other input terminal is connected to the ramp signal V ramp ; one input terminal of mux3 is connected to the output terminal of mux2, another input terminal is connected to V H , and the third input terminal is connected to V L , and the output terminal is connected to the lower board of C G . Among them, when performing coarse quantization, mux2 selects and enables V CM ; when performing fine quantization, mux2 selects and enables V ramp .

5. A SAR-SS type ADC circuit with a pre-judgment logic according to claim 4, characterized in that, RAMP_generator includes: a conversion circuit unit, a current source unit, a differential switch unit, and an operational amplifier array unit; The conversion circuit section includes: one resistor R, one resistor R dummy ; The second end of R is connected to the second end of R dummy ; The first end of R serves as the output end of the RAMP_generator for outputting V ramp ; The current source section includes 17 current sources I0 to I connected in parallel 16 ; The differential switch section includes: 34 switches S W,0 ~S W,33 ; Among them, I x By S W,x Connect the first end of R through S W,y Connect R dummy The first end of ; x∈{0,2,4,…,32}, y∈{1,3,5,…,33}; The operational amplifier array section includes: one operational amplifier A0, one capacitor C x , and one NMOS transistor N1; the negative input terminal of A0 is connected to the reference voltage V th , the positive input terminal is connected to the first terminal of C x , the second terminal of R, and the drain of N1, and the output terminal is connected to the second terminal of C x , the gate of N1; the source of N1 is grounded.

6. The SAR-SS type ADC circuit with a pre-judgment logic according to claim 4, characterized in that, The pre-judgment logic unit includes: two latches LATCH1 to LATCH2, one inverter INV, one exclusive OR gate XOR, one AND gate AND, and one two-to-one multiplexer mux1; The input terminals of LATCH1 and LATCH2 are connected to V COM ; The output terminal of LATCH1 is used to output a control signal PRE1. The output terminal of LATCH2 is connected to the input terminal of INV, and the output terminal of INV is used to output a control signal PRE2; One input terminal of AND is connected to PRE1, the other input terminal is connected to PRE2, and the output terminal is used to output a selection signal PRE; One input terminal of XOR is connected to PRE, and the other input terminal is connected to CLK; One input terminal of mux1 is connected to the output terminal of XOR, the other input terminal is connected to CLK, and the output terminal is used to output CLK_REAL.

7. The SAR-SS type ADC circuit with a pre-judgment logic according to claim 4, characterized in that, The data processing unit includes: one subtractor Subtractor, three latches LATCH3 to LATCH5, and one adaptive multi-sampling unit; LATCH3 is used to latch D sig,n <5:0>; LATCH4 is used to latch D ref,n <5:0>; The Subtractor is used to perform a subtraction operation on the outputs of LATCH3 and LATCH4, and to perform a sign correction on the subtraction result according to the highest bit E n <8:0> of E n <8> to obtain F n <5:0>; The adaptive multi-sampling unit is used to generate a selection signal "choose" according to D sig,n <0> to implement a Counter and then perform conditional multi-sampling based on "choose". Among them, if D sig,n <0> is 1, Counter performs 1 sampling count and outputs the sampling count result as E_6; if D sig,n <0> is 0, Counter performs 4 sampling counts and takes the average value of the sampling count results as E_6 for output; LATCH5 is used to latch E_6 and convert it to F n <11:6>.

8. A SAR-SS type ADC circuit with a pre-judgment logic according to claim 7, characterized in that, The input terminal of LATCH3 is connected to the output terminal of the Latch, and Output Terminal 1 is used to output D sig,n <5:0>, and Output Terminal 2 is used to output D sig,n <0>; The input terminal of LATCH4 is connected to the output terminal of Latch; The input terminal of the adaptive multi-sampling unit is connected to the first output terminal of LATCH3, and the output terminal is connected to the control terminal of Counter; One of the output terminals of the Counter is used to output E_6, and the second output terminal is used to output E n The highest bit E of <8:0> n <8>; One input terminal of Subtractor is connected to the output terminal of LATCH3, the second input terminal is connected to the output terminal of LATCH4, and the third input terminal is connected to the second output terminal of Counter; The input terminal of LATCH5 is connected to the first output terminal of Counter.

9. A SAR-SS type ADC module with a pre-judgment logic, characterized in that, Adopt the layout of a SAR-SS type ADC circuit with pre-judgment logic as described in any one of claims 1-8.

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