Flexible subchannel selection in shared communication channel

Abstract

The invention relates to flexible sub-channel selection in a shared communication channel. A system performs operations including storing a first value in a first memory location for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies to enable a sub-channel selection function; receiving a command directed to the memory device over the communication channel; in response to receiving the command, storing a second value in a second memory location, where the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location includes a preset value corresponding to a first component of the plurality of components of the memory device; and executing the command by the first component.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to flexible sub-channel selection in a shared communication channel. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] An embodiment of the present disclosure provides a memory device, comprising: a plurality of memory components, including a first memory component; and a processing device, which is operatively coupled to the plurality of memory components via a communication channel to perform an operation, the operation comprising: storing a first value in a first memory location of the first memory component, wherein the first memory location is used to select a subchannel among a plurality of subchannels of the communication channel, wherein each of the plurality of subchannels corresponds to one or more corresponding memory components among the plurality of memory components, wherein the first value specifies enabling a subchannel selection function; receiving a command directed to the memory device through the communication channel; in response to receiving the command, storing a second value specified by the command in a second memory location of the first memory component; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and executing the command by the first memory component.

[0004] Another embodiment of the present disclosure provides a method, comprising: storing, by a processing device, a first value in a first memory location of a first memory component among a plurality of memory components of a memory device, wherein the first memory location is used to select a subchannel among a plurality of subchannels in a communication channel, wherein each of the plurality of subchannels corresponds to one or more memory components among the plurality of memory components of the memory device, wherein the first value specifies enabling a subchannel selection function; receiving a command directed to the memory device through the communication channel; in response to receiving the command, storing a second value specified by the command in a second memory location of the first memory component; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and executing the command by the first memory component.

[0005] Yet another embodiment of the present disclosure provides a non-transitory computer-readable storage medium comprising instructions, which, when executed by a processing device, causes the processing device to perform operations comprising: storing a first value in a first memory location of a first memory component among a plurality of memory components of a memory device, wherein the first memory location is used to select a subchannel among a plurality of subchannels in a communication channel, wherein each of the plurality of subchannels corresponds to one or more memory components of the plurality of memory components of the memory device, wherein the first value specifies enabling a subchannel selection function; receiving a command directed to the memory device through the communication channel; in response to receiving the command, storing a second value specified by the command in a second memory location of the first memory component; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and executing the command by the first memory component. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example system with a flexible sub-channel selection feature according to some embodiments of the present disclosure is described.

[0009] Figure 3 Example registers for implementing flexible sub-channel selection according to some embodiments of the present disclosure are described.

[0010] Figure 4A and 4B Describe the use of some embodiments according to the present disclosure Figure 3 The registers described in implement an example of flexible subchannel selection.

[0011] Figure 5 is a flow chart of an example method of flexible sub-channel selection according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to flexible sub-channel selection in a shared communication channel. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0014] The memory device may include a plurality of memory cells. The memory cells are formed on a silicon wafer in an array of columns and rows. The memory device may further include conductive lines connected to respective ones of the memory cells, which are referred to as word lines and bit lines. The intersection of the bit lines and the word lines constitutes the address of the memory cell. A block refers to a unit of a memory device for storing data hereinafter and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a memory bank of a memory device so as to allow concurrent operations on each memory bank. The memory device may include a circuit system for performing concurrent memory page accesses of two or more memory banks. For example, a memory device may include a plurality of access line driver circuits and power circuits that may be shared by the memory banks of the memory device to facilitate concurrent access of pages (including different page types) of two or more memory banks. For ease of description, these circuits may generally be referred to as independent memory bank driver circuits. Depending on the storage architecture employed, data may be stored across memory banks (i.e., in stripe form). Thus, one request to read a data segment (eg, corresponding to one or more data addresses) may result in read operations being performed on two or more memory banks of a memory device.

[0015] For example, a memory command sent by a host system requests the memory subsystem to perform a memory access or other operation on a memory device contained therein. Memory commands can generally be classified into corresponding categories, such as read commands, write commands, erase commands, move commands, etc. Memory commands may include commands that trigger hard post-package repair, commands that trigger soft post-package repair, mode register write commands, mode register read commands, commands that change memory device functions or settings, etc. The memory subsystem controller may receive memory commands from a host system externally connected to the memory subsystem. The memory subsystem may execute the memory command to perform a memory access or other operation, and may store the results of the memory command for retrieval by the host system after the memory subsystem reports that the execution of the memory command is completed.

[0016] A memory component refers to at least a portion of a memory device. In certain embodiments, a memory subsystem uses a single controller to drive multiple memory components via a shared communication channel. Multiple memory components may be multiple parts of the same memory device, multiple partitions from different memory devices, or a combination thereof. This mechanism allows for better performance, such as a larger bandwidth. However, in some scenarios, the controller will send commands related only to one of those memory components to multiple memory components of a shared communication channel. This is especially true during post-package repair (PPR), where one memory component (e.g., a bare die) needs to be repaired, but commands for repair are sent to multiple memory components of a shared communication channel. In such cases, multiple memory components of a shared communication channel may be repaired unnecessarily, which wastes repair resources. Another example is a test flow process, where one memory component (e.g., a bare die) needs to be tested, but commands for testing are sent to multiple memory components of a shared communication channel.

[0017] Aspects of the present disclosure address the above and other deficiencies by implementing a subchannel selection (SCS) component that allows selection of a subchannel of a communication channel shared by multiple memory components. A "memory component" refers to at least one portion of a memory device (e.g., a group of memory cells, one or more pages, one or more blocks, one or more memory banks, or one or more dies, etc.). A "communication channel" refers to a logical connection for the transfer of information, such as a digital bit stream, from one or more transmitters to several receivers (i.e., multiple memory components) through a physical medium (e.g., a communication bus). Part or all of the SCS component may reside in a memory subsystem controller or a local controller in a memory device.

[0018] The subchannel selection functionality will enable commands transmitted over a communication channel to be executed by a memory component corresponding to the selected subchannel, rather than by multiple memory components sharing the communication channel. Specifically, the SCS component may utilize one or more registers on the memory component to select a subchannel among a set of subchannels of the communication channel, each of the set of subchannels corresponding to a respective memory component of a plurality of memory components. A "register" refers to a portion (e.g., a unit) of memory allocated to store data.

[0019] A multiplexing-based channel access method may allow several data streams or signals to share the same communication channel, and a subchannel in a communication channel refers to a logical connection for information transmission from one or several senders to one receiver (i.e., one memory component) through a shared physical medium. Each subchannel in a communication channel may be identified by a subchannel identifier, and thus, each subchannel identifier corresponds to a corresponding memory component. The subchannel identifier is programmed inside each memory component accessible via a subchannel. In such a case, a specific memory component is assigned to a specific subchannel represented by the programmed subchannel identifier.

[0020] In some implementations, each memory component has two registers: a mode register and a sub-channel register. The two registers can work together to indicate whether the corresponding memory component is supported, enabled, and selected for the sub-channel selection feature. Specifically, the mode register can be used to store three values, called a mode support parameter, a mode enable parameter, and a mode selection parameter, which are used to support, enable, and select the sub-channel selection feature of the corresponding memory component.

[0021] The mode support parameter is, for example, a bit flag indicating whether the memory component supports (ie, is equipped with) a subchannel selection feature. In some implementations, the value of the mode support parameter is preset during manufacture of the memory device, and the mode support parameter is readable during operation of the memory device.

[0022] The mode enable parameter is, for example, a bit flag indicating whether the sub-channel selection feature is enabled for the memory component. In some implementations, the SCS component may modify the value of the mode enable parameter to enable or disable the sub-channel selection feature during operation of the memory device. That is, the mode support parameter indicates whether the memory component is equipped with the sub-channel selection feature at the manufacturing stage, while the mode enable parameter indicates whether the sub-channel selection feature is enabled in a memory component (which is already equipped with the sub-channel selection feature).

[0023] The mode selection parameter is used to indicate whether a memory component is selected for use with the sub-channel selection feature. That is, the mode selection parameter indicates whether to select a memory component (which has been equipped and enabled with the sub-channel selection feature) among the memory components of the shared communication channel to execute a command received via the shared communication channel, rather than ignoring the received command. In some embodiments, the SCS component may set the value of the mode selection parameter to a default value indicating that the corresponding memory component is selected. After evaluating the other values ​​stored in the two registers, as described in detail below, the SCS component may modify the value of the mode selection parameter to indicate that the corresponding memory component is not selected.

[0024] The subchannel register may be used to store two values ​​referred to as a subchannel identifier and a subchannel selection parameter, which are used to match the subchannel selection parameter with the subchannel identifier to identify a selected subchannel and a corresponding memory component.

[0025] The subchannel identifier identifies the subchannel assigned to the memory component. The subchannel identifier of the memory component may be preset during the manufacture of the memory device, indicating that the memory component corresponds to the subchannel identifier and that the subchannel identifier is readable during the operation of the memory device. In some embodiments, each memory component is assigned a unique subchannel identifier. In some embodiments, two or more memory components are assigned to the same subchannel identifier, and in such cases, memory components with the same subchannel identifier may be considered a group with respect to whether to execute a command or ignore a command. In some embodiments, the total number of subchannel identifiers that may be assigned to memory components is greater than the total number of memory components, and in such cases, additional memory components may be added to support flexibility in the number of memory components.

[0026] The subchannel selection parameters are used to identify valid (i.e., selected) subchannels, and the memory component has the subchannel selection feature equipped and enabled. In such cases, the memory component assigned to the valid (i.e., selected) subchannel will execute the issued command; the memory component assigned to the non-valid (i.e., unselected) subchannel will ignore the issued command. In some embodiments, the memory component may receive a command specifying a specific subchannel and write the specific subchannel information to the subchannel selection parameters. The SCS component may compare the subchannel selection parameters with the subchannel identifier. Based on this comparison, the mode selection parameters may be set.

[0027] In the event that the memory component is equipped with and has enabled the subchannel selection feature, in response to determining that the number stored in the subchannel selection parameter matches the subchannel identifier of the memory component, the SCS component of the memory component may set the mode selection parameter of the mode register of the memory component to a value indicating that the subchannel corresponding to the memory component is selected. The SCS component of the memory component directs the memory component to execute the command by evaluating that the mode selection parameter has a value indicating that the subchannel is selected for the memory component, the mode support parameter indicates that the memory component is equipped with the subchannel selection feature, and the mode enable parameter indicates that the subchannel selection feature is enabled for the memory component.

[0028] In the case where the memory component is equipped with and enabled for the subchannel selection feature, in response to determining that the number stored in the subchannel selection parameter does not match the subchannel identifier of the memory component, the SCS component of the memory component may set the mode selection parameter of the mode register of the memory component to a value indicating that the subchannel corresponding to the memory component is not selected. By evaluating that the mode selection parameter has a value indicating that the subchannel is not selected for the memory component, the mode support parameter indicates that the memory component is equipped with the subchannel selection feature, and the mode enable parameter indicates that the subchannel selection feature is enabled for the memory component, the SCS component of the memory component instructs the memory component to ignore the command. In some embodiments, when two or more memory components have the same preset subchannel identifier, these memory components can be instructed to execute or ignore the same commands as each other. Since each memory component can independently determine whether to execute or ignore a command, the total number of subchannels and the total number of memory components do not affect the determination made by each memory component. Therefore, the total number of subchannels may be greater than, equal to, or less than the total number of memory components.

[0029] In the event that a memory component has not been equipped with or enabled the subchannel selection feature, the SCS component of the memory component may still set the mode selection parameter of the mode register of the memory component to a value indicating that the subchannel corresponding to the memory component is selected, because in such a case, all memory components are selected, which means that the subchannel selection feature is not in use.

[0030] As described above, by modifying the value stored in the register, the local controller changes the operation from the standard mode to the sub-channel selection mode. In the standard mode, the memory subsystem controller sends commands to multiple or all memory components with a shared communication channel, and each memory component will process the command. In contrast, in the sub-channel selection mode, the memory subsystem controller sends commands to multiple or all memory components with a shared communication channel, and only the memory components that are found to have the above match will execute the command, while the other memory components will ignore the command. The sub-channel selection mode may be particularly useful for test processes and / or post-packaging repair processes.

[0031] The SCS component of the memory component may also change the operating mode from the subchannel selection mode back to the standard mode by modifying the value of the register. Specifically, the SCS component of the memory component may write the value of the mode enable parameter to a predefined value (e.g., 0) that disables the subchannel selection feature of the subchannel. The flexibility of switching between the standard mode and the subchannel selection mode provides better control over command execution.

[0032] Advantages of this method include improved performance of transmitting commands through a shared communication channel. By selecting sub-channels in a shared communication channel, the system can efficiently execute commands directed to memory components, thereby avoiding wasting resources for executing the commands by other memory components to which the commands should not be applied. For example, in a PPR situation, repairs will only be applied to memory components that need repair, thereby avoiding wasting resources for unnecessary repairs. In addition, the flexibility of switching between standard mode and sub-channel selection mode enhances the management of command execution.

[0033] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or such combinations.

[0034] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD), and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0035] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0036] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0037] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0038] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0039] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices such as memory device 140 may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0040] Some examples of non-volatile memory devices, such as memory device 130, include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where the non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0041] Each of the memory devices 130 may include one or more memory cell arrays, such as a memory array. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0042] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0043] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.) or another suitable processor.

[0044] The memory subsystem controller 115 may be a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0045] In some embodiments, local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0046] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0047] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0048] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0049] In one embodiment, the memory device 130 may include a subchannel selection (SCS) component 113B to perform flexible subchannel selection. In some implementations, the memory device 130 includes a first SCS register (also referred to as a mode register) and a second SCS register (also referred to as a subchannel register). For example, the first SCS register and the second SCS register may be part of the SCS component 113B. In some implementations, the memory subsystem 110 includes a subchannel selection (SCS) component 113A that performs one or more functions of the subchannel selection (SCS) component 113B. In some embodiments, the memory subsystem controller 115 includes at least a portion of the SCS component 113A. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In one embodiment, the SCS components 113A to B together perform subchannel selection. For example, in response to the memory subsystem controller 115 receiving one or more commands (e.g., a read command, a write command, an erase command, a move command, etc.) from a requester such as the host system 120, the SCS components 113A to B may select a subchannel corresponding to a memory component among the memory components sharing the communication channel in the communication channel and execute the command received by the memory component corresponding to the selected subchannel while ignoring the command received by the other memory components. Further details on the operation of the SCS components 113A to B are described below with respect to Figures 2 to 6 describe.

[0050] Figure 2 An example system for implementing sub-channel selection according to some embodiments of the present disclosure is described. System 200 includes a controller 115 and a plurality of memory (e.g., DRAM) components 250A to N. Controller 115 communicates with the plurality of memory components 250A to N via a shared communication channel (e.g., a command address (CA) channel 231). Controller 115 may include a memory controller 210 and a physical layer (PHY) controller 220. Memory controller 210 may be connected to physical layer (PHY) controller 220 via a media access control (MAC) layer. The MAC layer may provide a channel access control mechanism for several receivers connected to the same physical medium to share the physical medium.

[0051] In some implementations, for example, the memory components 250A to N and the physical layer (PHY) controller 220 communicate with each other through an interface, such as a high-speed very low swing-near ground (VLS-NG) signaling interface that operates at speeds up to 2 Gbps, using very low voltage swings to minimize power. The communication channel 231 may include a plurality of command address (CA) subchannels 231A to N. The CA subchannels 231A to N are used to deliver command and address packets from the controller physical layer (PHY) 220 to the memory components 250A to N, respectively. The number of subchannels in the communication channel implemented depends on the number and width of the memory devices and the required communication bandwidth.

[0052] The memory components 250A to N may include respective SCS components 213A to N. The memory components 250A to N may include first SCS registers 310A to N, respectively. The memory components 250A to N may include second SCS registers 320A to N, respectively. Figure 3 , 4A 4B to describe the functionality of the SCS components and the details of the configuration and use of the first SCS register and the second SCS register.

[0053] Figure 3 The first SCS register 310 and the second SCS register 320 may be used to select a specific sub-channel to transmit commands to a memory component. Figure 3 As shown in FIG. 1 , the first SCS register 310 can store 8 bits OP[0] to OP[7], where the last three bits OP[0], OP[1], OP[2] are used; the second SCS register 320 can store 8 bits OP[0] to OP[7], where all 8 bits are used.

[0054] Table 315 illustrates an example description of the first SCS register 310, including the function of each bit used in the first SCS register 310, the register type (e.g., read or write), the bit position within the register, and example data (e.g., the value of an operand).

[0055] The bit space OP[0] of the first SCS register 310, which may be referred to as a mode support parameter ("mode support"), indicates whether a memory component of the memory device supports a subchannel selection feature. OP[0] may be set to bit 0 or bit 1, where bit 0 indicates that the memory component does not support the subchannel selection feature, and bit 1 indicates that the memory component supports the subchannel selection feature. OP[0] may be set during development and manufacturing of the memory device, and thus may be read-only. To simplify the description, OP[0] of the first SCS register 310 is referred to as R1[0].

[0056] The bit space OP[1] of the first SCS register 310, which may be referred to as a mode enable parameter ("mode enable"), indicates whether a subchannel select feature is enabled or disabled for a memory component of the memory device. OP[1] may be bit 0 or bit 1, where bit 0 indicates that the subchannel select feature of the memory component is disabled and bit 1 indicates that the subchannel select feature of the memory component is enabled. In some embodiments, the default configuration of OP[1] may be bit 0. OP[1] may be read or written. To simplify the description, OP[1] of the first SCS register 310 is referred to as R1[1].

[0057] The bit space OP[2] of the first SCS register 310 (which may be referred to as a mode selection parameter ("mode select")) indicates whether the memory component is selected for the subchannel selection feature. In this case, commands transmitted using the shared communication channel will only be processed by the memory component corresponding to the selected subchannel. OP[2] may be bit 0 or bit 1, where bit 0 indicates that the memory component is not selected for the subchannel selection feature and bit 1 indicates that the memory component is selected for the subchannel selection feature. In some embodiments, the default configuration of OP[2] may be bit 1. OP[2] may be read-only. To simplify the description, OP[2] of the first SCS register 310 is referred to as R1[2].

[0058] Table 325 illustrates instance information of the second SCS register 320, including the function of a range of storage space used in the second SCS register 320, register type (e.g., read or write), operands, and instance data (e.g., values ​​of the operands).

[0059] The four bit spaces OP[3:0] (i.e., OP[3], OP[2], OP[1], OP[0], and ":" represents a range from its left term to its right term) of the second SCS register 320, which may be referred to as subchannel identifiers ("CH ID numbers"), represent the subchannel identifier numbers of the memory components of the memory device corresponding to each subchannel in the subchannels used for the subchannel selection feature. Figure 3In the example shown in , OP[3:0] can be one of bit

[0000] to bit

[1111] , for a total of sixteen values, where each bit value corresponds to a subchannel identifier number associated with a memory component. For example, bit

[0000] corresponds to subchannel 0, bit

[0001] corresponds to subchannel 1, bit

[0010] corresponds to subchannel 2, ..., and bit

[1111] corresponds to subchannel 15. In some implementations, OP[3:0] can be any value corresponding to a subchannel identifier number, where a subchannel identifier number can be associated with one or more memory components. OP[3:0] can be set during development and manufacture of a memory device so that a memory component is associated with a subchannel identifier number and can therefore be read-only. For example, OP[3:0] can be programmed via a one-time programmable fuse or a different mechanism based on the location of the memory component. To simplify the description, OP[3:0] of the second SCS register 320 is referred to as R2[3:0].

[0060] The four bit spaces OP[7:4] (i.e., OP[7], OP[6], OP[5], OP[4]) of the second SCS register 320, which may be referred to as a subchannel selection parameter ("CH Select"), represent the subchannel identifier number selected for the subchannel selection feature. Figure 3 , OP[7:4] may be one of bit

[0000] to bit

[1111] , for a total of sixteen values, where each bit value corresponds to a selected subchannel identifier number. For example, bit

[0000] corresponds to subchannel 0, bit

[0001] corresponds to subchannel 1, bit

[0010] corresponds to subchannel 2, ..., and bit

[1111] corresponds to subchannel 15. OP[7:4] may be write-only. OP[7:4] may be volatile, meaning that the value is not stored when power is off. To simplify the description, OP[7:4] of the second SCS register 320 is referred to as R2[7:4].

[0061] Although the first SCS register 310 and the second SCS register 320 described herein each use 8 bits, other numbers of bits may be applicable, for example, based on the number of memory components connected to the available subchannels. 5) subchannels to choose from, then 10 bits (i.e., 5*2) can be used for each of the first SCS register 310 and the second SCS register 320. In some implementations, the number of bits of the first SCS register 310 and the second SCS register 320 may be different. In certain implementations, the SCS register may contain mode register bits that are not part of the SCS. For example, the unused bits in the first SCS register may be assigned to some other purpose unrelated to the SCS. In addition, the parameters for the above-mentioned functions provided by the first and second SCS registers may be distributed across any number of registers. In some embodiments, certain features may be added or excluded from the SCS registers. For this example, the use of the first SCS register 310 and the second SCS register 320 will be described below.

[0062] In one example, R1[0] is bit 0, indicating that the memory component does not support the subchannel selection feature, and in this case, the memory device will operate under the normal circumstances that all memory components in all subchannels in the shared communication channel will execute the received command. Therefore, for each subchannel, R1[0] is bit 0, indicating that each subchannel will be selected, and the value of R1[1], R2[7:4] or R2[3:0] does not affect the result.

[0063] In another example, R1[0] is bit 1, indicating that the memory component supports the subchannel selection feature. When the memory device is powered on, for each subchannel, R1[2] and R1[1] can each be in a default value, that is, for each subchannel, R1[2] is bit 1, indicating that all subchannels are selected, and for each subchannel, R1[1] is bit 0, indicating that the subchannel selection feature is disabled for each subchannel. In this case, R2[3:0] for each subchannel corresponds to a different memory component of the memory device, and the value of R2[7:4] does not affect the result. Other examples will be relative to Figure 4A and 4B Explain in detail.

[0064] Figure 4A and 4B An example of using the SCS registers to implement the subchannel selection feature is described, specifically, by using the SCS registers relative to Figure 3 The first SCS register 310 and the second SCS register 320 are described. Figure 4A 4 , graph 401A illustrates a change from operation in standard mode to operation in sub-channel selection mode; graph 402A illustrates a change from operation in sub-channel selection mode to operation in standard mode. Figure 4B is corresponding to Figure 4A A flowchart illustrating an example method of operation.

[0065] exist Figure 3 and Figure 4A and 4B , a first SCS register 310 ("R1") and a second SCS register 320 ("R2") are used for each of the 16 subchannels in the shared communication channel, and each subchannel is connected to one of the 16 memory components of the memory device, as indicated by R2[3:0]. In some embodiments, the subchannel may be connected to multiple memory components (e.g., two memory components connected to each subchannel), where R2[3:0] will be the same for each of these multiple memory components. In this case, the number of available subchannels (e.g., 16) will be less than the number of memory components (e.g., 32). However, in other embodiments, not all available subchannels may be connected to memory components, and some subchannels may remain unused (e.g., each of the eight subchannels is connected to a memory component, while the other eight subchannels are not connected to any memory component). In this case, the number of available subchannels (e.g., 16) will be greater than the number of memory components (e.g., 8). For each subchannel, R1[0] is bit 1, indicating that the memory device supports the subchannel selection feature. Since the values ​​of R2[3:0] and R1[0] are preset during the development and manufacturing of the memory device, the values ​​of R2[3:0] and R1[0] are Figure 4A and 4B All operations described in remain the same.

[0066] Table 410A illustrates the states of R1 and R2 for 16 subchannels, where each row corresponds to one of the 16 subchannels. Figure 4A 4. The table containing R1 and R2 in 410A illustrates 16 subchannels together, but it should be noted that each row of the table may represent a separate register stored in the memory component. For example, the first row 411A of table 410A may be a register stored in memory component 250A (e.g., first SCS register 310A and second SCS register 320A), and the last row 413A of table 410A may be a register stored in memory component 250N (e.g., first SCS register 310N and second SCS register 320N). Table 410A may indicate the state of R1 and R2 in the above-described power-on scenario. As shown in table 410A, for each subchannel, R1[2] is bit 1, indicating that all subchannels are selected, and for each subchannel, R1[1] is bit 0, indicating that the subchannel selection feature is disabled for each subchannel. The value of R2[7:4] does not affect the result because the subchannel selection feature is disabled. Table 410A corresponds to operation 410B, in which the controller operates the memory device in standard mode.

[0067] As indicated by graph 420A, SCS components 113A-B write bit

[0001] to R2[7:4] for each subchannel, which corresponds to operation 420B, indicating identification of a channel identifier for selection. Table 425A illustrates the state of R1 and R2 for the 16 subchannels after writing R2[7:4]. As indicated by graph 430A, SCS components 113A-B write bit 1 to R1[1] for each subchannel, which corresponds to operation 430B, indicating enabling the subchannel selection feature for each subchannel.

[0068] After the SCS components 113A-B enable the subchannel selection feature for each subchannel, the SCS components 113A-B determine whether the value of R2[7:4] matches the value of R2[3:0]. In response to determining that the value of R2[7:4] matches the value of R2[3:0], the SCS components 113A-B set the value of R1[2] to bit 1 for the corresponding subchannel with the matching value. In response to determining that the value of R2[7:4] does not match the value of R2[3:0], the SCS components 113A-B set the value of R1[2] to bit 0 for the subchannel. Table 440A illustrates the states of R1 and R2 for the 16 subchannels after writing R1[1] and determining a match between R2[7:4] and R2[3:0]. Table 440A corresponds to operation 440B, in which the controller operates the memory device in a subchannel selection mode. In example table 440A, the memory subsystem controller sends a command to all memory components of all sub-channels in the shared communication channel, but only memory components with sub-channel identifiers pre-programmed to bit

[0001] (i.e., R2[3:0]) will execute the command. Thus, the command can only be executed by the memory components of a particular sub-channel.

[0069] Thereafter, the subchannel selection mode may need to be changed back to standard mode. As shown in Table 445A, which is the same as Table 440A, only one subchannel has R1[2] as bit 1, while the other subchannels have R1[2] as bit 0, and for each subchannel, R1[1] is bit 1. As indicated in Table 450A, the SCS components 113A-B write bit 0 to R1[1] for each subchannel, which corresponds to operation 450B, indicating that the subchannel selection feature is disabled for each subchannel. In response to detecting bit 0 in R1[1], the SCS components 113A-B change the value of R1[2] to bit 1 for each subchannel, indicating that all subchannels are selected for their corresponding memory components to execute the command. Table 460A corresponds to operation 410B, where the controller again operates the memory device in standard mode.

[0070] exist Figure 3 , 4AThe registers and their use illustrated in 4B are examples only, and other registers, such as different numbers or formats, may be used depending on the characteristics and available resources, as long as the registers facilitate the functions required to perform the flexible subchannel selection described herein. For example, in some embodiments, R1[2] may be omitted.

[0071] Figure 5 is a flowchart of an example method for implementing subchannel selection according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1 SCS component 113A or SCS component 113B and Figure 2 The SCS components 213A to N are executed by the SCS components 213A to N. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] In operation 510, the processing logic is configured to select one or more registers (i.e., one or more memory locations) of a subchannel in a plurality of subchannels in a communication channel, wherein each of the plurality of subchannels corresponds to one or more components of a plurality of components of the memory device, wherein the plurality of components of the memory device share the communication channel. In some embodiments, the register includes a first register and a second register, wherein the first register is used to store the value of one or more parameters for enabling or disabling subchannel selection, and the second register is used to store the value of one or more parameters for matching a subchannel identifier with a selected subchannel. In one example, the processing logic may write a bit value to the first register to enable or disable the subchannel selection function. In one example, the processing logic may write a bit value to the second register to represent the subchannel identifier of the selected subchannel. In some embodiments, one or more parameters of the register are preset during the development and manufacture of the memory device, for example, a parameter indicating whether the memory device supports a subchannel selection feature, or a parameter indicating a subchannel identifier associated with a memory component. In some embodiments, the communication channel includes a CA channel.

[0073] In some embodiments, processing logic stores a first value in a first memory location (e.g., in a register) for selecting a subchannel in a plurality of subchannels in a communication channel, wherein each of the plurality of subchannels corresponds to a component in a plurality of components of the memory device, and the first value specifies enabling a subchannel selection function. In some embodiments, the first value further specifies that the first component supports the subchannel selection function. In some embodiments, the first value further specifies that the subchannel selection function is selected for the first subchannel.

[0074] At operation 520, processing logic receives a command directed to a memory device via a shared communication channel. In some embodiments, the command is sent to all memory components of the shared communication channel, but only a selected memory component of the plurality of memory components will execute the command, as described at operation 550. In other embodiments, processing logic determines whether the command is directed to one memory component of the plurality of memory components, rather than all memory components of the shared communication channel. In some embodiments, the command may specify a first sub-channel identifier number (e.g., a mode register write) or information that can be used to obtain a first sub-channel identifier number (e.g., a mode register read).

[0075] In operation 530, in response to receiving the command, the processing logic modifies the value stored in the register. In some embodiments, each subchannel has its corresponding value stored in the register. By modifying the value stored in the register, the processing logic can then determine a match between the modified value and the preset value stored in the register. That is, for the memory component for which a match has been found, the processing logic changes the operation from the standard mode to the subchannel selection mode for the memory component.

[0076] In some implementations, in response to receiving the command, the processing logic obtains a first sub-channel identifier number from the command and stores a second value in a second memory location (e.g., in a register), wherein the second value is the same as the first sub-channel identifier number obtained from the command.

[0077] At operation 540, processing logic determines whether the second value matches a third value stored in a third memory location (e.g., in a register), wherein the third value stored in the third memory location is a preset value corresponding to a first component of a plurality of components of the memory device. In some embodiments, processing logic determines that the second value matches the third value, and in response, at operation 450, processing logic may execute a command by the first component. In such cases, processing logic may determine that the second value matches the third value but does not match the remaining third values ​​of a plurality of third values, wherein each third value of the plurality of third values ​​identifies a corresponding subchannel of a plurality of subchannels, and wherein each third value of the plurality of third values ​​is preset. Processing logic avoids executing the command by the remaining components of the plurality of components of the memory device other than the first component. This command may include a command for a test phase by selecting a single die and forcing an idle state on another die, a command for selective post-package repair of a product, or a command to exclude the use of a memory component in the event of a continuous failure during use of the memory component.

[0078] In some embodiments, in response to determining that the second value matches a third value in the plurality of third values, processing logic modifies a fourth value stored in a fourth memory location (e.g., in a register), wherein the fourth value specifies that the sub-channel selection functionality is selected for the first component. In some embodiments, processing logic stores a fifth value in a fifth memory location (e.g., in a register), and wherein the fifth value specifies that the first component supports the sub-channel selection functionality.

[0079] In some implementations, processing logic modifies the first value stored in the first register to disable the sub-channel selection function, and the command is executed by multiple components (rather than just the first component).

[0080] Figure 6 An example machine illustrating a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to execute operations of the controller (eg, execute an operating system to execute operations corresponding to Figure 1 SCS Components 113A to B and Figure 2In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0081] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0082] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 618, which communicate with each other via a bus 630.

[0083] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0084] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0085] In one embodiment, instructions 626 include implementing Figure 1 SCS Components 113A to B and Figure 2 The machine-readable storage medium 624 is a storage medium that stores instructions for the functionality of the SCS components 213A to N. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0086] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. Here, and in general, an algorithm is considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes for reasons of common usage, to refer to these signals, in principle, as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0087] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform that data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0088] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0090] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0091] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device, comprising: a plurality of memory components including a first memory component; and a processing device operatively coupled to the plurality of memory components via a communication channel to perform operations comprising: storing a first value in a first memory location of the first memory component, wherein the first memory location is used to select a subchannel of a plurality of subchannels of the communication channel, wherein each of the plurality of subchannels corresponds to one or more respective memory components of the plurality of memory components, wherein the first value specifies enabling of a subchannel selection function; receiving a command directed to the memory device via the communication channel; in response to receiving the command, storing a second value specified by the command in a second memory location of the first memory component; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and The command is executed by the first memory component.

2. The memory device of claim 1, wherein the second value comprises a first identifier corresponding to the first subchannel of the first memory component.

3. The memory device of claim 1 , wherein the operations further comprise: A determination is made as to whether the second value matches the third value of a plurality of third values, wherein each third value of the plurality of third values ​​identifies a corresponding subchannel of the plurality of subchannels, and wherein each third value of the plurality of third values ​​is predetermined.

4. The memory device of claim 3, wherein the operations further comprise: In response to determining that the second value does not match a remaining third value of the plurality of third values ​​other than the third value, execution of the command by a remaining memory component of the plurality of memory components other than the first memory component is avoided.

5. The memory device of claim 3, wherein the operations further comprise: In response to determining that the second value matches the third value of the plurality of third values, a fourth value stored in a fourth memory location of the first memory component is modified, wherein the fourth value specifies selection of the sub-channel selection function for the first memory component.

6. The memory device of claim 1, wherein the operations further comprise: A fifth value is stored in a fifth memory location of the first memory component, and wherein the fifth value specifies that the first memory component supports the sub-channel selection functionality.

7. The memory device of claim 1, wherein the operations further comprise: modifying the first value stored in the first memory location to disable the sub-channel selection function; and The commands are executed by the plurality of memory components.

8. A method comprising: storing, by a processing device, a first value in a first memory location of a first memory component of a plurality of memory components of a memory device, wherein the first memory location is used to select a subchannel of a plurality of subchannels in a communication channel, wherein each of the plurality of subchannels corresponds to one or more memory components of the plurality of memory components of the memory device, wherein the first value specifies enabling of a subchannel selection function; receiving a command directed to the memory device via the communication channel; in response to receiving the command, storing a second value specified by the command in a second memory location of the first memory component; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and The command is executed by the first memory component.

9. The method of claim 8, wherein the second value comprises a first identifier corresponding to the first subchannel of the first memory component.

10. The method according to claim 8, further comprising: A determination is made as to whether the second value matches the third value of a plurality of third values, wherein each third value of the plurality of third values ​​identifies a corresponding subchannel of the plurality of subchannels, and wherein each third value of the plurality of third values ​​is predetermined.

11. The method according to claim 10, further comprising: In response to determining that the second value does not match a remaining third value of the plurality of third values ​​other than the third value, execution of the command by a remaining memory component of the plurality of memory components other than the first memory component is avoided.

12. The method according to claim 10, further comprising: In response to determining that the second value matches the third value of a plurality of third values, a fourth value stored in a fourth memory location of the first memory component is modified, wherein the fourth value specifies selection of the sub-channel selection function for the first memory component.

13. The method according to claim 8, further comprising: A fifth value is stored in a fifth memory location of the first memory component, and wherein the fifth value specifies that the first memory component supports the sub-channel selection functionality.

14. The method according to claim 8, further comprising: modifying the first value stored in the first memory location to disable the sub-channel selection function; and The commands are executed by the plurality of memory components.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: storing a first value in a first memory location of a first memory component of a plurality of memory components of a memory device, wherein the first memory location is used to select a subchannel of a plurality of subchannels in a communication channel, wherein each of the plurality of subchannels corresponds to one or more memory components of the plurality of memory components of the memory device, wherein the first value specifies enabling of a subchannel selection function; receiving a command directed to the memory device via the communication channel; in response to receiving the command, storing a second value specified by the command in a second memory location of the first memory component; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and The command is executed by the first memory component.

16. The non-transitory computer-readable storage medium of claim 15, wherein the second value comprises a first identifier corresponding to the first subchannel of the first memory component.

17. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: A determination is made as to whether the second value matches the third value of a plurality of third values, wherein each third value of the plurality of third values ​​identifies a corresponding subchannel of the plurality of subchannels, and wherein each third value of the plurality of third values ​​is predetermined.

18. The non-transitory computer-readable storage medium of claim 17, the operations further comprising: In response to determining that the second value does not match a remaining third value of the plurality of third values ​​other than the third value, execution of the command by a remaining memory component of the plurality of memory components other than the first memory component is avoided.

19. The non-transitory computer-readable storage medium of claim 17, wherein the operations further comprise: In response to determining that the second value matches the third value of a plurality of third values, a fourth value stored in a fourth memory location of the first memory component is modified, wherein the fourth value specifies selection of the sub-channel selection function for the first memory component.

20. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: A fifth value is stored in a fifth memory location of the first memory component, and wherein the fifth value specifies that the first memory component supports the sub-channel selection functionality.

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