Semiconductor structure and forming method thereof, and memory

Abstract

The present disclosure relates to a semiconductor structure, a method for forming the same, and a memory. The method comprises: forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate and a word line structure, the substrate comprising a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extending along the direction in which the plurality of semiconductor pillars are spaced-apart and covering the periphery of each semiconductor pillar; the insulating portion being located above the word line structure, and an end of the insulating portion away from the word line structure being higher than an end of the semiconductor pillar, two adjacent insulating portions and the semiconductor pillar therebetween defining a bit line trench; forming a barrier layer covering the sidewalls of the bit line trench; forming a conductive material layer in the bit line trench having the barrier layer; performing a heat treatment on the conductive material layer to form the bit line structure; forming a contact hole penetrating the insulating portion and exposing the word line structure; forming an insulating layer on the hole wall of the contact hole; and forming a word line contact structure in the contact hole having the insulating layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. However, the DRAM manufacturing process is prone to structural defects due to process limitations, resulting in low product yield.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce leakage and improve product yield.

[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] An initial semiconductor structure is formed, the initial semiconductor structure comprising a substrate and a wordline structure, the substrate comprising a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the wordline structure extending along the direction in which the plurality of semiconductor pillars are spaced-apart and covering the periphery of each semiconductor pillar; the insulating portion is located above the wordline structure, and an end of the insulating portion away from the wordline structure is higher than an end of the semiconductor pillar; two adjacent insulating portions and the semiconductor pillar therebetween define a bitline trench;

[0007] forming a barrier layer covering sidewalls of the bit line trench;

[0008] forming a conductive material layer in the bit line trench having the barrier layer;

[0009] performing a heat treatment on the conductive material layer to form a bit line structure;

[0010] forming a contact hole penetrating the insulating portion and exposing the word line structure;

[0011] forming an insulating layer on a hole wall of the contact hole;

[0012] A word line contact structure is formed in the contact hole having the insulating layer.

[0013] For example, forming a barrier layer covering the sidewall of the bit line trench includes:

[0014] forming a barrier material layer on the sidewalls and bottom of the bit line trench;

[0015] Processing the barrier material layer by a reverse sputtering process so that the thickness of the barrier material layer at an end portion close to the semiconductor pillar is greater than the thickness at a side away from the semiconductor pillar;

[0016] The barrier material layer is etched back to expose the top surface of the semiconductor column, and the end of the barrier material layer away from the semiconductor column is lower than the surface of the insulating portion away from the word line structure, and the remaining barrier material layer is used as the barrier layer; the surface of the bit line structure away from the semiconductor column is flush with the end of the barrier layer away from the semiconductor column.

[0017] For example, the thickness of the barrier layer is 1 nm to 3 nm; the material of the barrier layer includes titanium nitride or tantalum nitride.

[0018] For example, the forming method further includes:

[0019] forming a passivation layer on a surface of a structure formed by the barrier layer, the bit line structure, and the insulating portion;

[0020] Chemical mechanical polishing is performed on the surface of the passivation layer so that the surface of the passivation layer is flush with the surface of the insulating portion away from the word line structure.

[0021] For example, the step of performing a heat treatment on the conductive material layer to form a bit line structure includes:

[0022] heat-treating the conductive material layer at a preset temperature so that metal ions in the conductive material layer diffuse into the semiconductor pillar to form a first conductive layer at the interface between the semiconductor pillar and the conductive material layer; and using the conductive material layer after the heat treatment as a second conductive layer;

[0023] The preset temperature is less than 450°C.

[0024] For example, forming the initial semiconductor structure includes:

[0025] Providing a substrate, the substrate comprising a plurality of first trenches spaced apart and distributed along a first direction, and an insulating material filling the first trenches;

[0026] Etching the substrate to form a plurality of second trenches spaced apart along a second direction, wherein the second direction intersects the first direction, and each of the second trenches and each of the first trenches divides the substrate into a plurality of semiconductor pillars;

[0027] Etching back the insulating material to form an insulating portion;

[0028] forming a word line structure extending along the first direction and covering the periphery of each of the semiconductor pillars spaced apart along the first direction, wherein the word line structure is located on the insulating portion, and a surface thereof away from the insulating portion is lower than a surface of the semiconductor pillar away from the bottom of the first trench;

[0029] doping an area of ​​the semiconductor column that is not covered by the word line structure and the insulating portion to form a source region;

[0030] forming a capacitor structure on the source region;

[0031] The substrate is etched at a side of the substrate away from the capacitor structure to form the bit line trench.

[0032] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

[0033] An initial semiconductor structure includes a substrate and a wordline structure. The substrate includes a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions located between two adjacent semiconductor pillars. The wordline structure extends along the direction in which the plurality of semiconductor pillars are spaced-apart and covers the periphery of each semiconductor pillar. The insulating portion is located above the wordline structure, and an end of the insulating portion away from the wordline structure is higher than an end of the semiconductor pillar. Two adjacent insulating portions and the semiconductor pillar therebetween define a bitline trench.

[0034] a barrier layer covering the sidewalls of the bit line trench;

[0035] a bit line structure at least partially located within the bit line trench having the barrier layer;

[0036] A word line contact structure, passing through the insulating portion and being in contact with the word line structure;

[0037] An insulating layer is located between the word line contact structure and the barrier layer, the bit line structure and the semiconductor pillar.

[0038] For example, the thickness of the barrier layer at the end portion close to the semiconductor pillar is greater than the thickness of the barrier layer at the end portion away from the semiconductor pillar.

[0039] For example, the material of the barrier layer includes titanium nitride or tantalum nitride, and the thickness of the barrier layer includes 1 nm to 3 nm.

[0040] For example, the bit line structure includes a first conductive layer and a second conductive layer, the first conductive layer is located at the top of the semiconductor column, the barrier layer is in contact with the first conductive layer near the end of the semiconductor column, and the second conductive layer is located in the bit line trench having the barrier layer and in contact with the surface of the first conductive layer.

[0041] For example, the semiconductor structure further includes:

[0042] The passivation layer is located on the surface of the bit line structure, and the surface of the passivation layer away from the bit line structure is flush with the surface of the insulating portion away from the word line structure.

[0043] For example, the surface of the word line structure away from the insulating portion is lower than the surface of the semiconductor column away from the bit line groove, and the area in the semiconductor column not covered by the word line structure and the insulating portion is the source region. The initial semiconductor structure also includes: a capacitor structure formed on the source region.

[0044] According to one aspect of the present disclosure, a memory is provided, comprising any one of the semiconductor structures described above.

[0045] For example, the memory further includes: a peripheral circuit bonded to the word line contact structure of the semiconductor structure.

[0046] The semiconductor structure, its formation method, and memory disclosed herein, since the insulating layer is located between the bit line structure and the word line contact structure, the bit line structure and the word line contact structure can be insulated and isolated by the insulating layer, which helps to reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure; at the same time, since the sidewalls of the bit line groove are covered with a barrier layer (that is, a barrier layer is also provided between the insulating layer and the bit line structure), the barrier layer can prevent metal ions in the bit line structure from diffusing into the insulating layer and the word line contact structure in contact with the insulating layer, which helps to further reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure and improve product yield.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0049] Figure 1Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0050] Figure 2 FIG. 1 is a top view of an initial semiconductor structure in an embodiment of the present disclosure.

[0051] Figure 3 Schematic diagram of an initial semiconductor structure in an embodiment of the present disclosure.

[0052] Figure 4 FIG. 1 is a schematic diagram of an embodiment of the present disclosure in which the substrate is turned upside down after forming the capacitor structure.

[0053] Figure 5 Schematic diagram of the structure after step S120 is completed in the embodiment of the present disclosure.

[0054] Figure 6 3 is a schematic diagram of the structure after completing step S310 in the embodiment of the present disclosure.

[0055] Figure 7 Schematic diagram of the structure after step S130 is completed in the embodiment of the present disclosure.

[0056] Figure 8 Schematic diagram of the structure after step S140 is completed in the embodiment of the present disclosure.

[0057] Figure 9 4 is a schematic diagram of the structure after completing step S420 in the embodiment of the present disclosure.

[0058] Figure 10 Schematic diagram of the structure after step S150 is completed in the embodiment of the present disclosure.

[0059] Figure 11 Schematic diagram of the structure after step S160 is completed in the embodiment of the present disclosure.

[0060] Figure 12 Schematic diagram of the structure after step S170 is completed in the embodiment of the present disclosure.

[0061] Figure 13 Schematic diagram of a memory in an embodiment of the present disclosure.

[0062] Description of reference numerals:

[0063] 1. Initial semiconductor structure; 11. Substrate; 111. Semiconductor pillar; 111a. Source region; 112. Insulating portion; 12. Word line structure; 13. Gate oxide layer; 101. Bit line trench; 102. Contact hole; 2. Barrier layer; 210. Barrier material layer; 3. Conductive material layer; 4. Bit line structure; 41. First conductive layer; 42. Second conductive layer; 5. Insulating layer; 6. Word line contact structure; 61. Titanium nitride layer; 62. Tungsten layer; 7. Passivation layer; 100. Semiconductor structure; 200. Peripheral circuit; x, first direction; y, second direction. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0065] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0066] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "the," or "the" can likewise be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0067] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. Such a substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. Furthermore, a substrate may comprise one or more semiconductor materials.

[0068] As used herein, the term "layer" refers to a portion of a material comprising an area having a thickness. A layer may extend over the entire underlying structure or superstructure, or may have an extent that is less than that of the underlying structure or superstructure. In addition, a layer may be an area of ​​a continuous structure, whether homogeneous or non-homogeneous, having a thickness that is less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below.

[0069] The terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0070] The present disclosure provides a method for forming a semiconductor structure. Figure 1 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 1 As shown, the forming method includes steps S110 to S170, wherein:

[0071] Step S110, forming an initial semiconductor structure, the initial semiconductor structure comprising a substrate and a wordline structure, the substrate comprising a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the wordline structure extending along the direction in which the plurality of semiconductor pillars are spaced-apart and covering the periphery of each semiconductor pillar; the insulating portion being located above the wordline structure, with an end of the insulating portion away from the wordline structure being higher than an end of the semiconductor pillar; and two adjacent insulating portions and the semiconductor pillar therebetween defining a bitline trench;

[0072] Step S120, forming a barrier layer covering the sidewalls of the bit line trench;

[0073] Step S130, forming a conductive material layer in the bit line trench having the barrier layer;

[0074] Step S140 , performing a heat treatment on the conductive material layer to form a bit line structure;

[0075] Step S150 , forming a contact hole penetrating the insulating portion and exposing the word line structure;

[0076] Step S160, forming an insulating layer on the hole wall of the contact hole;

[0077] Step S170 , forming a word line contact structure in the contact hole having the insulating layer.

[0078] In the method for forming a semiconductor structure disclosed herein, since the insulating layer is located between the bit line structure and the word line contact structure, the bit line structure and the word line contact structure can be insulated and isolated by the insulating layer, which helps to reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure; at the same time, since the sidewalls of the bit line groove are covered with a barrier layer (that is, a barrier layer is also provided between the insulating layer and the bit line structure), the barrier layer can prevent metal ions in the bit line structure from diffusing into the insulating layer and the word line contact structure in contact with the insulating layer, which helps to further reduce the risk of leakage or short circuit between the bit line structure and the word line contact structure and improve product yield.

[0079] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0080] like Figure 1 As shown, in step S110, an initial semiconductor structure is formed, the initial semiconductor structure including a substrate and a word line structure, the substrate including a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the word line structure extending along the direction in which the plurality of semiconductor pillars are spaced-apart and covering the periphery of each semiconductor pillar; the insulating portion is located above the word line structure, and the end of the insulating portion away from the word line structure is higher than the end of the semiconductor pillar, and two adjacent insulating portions and the semiconductor pillar therebetween define a bit line groove.

[0081] like Figure 2As shown, the substrate 11 may include a plurality of semiconductor pillars 111 arranged in an array, with each semiconductor pillar 111 arranged in rows and / or columns. For example, the substrate 11 may include a plurality of semiconductor groups, each semiconductor group including a plurality of semiconductor pillars 111 spaced apart along a first direction x, and each semiconductor group spaced apart along a second direction y. The second direction y intersects the first direction x; for example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that perpendicularity can be either absolutely perpendicular or approximately perpendicular, and deviations are inevitable during the manufacturing process. In the present disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y may be considered perpendicular. For example, the preset range may be 10°, meaning that the first direction x and the second direction y may be considered perpendicular if the angle between the first direction x and the second direction y is within a range greater than or equal to 80° and less than or equal to 100°.

[0082] like Figure 3 As shown, the insulating portion 112 may be located between two adjacent semiconductor pillars 111 along the first direction x and may fill the gap between the two adjacent semiconductor pillars 111. In some embodiments of the present disclosure, there may be multiple insulating portions 112, with one insulating portion 112 being provided between every two adjacent semiconductor pillars 111 along the first direction x. For example, the insulating portion 112 may be strip-shaped and may extend along the second direction y. Multiple insulating portions 112 may be spaced apart along the first direction x.

[0083] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 and Figure 3 As shown, the wordline structure 12 may be strip-shaped, extend along a first direction x, and wrap around the periphery of each semiconductor pillar 111 spaced apart along the first direction x, with a gate oxide layer 13 formed between the wordline structure 12 and the semiconductor pillar 111. An insulating portion 112 may be located above the wordline structure 12 and may contact the wordline structure 12. In some embodiments of the present disclosure, the end of the insulating portion 112 away from the wordline structure 12 is higher than the end of the semiconductor pillar 111, and two adjacent insulating portions 112 and the semiconductor pillar 111 therebetween jointly define a bitline trench 101.

[0084] In an exemplary embodiment of the present disclosure, the surface of the word line structure 12 away from the insulating portion 112 is lower than the surface of the semiconductor column 111 away from the bit line trench 101, and the area of ​​the semiconductor column 111 not covered by the word line structure 12 and the insulating portion 112 can be ion doped to form a source region 111a, and a capacitor structure (not shown in the figure) can be formed on the source region 111a.

[0085] In an exemplary embodiment of the present disclosure, forming the initial semiconductor structure 1 (ie, step S110) may include steps S210 to S270, wherein:

[0086] In step S210 , a substrate 11 is provided. The substrate 11 includes a plurality of first trenches spaced apart along a first direction x, and an insulating material filling the first trenches.

[0087] The substrate 11 may include a base, which may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and may be made of silicon or other semiconductor materials. The shape and material of the base are not particularly limited herein.

[0088] The substrate may be etched to form a plurality of first trenches spaced apart along a first direction x and extending along a second direction y. The first trenches may be filled with an insulating material by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The insulating material may be silicon oxide. It should be noted that the substrate and the insulating material may together constitute the substrate 11.

[0089] In step S220 , the substrate 11 is etched to form a plurality of second trenches spaced apart along a second direction y, where the second direction y intersects the first direction x, and each of the second trenches and the first trenches divides the substrate 11 into a plurality of semiconductor pillars 111 .

[0090] The structure formed by the substrate and the insulating material can be etched to form a plurality of second trenches spaced apart along the second direction y and extending along the first direction x. It should be noted that the second trenches have a different depth than the first trenches. For example, the second trenches are less than the first trenches. The second trenches and the first trenches can collectively divide the substrate into a plurality of semiconductor pillars 111.

[0091] In some embodiments of the present disclosure, the second trenches may be filled with insulating material, and the insulating material may fill each second trench. It should be noted that the insulating material filled in the second trenches may be the same as the insulating material filled in the first trenches.

[0092] In step S230 , the insulating material is etched back to form the insulating portion 112 .

[0093] The insulating material may be etched back to expose a portion of the sidewalls of the semiconductor pillars 111 . After the etching back, the insulating material remaining between the semiconductor pillars 111 spaced apart along the first direction x may be used as the insulating portion 112 .

[0094] In step S240, a word line structure 12 is formed that extends along the first direction x and covers the periphery of each of the semiconductor pillars 111 spaced apart along the first direction x. The word line structure 12 is located on the insulating portion 112, and its surface away from the insulating portion 112 is lower than the surface of the semiconductor pillar 111 away from the bottom of the first trench.

[0095] In an exemplary embodiment of the present disclosure, before forming the wordline structure 12, a gate oxide layer 13 may be formed on the sidewall surface of the semiconductor pillar 111 exposed above the insulating portion 112. For example, the gate oxide layer 13 may be formed on the surface of the semiconductor pillar 111 by in-situ water vapor oxidation or atomic layer deposition. After the gate oxide layer 13 is formed, the wordline structure 12 may be formed, and the wordline structure 12 may cover the surface of the gate oxide layer 13. That is, the gate oxide layer 13 is provided between the wordline structure 12 and the semiconductor pillar 111.

[0096] In step S250 , the region of the semiconductor pillar 111 that is not covered by the word line structure 12 and the insulating portion 112 is doped to form a source region 111 a .

[0097] After forming the wordline structure 12, ion doping can be performed on the region of the semiconductor pillar 111 not covered by the wordline structure 12 and the insulating portion 112 to form the source region 111a. For example, the region of the semiconductor pillar 111 not covered by the wordline structure 12 and the insulating portion 112 can be p-type doped to form a p-type doped region. For example, a p-type dopant material can be doped into the semiconductor pillar 111. The p-type dopant material can be an element in Group III of the periodic table, for example, boron. Of course, other elements can also be used, and these are not listed here.

[0098] Step S260 , forming a capacitor structure on the source region 111 a .

[0099] A capacitor structure may be formed on the source region 111a. The capacitor structure may include a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer. The lower electrode layer contacts the source region 111a, the capacitor dielectric layer is located on the surface of the lower electrode layer, and the upper electrode layer is located on the surface of the capacitor dielectric layer. Both the lower electrode layer and the upper electrode layer may be made of titanium nitride, and the capacitor dielectric layer may be made of a dielectric material with a relatively high dielectric constant.

[0100] In step S270 , the substrate 11 is etched at a side of the substrate 11 away from the capacitor structure to form the bit line trench 101 .

[0101] After forming the capacitor structure, the substrate 11 can be turned upside down so that the capacitor structure faces downward relative to the word line structure 12 and the insulating portion 112 faces upward relative to the word line structure 12. At this time, the original bottom surface of the substrate 11 faces upward and the original top surface faces downward. Figure 4 shown.

[0102] Please continue to see Figure 3 As shown, after the substrate 11 is flipped over, chemical mechanical polishing can be performed on the side of the substrate 11 away from the capacitor structure to expose the end of the insulating portion 112 away from the word line structure 12; the base is then etched to form bit line trenches 101 between adjacent insulating portions 112 spaced apart along the first direction x.

[0103] like Figure 1 As shown, in step S120 , a barrier layer 2 is formed to cover the sidewalls of the bit line trench 101 .

[0104] like Figure 5 As shown, barrier layer 2 can be a thin film covering the sidewalls (e.g., insulating portion 112) of bitline trench 101, or a coating covering the sidewalls of bitline trench 101. The specific form of barrier layer 2 is not particularly limited herein. The bottom end of barrier layer 2 can contact the top end of semiconductor pillar 111. Barrier layer 2 can be made of a material having an ion barrier function, such as titanium nitride or tantalum nitride.

[0105] The thickness of the blocking layer 2 may include 1nm to 3nm, for example, it may be 1nm, 1.5nm, 2nm, 2.5nm or 3nm. Of course, it may also be other thicknesses and are not listed here one by one. In some embodiments of the present disclosure, the thickness of each region of the blocking layer 2 may not be exactly the same in the depth direction of the bit line trench 101. For example, the thickness of the end of the blocking layer 2 close to the semiconductor pillar 111 is greater than the thickness of the side away from the semiconductor pillar 111, so as to reduce the risk of metal ions in the conductive material layer subsequently formed inside the bit line trench 101 diffusing along the interface between the insulating portion 112 and the semiconductor pillar 111 to the word line structure 12 below the insulating portion 112 and the word line contact structure subsequently formed through the insulating portion 112, which helps to reduce the probability of bridging between the bit line structure and the word line structure 12 and the word line contact structure subsequently formed, thereby reducing the probability of leakage or short circuit, and improving product yield.

[0106] In an exemplary embodiment of the present disclosure, forming the barrier layer 2 covering the sidewalls of the bit line trench 101 (and step S120) may include steps S310 to S330, wherein:

[0107] In step S310 , a barrier material layer 210 is formed on the sidewalls and bottom of the bit line trench 101 .

[0108] like Figure 6 As shown, the material of the barrier material layer 210 can be a material having ion blocking properties, such as titanium nitride or tantalum nitride. The barrier material layer 210 can be formed on the sidewalls (e.g., insulating portion 112) and bottom (e.g., top surface of semiconductor pillar 111) of the bitline trench 101 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, for process convenience, the barrier material layer 210 can also be formed simultaneously on top of the insulating portion 112. That is, the barrier material layer 210 can be formed on the surface of the structure formed by the insulating portion 112 and the semiconductor pillar 111. The thickness of the barrier material layer 210 can range from 1 nm to 3 nm, for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. Of course, other thicknesses are also possible and are not listed here.

[0109] In step S320 , the barrier material layer 210 is processed by a reverse sputtering process, so that the thickness of the barrier material layer 210 at the end close to the semiconductor pillar 111 is greater than the thickness at the side away from the semiconductor pillar 111 .

[0110] The blocking material layer 210 can be processed by a reverse sputtering process. During this process, at least a portion of the blocking material layer 210 at the bottom of the bit line trench 101 can be sputtered onto the side wall of the bit line trench 101, thereby causing the end of the blocking material layer 210 covering the side wall of the bit line trench 101 close to the semiconductor pillar 111 to show a material accumulation phenomenon. At this time, the thickness of the end of the blocking material layer 210 covering the side wall of the bit line trench 101 close to the semiconductor pillar 111 is greater than the thickness of the side away from the semiconductor pillar 111.

[0111] In step S330, the blocking material layer 210 is etched back to expose the top surface of the semiconductor pillar 111, and the end of the blocking material layer 210 away from the semiconductor pillar 111 is lower than the surface of the insulating portion 112 away from the word line structure 12, and the remaining blocking material layer 210 is used as the blocking layer 2; the surface of the bit line structure away from the semiconductor pillar 111 is flush with the end of the blocking layer 2 away from the semiconductor pillar 111.

[0112] The barrier material layer 210 can be etched back to expose the surface of the semiconductor pillar 111 at the bottom of the bit line trench 101. In this process, the barrier material layer 210 located on the top of the insulating portion 112 can also be removed at the same time, thereby disconnecting the barrier material layers 210 in different bit line trenches 101 from each other, and making the end of the barrier material layer 210 away from the semiconductor pillar 111 lower than the surface of the insulating portion 112 away from the word line structure 12. The remaining barrier material layer 210 in the bit line trench 101 after the back etching can be used as the barrier layer 2. In the embodiment of the present disclosure, the structure after completing step S330 is as follows: Figure 5 shown.

[0113] like Figure 1 As shown, in step S130 , a conductive material layer 3 is formed in the bit line trench 101 having the barrier layer 2 .

[0114] like Figure 7 As shown, the material of the conductive material layer 3 can be a metal or a non-metal with good conductivity, for example, cobalt (Co). The conductive material can be filled into the bit line trench 101 having the barrier layer 2 (i.e., the conductive material contacts the top surface of the semiconductor pillar 111) by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The conductive material can completely fill the bit line trench 101. The conductive material can then be etched back to make the surface of the conductive material flush with the end of the barrier layer 2 away from the semiconductor pillar 111. The conductive material remaining in the bit line trench 101 after the etch back can be used as the conductive material layer 3.

[0115] like Figure 1 As shown, in step S140 , the conductive material layer 3 is subjected to a heat treatment to form a bit line structure 4 .

[0116] In an exemplary embodiment of the present disclosure, the conductive material layer 3 may be heat-treated at a preset temperature, which may be less than 450° C. For example, the preset temperature may be 450° C., 440° C., 430° C., 420° C., 410° C., or 400° C. Of course, other temperatures are also possible and are not listed here.

[0117] Under the influence of the preset temperature, the metal ions in the conductive material layer 3 can diffuse into the semiconductor column 111, thereby forming a first conductive layer 41 at the interface between the semiconductor column 111 and the conductive material layer 3; for example, when the material of the semiconductor column 111 is silicon and the material of the conductive material layer 3 is cobalt (Co), the material of the first conductive layer 41 can be cobalt silicide (CoSi). The conductive material layer 3 that has not reacted after the heat treatment can be used as the second conductive layer 42 (its material is still cobalt (Co)). The second conductive layer 42 and the first conductive layer 41 together constitute the bit line structure 4. In the embodiment of the present disclosure, the structure after completing step S140 is as follows Figure 8 shown.

[0118] It should be noted that in the present disclosure, only one heat treatment is required during the formation of the bitline structure 4. In the bitline structure 4, the resistance of the second conductive layer 42 is relatively low. Even if the resistance of the first conductive layer 41 is relatively high, the combination of the second conductive layer 42 and the first conductive layer 41 can reduce the overall resistance of the bitline structure 4. Compared to the existing solution of forming CoSi through a first heat treatment and then forming CoSi2 with relatively low resistance through a second heat treatment, the present disclosure can ensure that the bitline structure 4 has a low resistance while eliminating one heat treatment process, thereby simplifying the process and reducing manufacturing costs.

[0119] In an exemplary embodiment of the present disclosure, after forming the bit line structure 4, the method for forming the semiconductor structure 100 of the present disclosure may further include steps S410 and S420, wherein:

[0120] In step S410 , a passivation layer 7 is formed on the surface of the structure formed by the barrier layer 2 , the bit line structure 4 , and the insulating portion 112 .

[0121] A passivation layer 7 can be formed on the surface of the structure formed by the barrier layer 2, the bitline structure 4, and the insulating portion 112 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The passivation layer 7 can fill the remaining gap in the bitline trench 101. The passivation layer 7 can be made of an insulating material. The passivation layer 7 can be used to insulate and isolate the surface of the bitline structure 4, thereby reducing the probability of leakage or short circuit between the bitline structure 4 and other subsequently formed structures. For example, the passivation layer 7 can be made of silicon nitride.

[0122] In step S420 , chemical mechanical polishing is performed on the surface of the passivation layer 7 so that the surface of the passivation layer 7 is flush with the surface of the insulating portion 112 away from the word line structure 12 .

[0123] In some embodiments of the present disclosure, a chemical mechanical polishing process can be used to planarize the surface of the passivation layer 7. During this process, the surface of the insulating portion 112 can also be polished synchronously to make the surface of the passivation layer 7 flush with the surface of the insulating portion 112, so as to provide a flat process reference for subsequent processes. In the embodiment of the present disclosure, the structure after completing step S420 is as follows: Figure 9 shown.

[0124] like Figure 1 As shown, in step S150 , a contact hole 102 is formed penetrating the insulating portion 112 and exposing the word line structure 12 .

[0125] like Figure 10As shown, a contact hole 102 can be formed by etching through the insulating portion 112 and exposing the word line structure 12. In a direction parallel to the substrate 11, the cross-section of the contact hole 102 can be circular, elliptical, rectangular, polygonal, or irregular, without particular limitation. The number of contact holes 102 can be one or more, without particular limitation.

[0126] like Figure 1 As shown, in step S160 , an insulating layer 5 is formed on the hole wall of the contact hole 102 .

[0127] The thickness of the insulating layer 5 may be less than 4 nm, for example, it may be 4 nm, 3.5 nm, 3 nm, 2.5 nm or 2 nm, etc., and the thickness of the insulating layer 5 is not particularly limited here. The insulating layer 5 may be formed on the inner wall of the contact hole 102 so as to insulate and isolate the bit line structure 4 from the word line contact structure through the insulating layer 5, thereby helping to reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure subsequently formed in the contact hole 102. In the embodiment of the present disclosure, the structure after completing step S160 is as follows: Figure 11 shown.

[0128] In some embodiments of the present disclosure, in the first direction x, relatively distributed hole walls in the contact hole 102 may be formed by the semiconductor pillar 111, the bit line structure 4, and the passivation layer 7, and the insulating layer 5 may cover the sidewalls of the semiconductor pillar 111, the bit line structure 4, and the passivation layer 7. For example, during the formation of the insulating layer 5, for process convenience, the insulating layer 5 may simultaneously cover the bottom of the contact hole 102 (i.e., the surface of the word line structure 12). Subsequently, the insulating layer 5 at the bottom of the contact hole 102 may be removed by etching to expose the surface of the word line structure 12, so that a word line contact structure subsequently formed in the contact hole 102 can contact the word line structure 12, thereby electrically leading the word line structure 12 out.

[0129] In an exemplary embodiment of the present disclosure, the material of the insulating layer 5 may be silicon nitride. When the material of the blocking layer 2 is titanium nitride or tantalum nitride, since the materials of the insulating layer 5 and the blocking layer 2 are both nitrides, the insulating layer 5 and the blocking layer 2 have better adhesion, and the interface between the insulating layer 5 and the blocking layer 2 is more reliable. Even if the insulating layer 5 at the bottom of the contact hole 102 is damaged to a certain extent on the hole wall when etching back, making it weaker, its barrier effect on metal ions can also be guaranteed, reducing the probability of metal ions diffusing from the bit line structure 4 to the word line structure 12, further reducing the probability of leakage or short circuit, and improving product yield.

[0130] like Figure 1 As shown, in step S170 , a word line contact structure 6 is formed in the contact hole 102 having the insulating layer 5 .

[0131] like Figure 12 As shown, a wordline contact structure 6 can be formed in a contact hole 102 having an insulating layer 5 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. That is, the insulating layer 5 is located between the bitline structure 4 and the wordline contact structure 6. The insulating layer 5 can insulate and isolate the bitline structure 4 from the wordline contact structure 6, thereby reducing the risk of leakage or short circuit between the bitline structure 4 and the wordline contact structure 6. At the same time, because the sidewalls of the bitline trench 101 are covered with a barrier layer 2 (that is, a barrier layer 2 is further provided between the insulating layer 5 and the bitline structure 4), the barrier layer 2 can prevent metal ions in the bitline structure 4 from diffusing into the insulating layer 5 and the wordline contact structure 6 in contact with the insulating layer 5, thereby further reducing the risk of leakage or short circuit between the bitline structure 4 and the wordline contact structure 6, thereby improving product yield.

[0132] In some embodiments of the present disclosure, the wordline contact structure 6 may be made of a conductive material, such as titanium nitride, tungsten, or a combination thereof. For example, the wordline contact structure 6 may include a titanium nitride layer 61 and a tungsten layer 62 . The titanium nitride layer 61 may conformally cover the sidewalls and bottom of the contact hole 102 , while the tungsten layer 62 may be located on the surface of the titanium nitride layer 61 and may completely fill the contact hole 102 . The titanium nitride layer 61 may prevent tungsten in the tungsten layer 62 from diffusing into other surrounding structures, thereby improving device reliability.

[0133] It should be noted that although the steps of the method for forming the semiconductor structure 100 of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0134] The present disclosure also provides a semiconductor structure, such as Figure 12 As shown, the semiconductor structure 100 may include an initial semiconductor structure 1, a barrier layer 2, a bit line structure 4, a word line contact structure 6, and an insulating layer 5, wherein:

[0135] The initial semiconductor structure 1 includes a substrate 11 and a wordline structure 12. The substrate 11 includes a plurality of spaced-apart semiconductor pillars 111 and a plurality of insulating portions 112 located between two adjacent semiconductor pillars 111. The wordline structure 12 extends along the direction in which the plurality of semiconductor pillars 111 are spaced apart and wraps around the periphery of each semiconductor pillar 111. The insulating portion 112 is located above the wordline structure 12, and an end of the insulating portion 112 away from the wordline structure 12 is higher than an end of the semiconductor pillar 111. Two adjacent insulating portions 112 and the semiconductor pillar 111 therebetween define a bitline trench 101.

[0136] The barrier layer 2 covers the sidewalls of the bit line trench 101;

[0137] The bit line structure 4 is at least partially located in the bit line trench 101 having the barrier layer 2;

[0138] The word line contact structure 6 passes through an insulating portion 112 and is in contact with the word line structure 12;

[0139] The insulating layer 5 is located between the word line contact structure 6 and the barrier layer 2 , the bit line structure 4 and the semiconductor pillar 111 .

[0140] In the semiconductor structure 100 disclosed herein, since the insulating layer 5 is located between the bit line structure 4 and the word line contact structure 6, the bit line structure 4 and the word line contact structure 6 can be insulated and isolated by the insulating layer 5, which helps to reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6; at the same time, since the sidewalls of the bit line groove 101 are covered with the barrier layer 2 (that is, a barrier layer 2 is also provided between the insulating layer 5 and the bit line structure 4), the barrier layer 2 can prevent metal ions in the bit line structure 4 from diffusing into the insulating layer 5 and the word line contact structure 6 in contact with the insulating layer 5, which helps to further reduce the risk of leakage or short circuit between the bit line structure 4 and the word line contact structure 6 and improve product yield.

[0141] The following describes in detail the various parts and details of the semiconductor structure 100 disclosed herein:

[0142] like Figure 2 As shown, the substrate 11 may include a plurality of semiconductor pillars 111 arranged in an array, with each semiconductor pillar 111 arranged in rows and / or columns. For example, the substrate 11 may include a plurality of semiconductor groups, each semiconductor group including a plurality of semiconductor pillars 111 spaced apart along a first direction x, and each semiconductor group spaced apart along a second direction y. The second direction y intersects the first direction x; for example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that perpendicularity can be either absolutely perpendicular or approximately perpendicular, and deviations are inevitable during the manufacturing process. In the present disclosure, angular deviations may occur due to manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y may be considered perpendicular. For example, the preset range may be 10°, meaning that the first direction x and the second direction y may be considered perpendicular if the angle between the first direction x and the second direction y is within a range greater than or equal to 80° and less than or equal to 100°.

[0143] like Figure 3As shown, the insulating portion 112 may be located between two adjacent semiconductor pillars 111 along the first direction x and may fill the gap between the two adjacent semiconductor pillars 111. In some embodiments of the present disclosure, there may be multiple insulating portions 112, with one insulating portion 112 being provided between every two adjacent semiconductor pillars 111 along the first direction x. For example, the insulating portion 112 may be strip-shaped and may extend along the second direction y. Multiple insulating portions 112 may be spaced apart along the first direction x.

[0144] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 and Figure 3 As shown, the wordline structure 12 may be strip-shaped, extend along a first direction x, and wrap around the periphery of each semiconductor pillar 111 spaced apart along the first direction x, with a gate oxide layer 13 formed between the wordline structure 12 and the semiconductor pillar 111. An insulating portion 112 may be located above the wordline structure 12 and may contact the wordline structure 12. In some embodiments of the present disclosure, the end of the insulating portion 112 away from the wordline structure 12 is higher than the end of the semiconductor pillar 111, and two adjacent insulating portions 112 and the semiconductor pillar 111 therebetween jointly define a bitline trench 101.

[0145] In an exemplary embodiment of the present disclosure, the surface of the word line structure 12 away from the insulating portion 112 is lower than the surface of the semiconductor column 111 away from the bit line trench 101, and the area of ​​the semiconductor column 111 not covered by the word line structure 12 and the insulating portion 112 can be ion doped to form a source region 111a, and a capacitor structure (not shown in the figure) can be formed on the source region 111a.

[0146] like Figure 5 As shown, barrier layer 2 can be a thin film covering the sidewalls (e.g., insulating portion 112) of bitline trench 101, or a coating covering the sidewalls of bitline trench 101. The specific form of barrier layer 2 is not particularly limited herein. The bottom end of barrier layer 2 can contact the top end of semiconductor pillar 111. Barrier layer 2 can be made of a material having an ion barrier function, such as titanium nitride or tantalum nitride.

[0147] The thickness of the blocking layer 2 may include 1nm to 3nm, for example, it may be 1nm, 1.5nm, 2nm, 2.5nm or 3nm. Of course, it may also be other thicknesses that are not listed here one by one. In some embodiments of the present disclosure, the thickness of each region of the blocking layer 2 may not be exactly the same in the depth direction of the bit line trench 101. For example, the thickness of the end of the blocking layer 2 close to the semiconductor pillar 111 is greater than the thickness of the side away from the semiconductor pillar 111, so as to reduce the risk of metal ions in the conductive material layer 3 subsequently formed inside the bit line trench 101 diffusing along the interface between the insulating portion 112 and the semiconductor pillar 111 to the word line structure 12 below the insulating portion 112 and the word line contact structure subsequently formed through the insulating portion 112, which helps to reduce the probability of bridging between the bit line structure 4 and the word line structure 12 and the word line contact structure subsequently formed, thereby reducing the probability of leakage or short circuit, and improving product yield.

[0148] like Figure 8 As shown, the bitline structure 4 may be at least partially located within the bitline trench 101 having the barrier layer 2. For example, the bitline structure 4 may include a first conductive layer 41 and a second conductive layer 42. The second conductive layer 42 may be located within the bitline trench 101 above the semiconductor pillar 111. The material of the second conductive layer 42 may be a metal material, for example, cobalt (Co). The first conductive layer 41 may be an interface layer formed between the second conductive layer 42 and the semiconductor pillar 111 as metal ions (e.g., cobalt (Co)) in the second conductive layer 42 diffuse into the semiconductor pillar 111. That is, the first conductive layer 41 may be located on top of the semiconductor pillar 111, the barrier layer 2 may contact the first conductive layer 41 near the end of the semiconductor pillar 111, and the second conductive layer 42 may be located within the bitline trench 101 having the barrier layer 2 and contact the surface of the first conductive layer 41. When the material of the semiconductor pillar 111 is silicon, the material of the first conductive layer 41 can be metal silicide (such as cobalt silicide (CoSi)), the material of the second conductive layer 42 can be metal (such as cobalt (Co)), and the first conductive layer 41 and the second conductive layer 42 include the same metal.

[0149] In an exemplary embodiment of the present disclosure, Figure 9 As shown, the semiconductor structure 100 of the present disclosure may further include a passivation layer 7. The passivation layer 7 may be located on the surface of the bitline structure 4. The passivation layer 7 may fill the remaining gap in the bitline trench 101, and its surface away from the bitline structure 4 is flush with the surface of the insulating portion 112 away from the wordline structure 12. The passivation layer 7 may be made of an insulating material. The passivation layer 7 may be used to insulate and isolate the surface of the bitline structure 4, thereby reducing the probability of leakage or short circuit between the bitline structure 4 and other subsequently formed structures. For example, the passivation layer 7 may be made of silicon nitride.

[0150] like Figure 12As shown, the word line contact structure 6 may pass through an insulating portion 112 and be in contact with the word line structure 12. In the direction parallel to the substrate 11, the cross-section of the word line contact structure 6 may be circular, elliptical, rectangular, polygonal or irregular in shape, which is not particularly limited here. In some embodiments of the present disclosure, the material of the word line contact structure 6 may be a conductive material, for example, it may include titanium nitride, tungsten or a combination thereof. For example, the word line contact structure 6 may include a titanium nitride layer 61 and a tungsten layer 62, wherein the titanium nitride layer 61 may be conformally coated on the bottom and sidewalls of the tungsten layer 62, and the titanium nitride layer 61 may be in contact with the surface of the word line structure 12, and the titanium nitride layer 61 may prevent the tungsten in the tungsten layer 62 from diffusing into other surrounding structures, thereby helping to improve device reliability.

[0151] In an exemplary embodiment of the present disclosure, an insulating layer 5 may be provided between the wordline contact structure 6 and the barrier layer 2, the bitline structure 4, and the semiconductor pillar 111. The thickness of the insulating layer 5 may be less than 4 nm, for example, 4 nm, 3.5 nm, 3 nm, 2.5 nm, or 2 nm, and the thickness of the insulating layer 5 is not particularly limited herein. The insulating layer 5 may be located on the sidewalls of the wordline contact structure 6 to facilitate insulation isolation between the bitline structure 4 and the wordline contact structure 6 via the insulating layer 5, thereby reducing the risk of leakage or short circuit between the bitline structure 4 and the wordline contact structure 6.

[0152] In an exemplary embodiment of the present disclosure, the material of the insulating layer 5 may be silicon nitride. When the material of the blocking layer 2 is titanium nitride or tantalum nitride, since the materials of the insulating layer 5 and the blocking layer 2 are both nitrides, the insulating layer 5 and the blocking layer 2 have better adhesion, and the interface between the insulating layer 5 and the blocking layer 2 is more reliable. Even if the insulating layer 5 at the bottom of the contact hole 102 is damaged to a certain extent on the hole wall when etching back, making it weaker, its barrier effect on metal ions can also be guaranteed, reducing the probability of metal ions diffusing from the bit line structure 4 to the word line structure 12, further reducing the probability of leakage or short circuit, and improving product yield.

[0153] The present disclosure also provides a memory device, such as Figure 13 As shown, the memory may include the semiconductor structure 100 in any of the above embodiments, and its specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure 100 and the formation method of the semiconductor structure 100, which will not be repeated here.

[0154] In some embodiments of the present disclosure, the memory of the present disclosure may further include a peripheral circuit 200 , and the peripheral circuit 200 may be bonded to the word line contact structure 6 in the semiconductor structure 100 of the present disclosure.

[0155] For example, during the manufacturing process, the peripheral circuit 200 can be processed separately from the semiconductor structure 100, that is, the peripheral circuit 200 can be formed on a substrate, and then the substrate carrying the peripheral circuit 200 can be coupled to the word line contact structure 6 in the semiconductor structure 100 of the present invention by bonding, so that the peripheral circuit 200 is electrically connected to the word line structure 12 in the semiconductor structure 100, so that the word line structure 12 can be controlled to be opened or closed by the peripheral circuit 200.

[0156] For example, the memory may be a 4F2 3D dynamic random access memory (DRAM) or a static random access memory (SRAM), etc. Of course, other storage devices may also be used, which are not listed here one by one.

[0157] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: An initial semiconductor structure is formed, the initial semiconductor structure comprising a substrate and a wordline structure, the substrate comprising a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions respectively located between two adjacent semiconductor pillars, the wordline structure extending along the direction in which the plurality of semiconductor pillars are spaced-apart and covering the periphery of each semiconductor pillar; the insulating portion is located above the wordline structure, and an end of the insulating portion away from the wordline structure is higher than an end of the semiconductor pillar; two adjacent insulating portions and the semiconductor pillar therebetween define a bitline trench; forming a barrier layer covering sidewalls of the bit line trench; forming a conductive material layer in the bit line trench having the barrier layer; performing a heat treatment on the conductive material layer to form a bit line structure; forming a contact hole penetrating the insulating portion and exposing the word line structure; forming an insulating layer on a hole wall of the contact hole; A word line contact structure is formed in the contact hole having the insulating layer.

2. The forming method according to claim 1, wherein: The forming of a barrier layer covering the sidewall of the bit line trench comprises: forming a barrier material layer on the sidewalls and bottom of the bit line trench; Processing the barrier material layer by a reverse sputtering process so that the thickness of the barrier material layer at an end portion close to the semiconductor pillar is greater than the thickness at a side away from the semiconductor pillar; The barrier material layer is etched back to expose the top surface of the semiconductor column, and the end of the barrier material layer away from the semiconductor column is lower than the surface of the insulating portion away from the word line structure, and the remaining barrier material layer is used as the barrier layer; the surface of the bit line structure away from the semiconductor column is flush with the end of the barrier layer away from the semiconductor column.

3. The forming method according to claim 2, wherein: The thickness of the barrier layer is 1 nm to 3 nm; the material of the barrier layer includes titanium nitride or tantalum nitride.

4. The forming method according to claim 2, wherein: The forming method further comprises: forming a passivation layer on a surface of a structure formed by the barrier layer, the bit line structure, and the insulating portion; Chemical mechanical polishing is performed on the surface of the passivation layer so that the surface of the passivation layer is flush with the surface of the insulating portion away from the word line structure.

5. The forming method according to any one of claims 1 to 4, characterized in that: The step of performing a heat treatment on the conductive material layer to form a bit line structure includes: heat-treating the conductive material layer at a preset temperature so that metal ions in the conductive material layer diffuse into the semiconductor pillar to form a first conductive layer at the interface between the semiconductor pillar and the conductive material layer; and using the conductive material layer after the heat treatment as a second conductive layer; The preset temperature is less than 450°C.

6. The forming method according to any one of claims 1 to 4, characterized in that: Forming the initial semiconductor structure includes: Providing a substrate, the substrate comprising a plurality of first trenches spaced apart and distributed along a first direction, and an insulating material filling the first trenches; Etching the substrate to form a plurality of second trenches spaced apart along a second direction, wherein the second direction intersects the first direction, and each of the second trenches and each of the first trenches divides the substrate into a plurality of semiconductor pillars; Etching back the insulating material to form an insulating portion; forming a word line structure extending along the first direction and covering the periphery of each of the semiconductor pillars spaced apart along the first direction, wherein the word line structure is located on the insulating portion, and a surface thereof away from the insulating portion is lower than a surface of the semiconductor pillar away from the bottom of the first trench; doping an area of ​​the semiconductor column that is not covered by the word line structure and the insulating portion to form a source region; forming a capacitor structure on the source region; The substrate is etched at a side of the substrate away from the capacitor structure to form the bit line trench.

7. A semiconductor structure, characterized in that include: An initial semiconductor structure includes a substrate and a wordline structure. The substrate includes a plurality of spaced-apart semiconductor pillars and a plurality of insulating portions located between two adjacent semiconductor pillars. The wordline structure extends along the direction in which the plurality of semiconductor pillars are spaced-apart and covers the periphery of each semiconductor pillar. The insulating portion is located above the wordline structure, and an end of the insulating portion away from the wordline structure is higher than an end of the semiconductor pillar. Two adjacent insulating portions and the semiconductor pillar therebetween define a bitline trench. a barrier layer covering the sidewalls of the bit line trench; a bit line structure at least partially located within the bit line trench having the barrier layer; A word line contact structure, passing through the insulating portion and being in contact with the word line structure; An insulating layer is located between the word line contact structure and the barrier layer, the bit line structure and the semiconductor pillar.

8. The semiconductor structure according to claim 7, wherein: The thickness of the barrier layer at an end portion close to the semiconductor pillar is greater than the thickness of the barrier layer at a side away from the semiconductor pillar.

9. The semiconductor structure according to claim 7, wherein: The material of the barrier layer includes titanium nitride or tantalum nitride, and the thickness of the barrier layer includes 1 nm to 3 nm.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: The bit line structure includes a first conductive layer and a second conductive layer, the first conductive layer is located at the top of the semiconductor column, the barrier layer is in contact with the first conductive layer near the end of the semiconductor column, and the second conductive layer is located in the bit line trench having the barrier layer and in contact with the surface of the first conductive layer.

11. The semiconductor structure according to claim 10, wherein: The semiconductor structure further comprises: The passivation layer is located on the surface of the bit line structure, and the surface of the passivation layer away from the bit line structure is flush with the surface of the insulating portion away from the word line structure.

12. The semiconductor structure according to claim 10, wherein: The surface of the word line structure away from the insulating portion is lower than the surface of the semiconductor pillar away from the bit line trench, and the area of ​​the semiconductor pillar not covered by the word line structure and the insulating portion is a source region. The initial semiconductor structure further includes: A capacitor structure is formed on the source region.

13. A memory, characterized in that: The semiconductor structure comprises the semiconductor structure according to any one of claims 7 to 12.

14. The memory according to claim 13, wherein: The memory further comprises: The peripheral circuit is bonded to the word line contact structure of the semiconductor structure.

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