Preparation method of ETOX NOR type flash memory device

Abstract

The invention provides a preparation method of an ETOX NOR type flash memory device, and the method comprises the steps: carrying out the spin-coating of a first spin-coating carbon layer on a storage region and a peripheral logic region, taking the first spin-coating carbon layer as a mask of the peripheral logic region, and carrying out the first thinning of a control gate material layer of the storage region through a one-time etchback technology; furthermore, after the self-aligned source line ion implantation, a second spin-coating carbon layer is spin-coated, and the second spin-coating carbon layer is used as a mask of a peripheral logic region to carry out second thinning on the storage region control gate material layer through the re-etching process again, so that a final storage region control gate is obtained. According to the preparation method of the ETOX NOR type flash memory device provided by the invention, the depth-to-width ratio of the first deep groove and the second deep groove between the control gates can be reduced, the filling window of the interlayer insulating dielectric layer is enlarged, and meanwhile, the production cost can be saved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing an ETOX NOR flash memory device. Background Art

[0002] In order to increase the filling window of the interlayer insulating dielectric layer (equivalent to reducing the aspect ratio of the deep trenches between the control gates), the current 4X nanometer NOR Flash process platform usually adds a photolithography and etching process after the control gate material layer is deposited, and the flat (flat) control gate material layer of the storage area is thinned to a certain thickness through the back etching process. Furthermore, after etching to form the deep trenches in the storage area and the SAS (self-aligned source, self-aligned source line injection) process, another layer of photolithography and etching process is added to thin the strip-shaped control gate of the storage area to a certain thickness again. It can be seen that the preparation method of the traditional ETOX NOR flash memory device needs to add the above two photolithography and etching processes to thin the control gate and thereby achieve the purpose of increasing the filling window of the interlayer insulating dielectric layer, resulting in high manufacturing costs. Summary of the invention

[0003] The present application provides a method for preparing an ETOX NOR flash memory device, which can solve the problem of high manufacturing cost of increasing the filling window of the interlayer insulating dielectric layer (reducing the aspect ratio of the deep trench between the control gates) in the traditional method for preparing the ETOX NOR flash memory device.

[0004] The present application embodiment provides a method for preparing an ETOX NOR flash memory device, comprising: A substrate is provided, wherein the substrate comprises a storage area and a peripheral logic area, wherein a pad oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are sequentially formed on the substrate surface of the storage area, and a gate oxide layer and a control gate material layer are sequentially formed on the substrate surface of the peripheral logic area; Etching the control gate material layer, the ONO dielectric layer, the floating gate material layer and the pad oxide layer of the storage area to the surface of the substrate to form a plurality of first deep trenches and second deep trenches, wherein the first deep trenches and the second deep trenches are arranged in a staggered manner; forming a first spin-on carbon layer, wherein the first spin-on carbon layer fills the first deep trench and the second deep trench, and covers the control gate material layer of the storage area and the control gate material layer of the peripheral logic area; By means of an etch-back process, the first spin-on carbon layer of a certain thickness is etched, and at the same time, a control gate material layer of a first thickness of the storage area is etched back; removing the remaining thickness of the first spin-on carbon layer; Forming a source line ion implantation region in the substrate at the bottom of the first deep trench by a self-aligned implantation process; forming a second spin-on carbon layer, wherein the second spin-on carbon layer fills the first deep trench and the second deep trench, and covers the control gate material layer of the storage area and the control gate material layer of the peripheral logic area; Etching the second spin-on carbon layer of a certain thickness through an etch-back process, and at the same time, etching back the control gate material layer of a second thickness of the storage area; and The remaining thickness of the second spin-on carbon layer is removed.

[0005] Optionally, in the preparation method of the ETOX NOR flash memory device, the first spin-coated carbon layer of a certain thickness is etched through a back etching process. At the same time, in the process of back etching the control gate material layer of the first thickness of the storage area, the etching gas includes: SO2 and O2, the flow rate of SO2 gas is 50sccm~100sccm; the flow rate of O2 gas is 10sccm~30sccm; the etching time is 50s~100s; and the process temperature is 20℃~60℃.

[0006] Optionally, in the preparation method of the ETOX NOR flash memory device, the second spin-coated carbon layer of a certain thickness is etched through a back etching process. At the same time, in the process of back etching the control gate material layer of the second thickness of the storage area, the etching gas includes: HBr and O2, the flow rate of HBr gas is 200sccm~500sccm; the etching time is 200s~400s; the process temperature is 40℃~60℃.

[0007] Optionally, in the method for preparing the ETOX NOR flash memory device, before etching back the control gate material layer of the first thickness of the storage area, the thickness of the control gate material layer of the storage area is 2000Å~2100Å.

[0008] Optionally, in the method for preparing the ETOX NOR flash memory device, a first thickness of the control gate material layer of the storage area that is etched back and removed is 350Å-450Å.

[0009] Optionally, in the method for preparing the ETOX NOR flash memory device, the second thickness of the control gate material layer of the storage area that is etched back and removed is 600Å-700Å.

[0010] Optionally, in the method for preparing the ETOX NOR flash memory device, after forming the plurality of first deep trenches and the second deep trenches and before forming the first spin-on carbon layer, the method for preparing the ETOX NOR flash memory device further comprises: Through an ion implantation process, lightly doped drain regions are correspondingly formed in the substrate at the bottom of the first deep trench and the second deep trench.

[0011] Optionally, in the method for preparing the ETOX NOR flash memory device, the step of forming a source line ion implantation region in the substrate at the bottom of the first deep trench by a self-aligned implantation process comprises: A source line ion implantation region is formed at the bottom of the lightly doped drain region at the bottom of the first deep trench through a self-aligned implantation process.

[0012] Optionally, in the method for preparing the ETOX NOR flash memory device, after removing the remaining thickness of the second spin-on carbon layer, the method for preparing the ETOX NOR flash memory device further comprises: The control gate material layer and the gate oxide layer of the peripheral logic region are etched to form a plurality of third deep trenches.

[0013] The technical solution of this application has at least the following advantages: The present application adjusts the order of self-aligned source line ion implantation and etching of the control gate material layer of the peripheral logic area, adjusts the self-aligned source line ion implantation to before etching the control gate material layer of the peripheral logic area, and before the self-aligned source line ion implantation, spin-coats a first spin-on carbon layer (SOC) on the storage area and the peripheral logic area, utilizes the height difference between the first spin-on carbon layer on the control gate material layer of the storage area and the first spin-on carbon layer on the control gate material layer of the peripheral logic area, and uses the first spin-on carbon layer as a mask of the peripheral logic area to perform a first thinning of the storage area control gate material layer through a back-etching process; further, after the self-aligned source line ion implantation, spin-coats a second spin-on carbon layer (SOC), performs a second back-etching process again, and uses the second spin-on carbon layer as a mask of the peripheral logic area to perform a second thinning of the storage area control gate material layer, thereby obtaining a final storage area control gate. Compared with the conventional ETOX NOR flash memory device preparation method, the ETOX NOR flash memory device provided by the present application has a novel structure, a novel structure, and a novel structure. The preparation method of the NOR flash memory device can save two layers of masks / two photolithography processes, save production costs, and at the same time, can reduce the aspect ratio of the first deep trench and the second deep trench between the control gates, and increase the filling window of the interlayer insulating dielectric layer.

[0014] In addition, the thickness of the control gate material layer of different devices (high voltage devices, medium voltage devices, low voltage devices, etc.) in the peripheral logic area is no different from that of traditional ETOX NOR flash memory devices, so there is no need to additionally adjust the thickness of the control gate material layer in the peripheral logic area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 is a flow chart of a method for preparing an ETOX NOR flash memory device according to an embodiment of the present invention; Figure 2-Figure 9 It is a schematic diagram of the semiconductor structure in each process step of preparing an ETOX NOR flash memory device according to an embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 11-lightly doped drain region, 12-source line ion implantation region, 21-pad oxide layer, 22-gate oxide layer, 30-floating gate material layer, 40-ONO dielectric layer, 50-control gate material layer, 51-first deep trench, 52-second deep trench, 53-third deep trench, 61-first spin-coated carbon layer, 62-second spin-coated carbon layer. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] The present application embodiment provides a method for preparing an ETOX NOR flash memory device, referring to Figure 1-Figure 9 , Figure 1 is a flow chart of a method for preparing an ETOX NOR flash memory device according to an embodiment of the present invention; Figure 2-Figure 9 1 is a schematic diagram of a semiconductor structure in each process step of preparing an ETOX NOR flash memory device according to an embodiment of the present invention. The method for preparing the ETOX NOR flash memory device includes: First, refer to Figure 2 , Figure 2 It is a schematic diagram of the semiconductor structure after the first deep trench and the second deep trench are formed in an embodiment of the present application. A substrate 10 is provided, and the substrate 10 includes a storage area and a peripheral logic area. A pad oxide layer 21, a floating gate material layer 30, an ONO dielectric layer 40 and a control gate material layer 50 are sequentially formed on the surface of the substrate 10 in the storage area, and a gate oxide layer 22 and a control gate material layer 50 are sequentially formed on the surface of the substrate 10 in the peripheral logic area.

[0022] In this embodiment, the conductivity type of the doped ions in the substrate of the storage area is P type. Several shallow trench isolation structures (not shown) for isolating different storage cells may also be formed in the substrate of the storage area. In addition, a deep N well, a high-voltage P well on the deep N well, and a CVT region (not shown) on the high-voltage P well may also be formed in the substrate of the storage area.

[0023] Furthermore, the peripheral logic region may include multiple device regions, such as a high-voltage device region, a medium-voltage device region, and a low-voltage device region, and a respective well region (not shown) is formed in the substrate of each device region. In addition, in the peripheral logic region, the thickness of the gate oxide layer 22 of different device regions is different. Specifically, the thickness of the gate oxide layer 22 of the high-voltage device region is greater than the thickness of the gate oxide layer 22 of the medium-voltage device region, and greater than the thickness of the gate oxide layer 22 of the low-voltage device region.

[0024] Then, continue to refer to Figure 2 , etching the control gate material layer 50, the ONO dielectric layer 40, the floating gate material layer 30 and the pad oxide layer 21 of the storage area to the surface of the substrate 10 to form a plurality of first deep trenches 51 and second deep trenches 52, wherein the first deep trenches 51 and the second deep trenches 52 are arranged alternately.

[0025] In this embodiment, the photoresist layer can be used as a mask to protect the peripheral logic area, and the control gate material layer 50, ONO dielectric layer 40, floating gate material layer 30 and pad oxide layer 21 of the storage area are etched to the surface of the substrate 10 using a dry etching process to form a plurality of first deep trenches 51 and second deep trenches 52.

[0026] For further reference, Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after the lightly doped drain region is formed in an embodiment of the present application. After forming a plurality of first deep trenches 51 and a second deep trench 52, and before forming a first spin-on carbon layer, the method for preparing the ETOX NOR flash memory device may further include: forming a plurality of lightly doped drain regions 11 in the substrate at the bottom of the first deep trenches 51 and the second deep trenches 52 correspondingly through an ion implantation process.

[0027] In this embodiment, the conductivity type of the doping ions in the lightly doped drain region 11 is N-type doping.

[0028] Next, refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after the first spin-coated carbon layer is formed in an embodiment of the present application, forming a first spin-coated carbon layer 61, which fills the first deep trench 51 and the second deep trench 52, and covers the control gate material layer 50 of the storage area and the control gate material layer 50 of the peripheral logic area.

[0029] It is worth noting that the first spin-on carbon layer 61 is made of SOC material, which has a strong filling capacity, and its anti-etching performance and ease of removal are better than those of photoresist.

[0030] For further reference, Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after the first spin-on carbon layer and the control gate material layer are etched back in an embodiment of the present application. Through the back etching process, the first spin-on carbon layer 61 of a certain thickness is etched, and at the same time, the control gate material layer 50 of the first thickness of the storage area is etched back.

[0031] Preferably, the first spin-coated carbon layer 61 of a certain thickness is etched through a back etching process. At the same time, in the process of back etching the control gate material layer 50 of the first thickness of the storage area, the etching gases include: SO2 and O2, the flow rate of SO2 gas is 50sccm~100sccm; the flow rate of O2 gas is 10sccm~30sccm; the etching time is 50s~100s; and the process temperature is 20℃~60℃.

[0032] Next, refer to Figure 6 , Figure 6 It is a schematic diagram of the semiconductor structure after the source line ion implantation region is formed in the embodiment of the present application, and the remaining thickness of the first spin-on carbon layer 61 is removed.

[0033] In this embodiment, a dry strip and wet strip process is used to remove the remaining thickness of the first spin-on carbon layer 61 .

[0034] For further information, please refer to Figure 6 , through a self-aligned implantation process, a source line ion implantation region 12 is formed at the bottom of the lightly doped drain region at the bottom of the first deep trench.

[0035] In this embodiment, the conductivity types of the doped ions in the source line ion implantation region 12 are P type and N type.

[0036] Next, refer to Figure 7 , Figure 7 It is a schematic diagram of the semiconductor structure after the second spin-coated carbon layer is formed in an embodiment of the present application, forming a second spin-coated carbon layer 62, which fills the first deep trench 51 and the second deep trench 52, and covers the control gate material layer 50 of the storage area and the control gate material layer 50 of the peripheral logic area.

[0037] For further reference, Figure 8 , Figure 8 It is a schematic diagram of the semiconductor structure after the second spin-on carbon layer and the control gate material layer are etched back in an embodiment of the present application. Through the back etching process, the second spin-on carbon layer 62 of a certain thickness is etched, and at the same time, the control gate material layer 50 of the second thickness of the storage area is etched back.

[0038] Specifically, the second spin-coated carbon layer 62 of a certain thickness is etched through the back etching process. At the same time, in the process of back etching the second thickness of the control gate material layer 50 of the storage area, the etching gas includes: HBr and O2, the flow rate of HBr gas is 200sccm~500sccm; the etching time is 200s~400s; the process temperature is 40℃~60℃.

[0039] Preferably, before etching back the control gate material layer 50 of the first thickness in the storage area, the thickness of the control gate material layer 50 in the storage area is 2000Å-2100Å. In this embodiment, the thickness of the control gate material layer 50 in the storage area is 2050Å.

[0040] Preferably, the first thickness of the control gate material layer 50 of the storage region removed by etching back is 350Å-450Å. In this embodiment, the first thickness of the control gate material layer 50 of the storage region removed by etching back is 400Å.

[0041] Further, the second thickness of the control gate material layer 50 of the storage region removed by etching back is 600Å-700Å. In this embodiment, the second thickness of the control gate material layer 50 of the storage region removed by etching back is 650Å.

[0042] Finally, reference Fig. 9 , Fig. 9 It is a schematic diagram of the semiconductor structure after the third deep trench is formed in the embodiment of the present application, and the remaining thickness of the second spin-on carbon layer 62 is removed.

[0043] For further information, please refer to Fig. 9 After removing the remaining thickness of the second spin-on carbon layer 62, the method for preparing the ETOXNOR flash memory device may further include: etching the control gate material layer 50 and the gate oxide layer 22 of the peripheral logic region to form a plurality of third deep trenches 53. The control gate material layer 50 is used as the gate of the device in the peripheral logic region, so while etching the control gate material layer 50 and the gate oxide layer 22 of the peripheral logic region to form a plurality of third deep trenches 53, corresponding gates on different device regions (high voltage device region, medium voltage device region, low voltage device region) can be obtained.

[0044] The present application adjusts the order of self-aligned source line ion implantation and etching the control gate material layer of the peripheral logic area, and before the self-aligned source line ion implantation, a first spin-on carbon layer (SOC) is spin-coated on the storage area and the peripheral logic area, and the height difference between the first spin-on carbon layer on the storage area control gate material layer and the first spin-on carbon layer on the peripheral logic area control gate material layer is utilized, and the first spin-on carbon layer is used as a mask of the peripheral logic area, and the storage area control gate material layer is thinned for the first time through a back etching process; further, after the self-aligned source line ion implantation, a second spin-on carbon layer (SOC) is spin-coated, and the storage area control gate material layer is thinned for the second time through a back etching process, so as to obtain the final storage area control gate, reduce the aspect ratio of the first deep trench and the second deep trench between the control gates, and increase the filling window of the interlayer insulating dielectric layer. Compared with the traditional ETOX NOR flash memory device preparation method, the ETOX provided by the present application The preparation method of the NOR flash memory device can save two layers of masks / two photolithography processes, while increasing the filling window of the interlayer insulating dielectric layer, saving production costs. In addition, the thickness of the control gate material layer of the peripheral logic area of ​​the flash memory device provided by the present application is the same as the thickness of the control gate material layer (BSL) of the peripheral logic area of ​​the traditional flash memory device, and there is no need to additionally adjust the peripheral logic area device caused by the difference in the thickness of the control gate material layer.

[0045] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing an ETOX NOR flash memory device, characterized in that: include: A substrate is provided, wherein the substrate comprises a storage area and a peripheral logic area, wherein a pad oxide layer, a floating gate material layer, an ONO dielectric layer and a control gate material layer are sequentially formed on the substrate surface of the storage area, and a gate oxide layer and a control gate material layer are sequentially formed on the substrate surface of the peripheral logic area; Etching the control gate material layer, the ONO dielectric layer, the floating gate material layer and the pad oxide layer of the storage area to the surface of the substrate to form a plurality of first deep trenches and second deep trenches, wherein the first deep trenches and the second deep trenches are arranged in a staggered manner; forming a first spin-on carbon layer, wherein the first spin-on carbon layer fills the first deep trench and the second deep trench, and covers the control gate material layer of the storage area and the control gate material layer of the peripheral logic area; By means of an etch-back process, the first spin-on carbon layer of a certain thickness is etched, and at the same time, a control gate material layer of a first thickness of the storage area is etched back; removing the remaining thickness of the first spin-on carbon layer; Forming a source line ion implantation region in the substrate at the bottom of the first deep trench by a self-aligned implantation process; forming a second spin-on carbon layer, wherein the second spin-on carbon layer fills the first deep trench and the second deep trench, and covers the control gate material layer of the storage area and the control gate material layer of the peripheral logic area; Etching the second spin-on carbon layer of a certain thickness through an etch-back process, and at the same time, etching back the control gate material layer of a second thickness of the storage area; as well as The remaining thickness of the second spin-on carbon layer is removed.

2. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: The first spin-coated carbon layer of a certain thickness is etched through the back etching process. At the same time, in the process of back etching the control gate material layer of the first thickness of the storage area, the etching gases include: SO2 and O2, the flow rate of SO2 gas is 50sccm~100sccm; the flow rate of O2 gas is 10sccm~30sccm; the etching time is 50s~100s; the process temperature is 20℃~60℃.

3. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: The second spin-coated carbon layer of a certain thickness is etched through the back etching process. At the same time, in the process of back etching the second thickness of the control gate material layer of the storage area, the etching gas includes: HBr and O2, the flow rate of HBr gas is 200sccm~500sccm; the etching time is 200s~400s; the process temperature is 40℃~60℃.

4. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: Before etching back the control gate material layer of the first thickness in the storage area, the thickness of the control gate material layer in the storage area is 2000Å-2100Å.

5. The method for preparing the ETOX NOR flash memory device according to claim 4, characterized in that: The first thickness of the control gate material layer of the storage area removed by etching back is 350Å~450Å.

6. The method for preparing the ETOX NOR flash memory device according to claim 5, characterized in that: The second thickness of the control gate material layer of the storage area removed by etching back is 600Å-700Å.

7. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: After forming the plurality of first deep trenches and the second deep trenches and before forming the first spin-on carbon layer, the method for preparing the ETOX NOR flash memory device further includes: Through an ion implantation process, lightly doped drain regions are correspondingly formed in the substrate at the bottom of the first deep trench and the second deep trench.

8. The method for preparing the ETOX NOR flash memory device according to claim 7, characterized in that: The step of forming a source line ion implantation region in the substrate at the bottom of the first deep trench by a self-aligned implantation process comprises: By means of a self-aligned implantation process, a source line ion implantation region is formed at the bottom of the lightly doped drain region at the bottom of the first deep trench.

9. The method for preparing the ETOX NOR flash memory device according to claim 1, characterized in that: After removing the remaining thickness of the second spin-on carbon layer, the method for preparing the ETOX NOR flash memory device further comprises: The control gate material layer and the gate oxide layer of the peripheral logic region are etched to form a plurality of third deep trenches.

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