Isolation composite PNP tube, high-voltage electrostatic protection structure and electronic equipment

Abstract

The application relates to the technical field of electrostatic protection, and particularly discloses an isolated composite PNP tube, a high-voltage electrostatic protection structure and electronic equipment, which comprises a P-type substrate, a P-type epitaxial layer arranged on the P-type substrate, and an N-type buried layer arranged between the P-type substrate and the P-type epitaxial layer; a plurality of spaced active regions are arranged on the surface of the P-type epitaxial layer; the active regions located in the outer region are connected with metal wires and then serve as lead-out ends of an isolated ground end; the plurality of active regions located in the central region are connected with metal wires and then serve as lead-out ends of a collector of a longitudinal PNP tube, a collector of a transverse PNP tube and a base and an emitter shared by the longitudinal PNP tube and the transverse PNP tube; and the active regions located between the outer region and the central region are connected with metal wires and then serve as lead-out ends of an isolated port. The isolated composite PNP tube provided by the application has strong high-voltage electrostatic protection capability and can effectively prevent negative pulse triggering latching when being applied to the high-voltage electrostatic protection structure.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic protection, and in particular to an isolated composite PNP tube, a high-voltage electrostatic protection structure and electronic equipment. Background Art

[0002] With the continuous advancement of modern integrated circuit technology, high-voltage MOS devices have become increasingly easy to integrate into conventional CMOS processes. Due to their high drive current and high breakdown voltage, high-voltage MOS devices are widely used in high-voltage integrated circuits such as driver circuits, power management switches, and motor control systems. However, this presents a challenge: these high-voltage MOS devices must be equipped with corresponding high-voltage electrostatic discharge (ESD) devices for safe and reliable operation. Because they operate at high voltage, high-voltage ESD devices consume high power and generally have weak ESD discharge capabilities. Furthermore, it is difficult to design a holding voltage higher than the operating voltage. Therefore, these high-voltage ESD devices are often not suitable for use on high-voltage power supply pins, as latch-up is likely to occur. Furthermore, in power management and motor drive circuits, some pins often experience negative pulses. When a negative pulse occurs on a pin, the high-voltage ESD device is likely to be affected, forming a PNPN latch-up structure with the N-type region of the negative pulse pin. Once latch-up occurs, the resulting latch-up inevitably damages the circuit, causing instantaneous circuit failure.

[0003] Therefore, how to provide a high-voltage electrostatic protection solution that has both strong high-voltage ESD protection capability and can effectively prevent negative pulses from triggering latch-up has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0004] The present invention provides an isolated composite PNP transistor, a high-voltage electrostatic protection structure and an electronic device, which solve the problem in the related art that it is impossible to have both high-voltage ESD protection capability and prevent negative pulse triggering latch.

[0005] As a first aspect of the present invention, an isolated composite PNP transistor is provided, comprising:

[0006] A P-type substrate, a P-type epitaxial layer disposed on the P-type substrate, and an N-type buried layer disposed between the P-type substrate and the P-type epitaxial layer;

[0007] A plurality of active regions are sequentially arranged at intervals on the surface of the P-type epitaxial layer, and a field region is arranged between every two adjacent active regions, wherein both the active region and the field region extend along the surface of the P-type epitaxial layer toward the P-type substrate;

[0008] The active regions located in the outer regions can be connected to metal wires and serve as lead-out terminals for the isolated ground terminal. The multiple active regions located in the central region can be connected to metal wires and serve as lead-out terminals for the collector of the vertical PNP transistor, the collector of the horizontal PNP transistor, and the base and emitter shared by the vertical and horizontal PNP transistors. The active region located between the outer regions and the central region can be connected to metal wires and serve as lead-out terminals for the isolated port.

[0009] The lead-out end of the collector of the longitudinal PNP tube is connected to the lead-out end of the collector of the lateral PNP tube, the lead-out end of the base shared by the longitudinal PNP tube and the lateral PNP tube is connected to the lead-out end of the emitter, the lead-out end of the isolated ground end is used to connect to the ground pin of the power supply circuit, and the lead-out end of the isolated port is used to connect to the high-voltage pin of the power supply circuit.

[0010] Furthermore, a first active region, a second active region, a third active region, a fourth active region, a fifth active region, a sixth active region, a seventh active region, an eighth active region and a ninth active region are sequentially arranged on the surface of the P-type epitaxial layer.

[0011] Deep P-well regions are provided at the locations of the first active region and the ninth active region, P-well regions are provided in the deep P-well regions, and P+ implantation diffusion regions are provided in the P-well regions. The locations of the first active region and the ninth active region are both connected to metal lines and serve as lead-out terminals of the isolated ground terminal.

[0012] Deep N-well regions are provided at the locations of the second active region and the eighth active region, N-well regions are provided within the deep N-well regions, and N+ implantation diffusion regions are provided within the N-well regions. The locations of the second active region and the eighth active region are both connected to metal lines and serve as lead-out ends of the isolation port.

[0013] Deep P-well regions are set up at the positions of the third active region to the seventh active region, wherein P-well regions are set up in the deep P-well regions corresponding to the third active region and the seventh active region, and P+ injection diffusion regions are set up in the P-well regions. The positions of the third active region and the seventh active region are connected to metal wires and serve as the lead-out end of the collector of the vertical PNP; N-well regions are set up in the deep P-well regions corresponding to the fourth active region to the sixth active region, and N+ injection diffusion regions are set up in the N-well regions corresponding to the fourth active region and the sixth active region. The positions of the fourth active region and the sixth active region are connected to metal wires and serve as the lead-out end of the base shared by the vertical PNP tube and the horizontal PNP tube; the position of the fifth active region is connected to a metal wire and serves as the lead-out end of the collector of the horizontal PNP tube and the lead-out end of the emitter shared by the vertical PNP tube and the horizontal PNP tube.

[0014] Furthermore, a first P-type drift region, a second P-type drift region, a third P-type drift region, a fourth P-type drift region, and a fifth P-type drift region are arranged at intervals in the N-well region corresponding to the fifth active region; a P+ injection diffusion region is arranged in each of the first P-type drift region, the second P-type drift region, the third P-type drift region, the fourth P-type drift region, and the fifth P-type drift region; and the P+ injection diffusion regions corresponding to the first P-type drift region, the third P-type drift region, and the fifth P-type drift region are connected to metal wires and serve as lead-out ends of collectors of lateral PNP transistors;

[0015] The P+ injection diffusion regions corresponding to the second P-type drift region and the fourth P-type drift region are connected to metal wires and serve as lead-out ends of the emitter shared by the vertical PNP transistor and the horizontal PNP transistor.

[0016] Furthermore, a thin oxide layer is provided between the first P-type drift region and the second P-type drift region, between the second P-type drift region and the third P-type drift region, between the third P-type drift region and the fourth P-type drift region, and between the fourth P-type drift region and the fifth P-type drift region, and the thickness of the thin oxide layer is 800 angstroms to 1200 angstroms.

[0017] Furthermore, an outer oxide layer is set above the field area and the active area, wherein the outer oxide layer corresponding to the P+ injection diffusion area of ​​each active area and the outer oxide layer corresponding to the N+ injection diffusion area are removed to form contact holes, and a metal line is set in each of the contact holes.

[0018] Furthermore, the thickness of the outer oxide layer is 7000 angstroms to 12000 angstroms.

[0019] Furthermore, a field oxide layer is provided in each field region, and the thickness of the field oxide layer is 5500 angstroms to 7000 angstroms.

[0020] As another aspect of the present invention, a high-voltage electrostatic protection structure is provided, comprising: a plurality of the aforementioned isolated composite PNP transistors connected in series, each of the isolated composite PNP transistors comprising a lateral PNP transistor and a longitudinal PNP transistor, the collector of the lateral PNP transistor being connected to the collector of the longitudinal PNP transistor to form a collector connection end, the lateral PNP transistor and the longitudinal PNP transistor sharing an emitter and a base, and the emitter and base being connected to form an emitter-base connection end;

[0021] Each two adjacent isolated composite PNP transistors are connected in series by connecting the collector connection end of one of the isolated composite PNP transistors to the emitter and base connection ends of the other isolated composite PNP transistor;

[0022] The emitter and base connection ends of the isolated composite PNP transistor at the head end are used to connect to the high voltage pin of the power circuit, and the collector connection end of the isolated composite PNP transistor at the tail end is used to connect to the ground pin of the power circuit;

[0023] The isolated port of each isolated composite PNP tube is used to connect to the high voltage pin of the power supply circuit.

[0024] Furthermore, each of the isolated composite PNP transistors includes a multi-finger structure, and the number of fingers of each isolated composite PNP transistor ranges from 8 to 12, and the total width is at least 1000 μm.

[0025] As another aspect of the present invention, an electronic device is provided, which includes: a power supply circuit and the high-voltage electrostatic protection structure described above, the high-voltage pin of the power supply circuit is connected to the emitter and base connection ends of the isolated composite PNP tube of the high-voltage electrostatic protection structure, the high-voltage pin of the power supply circuit can also be connected to the isolation port of each isolated composite PNP tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the collector connection end of the isolated composite PNP tube of the high-voltage electrostatic protection structure.

[0026] The isolated composite PNP transistor provided by the present invention has a base N-well that is heavily surrounded internally by a deep P-well, a deep N-well at the isolation end, and an N-buried layer. The high-voltage pin of the power supply circuit is connected to the emitter P+ of the isolated composite PNP transistor, but its base N-well is heavily surrounded as described above. Therefore, the emitter P+ and the base N-well cannot form a PNPN latch structure with the negative pulse PN junction (i.e., the PN junction formed by the P-type ground and the N-type region at the negative pulse pin), thereby avoiding circuit failure in the presence of extreme negative pulses and greatly improving the circuit's reliability. Therefore, the isolated composite PNP transistor provided by the present invention, when used in a high-voltage electrostatic protection structure, can not only provide effective protection but also prevent the occurrence of negative pulse-triggered latching, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0028] Figure 1 This is a cross-sectional structural diagram of the isolated composite PNP tube provided by the present invention.

[0029] Figure 2 This is a circuit schematic diagram of the high-voltage electrostatic protection structure provided by the present invention. DETAILED DESCRIPTION

[0030] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0033] Conventional ESD protection for high-voltage pins typically uses a high-voltage NMOS transistor with the same operating voltage as the ESD protection device. As is well known, high-voltage NMOS devices, due to their high breakdown voltage, consume large power at high voltages and have weak ESD capabilities. Furthermore, their low holding voltage makes them unsuitable for use on power pins. Using a high-voltage PMOS or PNP transistor for ESD protection improves discharge capability and holding voltage. However, when a negative pulse appears in the N-type region connected to another pin, the P-type region of the high-voltage PMOS or PNP connected to that high-voltage pin, its N-type substrate or base, the P-type ground, and the aforementioned N-type negative pulse region form a PNPN latch structure, instantly destroying the circuit.

[0034] Based on this, an isolated composite PNP tube is provided in this embodiment. Figure 1 : is a cross-sectional view of an isolated composite PNP tube provided according to an embodiment of the present invention, as shown in FIG. Figure 1 Shown, including:

[0035] A P-type substrate 200, a P-type epitaxial layer 202 disposed on the P-type substrate 200, and an N-type buried layer 201 disposed between the P-type substrate 200 and the P-type epitaxial layer 202;

[0036] A plurality of active regions are sequentially arranged at intervals on the surface of the P-type epitaxial layer 202, and a field region is provided between every two adjacent active regions, and both the active region and the field region extend along the surface of the P-type epitaxial layer 202 toward the P-type substrate 200;

[0037] The active regions located in the outer regions can be connected to metal wires and serve as lead-out terminals for the isolated ground terminal. The multiple active regions located in the central region can be connected to metal wires and serve as lead-out terminals for the collector of the vertical PNP transistor, the collector of the horizontal PNP transistor, and the base and emitter shared by the vertical and horizontal PNP transistors. The active region located between the outer regions and the central region can be connected to metal wires and serve as lead-out terminals for the isolated port.

[0038] The lead-out end of the collector of the longitudinal PNP tube is connected to the lead-out end of the collector of the lateral PNP tube, the lead-out end of the base shared by the longitudinal PNP tube and the lateral PNP tube is connected to the lead-out end of the emitter, the lead-out end of the isolated ground end is used to connect to the ground pin of the power supply circuit, and the lead-out end of the isolated port is used to connect to the high-voltage pin of the power supply circuit.

[0039] In the isolated composite PNP transistor provided by an embodiment of the present invention, the base N-well is heavily surrounded by a deep P-well, a deep N-well at the isolation end, and an N-buried layer. The high-voltage pin of the power supply circuit is connected to the emitter P+ of the isolated composite PNP transistor, but its base N-well is heavily surrounded as described above. Therefore, the emitter P+ and the base N-well cannot form a PNPN latch structure with the negative pulse PN junction (i.e., the PN junction formed by the P-type ground and the N-type region at the negative pulse pin), thereby avoiding circuit failure in the event of an extreme negative pulse and greatly improving the circuit's reliability. Therefore, the isolated composite PNP transistor provided by the present invention, when used in a high-voltage electrostatic protection structure, can not only play an effective protective role but also prevent the occurrence of negative pulse-triggered latching, thereby improving reliability.

[0040] In the embodiment of the present invention, Figure 1 As shown, a first active region 213, a second active region 214, a third active region 215, a fourth active region 216, a fifth active region 217, a sixth active region 218, a seventh active region 219, an eighth active region 220 and a ninth active region 221 are sequentially arranged on the surface of the P-type epitaxial layer 202.

[0041] Deep P-well regions 203 are provided at the locations of the first active region 213 and the ninth active region 221. P-well regions 205 are provided in the deep P-well regions 203, and P+ implantation diffusion regions 207 are provided in the P-well regions 205. The locations of the first active region 213 and the ninth active region 221 are both connected to metal lines 212 to serve as lead-out terminals of the isolated ground terminals.

[0042] Deep N-well regions 204 are provided at the locations of the second active region 214 and the eighth active region 220. N-well regions 206 are provided in the deep N-well regions 204, and N+ implantation diffusion regions 208 are provided in the N-well regions 206. The locations of the second active region 214 and the eighth active region 220 are both connected to metal lines 212 and serve as lead-out ends of the isolation ports.

[0043] Deep P-well regions 203 are provided at the locations of the third active region 215 to the seventh active region 219, wherein P-well regions 205 are provided in the deep P-well regions 203 corresponding to the third active region 215 and the seventh active region 219, and P+ implantation diffusion regions 207 are provided in the P-well regions 205. The locations of the third active region 215 and the seventh active region 219 are connected to the metal wire 212 and serve as the lead-out end of the collector of the vertical PNP. In the deep P-well regions 203 corresponding to the fourth active region 216 to the sixth active region 218, N-well regions 206 are provided, and N+ injection diffusion regions 208 are provided in the N-well regions 206 corresponding to the fourth active region 216 and the sixth active region 218. The positions of the fourth active region 216 and the sixth active region 218 are connected to the metal wire 212 and serve as the lead-out end of the base shared by the longitudinal PNP tube and the lateral PNP tube; the position of the fifth active region 217 is connected to the metal wire 212 and serves as the lead-out end of the collector of the lateral PNP tube and the lead-out end of the emitter shared by the longitudinal PNP tube and the lateral PNP tube.

[0044] Specifically, a P-type epitaxial layer 202 is formed above a P-type substrate 200, within which the isolated composite PNP transistor is fabricated. An N-type buried layer 201 is positioned between the P-type substrate 200 and the P-type epitaxial layer 202. On the surface of the P-type epitaxial layer 202, a first active region 213, a second active region 214, a third active region 215, a fourth active region 216, a fifth active region 217, a sixth active region 218, a seventh active region 219, an eighth active region 220, and a ninth active region 221 are sequentially positioned. Field regions are located on both sides of each active region, and a 5500-7000 angstrom thick field oxide layer 209 is placed above the field regions to isolate each active region.

[0045] In this embodiment of the present invention, deep P-well regions 203 are provided in both the first active region 213 and the ninth active region 221, serving as the isolated ground terminal of the isolated composite PNP transistor. Within each deep P-well region 203, P+ implant diffusion regions 207 and P-well regions 205 are provided to increase the impurity concentration there. This region forms a good ohmic contact through contact holes and metal lines, serving as the lead-out terminal for the isolated ground terminal. Deep N-well regions 204 are provided in both the second active region 214 and the eighth active region 220, serving as the isolated port of the isolated composite PNP transistor. Deep N-well regions 204 diffuse downward 5-6 microns from the P-type epitaxial surface, contacting and communicating with the N-type buried layer 201. Within each deep N-well region 204, N+ implant diffusion regions 208 and N-well regions 206 are provided to increase the impurity concentration there. This region forms a good ohmic contact through contact holes and metal lines, serving as the lead-out terminal for the isolated port.

[0046] In this embodiment of the present invention, a large deep P-well region 203 is provided below the third active region 215 to the seventh active region 219. Within the deep P-well 203 at the locations of the third active region 215 and the seventh active region 219, a P+ implant diffusion region 207 and a P-well region 205 are provided to increase the impurity concentration there. This allows for a good ohmic contact to be formed through contact holes and metal lines, serving as the collector lead terminal of the vertical PNP in the isolated composite PNP transistor.

[0047] In this embodiment of the present invention, a large N-well region 206 is provided below the fourth active region 216 through the sixth active region 218. The N-well region 206 is located within the deep P-well region 203, meaning that both the lateral and vertical dimensions of the N-well region 206 are smaller than those of the deep P-well region 203. N+ implant diffusion regions 208 are provided within the N-well region 206 at the locations of the fourth active region 216 and the sixth active region 218 to increase the impurity concentration there. This allows for a good ohmic contact to be formed through contact holes and metal lines, serving as the base terminal of the isolated composite PNP transistor.

[0048] In an embodiment of the present invention, a first P-type drift region, a second P-type drift region, a third P-type drift region, a fourth P-type drift region, and a fifth P-type drift region are arranged at intervals in the N-well region 206 corresponding to the fifth active region 217. P+ injection diffusion regions are arranged in each of the first P-type drift region, the second P-type drift region, the third P-type drift region, the fourth P-type drift region, and the fifth P-type drift region. The P+ injection diffusion regions corresponding to the first P-type drift region, the third P-type drift region, and the fifth P-type drift region are connected to metal wires and serve as the lead-out end of the collector of the lateral PNP transistor.

[0049] The P+ injection diffusion regions corresponding to the second P-type drift region and the fourth P-type drift region are connected to metal wires and serve as lead-out ends of the emitter shared by the vertical PNP transistor and the horizontal PNP transistor.

[0050] Furthermore, a thin oxide layer 211 is provided between the first P-type drift region and the second P-type drift region, between the second P-type drift region and the third P-type drift region, between the third P-type drift region and the fourth P-type drift region, and between the fourth P-type drift region and the fifth P-type drift region. The thickness of the thin oxide layer 211 is 800 angstroms to 1200 angstroms.

[0051] Specifically, in this embodiment of the present invention, five spaced-apart P-type drift regions 222 are positioned at the location of the fifth active region 217. A thin oxide layer 211 with a thickness of 800 to 1200 angstroms is positioned between each pair of P-type drift regions 222 to prevent short circuits between the P-type drift regions 222 during surface metallization. A P+ implant diffusion region 207 is positioned within each P-type drift region 222 to increase the impurity concentration on the surface. The P+ implant diffusion regions 207 within the first, third, and fifth P-type drift regions 222 form good ohmic contacts with metal lines through contact holes, serving as collector terminals for the lateral PNP transistors in the isolated composite PNP transistor. The P+ implant diffusion regions 207 within the second and fourth P-type drift regions 222 also form good ohmic contacts with metal lines through contact holes, serving as emitter terminals for the isolated composite PNP transistors.

[0052] In an embodiment of the present invention, an outer oxide layer 210 is set above the field area and the active area, wherein the outer oxide layer corresponding to the P+ injection diffusion area of ​​each active area and the outer oxide layer corresponding to the N+ injection diffusion area are removed to form contact holes, and a metal line 212 is set in each of the contact holes.

[0053] Specifically, the thickness of the outer oxide layer is 7000 angstroms to 12000 angstroms.

[0054] In the embodiment of the present invention, a field oxide layer 209 is disposed in each field region, and the thickness of the field oxide layer 209 is 5500 angstroms to 7000 angstroms.

[0055] In this embodiment of the present invention, an outer oxide layer 210 with a thickness of 7,000 to 12,000 angstroms is provided above all field oxide layers and active areas, covering the entire wafer surface. This outer oxide layer 210 is removed at the corresponding locations of the P+ implant diffusion regions 207 and the N+ implant diffusion regions 208 in each active area, forming contact holes directly reaching the silicon surface. At the location of each contact hole, a metal wire 212 is provided to contact the silicon surface, leading out each port of the isolated composite PNP transistor, forming a complete isolated composite PNP transistor structure.

[0056] When the isolated composite PNP transistor of the embodiment of the present invention is applied to Figure 2In the illustrated high-voltage electrostatic protection structure, the metal lines connecting the longitudinal PNP collector 207 in the third active region 215 and the seventh active region 219 of the isolated composite PNP transistor are short-circuited with the metal lines connecting the lateral PNP collector 207 in the first, third, and fifth P-type drift regions 222 in the fifth active region 217. Simultaneously, the metal lines connecting the isolated composite PNP base 208 in the fourth active region 216 and the sixth active region 218 are short-circuited with the metal lines connecting the isolated composite PNP emitter 207 in the second and fourth P-type drift regions 222 in the fifth active region 217. The metal lines of isolated composite PNP1 through isolated composite PNP4 are short-circuited in the same manner and are connected in series.

[0057] In this embodiment of the present invention, the breakdown voltage from the isolated terminal of the isolated composite PNP transistor to ground is greater than 100V (i.e., the breakdown voltage of the deep N-well region 204 and the deep P-well region 203). The breakdown voltage from the emitter P-type drift region 222 of the isolated composite PNP transistor to the lateral PNP collector P-type drift region 222 is 15-20V; the breakdown voltage from the emitter P-type drift region 222 of the isolated composite PNP transistor to the vertical PNP collector deep P-well 203 is also 15-20V. Therefore, the breakdown voltage from the emitter of the isolated composite PNP transistor to the short-circuited collector terminal of the vertical PNP and lateral PNP transistors is 15-20V.

[0058] like Figure 2 As shown in the figure, the isolated composite PNP2 to isolated composite PNP4 connected in series with the isolated composite PNP1 tube have the same structure and connection method as the isolated composite PNP1, and the breakdown voltage of each port is also the same as the isolated composite PNP1. Figure 2 The ESD voltage is introduced into the high-voltage pin 100. At this time, since the breakdown voltage of each isolated port connected to the high-voltage pin 100 to the ground is greater than 100V, the ESD voltage will break down the emitter and collector short-circuited ends of the isolated composite PNP1 with a lower breakdown voltage (15~20V), and then the ESD energy will reach the emitter and base short-circuited ends of the isolated composite PNP2. Similarly, the ESD energy will break down the emitter and collector short-circuited ends of the isolated composite PNP2 with a lower breakdown voltage. By analogy, the ESD energy will gradually break down the emitter and collector short-circuited ends of the isolated composite PNP3 and the isolated composite PNP4, and finally reach the ground pin 121, completing the discharge of the ESD energy introduced from the high-voltage pin 100 to the ground pin 121. It should be noted that Figure 1The structure of the isolated composite PNP transistor of the present invention adds a high-voltage PMOS P-type drift region 222 at the emitter to increase the emitter junction depth and reduce the vertical base region width, thereby increasing the vertical PNP's amplification factor and electrostatic discharge. This is because the electrostatic discharge capability of the vertical PNP is stronger than that of the horizontal PNP. In addition, in order to appropriately discharge more ESD energy in the vertical direction, the distance between the collector P-type drift region and the emitter P-type drift region of the horizontal PNP can also be appropriately increased to reduce the horizontal PNP amplification factor and reduce the horizontal ESD discharge, thereby making the ESD energy discharge path within the isolated composite PNP more reasonable.

[0059] Conversely, when ESD energy is introduced from the ground pin 121, the PN junctions formed by the isolation terminals and the ground terminals of the isolation composites PNP1 to PNP4 are both in forward bias. The isolation terminals of the isolation composites PNP1 to PNP4 are all connected to the high-voltage pin 100. Therefore, the ESD energy is discharged in parallel to the high-voltage pin through the four isolation terminal PN junctions of the isolation composites PNP1 to PNP4, thereby completing the discharge from the ground pin 121 to the high-voltage pin 100. It should be understood that the forward PN junction has a strong electrostatic discharge capability, and the structure of the present invention uses four large-area forward PN junctions to discharge in parallel simultaneously, which increases its discharge capability exponentially. Therefore, the high-voltage electrostatic protection structure of the present invention can achieve the discharge of forward and reverse ESD energy from the high-voltage pin to the ground pin. Testing has shown that the forward and reverse ESD discharge levels of the high-voltage electrostatic protection structure of the present invention both reach above 8000V in the human body model. It should also be noted here that when a negative pulse appears in the N-type region connected to the remaining pins, the emitter and base PN junctions of the isolated composite PNP tube of the present invention are surrounded and isolated by the collector deep P-well, the isolation end deep N-well and the N-type buried layer, and therefore will not form a PNPN latch structure with the negative pulses in the N-type regions of the remaining pins, thereby avoiding damage to the circuit under special abnormal circumstances and greatly improving the reliability of the circuit.

[0060] It should be noted that the photolithography layer and process of the isolated composite PNP tube of the present invention are compatible with existing high-voltage MOS tubes, that is, no additional platemaking and process costs will be generated. Therefore, the isolated composite PNP tube of the present invention can be used in high-voltage electrostatic protection structures without increasing costs. While improving the high-voltage electrostatic protection capability, it can also effectively prevent the occurrence of latch structures.

[0061] As another embodiment of the present invention, a high-voltage electrostatic protection structure is provided, wherein, Figure 2As shown, it includes: a plurality of the above-mentioned isolated composite PNP transistors connected in series, each of the isolated composite PNP transistors includes a lateral PNP transistor and a longitudinal PNP transistor, the collector of the lateral PNP transistor is connected to the collector of the longitudinal PNP transistor to form a collector connection end, the lateral PNP transistor and the longitudinal PNP transistor share an emitter and a base, and the emitter and the base are connected to form an emitter-base connection end;

[0062] Each two adjacent isolated composite PNP transistors are connected in series by connecting the collector connection end of one of the isolated composite PNP transistors to the emitter and base connection ends of the other isolated composite PNP transistor;

[0063] The emitter and base connection ends of the isolated composite PNP transistor at the head end are used to connect to the high voltage pin of the power circuit, and the collector connection end of the isolated composite PNP transistor at the tail end is used to connect to the ground pin of the power circuit;

[0064] The isolated port of each isolated composite PNP tube is used to connect to the high voltage pin of the power supply circuit.

[0065] In an embodiment of the present invention, each of the isolated composite PNP transistors includes a multi-finger structure, the number of fingers of each isolated composite PNP transistor ranges from 8 to 12, and the total width is at least 1000 μm.

[0066] Specifically, if Figure 2 As shown, the emitter 102 of the first isolated composite PNP transistor PNP1 is connected to the port of the high-voltage pin 100. The base 103 and emitter 102 of the first isolated composite PNP transistor PNP1 are short-circuited together, and the collector of the vertical PNP transistor in the first isolated composite PNP transistor PNP1 and the collector of the lateral PNP transistor in the first isolated composite PNP transistor PNP1 are short-circuited together. The isolation port 101 of the first isolated composite PNP transistor PNP1 is connected to the high-voltage pin 100.

[0067] In this embodiment of the present invention, the collector short-circuit terminals of the vertical PNP and lateral PNP transistors in the first isolated composite PNP transistor PNP1 are connected to the emitter 107 of the second isolated composite PNP transistor PNP2. The base 108 and emitter 107 of the second isolated composite PNP transistor PNP2 are short-circuited together, and the collector of the vertical PNP transistor in the second isolated composite PNP transistor PNP2 is short-circuited with the collector of the lateral PNP transistor in the second isolated composite PNP transistor PNP2. The isolation port 106 of the second isolated composite PNP transistor PNP2 is also connected to the high-voltage pin 100.

[0068] Similarly, the third and fourth isolated composite PNP transistors PNP3 and PNP4 are connected in the same manner as the second isolated composite PNP transistor PNP2: their bases and emitters are short-circuited, and their vertical and horizontal collectors are short-circuited. The isolated ports of the third and fourth isolated composite PNP transistors PNP3 and PNP4 are both connected to high-voltage pin 100. The collector of the fourth isolated composite PNP transistor PNP4 is short-circuited to ground pin 121, forming a complete high-voltage ESD protection structure to prevent negative pulses from triggering latch-up.

[0069] In an embodiment of the present invention, the high-voltage ESD protection structure is specifically constructed from four low-voltage, isolated composite PNP transistors connected in series. Its ESD capability is comparable to the ESD level of a single isolated composite PNP transistor. As is well known, low-voltage PNP transistors have strong discharge capabilities, and therefore the high-voltage ESD protection structure of the present invention exhibits a stronger discharge capability. Furthermore, because the PNP transistor has a high holding voltage (almost equal to its breakdown voltage), the holding voltage of the structure of the present invention is equal to the sum of the holding voltages of the four low-voltage, isolated composite PNP transistors. Therefore, the holding voltage of the high-voltage ESD protection structure of the present invention is relatively high (approximately 60-80V), making it suitable for high-voltage and power pins. Furthermore, when a negative pulse occurs in the N-type region connected to the remaining pins, the high-voltage pin, connected to the emitter and base of the isolated composite PNP transistor of the present invention, is completely surrounded by the collector deep P-well, the deep N-well at the isolation terminal, and the N-buried layer. This prevents the pin from forming a PNPN latch-up structure with the negative pulse N-type region of the remaining pins, effectively protecting the circuit.

[0070] In summary, the high-voltage electrostatic protection structure of the present invention has the following advantages: (1) The structure can discharge ESD energy bidirectionally from the high-voltage pin to the ground pin. (2) The electrostatic discharge capability of the high-voltage electrostatic protection structure is very strong. (3) The maintenance voltage of the high-voltage electrostatic protection structure is equal to the sum of the maintenance voltages of the four isolated composite PNPs, that is, 60~80V. Therefore, the structure can meet the use of high-voltage power supply. (4) When abnormal negative pulses appear on the other pins, the high-voltage pin connected to the high-voltage electrostatic protection structure will not form a latch structure with the other pins, thereby improving the reliability and safety of the circuit under extreme conditions, extending the service life of the circuit, and complying with the national energy conservation and environmental protection policy. Therefore, the high-voltage electrostatic protection structure of the present invention can fully achieve good electrostatic protection for the high-voltage pins of the circuit (including the power pins) and has high reliability against negative pulses.

[0071] It should be understood that, for the sake of ease of explanation, the present invention only cites a high-voltage electrostatic protection structure when the high-voltage pin is 60~80V. For those skilled in the art, it is easy to obtain a high-voltage ESD protection structure of different voltage levels by increasing or decreasing the number of isolated composite PNP tubes. At the same time, for the sake of ease of explanation, the present invention only cites a structure with 2 emitter fingers in the isolated composite PNP tube. For those skilled in the art, it is easy to obtain a structure with different ESD discharge capabilities by increasing the number of emitter and collector fingers. The high-voltage electrostatic protection structure proposed in the present invention can be applied not only between the high-voltage pin and the ground pin described in the present invention, but also between the other different functional pins.

[0072] It should be noted that the electrostatic discharge principle of the high-voltage electrostatic protection structure of the present invention can be specifically referred to the relevant description in the isolated composite PNP tube above, and will not be repeated here.

[0073] As another embodiment of the present invention, an electronic device is provided, which includes: a power supply circuit and the high-voltage electrostatic protection structure described above, the high-voltage pin of the power supply circuit is connected to the emitter and base connection terminals of the isolated composite PNP tube of the high-voltage electrostatic protection structure, the high-voltage pin of the power supply circuit can also be connected to the isolation port of each isolated composite PNP tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the collector connection terminal of the isolated composite PNP tube of the high-voltage electrostatic protection structure.

[0074] The electronic device of the embodiment of the present invention adopts the high-voltage electrostatic protection structure described above and can be applied to high-voltage power supply circuits. It can play a role in electrostatic protection under high voltage of the power supply circuit, improve the reliability and safety of the power supply circuit under extreme conditions, and extend the service life of the power supply circuit.

[0075] The specific working principle of the electronic device of the present invention can be referred to the specific description of the high-voltage electrostatic protection structure above, which will not be repeated here.

[0076] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An isolated composite PNP tube, characterized in that: include: A P-type substrate, a P-type epitaxial layer disposed on the P-type substrate, and an N-type buried layer disposed between the P-type substrate and the P-type epitaxial layer; A plurality of active regions are sequentially arranged at intervals on the surface of the P-type epitaxial layer, and a field region is arranged between every two adjacent active regions, wherein both the active region and the field region extend along the surface of the P-type epitaxial layer toward the P-type substrate; The active regions located in the outer regions can be connected to metal wires and serve as lead-out terminals for the isolated ground terminal. The multiple active regions located in the central region can be connected to metal wires and serve as lead-out terminals for the collector of the vertical PNP transistor, the collector of the horizontal PNP transistor, and the base and emitter shared by the vertical and horizontal PNP transistors. The active region located between the outer regions and the central region can be connected to metal wires and serve as lead-out terminals for the isolated port. The lead end of the collector of the longitudinal PNP tube is connected to the lead end of the collector of the lateral PNP tube, the lead end of the base shared by the longitudinal PNP tube and the lateral PNP tube is connected to the lead end of the emitter, the lead end of the isolated ground terminal is used to connect to the ground pin of the power circuit, and the lead end of the isolated port is used to connect to the high-voltage pin of the power circuit; Wherein, a first active region, a second active region, a third active region, a fourth active region, a fifth active region, a sixth active region, a seventh active region, an eighth active region and a ninth active region are sequentially arranged on the surface of the P-type epitaxial layer. Deep P-well regions are provided at the locations of the first active region and the ninth active region, P-well regions are provided in the deep P-well regions, and P+ implantation diffusion regions are provided in the P-well regions. The locations of the first active region and the ninth active region are both connected to metal lines and serve as lead-out terminals of the isolated ground terminal. Deep N-well regions are provided at the locations of the second active region and the eighth active region, N-well regions are provided within the deep N-well regions, and N+ implantation diffusion regions are provided within the N-well regions. The locations of the second active region and the eighth active region are both connected to metal lines and serve as lead-out ends of the isolation port. Deep P-well regions are set up at the positions of the third active region to the seventh active region, wherein P-well regions are set up in the deep P-well regions corresponding to the third active region and the seventh active region, and P+ injection diffusion regions are set up in the P-well regions. The positions of the third active region and the seventh active region are connected to metal wires and serve as the lead-out end of the collector of the vertical PNP; N-well regions are set up in the deep P-well regions corresponding to the fourth active region to the sixth active region, and N+ injection diffusion regions are set up in the N-well regions corresponding to the fourth active region and the sixth active region. The positions of the fourth active region and the sixth active region are connected to metal wires and serve as the lead-out end of the base shared by the vertical PNP tube and the horizontal PNP tube; the position of the fifth active region is connected to a metal wire and serves as the lead-out end of the collector of the horizontal PNP tube and the lead-out end of the emitter shared by the vertical PNP tube and the horizontal PNP tube.

2. The isolated composite PNP tube according to claim 1, characterized in that: A first P-type drift region, a second P-type drift region, a third P-type drift region, a fourth P-type drift region, and a fifth P-type drift region are arranged at intervals in the N-well region corresponding to the fifth active region, a P+ injection diffusion region is arranged in each of the first P-type drift region, the second P-type drift region, the third P-type drift region, the fourth P-type drift region, and the fifth P-type drift region, and the P+ injection diffusion regions corresponding to the first P-type drift region, the third P-type drift region, and the fifth P-type drift region are connected to metal wires and serve as lead-out ends of collectors of lateral PNP transistors; The P+ injection diffusion regions corresponding to the second P-type drift region and the fourth P-type drift region are connected to metal wires and serve as lead-out ends of the emitter shared by the vertical PNP transistor and the horizontal PNP transistor.

3. The isolated composite PNP tube according to claim 2, characterized in that: A thin oxide layer is provided between the first P-type drift region and the second P-type drift region, between the second P-type drift region and the third P-type drift region, between the third P-type drift region and the fourth P-type drift region, and between the fourth P-type drift region and the fifth P-type drift region. The thickness of the thin oxide layer is 800 angstroms to 1200 angstroms.

4. The isolated composite PNP tube according to claim 1, characterized in that: An outer oxide layer is set above the field area and the active area, wherein the outer oxide layer corresponding to the P+ injection diffusion area of ​​each active area and the outer oxide layer corresponding to the N+ injection diffusion area are removed to form contact holes, and a metal line is set in each of the contact holes.

5. The isolated composite PNP tube according to claim 4, characterized in that: The thickness of the outer oxide layer is 7000 angstroms to 12000 angstroms.

6. The isolated composite PNP tube according to claim 1, characterized in that: A field oxide layer is provided in each field region, and the thickness of the field oxide layer is 5500 angstroms to 7000 angstroms.

7. A high-voltage electrostatic protection structure, characterized in that: include: A plurality of isolated composite PNP transistors according to any one of claims 1 to 6 connected in series, each of the isolated composite PNP transistors comprising a lateral PNP transistor and a longitudinal PNP transistor, the collector of the lateral PNP transistor being connected to the collector of the longitudinal PNP transistor to form a collector connection end, the lateral PNP transistor and the longitudinal PNP transistor sharing an emitter and a base, and the emitter and base being connected to form an emitter-base connection end; Each two adjacent isolated composite PNP transistors are connected in series by connecting the collector connection end of one of the isolated composite PNP transistors to the emitter and base connection ends of the other isolated composite PNP transistor; The emitter and base connection ends of the isolated composite PNP transistor at the head end are used to connect to the high voltage pin of the power circuit, and the collector connection end of the isolated composite PNP transistor at the tail end is used to connect to the ground pin of the power circuit; The isolated port of each isolated composite PNP tube is used to connect to the high voltage pin of the power supply circuit.

8. The high-voltage electrostatic protection structure according to claim 7, characterized in that: Each of the isolated composite PNP tubes includes a multi-finger structure, and the number of fingers of each isolated composite PNP tube ranges from 8 to 12, and the total width is at least 1000 μm.

9. An electronic device, characterized in that: include: The power supply circuit and the high-voltage electrostatic protection structure described in claim 7 or 8, the high-voltage pin of the power supply circuit is connected to the emitter and base connection ends of the isolated composite PNP tube of the high-voltage electrostatic protection structure, the high-voltage pin of the power supply circuit can also be connected to the isolation port of each isolated composite PNP tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the collector connection end of the isolated composite PNP tube of the high-voltage electrostatic protection structure.

Images