Anti-ferroelectric thin film transistor and preparation method thereof

Abstract

The invention relates to the field of semiconductors, and discloses an anti-ferroelectric thin film transistor and a preparation method thereof, a bottom gate electrode structure is formed on the surface area of a substrate layer with an insulating layer, and an anti-ferroelectric thin film layer is formed on the substrate layer with the insulating layer and the bottom gate electrode structure. And sequentially forming a top electrode structure and an oxide semiconductor layer above the anti-ferroelectric thin film layer, and forming a source layer and a drain layer above the oxide semiconductor layer and the anti-ferroelectric thin film layer to obtain the anti-ferroelectric thin film transistor. For the anti-ferroelectric thin film transistor, the compactness of the device structure is realized, and the device can be applied to various intelligent sensing systems; in the use process, an electric pulse signal is applied to the top electrode structure, so that LIF neuron behaviors in an electrical mode can be realized; by applying optical pulse signals on the oxide semiconductor layer, LIF neuron behaviors in an optical mode can be realized, namely, electrical and optical dual sensing capabilities are realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an antiferroelectric thin film transistor and a method for preparing the same. Background Art

[0002] In recent years, with the rapid development of intelligent technology and the advent of the post-Moore era, bionic neuromorphic computing has attracted increasing attention due to its excellent bionic characteristics and high energy efficiency. Artificial sensory neurons, as a key component of bionic neuromorphic computing, have the ability to sense external stimuli and transmit nerve impulses to subsequent processing systems, and are an important cornerstone for realizing the in-sensor computing paradigm.

[0003] However, due to the high complexity of semiconductor technology, traditional unimodal sensory neurons often only perceive a specific stimulus. When multiple stimuli need to be perceived simultaneously, these neurons often need to rely on complex external circuits and algorithms, which not only limits their application scope in complex and changing environments, but also may face the dual challenges of perception accuracy and response speed when processing multiple stimuli due to the singleness of the original design.

[0004] Therefore, how to realize stable, reliable, and low-power multimodal sensory neurons has become an important issue that needs to be solved urgently. Summary of the invention

[0005] In view of this, the embodiments of the present application provide an antiferroelectric thin film transistor and a method for preparing the same, which can effectively solve the problem that traditional single-mode sensory neurons only perceive specific stimuli and require external support when processing multiple stimuli, and face problems such as perception accuracy and response speed.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing an antiferroelectric thin film transistor, comprising:

[0007] providing a substrate layer with an insulating layer;

[0008] forming a bottom gate electrode structure in a surface region of the substrate layer with the insulating layer;

[0009] forming an antiferroelectric thin film layer on the substrate layer with the insulating layer and the bottom gate electrode structure;

[0010] forming a top electrode structure and an oxide semiconductor layer in sequence above the antiferroelectric thin film layer;

[0011] A source electrode layer and a drain electrode layer are formed above the oxide semiconductor layer and the antiferroelectric thin film layer to obtain an antiferroelectric thin film transistor.

[0012] In some embodiments, forming a bottom gate electrode structure on the surface region of the substrate layer with the insulating layer includes:

[0013] Performing magnetron sputtering on the surface area of ​​the substrate layer with the insulating layer to deposit a first film of a preset thickness;

[0014] Coating a photoresist on the surface area of ​​the first film, and patterning the photoresist to form a photoresist pattern having the bottom gate electrode structure;

[0015] The surface area of ​​the first film not coated by the photoresist is processed by wet etching to form the bottom gate electrode structure on the surface of the substrate layer with the insulating layer.

[0016] In some embodiments, the step of forming an antiferroelectric thin film layer on the substrate layer with the insulating layer and the bottom gate electrode structure comprises:

[0017] On the substrate layer with the insulating layer and the surface of the bottom gate electrode structure, the first dielectric layer and the second dielectric layer are alternately and cyclically deposited for a preset number of times at a preset ratio to form an antiferroelectric thin film layer with a preset thickness.

[0018] In some embodiments, forming a top electrode structure above the antiferroelectric thin film layer includes:

[0019] Performing magnetron sputtering on a portion of the antiferroelectric thin film layer to deposit the first thin film with a preset thickness;

[0020] Coating a photoresist on a portion of the first film, and patterning the photoresist to form the photoresist pattern having the top electrode structure;

[0021] The surface area of ​​the first film not coated by the photoresist is subjected to an etching process to form the top electrode structure on the surface of a portion of the antiferroelectric film layer.

[0022] In some embodiments, after the etching treatment is performed on the surface area of ​​the first film not coated by the photoresist to form the top electrode structure on the surface of a portion of the antiferroelectric film layer, the method further comprises:

[0023] The antiferroelectric thin film layer is subjected to a rapid annealing treatment for a preset time to recrystallize the antiferroelectric thin film layer.

[0024] In some embodiments, forming an oxide semiconductor layer above the antiferroelectric thin film layer includes:

[0025] Coating a photoresist on a portion of the antiferroelectric thin film layer, and exposing and developing the photoresist using a mask to form a photoresist pattern complementary to the mask;

[0026] Performing magnetron sputtering on the patterned photoresist to deposit a second film of a preset thickness;

[0027] The photoresist is dissolved by a solvent, so that the second film deposited on the surface of the photoresist is peeled off to form an oxide semiconductor layer.

[0028] In some embodiments, forming a source electrode layer and a drain electrode layer above the oxide semiconductor layer and the antiferroelectric thin film layer includes:

[0029] Coating the photoresist on the oxide semiconductor layer, and patterning the photoresist to form a photoresist pattern having the shape of the source electrode layer and the drain electrode layer;

[0030] Performing magnetron sputtering on the patterned photoresist to deposit a first conductive metal;

[0031] Performing magnetron sputtering on the first conductive metal to deposit a second conductive metal;

[0032] The photoresist is dissolved by a dissolving agent, so that the second conductive metal deposited on the surface of the photoresist is stripped off to form the source electrode layer and the drain electrode layer.

[0033] In some embodiments, the method of dissolving the photoresist with a solvent to remove the second conductive metal deposited on the surface of the photoresist to form the source electrode layer and the drain electrode layer includes:

[0034] The oxide semiconductor layer located below the source electrode layer and the drain electrode layer is annealed to recrystallize the oxide semiconductor layer.

[0035] In a second aspect, an embodiment of the present application provides an antiferroelectric thin film transistor, comprising:

[0036] A substrate layer with an insulating layer;

[0037] A bottom gate electrode structure, wherein the bottom gate electrode structure is located in a surface area above a portion of the substrate layer with the insulating layer, and the bottom gate electrode structure extends in a direction parallel to the surface area above the substrate layer with the insulating layer;

[0038] an antiferroelectric thin film layer, the antiferroelectric thin film layer being located above the substrate layer with the insulating layer and the bottom gate electrode structure, and the antiferroelectric thin film layer extending in a direction parallel to the bottom gate electrode structure;

[0039] A top electrode structure, wherein the top electrode structure is located on a portion of the antiferroelectric thin film layer;

[0040] an oxide semiconductor layer, wherein the oxide semiconductor layer is located on a portion of the antiferroelectric thin film layer;

[0041] A source electrode layer and a drain electrode layer, wherein the source electrode layer and the drain electrode layer are located on the oxide semiconductor layer and a portion of the antiferroelectric thin film layer.

[0042] In some embodiments, the thickness of the antiferroelectric thin film layer is in the range of 8 nm to 12 nm.

[0043] The embodiments of the present application have the following beneficial effects:

[0044] The present application discloses an antiferroelectric thin film transistor and a preparation method thereof. The antiferroelectric thin film transistor is obtained by forming a bottom gate electrode structure on the surface area of ​​a substrate layer with an insulating layer, forming an antiferroelectric thin film layer on the substrate layer with an insulating layer and the bottom gate electrode structure, sequentially forming a top electrode structure and an oxide semiconductor layer on the antiferroelectric thin film layer, and forming a source layer and a drain layer on the oxide semiconductor layer and the antiferroelectric thin film layer. The antiferroelectric thin film transistor not only realizes the compactness of the device structure, but also can be applied to various intelligent sensing systems; moreover, during use, by applying an electric pulse signal on the top electrode structure, the polarization and depolarization characteristics of the antiferroelectric thin film are triggered, and the LIF neuron behavior in the electrical mode is realized; by applying an optical pulse signal on the oxide semiconductor layer, the photosensitivity of the oxide semiconductor is utilized to realize the LIF neuron behavior in the optical mode. The antiferroelectric thin film transistor and the preparation method thereof of the present application realize the dual perception capability of electrical and optical signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A schematic structural diagram of an antiferroelectric thin film transistor according to an embodiment of the present application is shown;

[0047] Figure 2 - Figure 7 The corresponding structural schematic diagrams obtained by various preparation processes of an antiferroelectric thin film transistor according to an embodiment of the present application are shown;

[0048] Figure 8 A flow chart showing a method for preparing an antiferroelectric thin film transistor according to an embodiment of the present application is shown;

[0049] Fig. 9 A schematic diagram showing a performance test of an antiferroelectric thin film transistor in an antiferroelectric thin film transistor in an embodiment of the present application is shown;

[0050] Fig.10 A schematic diagram showing the application of an electric pulse signal to an antiferroelectric thin film layer in an antiferroelectric thin film transistor according to an embodiment of the present application is shown;

[0051] Fig.11 A schematic diagram of applying an optical pulse signal to an oxide semiconductor layer in an antiferroelectric thin film transistor according to an embodiment of the present application is shown.

[0052] Explanation of reference numerals: 10: antiferroelectric thin film transistor; 101: substrate layer with insulating layer; 102: bottom gate electrode structure; 103: antiferroelectric thin film layer; 104: top electrode structure; 105: oxide semiconductor layer; 106: source layer and drain layer. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0054] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0055] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0056] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0057] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0058] Considering that traditional unimodal sensory neurons often only perceive a specific stimulus. When it is necessary to perceive multiple stimuli at the same time, these neurons often need to rely on complex external circuits and algorithms, which not only limits their application scope in complex and changing environments, but also may face the dual challenges of perception accuracy and response speed when processing multiple stimuli due to the singleness of the original design intention. Therefore, an antiferroelectric thin film transistor and a preparation method thereof are proposed, providing a substrate layer with an insulating layer; forming a bottom gate electrode structure on the surface area of ​​the substrate layer with an insulating layer; forming an antiferroelectric thin film layer on the substrate layer with an insulating layer and the bottom gate electrode structure; forming a top electrode structure and an oxide semiconductor layer in sequence above the antiferroelectric thin film layer; forming a source layer and a drain layer above the oxide semiconductor layer and the antiferroelectric thin film layer, thereby obtaining an antiferroelectric thin film transistor. By utilizing the polarization and depolarization characteristics of the antiferroelectric film, an electrical pulse signal is applied to the top electrode structure to control the source-drain current to simulate the state of the neuron membrane potential under stimulation, realizing the LIF neuron behavior in the electrical mode (Leaky Integrate-and-Fire, leaky integral ignition neuron model), which is a simplified mathematical model for simulating the behavior of biological neurons. This model simulates the dynamic behavior of neurons based on the basic physiological characteristics of neurons, such as the accumulation, leakage, and threshold release of membrane potential. By utilizing the photosensitivity of oxide semiconductors, a light pulse signal is applied to the oxide semiconductor layer. The light pulse signal causes the oxide semiconductor layer to generate photogenerated carriers. The generation and recombination of photogenerated carriers affect the conductivity of the semiconductor layer, thereby controlling the source-drain current and realizing the LIF neuron behavior in the optical mode. The antiferroelectric thin-film transistor and its preparation method of the present application, on the basis of significantly improving the stability and repeatability of the antiferroelectric thin-film transistor, effectively reduce the hardware cost and realize the dual perception capability of electrical signals and optical signals. It not only optimizes the overall performance of the device, but also significantly promotes the compactness of the device structure, laying a solid foundation for building a more efficient, flexible and multifunctional intelligent sensing system.

[0059] The structure and preparation method of the antiferroelectric thin film transistor 10 according to the embodiment of the present application are described in detail below.

[0060] like Figure 1 As shown, the embodiment of the present application provides an antiferroelectric thin film transistor 10, comprising:

[0061] A substrate layer 101 with an insulating layer;

[0062] A bottom gate electrode structure 102, the bottom gate electrode structure 102 is located in a surface region above a portion of the substrate layer 101 with the insulating layer, and the bottom gate electrode structure 102 extends in a direction parallel to the surface region above the substrate layer 101 with the insulating layer;

[0063] An antiferroelectric thin film layer 103, the antiferroelectric thin film layer 103 is located on the substrate layer 101 with an insulating layer and the bottom gate electrode structure 102, and the antiferroelectric thin film layer 103 extends in a direction parallel to the bottom gate electrode structure 102;

[0064] A top electrode structure 104, wherein the top electrode structure 104 is located on a portion of the antiferroelectric thin film layer 103;

[0065] An oxide semiconductor layer 105, wherein the oxide semiconductor layer 105 is located on the antiferroelectric thin film layer 103;

[0066] The source electrode layer and the drain electrode layer 106 are located on the oxide channel and a portion of the antiferroelectric thin film layer 103 .

[0067] In the above-mentioned antiferroelectric thin film transistor 10, the substrate layer 101 with an insulating layer provides basic support for the entire antiferroelectric thin film transistor 10, and usually adopts a doped Si substrate with an insulating layer, and the doping type can be N-type or P-type. The N-type substrate layer is suitable for the flow of electrons, while the P-type substrate layer is suitable for the flow of holes. Common substrate materials include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and flexible substrate layers such as PT plastics.

[0068] In the above-mentioned antiferroelectric thin film transistor 10, the bottom gate electrode structure 102 is located in a specific surface area above the substrate layer 101 with an insulating layer. The bottom gate electrode structure 102 can control the flow of carriers in the channel by voltage, thereby adjusting the conductivity of the device. For example, in the bottom gate electrode structure, the electrode is an electrode of titanium nitride, tungsten, aluminum and / or copper material. It is worth noting that the bottom gate electrode structure 102 does not cover the entire substrate, but is formed in a certain part of the substrate, so as to ensure that the electric field is generated in the required area. That is, the bottom gate electrode extends in parallel along the surface area of ​​the substrate, usually in the form of a rectangle, so that the electric field distribution is more uniform, thereby improving the device performance.

[0069] In the above-mentioned antiferroelectric thin film transistor 10, the antiferroelectric thin film layer 103 is located above the substrate layer 101 with an insulating layer and the bottom gate electrode structure 102. The antiferroelectric thin film layer 103 is a hafnium-based antiferroelectric material with antiferroelectric properties, which can induce polarization effect through an electric field and spontaneously depolarize after the electric field is removed, thereby affecting the electrical properties of the semiconductor device. For example, hafnium zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, hafnium lanthanum oxide, hafnium yttrium oxide, hafnium gadolinium oxide and hafnium strontium oxide. The antiferroelectric thin film layer 103 can effectively adjust the concentration of carriers in the channel, thereby controlling the conductive properties of the device. The antiferroelectric thin film layer 103 extends in the parallel direction of the gate structure, ensuring the uniform distribution of the electric field in the dielectric layer, thereby enhancing the stability and performance of the device.

[0070] In the above-mentioned antiferroelectric thin film transistor 10, the top electrode structure 104 is located above a portion of the antiferroelectric thin film layer 103. The top electrode structure 104 is mainly used to apply voltage to control the performance of the device. The top electrode structure 104 allows the top electrode to directly contact the antiferroelectric thin film layer 103. By applying an appropriate voltage or signal on the top electrode structure 104, the polarization state of the antiferroelectric thin film layer 103 can be adjusted, thereby affecting the conductivity and switching characteristics of the device.

[0071] In the above-mentioned antiferroelectric thin film transistor 10, the oxide semiconductor layer 105 is located above a portion of the antiferroelectric thin film layer 103. The oxide semiconductor layer 105 is usually made of an oxide material, and has good electrical conductivity and high electron mobility. For example, indium gallium zinc oxide (or indium gallium zinc oxide), indium trioxide, gallium trioxide and zinc oxide. The main function of the oxide semiconductor layer 105 is to serve as a carrier channel, and to control the source-drain current by adjusting the electric field applied to its gate, and to effectively utilize the polarization effect of the antiferroelectric dielectric to adjust the source-drain current.

[0072] In the above-mentioned antiferroelectric thin film transistor 10, the source layer and the drain layer 106 are respectively located above a portion of the oxide semiconductor layer 105 and a portion of the antiferroelectric thin film layer 103. The electrodes of the source layer and the drain layer 106 are, for example, electrodes of titanium nitride, tungsten, gold, cadmium and / or copper materials. The source layer is responsible for injecting carriers (such as electrons or holes) into the oxide semiconductor channel, while the drain layer collects carriers flowing out of the oxide semiconductor channel, so that current can flow between the source and the drain, and the current is regulated by the conductivity of the oxide channel. At the same time, the presence of the antiferroelectric thin film layer 103 can enhance the electric field effect and improve the switching performance and stability of the device.

[0073] The antiferroelectric thin film transistor proposed in the embodiment of the present application is obtained by forming a bottom gate electrode structure on the surface area of ​​the substrate layer with an insulating layer, forming an antiferroelectric thin film layer on the substrate layer with an insulating layer and the bottom gate electrode structure, forming a top electrode structure and an oxide semiconductor layer in sequence above the antiferroelectric thin film layer, and forming a source layer and a drain layer above the oxide semiconductor layer and the antiferroelectric thin film layer. For the antiferroelectric thin film transistor, not only the compactness of the device structure is achieved, but also it can be applied to various intelligent sensing systems; moreover, during use, by applying an electric pulse signal on the top electrode structure to trigger the polarization and depolarization characteristics of the antiferroelectric thin film, the LIF neuron behavior in the electrical mode can be achieved; by applying an optical pulse signal on the oxide semiconductor layer, the photosensitivity of the oxide semiconductor can be used to achieve the LIF neuron behavior in the optical mode, that is, the dual perception ability of the electrical signal and the optical signal is achieved.

[0074] Based on the above-mentioned antiferroelectric thin film transistor, an embodiment of the present application further provides a method for preparing an antiferroelectric thin film transistor.

[0075] For example, Figure 8 As shown, the method for preparing an antiferroelectric thin film transistor comprises the following steps:

[0076] Step S100, providing a substrate layer 101 with an insulating layer, such as Figure 2 shown.

[0077] For example, in semiconductor devices, the substrate is the basic material for building the entire structure. The substrate not only provides physical support, but also has an important impact on the electrical characteristics of the device. In order to optimize performance, the substrate material is usually selected as an N-type or P-type substrate material with an insulating oxide layer. For example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), PT plastic, etc.

[0078] Specifically, an insulating oxide layer refers to a layer of insulating oxide, usually silicon dioxide (SiO2), covering the surface of the substrate. The function of this insulating layer is to isolate different parts of the circuit, reduce parasitic capacitance, and improve overall device performance.

[0079] For example, N-type substrate: contains excess electrons, suitable for applications requiring high carrier concentration, and is usually used in electronic components. P-type substrate: contains excess holes, suitable for situations where the flow of holes needs to be controlled, and is usually used in devices that need to adjust the direction of current. Commonly used substrate materials include: Silicon (Si): Due to its mature process and wide application, it is the most commonly used substrate material. Germanium (Ge): has higher electron mobility, but the cost is higher. Compound semiconductors (such as gallium arsenide GaAs): suitable for high-frequency and optoelectronic applications, with superior performance but high manufacturing costs. Flexible materials (such as PT plastics, etc.) are suitable for bionic functional applications such as electronic skin.

[0080] Step S200, forming a bottom gate electrode structure 102 on the surface area of ​​the substrate layer 101 with an insulating layer, such as Figure 3 shown.

[0081] Exemplarily, the substrate layer 101 with an insulating layer is the basis of the entire device, the surface area refers to the uppermost surface of the substrate material of the substrate layer 101 with an insulating layer, and the bottom gate electrode structure refers to a rectangular electrode structure formed on the surface area of ​​the substrate layer 101 with an insulating layer.

[0082] In an optional embodiment, in step S200, forming a bottom gate electrode structure 102 on the surface region of the substrate layer 101 with an insulating layer includes:

[0083] Performing magnetron sputtering on the surface area of ​​the substrate layer 101 with the insulating layer to deposit a first thin film with a preset thickness;

[0084] Exemplarily, the first film is deposited on the surface area of ​​the substrate layer 101 with an insulating layer by magnetron sputtering technology. During the deposition process, the sputtering power, gas flow rate, deposition time and substrate temperature need to be precisely controlled to ensure the thickness and structural uniformity of the first film. The sputtered atoms condense on the substrate surface to form a uniform film to ensure its conductivity and good bonding with subsequent layers. For example, the first film material can be titanium nitride, tungsten, aluminum and / or copper, etc.; the preset thickness can be 20nm, 30nm, etc.; the power of magnetron sputtering can be 100W, the argon gas flow rate is 1.5mT; the sputtering time is 45min, etc.

[0085] Coating a photoresist on a portion of the surface area of ​​the first film, and patterning the photoresist to form a photoresist pattern having a bottom gate electrode structure 102;

[0086] Exemplarily, after the deposition is completed, a layer of photoresist is coated on a portion of the surface area of ​​the first film. Photoresist is a photosensitive material used in the subsequent patterning process. The photoresist can be evenly coated using a spin coating method to ensure that its thickness is uniform. The selection of photoresist is usually based on its photosensitive properties and subsequent processing requirements. Subsequently, the photoresist is exposed and the desired structure is patterned through a mask. Under the irradiation of ultraviolet light or an electron beam, the photoresist undergoes a chemical reaction to form a pattern. The unexposed photoresist is removed during the development process, leaving a patterned photoresist structure.

[0087] The surface area of ​​the first film not coated by the photoresist is etched to form a bottom gate electrode structure 102 on the surface of the substrate layer 101 with the insulating layer.

[0088] Exemplarily, a wet etching process is performed to remove the first film region not protected by the photoresist, and an appropriate etchant (e.g., hydrofluoric acid, sulfuric acid or other specific chemical reagent) is selected to selectively dissolve the first film region exposed to the outside through a chemical reaction. The presence of the photoresist protects the film structure below it and avoids the influence of the etchant. After the etching process, the desired bottom gate electrode structure 102 is formed, and the shape and size of the bottom gate electrode accurately correspond to the previously patterned photoresist pattern, thereby laying the foundation for subsequent device processing. For example, the thickness of the bottom gate electrode structure 102 can be 20nm, etc.

[0089] Step S300, forming an antiferroelectric thin film layer 103 on the substrate layer 101 with an insulating layer and the bottom gate electrode structure 102, such as Figure 4 shown.

[0090] Exemplarily, the antiferroelectric thin film layer 103 is generally composed of a hafnium-based antiferroelectric material having good electrical properties, for example, a hafnium-based antiferroelectric material such as HfZrO2, HfAlO2, HfSiO2, HfLaO2, HfYO2, HfGdO2 and / or HfSrO2. These materials can generate polarization when an electric field is applied, and spontaneously depolarize after the electric field is removed, showing volatile characteristics.

[0091] In an optional embodiment, an antiferroelectric thin film layer 103 is formed on the substrate layer 101 with an insulating layer and the bottom gate electrode structure 102, including:

[0092] On the surface of the substrate layer 101 with the insulating layer and the bottom gate electrode structure 102, the first dielectric layer and the second dielectric layer are alternately and cyclically deposited for a preset number of times at a preset ratio to form an antiferroelectric thin film layer 103 with a preset thickness.

[0093] For example, the first dielectric layer is hafnium oxide (HfO 2 ), the second dielectric layer is zirconium oxide (ZrO 2). Taking the atomic layer deposition (ALD) technology as an example, a layer of atoms can be precisely grown on the surface of the substrate layer 101 with an insulating layer and the bottom gate electrode structure 102 by using the deposition technology. 2 and ZrO 2 The calculation of the thickness of the single atomic layer shows that it takes about 130 cycles to grow a 10nm thick antiferroelectric film. During the preparation process, the ratio of hafnium oxide to zirconium oxide is set to 1:6, and 18 macrocycles are grown alternately, each macrocycle includes 1 HfO 2 Growth cycle and 6 ZrO 2 Growth cycle. Through this alternating growth method, HfO 2 and ZrO 2 The mixture is mixed in a preset ratio to form an antiferroelectric thin film layer 103 having good antiferroelectric properties and a thickness of 10 nm.

[0094] It is worth noting that the growth temperature of atomic layer deposition ALD is set to 260°C, which helps to improve the reaction efficiency and film quality. In the atomic layer deposition process, the precursors used are tetra(ethylmethylammonium)hafnium(IV) and tetra(ethylmethylammonium)zirconium(IV), which are the sources of hafnium and zirconium respectively, and H2O participates in the reaction as an oxygen source. These choices ensure the high purity and high quality of the grown film.

[0095] Step S400, forming a top electrode structure 104 on the antiferroelectric thin film layer 103, such as Figure 5 shown.

[0096] Exemplarily, the top electrode structure 104 refers to a square electrode located above the antiferroelectric thin film layer 103, which is usually used to apply an electric field or read out an electric signal. The top electrode can be titanium nitride, aluminum, titanium or other conductive materials, and its function is to control and utilize the electrical properties of the antiferroelectric thin film layer 103. It is worth noting that the top electrode structure 104 needs to be consistent with the material and thickness of the bottom gate electrode structure to ensure the symmetry of the antiferroelectric hysteresis loop.

[0097] In an optional embodiment, a top electrode structure 104 is formed on the antiferroelectric thin film layer 103, comprising:

[0098] Magnetron sputtering is performed on a portion of the antiferroelectric thin film layer 103 to deposit a first thin film of a preset thickness.

[0099] For example, magnetron sputtering is a commonly used thin film deposition technology, which uses ions in plasma to bombard a target material, sputtering atoms or molecules of the target material and depositing them on the antiferroelectric thin film layer 103. The first film refers to a TiN titanium nitride film, which is an excellent conductive material with high hardness and chemical stability.

[0100] In detail, a TiN film with a thickness of 30 nm is deposited on the antiferroelectric film layer 103 using magnetron sputtering technology. The power of the magnetron sputtering is 100 W, the argon gas flow rate is 1.5 mT, and the sputtering time is 45 min. It is worth noting that in this embodiment, the preset thickness is 30 nm, while in other embodiments, the thickness, power, flow rate, and time can be set according to actual conditions.

[0101] A photoresist is coated on the first film and patterned to form a photoresist pattern having a top electrode structure 104 .

[0102] Exemplarily, a layer of positive photoresist is uniformly coated on the surface of the TiN film, for example, using a spin coating technique to ensure the uniformity and required thickness of the photoresist layer. After coating, pre-baking is performed to heat the photoresist to remove the solvent therein, enhance the adhesion of the photoresist, and prepare for subsequent exposure. The TiN film coated with the positive photoresist is placed in a photolithography machine and exposed using ultraviolet light or other light sources of appropriate wavelengths. In this step, specific areas of the photoresist absorb light and undergo chemical reactions, making these areas more soluble in the subsequent development process. After exposure, the TiN film is immersed in a developer, and the unexposed photoresist is removed, while the exposed areas are left, thereby forming a pattern of the top electrode.

[0103] The surface area of ​​the first thin film not coated by the photoresist is processed by wet etching to form a top electrode structure 104 on the surface of a portion of the antiferroelectric thin film layer 103 .

[0104] Exemplarily, wet etching is a technique for removing materials using chemical solutions. In the present embodiment, it is used to remove the part not covered by the photoresist in the TiN film. The etching solution usually contains a chemical composition that can selectively dissolve a specific material so as to remove the material without affecting the area protected by the photoresist. The area not coated with the photoresist refers to that in the photolithography process, the photoresist only covers certain specific areas, and the uncovered part will be exposed to the outside and become the target area of ​​the wet etching. By wet etching the area not protected by the photoresist, the film material in these areas can be removed, thereby forming the required top electrode structure 104 on the surface of the antiferroelectric film layer 103.

[0105] For example, using a 30% H 2 O 2 When the solution wet-etches the TiN electrode, the portion of the electrode without the photoresist will be etched, thereby achieving patterning of the top TiN electrode. The wet-etching time is set to 20 minutes to ensure that the TiN film at the non-bottom electrode is completely etched.

[0106] In an optional embodiment, after the film surface area not coated with the photoresist is treated by wet etching to form a top electrode structure 104 on the surface of a portion of the antiferroelectric film layer 103, the method includes:

[0107] The antiferroelectric thin film layer 103 is subjected to a rapid annealing treatment for a preset time to recrystallize the antiferroelectric thin film layer 103 .

[0108] Demonstratively, Rapid Thermal Annealing (RTA) is a heat treatment process that heats and cools rapidly in a short time. In this embodiment, the antiferroelectric film layer 103 is subjected to rapid thermal annealing by heating at a temperature of 550°C in a pure nitrogen atmosphere for 30 seconds to promote the recrystallization of the film. In this process, the clamping stress applied by the upper and lower electrodes helps to improve the microstructural quality of the film, and the antiferroelectric film exhibits good antiferroelectric properties after annealing. The antiferroelectric film does not exhibit antiferroelectric properties in the portion not covered by the top electrode structure 104. Excellent antiferroelectric performance is a prerequisite for antiferroelectric capacitors to regulate the source-drain current of thin-film transistors, and is the basis for realizing LIF neurons under electrical pulse signals.

[0109] Step S500 , forming an oxide semiconductor layer 105 on the antiferroelectric thin film layer 103 .

[0110] For example, after the antiferroelectric thin film layer 103 is annealed, the oxide semiconductor layer 105 can be formed on the antiferroelectric thin film layer 103 using photolithography, magnetron sputtering or other thin film deposition techniques to ensure that the formed oxide semiconductor layer 105 has the required thickness, uniformity and electrical properties, such as Figure 6 shown.

[0111] In an optional embodiment, forming an oxide semiconductor layer 105 on the antiferroelectric thin film layer 103 includes:

[0112] Coating a photoresist on a portion of the antiferroelectric thin film layer 103, and exposing and developing the photoresist using a mask to form a photoresist pattern complementary to the mask;

[0113] Exemplarily, a photoresist is coated on a portion of the antiferroelectric thin film layer 103, and then ultraviolet light is projected onto the photoresist through a mask. After exposure, the photoresist is patterned by a developer, and finally a pattern complementary to the mask is left.

[0114] For example, photoresist is a photosensitive material that is usually coated on the surface of a film. The coating method can be spin coating, spray coating, etc.; a mask is a template that is usually composed of a transparent substrate (such as quartz) and an opaque area (usually made of metal or other opaque materials). The mask is used to control the area where light is irradiated, that is, it projects the pattern onto the photoresist. The pattern on the mask is projected onto the antiferroelectric film coated with photoresist by ultraviolet light (or other light sources of suitable wavelengths). After exposure, the photoresist undergoes a chemical reaction in the part irradiated by light. For positive photoresist, the exposed part becomes easier to dissolve; for negative photoresist, the exposed part becomes more difficult to dissolve. Then it is immersed in a developer to remove the part that is dissolved after exposure, leaving the photoresist pattern in the unexposed part. In this way, the pattern on the photoresist (complementary to the mask pattern) is transferred to the antiferroelectric film. "Complementary" means that the pattern on the mask is opposite to the pattern finally formed in the photoresist.

[0115] Performing magnetron sputtering on the patterned photoresist to deposit a second film of a preset thickness;

[0116] Demonstratively, the second film is an a-IGZO film with a preset thickness of 20 nanometers. Specifically, a 20nm thick a-IGZO (amorphous indium gallium zinc oxide) film is grown on a portion of the antiferroelectric film using magnetron sputtering technology. In this step, the power of the magnetron sputtering equipment is set to 100 watts to ensure the efficiency and stability of the sputtering process; at the same time, the flow rate of argon gas is precisely controlled to 6 standard cubic centimeters per minute (6sccm), providing the necessary atmosphere for the sputtering process. The entire sputtering process lasts for 300 seconds. During this period, the a-IGZO material is uniformly and densely deposited on the antiferroelectric film, forming a film with a thickness of 20 nanometers, which lays a solid foundation for the subsequent performance optimization and improvement of semiconductor devices.

[0117] The photoresist is dissolved by a dissolving agent, so that the second film deposited on the surface of the photoresist is peeled off, thereby forming the oxide semiconductor layer 105 .

[0118] For example, acetone is used as a solvent to dissolve the photoresist. In this process, the area not covered and protected by the photoresist will be completely exposed. Subsequently, using the dissolving effect of acetone, the corresponding a-IGZO (amorphous indium gallium zinc oxide) film portion under the photoresist will be accurately removed. At the same time, those a-IGZO film areas that are effectively protected by the photoresist will remain on the antiferroelectric film layer 103. After the photoresist is completely dissolved and removed, the a-IGZO film retained on the antiferroelectric film constitutes a 20nm thick oxide semiconductor layer 105 with a precise pattern.

[0119] It is worth noting that the oxide semiconductor layer 105 can not only serve as the channel layer of the antiferroelectric thin film transistor 10, but also serve as the photosensitive layer in the neuron optical mode. The oxide semiconductor resistance is regulated by the gate voltage and the light signal in the bottom gate electrode structure 102 in the antiferroelectric thin film transistor 10, providing a way to realize the photoelectric fusion sensory neurons.

[0120] Step S600, forming a source electrode layer and a drain electrode layer 106 on the oxide semiconductor layer 105 and the antiferroelectric thin film layer 103, so as to obtain an antiferroelectric thin film transistor 10, such as Figure 7 shown.

[0121] Exemplarily, the source layer and the drain layer 106 are important components of the thin film transistor, which are used to inject and collect carriers (usually electrons or holes) into the oxide semiconductor layer 105. They are located on both sides of the oxide semiconductor layer 105, and the current flow in the channel can be regulated by controlling the voltage difference between the source and the drain. The source layer and the drain layer 106 are usually formed on the oxide semiconductor layer 105 by methods such as physical vapor deposition or chemical vapor deposition. Before deposition, photolithography and etching techniques are usually used to define the precise position and shape of the source and drain. The source layer and the drain layer 106 are usually made of conductive materials, such as gold, titanium, cadmium, copper, aluminum and / or titanium nitride materials. These materials have good conductivity and adhesion to the oxide semiconductor layer 105. When the source layer and the drain layer 106 are formed on the oxide semiconductor layer 105 and the antiferroelectric thin film layer 103, a complete antiferroelectric thin film transistor 10 (AFe-TFT) is formed.

[0122] In an optional embodiment, a source layer and a drain layer 106 are formed on the oxide semiconductor layer 105 and the antiferroelectric thin film layer 103 to obtain an antiferroelectric thin film transistor 10. The antiferroelectric thin film transistor 10 comprises:

[0123] A photoresist is applied on the oxide semiconductor layer 105 and patterned to form a photoresist pattern having the shape of the source electrode layer and the drain electrode layer 106 .

[0124] For example, the photoresist is evenly coated on the oxide semiconductor layer 105 by spin coating, spray coating or other methods. The thickness of the photoresist layer after coating is usually controlled by process parameters (such as spin coating speed, photoresist concentration, etc.). After the photoresist is coated, the photoresist is exposed using a mask and a light source. The mask has a pattern corresponding to the shape of the source layer and the drain layer 106. During the exposure process, only the light allowed by the opening of the mask can be irradiated on the photoresist. After exposure, the photoresist undergoes chemical changes. Next, the photoresist is placed in a developer to remove (for positive photoresist) or retain (for negative photoresist) the photoresist in the exposed area through a chemical reaction. In this way, a photoresist pattern corresponding to the mask pattern is formed.

[0125] Magnetron sputtering is performed on the patterned photoresist to deposit a first conductive metal.

[0126] Exemplarily, the first conductive metal is Ti titanium metal. In the magnetron sputtering process, the first conductive metal is placed on a sputtering target, and the sputtering process is started by applying a high voltage and a magnetic field. The sputtered metal atoms or molecules fly along a specific path to the top of the patterned photoresist under the action of the electric field and the magnetic field. Due to the masking effect of the photoresist pattern, only metal atoms or molecules in the shape of the source layer and the drain layer 106 can be deposited on the oxide semiconductor layer 105 to form a Ti layer. The thickness of the deposited metal layer can be adjusted by controlling the sputtering time and the distance between the target and the substrate.

[0127] For example, in order to ensure that the titanium layer can be uniformly and firmly deposited on the oxide semiconductor layer 105 and the antiferroelectric film layer 103, a magnetron sputtering device is used for deposition. The specific parameters are set as follows: the thickness of the deposited titanium layer is 5 nanometers, the sputtering power is set to 100 watts, argon is used as the sputtering gas, its flow rate is controlled at 3 millitorr, and the sputtering time is set to 150 seconds. The selection of these parameters is intended to optimize the sputtering efficiency and deposition quality, ensuring that the titanium layer can accurately cover the source layer and the drain layer 106 area defined by the photoresist pattern, while maintaining good adhesion and conductivity. In other embodiments, the first conductive metal can also be chromium, nickel, etc.

[0128] Magnetron sputtering is performed on the first conductive metal to deposit the second conductive metal.

[0129] Exemplarily, the second conductive metal is Au metal. After the deposition of the Ti layer is completed, a second magnetron sputtering is performed on the Ti layer to deposit Au metal. For example, the deposition of Au metal is performed by magnetron sputtering equipment using the following parameters: power: 100W; argon gas flow: 3mT; sputtering time: 900s; these parameters are selected to optimize the deposition quality of the Au layer, ensuring that Au can be evenly and firmly covered on the Ti layer and form a good contact with the Ti layer. The deposited Au layer will serve as part of the final electrode, corresponding to the source layer and the drain layer 106, and together constitute the conductive channel of the antiferroelectric thin film transistor 10.

[0130] The photoresist is dissolved by a dissolving agent, so that the second conductive metal deposited on the surface of the photoresist is stripped off to form a source electrode layer and a drain electrode layer 106 .

[0131] Exemplarily, after the metal deposition is completed, a solvent is used to remove the remaining photoresist and any unwanted metal layer portions thereon. The solvent used in the stripping process needs to be able to selectively dissolve the photoresist while not damaging the deposited metal layer. When the photoresist is dissolved and removed, the second conductive metal attached to the photoresist, and possibly part of the first conductive metal, will also be stripped away, leaving only the metal layer deposited in the desired area, i.e., the source and drain layers 106.

[0132] In an optional embodiment, after dissolving the photoresist with a dissolving agent to remove the second conductive metal deposited on the surface of the photoresist and forming the source electrode layer and the drain electrode layer 106, the method further includes:

[0133] Annealing treatment is performed on the oxide semiconductor layer 105 located below the source and drain electrode layers 106 to recrystallize the oxide semiconductor layer 105 .

[0134] For example, the IGZO (Indium Gallium Zinc Oxide) film in the oxide semiconductor layer 105 is usually annealed in an air atmosphere. The purpose of the annealing step is to recrystallize the oxide semiconductor layer, reduce the defects of the film in the oxide semiconductor layer, and obtain good thin film transistor performance. At the same time, the low temperature annealing step will not affect the performance of the antiferroelectric film. Specific parameters include: in an air atmosphere, the temperature is accurately set at 300°C and maintained at this temperature for up to 20 minutes.

[0135] It is worth noting that the annealing conditions are so mild because we need to optimize the performance of the IGZO film while ensuring that the structure and performance of the adjacent antiferroelectric film are not damaged. The annealing treatment strategy of this embodiment successfully optimizes the microstructure and performance of the IGZO film while maintaining the stability of the IGZO film and antiferroelectric capacitor performance.

[0136] It is worth noting that Fig. 9 As shown, after obtaining the antiferroelectric thin film transistor 10 that meets the design requirements, the present application also performs a performance test on the antiferroelectric thin film transistor 10. That is, by applying an electric pulse signal to the top electrode structure 104 and an optical pulse signal to the oxide semiconductor layer 105, the change of the neuron membrane potential is simulated.

[0137] (1) In the electrical mode of the test device, the function of neurons is simulated by applying an electric pulse signal to the top electrode structure 104 of the antiferroelectric thin film transistor 10. That is, the electric pulse signal triggers the polarization (causing the gate voltage to accumulate) and depolarization characteristics (causing the gate voltage to decrease) of the antiferroelectric film, and the accumulation and decrease of the gate voltage will control the source-drain voltage in the source layer and the drain layer 106, thereby regulating the source-drain current to simulate the state of the neuron membrane potential under stimulation.

[0138] Under the action of the electric pulse signal, the antiferroelectric film is polarized, resulting in the accumulation of the gate voltage in the bottom gate electrode structure 102; when the electric pulse signal is stopped, the antiferroelectric film is spontaneously depolarized, and the gate voltage in the bottom gate electrode structure 102 is reduced. These two processes jointly affect the source-drain current of the antiferroelectric thin film transistor. The change of the source-drain current in the source layer and the drain layer 106 simulates the response of the neuron membrane potential under stimulation. When the gate voltage accumulates to a certain extent, the source-drain current increases, simulating the excitement of the neuron; when the gate voltage decreases, the source-drain current decreases, simulating the inhibition of the neuron.

[0139] For example, the specific settings of the electric pulse signal are: the pulse period is 200 μs; the voltage amplitude is 0-7V; the duty cycle is 50%; Fig.10 As shown in the figure, as the electric pulse is applied, the gate voltage gradually accumulates, causing the source-drain current to increase. When the source-drain current reaches or exceeds the set threshold current (5μA), the neuron is considered to have "fired", that is, an action potential has been generated. Fig.10 As shown, the neuron reached the threshold current for firing under the fourth electric pulse.

[0140] Under the continuous application of electric pulses, the gate voltage continues to accumulate, resulting in the accumulation of source-drain current (integration process). When the source-drain current accumulates to the set threshold current, the control stops applying electric pulses, and the gate voltage automatically decreases, resulting in the source-drain current decreasing back to the initial state (leakage process). This process simulates the leakage phenomenon of neuronal membrane potential. Fig.10 As shown, the leakage time is 16ms, after which the source-drain current returns to the initial state and the electrical mode neuron returns to the resting period.

[0141] The test results show that the antiferroelectric thin film transistor 10 successfully simulates the "leakage-integration-firing" performance of neurons in the electrical mode. That is, by precisely controlling the parameters of the electrical pulse signal, the device can accurately simulate the typical behavior pattern of neurons.

[0142] (2) In the optical mode of the test device, a light pulse signal is applied to the oxide semiconductor layer 105 of the antiferroelectric thin film transistor 10 exposed to the field of view to simulate the function of neurons.

[0143] It can be understood that oxide semiconductors can generate photogenerated carriers under light, and when the light pulse signal irradiates the oxide semiconductor layer 105, the photons interact with the electrons in the semiconductor material, resulting in the generation of photogenerated carriers. When the light pulse signal causes the conductivity of the oxide semiconductor layer 105 to increase, the source-drain current will also increase accordingly, simulating the excited state of neurons; and when the conductance decreases due to the recombination of photogenerated carriers, the source-drain current decreases, simulating the inhibited state of neurons.

[0144] For example, Fig.11 As shown, an ultraviolet light pulse signal is used as the stimulus source. The period of the light pulse signal is 50ms, the wavelength is 365nm, and the light intensity is 0.84W / cm 2 . Under the continuously applied light pulse signal, the photogenerated carriers in the oxide semiconductor layer 105 continue to accumulate (integration process), causing the source-drain current to gradually increase. When the source-drain current reaches or exceeds the set ignition threshold current (for example, 5μA), it is considered that the photomodal neuron has reached the ignition state, that is, an action potential has been generated. Under the 11th light pulse, the neuron reached the ignition threshold current. After reaching the ignition state, the control stops applying the light pulse, and the source-drain current gradually decreases back to the initial state (leakage process). This is due to the gradual recombination of the photogenerated carriers in the oxide semiconductor. After a period of time (for example, 24s), the source-drain current returns to the initial state, indicating that the photomodal neuron has returned to the resting period.

[0145] The test results show that the antiferroelectric thin film transistor 10 achieves good neuron "leakage-integration-firing" performance in the optical mode, which means that by precisely controlling the parameters of the optical pulse signal and monitoring the changes in the source-drain current, the device can be used to simulate the typical behavior pattern of neurons.

[0146] It can be seen from the above tests that the antiferroelectric thin film transistor 10 can exhibit good LIF neuron performance regardless of the optical mode or the electrical mode, that is, the antiferroelectric thin film transistor of the embodiment of the present application realizes the dual perception capability of electrical signals and optical signals.

[0147] It is worth noting that the values ​​of the above parameters are only examples and can be adaptively adjusted according to specific circumstances.

[0148] The antiferroelectric thin film transistor of the embodiment of the present application realizes LIF neuron behavior in the electrical mode by applying an electric pulse signal to the top electrode structure in the antiferroelectric thin film transistor to trigger the polarization and depolarization characteristics of the antiferroelectric thin film; and realizes LIF neuron behavior in the optical mode by applying an optical pulse signal to the oxide semiconductor layer in the antiferroelectric thin film transistor and utilizing the photosensitivity of the oxide semiconductor. That is, the antiferroelectric thin film transistor of the present application realizes dual perception capabilities of electrical signals and optical signals.

[0149] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A method for preparing an antiferroelectric thin film transistor, characterized in that: include: providing a substrate layer with an insulating layer; forming a bottom gate electrode structure in a surface region of the substrate layer with the insulating layer; forming an antiferroelectric thin film layer on the substrate layer with the insulating layer and the bottom gate electrode structure; forming a top electrode structure and an oxide semiconductor layer in sequence above the antiferroelectric thin film layer; A source electrode layer and a drain electrode layer are formed above the oxide semiconductor layer and the antiferroelectric thin film layer to obtain an antiferroelectric thin film transistor.

2. The method for preparing an antiferroelectric thin film transistor according to claim 1, characterized in that: The forming of a bottom gate electrode structure in the surface area of ​​the substrate layer with the insulating layer comprises: Performing magnetron sputtering on the surface area of ​​the substrate layer with the insulating layer to deposit a first film of a preset thickness; Coating a photoresist on the surface area of ​​the first film, and patterning the photoresist to form a photoresist pattern having the bottom gate electrode structure; The surface area of ​​the first film not coated by the photoresist is processed by wet etching to form the bottom gate electrode structure on the surface of the substrate layer with the insulating layer.

3. The method for preparing an antiferroelectric thin film transistor according to claim 1, characterized in that: The step of forming an antiferroelectric thin film layer on the substrate layer with the insulating layer and the bottom gate electrode structure comprises: On the substrate layer with the insulating layer and the surface of the bottom gate electrode structure, the first dielectric layer and the second dielectric layer are alternately and cyclically deposited for a preset number of times at a preset ratio to form an antiferroelectric thin film layer with a preset thickness.

4. The method for preparing an antiferroelectric thin film transistor according to claim 1, characterized in that: The forming of a top electrode structure above the antiferroelectric thin film layer comprises: Performing magnetron sputtering on a portion of the antiferroelectric thin film layer to deposit the first thin film with a preset thickness; Coating a photoresist on a portion of the first film, and patterning the photoresist to form the photoresist pattern having the top electrode structure; The surface area of ​​the first film not coated by the photoresist is subjected to an etching process to form the top electrode structure on the surface of a portion of the antiferroelectric film layer.

5. The method for preparing an antiferroelectric thin film transistor according to claim 4, characterized in that: After the etching treatment is performed on the surface area of ​​the first film not coated by the photoresist to form the top electrode structure on the surface of a portion of the antiferroelectric film layer, the method comprises: The antiferroelectric thin film layer is subjected to a rapid annealing treatment for a preset time to recrystallize the antiferroelectric thin film layer.

6. The method for preparing an antiferroelectric thin film transistor according to claim 1, characterized in that: The step of forming an oxide semiconductor layer above the antiferroelectric thin film layer comprises: Coating a photoresist on a portion of the antiferroelectric thin film layer, and exposing and developing the photoresist using a mask to form a photoresist pattern complementary to the mask; Performing magnetron sputtering on the patterned photoresist to deposit a second film of a preset thickness; The photoresist is dissolved by a solvent, so that the second film deposited on the surface of the photoresist is peeled off to form an oxide semiconductor layer.

7. The method for preparing an antiferroelectric thin film transistor according to claim 1, characterized in that: The forming of a source electrode layer and a drain electrode layer above the oxide semiconductor layer and the antiferroelectric thin film layer comprises: Coating the photoresist on the oxide semiconductor layer, and patterning the photoresist to form a photoresist pattern having the shape of the source electrode layer and the drain electrode layer; Performing magnetron sputtering on the patterned photoresist to deposit a first conductive metal; Performing magnetron sputtering on the first conductive metal to deposit a second conductive metal; The photoresist is dissolved by a dissolving agent, so that the second conductive metal deposited on the surface of the photoresist is stripped off to form the source electrode layer and the drain electrode layer.

8. The method for preparing an antiferroelectric thin film transistor according to claim 1, characterized in that: After the photoresist is dissolved by a dissolving agent so that the second conductive metal deposited on the surface of the photoresist is stripped off and the source electrode layer and the drain electrode layer are formed, the method comprises: The oxide semiconductor layer located below the source electrode layer and the drain electrode layer is annealed to recrystallize the oxide semiconductor layer.

9. An antiferroelectric thin film transistor, characterized in that: include: A substrate layer with an insulating layer; A bottom gate electrode structure, wherein the bottom gate electrode structure is located in a surface area above a portion of the substrate layer with the insulating layer, and the bottom gate electrode structure extends in a direction parallel to the surface area above the substrate layer with the insulating layer; an antiferroelectric thin film layer, the antiferroelectric thin film layer being located above the substrate layer with the insulating layer and the bottom gate electrode structure, and the antiferroelectric thin film layer extending in a direction parallel to the bottom gate electrode structure; A top electrode structure, wherein the top electrode structure is located on a portion of the antiferroelectric thin film layer; an oxide semiconductor layer, wherein the oxide semiconductor layer is located on a portion of the antiferroelectric thin film layer; A source electrode layer and a drain electrode layer, wherein the source electrode layer and the drain electrode layer are located on the oxide semiconductor layer and a portion of the antiferroelectric thin film layer.

10. The antiferroelectric thin film transistor according to claim 9, characterized in that: The thickness of the antiferroelectric thin film layer is in the range of 8nm-12nm.

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