Indium oxide interface layer field effect transistor with improved contact resistance and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly relates to an indium oxide interface layer field effect transistor with improved contact resistance and a preparation method thereof, and the method specifically comprises the following steps: selecting a gate electrode, and preparing a gate dielectric layer on the gate electrode through an atomic layer deposition technology; preparing a channel layer on the gate dielectric layer through an atomic layer deposition technology, and then carrying out electron beam exposure and isolation region etching on the channel layer to obtain a channel region; carrying out atomic deposition on an indium oxide material on the channel region by adopting atomic deposition equipment to obtain a contact layer, and then carrying out electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; and then electron beam exposure and metal deposition are carried out on the source-drain region contact layer to prepare a metal electrode, so that the indium oxide interface layer field effect transistor with improved contact resistance is obtained, and the field effect transistor can be widely applied to the technical field of semiconductor devices.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to an indium oxide interface layer field effect transistor with improved contact resistance and a preparation method thereof. Background Art

[0002] As the feature size of Si metal oxide semiconductor field effect transistors (MOSFETs) develops to 3 nm technology nodes and below, the proportion of channel resistance in the on-resistance of MOSFET devices gradually decreases, and contact resistance plays an increasingly important role in the total on-resistance. In short-channel devices, the total on-resistance of the transistor is determined by the resistance at the metal semiconductor contact (S / D), so minimizing contact resistance is crucial for the industry to further reduce the scale of complementary metal oxide semiconductor (CMOS) integrated circuits and extend Moore's Law.

[0003] In terms of contact resistance optimization, there are several traditional solutions: optimization of metal materials, selecting appropriate metals can effectively reduce the contact barrier of gold semiconductor contacts and thus reduce contact resistance. In practice, Ni, Pt, Pd, W, and Ti are often used as contact metals; optimization of interface processes, in the process of depositing metals in the electron beam evaporation coating system, the vacuum degree of the equipment is improved to make the deposited metal roughness lower and the interface quality better; high-concentration doping is performed in the source and drain contact areas to increase the carrier concentration in the contact area and reduce the contact resistance; optimization of the heat treatment process, and appropriate heat treatment processes can improve the contact resistance. By controlling the annealing temperature, time, atmosphere and other conditions, the bonding quality between metal and semiconductor can be improved. The above traditional optimization solutions can improve the contact resistance of gold semiconductor contacts, but the effect is often not obvious, and some measures may even have a negative impact on other electrical parameters of the device. For example, heavy doping will lead to large leakage current, which requires lightly doped drain process (LDD) improvement, and pure oxygen high temperature annealing will reduce mobility, and sometimes increase contact resistance. Therefore, we need a stable and effective contact resistance improvement solution.

[0004] The new oxide material, indium trioxide (In2O3), has a high carrier mobility due to its high overlap of the outermost s orbital. Its more oxygen vacancies can also provide a larger carrier concentration. The wide bandgap leads to its extremely low leakage current, the low contact barrier leads to its low contact resistance, and the low thermal budget makes it compatible with the back-end (BEOL) process, making it an excellent material for improving the contact resistance of MOSFET.

[0005] In addition, compared with traditional magnetron growth channel materials, a new generation of deposition method - atomic layer deposition (ALD) is used to improve the interface process. Atomic layer deposition is a highly controllable thin film deposition technology developed from chemical vapor deposition. It utilizes the self-limiting behavior and complementary reaction of the precursor during the chemical reaction. Self-limiting behavior means that no matter how much pulse volume of the precursor is, when all active sites on the surface of the reactant are reacted, the chemical reaction reaches a self-saturated state. The complementary reaction refers to the chemical reaction of ALD, which involves at least two different molecules exposed to the surface for thin film deposition. These two mechanisms cause ALD to generate high-quality, conformal, and low-roughness deposited films even at relatively low temperatures. These advantages have enabled ALD to play an important role in the field of thin film deposition. Summary of the invention

[0006] In view of the defects of the prior art, the present invention provides an indium oxide interface layer field effect transistor with improved contact resistance and a preparation method thereof, the purpose of which is to solve the technical problem that the contact resistance of the source and drain regions of the existing field effect transistor is large, resulting in a small on-state current of the short channel device and a small switch ratio. To achieve the above purpose, the present invention adopts the following technical solutions: According to a first aspect of the present invention, there is provided an indium oxide interface layer field effect transistor with improved contact resistance, wherein the structure is a back-gate structure, specifically comprising, from bottom to top, a gate electrode, a gate dielectric layer, a channel layer, a drain-source contact layer, and a metal electrode, wherein the channel layer is located in the middle region of the gate dielectric layer and the edges of the gate dielectric layer are not covered by the channel layer, the drain-source contact layers are spaced at both ends of the channel layer, the metal electrodes are arranged on the top of the drain-source contact layers, and the material of the drain-source contact layers is indium trioxide.

[0007] According to another first aspect of the present invention, specifically: from bottom to top, it includes a substrate, a channel layer, a drain-source contact layer, and a metal electrode, the channel layer is located in the middle area of ​​the substrate and the four edges of the substrate are not covered by the channel layer, the drain-source contact layers are spaced at both ends of the channel layer, the metal electrodes are arranged on the top of the drain-source contact layers, the channel layer, the drain-source contact layer, and the uncovered surfaces of the metal electrodes are covered with a gate dielectric layer, the area of ​​the gate dielectric layer between the spaced metal electrodes is a recessed area, the area of ​​the gate dielectric layer on the top of the metal electrode is a raised area, the gate electrode is arranged on the top of the gate dielectric layer, the gate electrode completely covers the recessed area and continues to the raised area, and the gate electrode does not completely cover the raised area, and the material of the drain-source contact layer is indium trioxide.

[0008] Preferably, the thickness of the drain-source region contact layer is 0.4-2 nm.

[0009] Preferably, the material of the gate electrode is selected from one or more of silicon, platinum and gold.

[0010] Preferably, the material of the gate dielectric layer is selected from one or more of silicon oxide, hafnium oxide, aluminum oxide, lanthanum oxide, antimony oxide, zirconium oxide, hafnium aluminum oxide, hafnium oxide silicate, and hafnium lanthanum oxide.

[0011] Preferably, the material of the channel layer is selected from amorphous oxides, preferably one or more of zinc oxide, indium oxide, gallium oxide, indium gallium zinc oxide, indium tin oxide, indium gallium tin oxide, and indium gallium oxide; and the channel layer is an n-type channel.

[0012] According to another aspect of the present invention, a method for preparing an indium oxide interface layer field effect transistor with improved contact resistance is provided, which specifically comprises the following steps: (1) selecting a gate electrode and preparing a gate dielectric layer on the gate electrode by atomic layer deposition technology; (2) preparing a channel layer on the gate dielectric layer by atomic layer deposition technology, and then performing electron beam exposure and isolation region etching on the channel layer to obtain a channel region; (3) using an atomic deposition device to atomically deposit an indium trioxide material on the channel region to obtain a contact layer, and then performing electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; (4) Then, electron beam exposure and metal deposition are performed on the source-drain contact layer to prepare a metal electrode, thereby obtaining the indium oxide interface layer field effect transistor.

[0013] According to another aspect of the present invention, a method for preparing an indium oxide interface layer field effect transistor with improved contact resistance is provided, which specifically comprises the following steps: S1: selecting a substrate, preparing a channel layer on the substrate by atomic layer deposition technology, and then performing electron beam exposure and isolation region etching on the channel layer to obtain a channel region; S2 uses an atomic deposition device to atomically deposit an indium trioxide material on the channel region to obtain a contact layer, and then performs electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; S3 then performs electron beam exposure and metal deposition on the source and drain contact layer to prepare a metal electrode; S4: coating the substrate, the channel layer, the drain-source contact layer, and the metal electrode with a gate dielectric layer by atomic layer deposition technology; S5: preparing a gate electrode on the gate dielectric layer by electron beam evaporation, thereby obtaining the indium oxide interface layer field effect transistor.

[0014] Preferably, in step (1), the gate electrode is pre-treated, and the specific steps of the pre-treatment are: placing the gate electrode in a mixed solution of ammonia water and hydrogen peroxide, heating it, and then cleaning it.

[0015] Preferably, in step (3) or step S2, the preparation step of the contact layer is specifically: (3-(dimethylamino)propyl)-dimethylindium is introduced into the atomic deposition device, and then nitrogen or argon is introduced for a first purge, and then a water pulse is introduced to oxidize the (3-(dimethylamino)propyl)-dimethylindium on the channel layer to generate indium trioxide, and nitrogen or argon is introduced again for a second purge.

[0016] Preferably, in step (3) or step S2, the temperature of the In2O3 deposition reaction is 90~150°C, the source temperature of the (3-(dimethylamino)propyl)-dimethylindium is 65~80°C, the time of the water pulse is 0.4~1 s, and the time of the first and second nitrogen purges is 20~40s.

[0017] In general, the above technical solution conceived by the present invention has the following technical advantages compared with the prior art: (1) The active region contact layer material of the present invention is selected from In2O3 because In2O3 itself has a large number of oxygen vacancies and a large carrier concentration, which can reach 100 cm 2 / V·s or above; at the same time, it has a relatively low contact barrier when in contact with metal, which is conducive to the thermal emission of electrons to cross the contact barrier, increase the on-current, and help reduce the contact resistance; the specific choice of stacking In2O3 in the source and drain regions can ensure that the contact resistance is reduced without affecting the device channel doping concentration and field effect mobility, thereby improving the overall performance of the field effect transistor and paving the way for the development of field effect transistors in the post-Moore era.

[0018] (2) The present invention uses atomic layer deposition technology to deposit the In2O3 contact layer. Since the atomic layer deposition technology is a self-limiting reaction growth, the deposited material grows layer by layer. Even in a special morphology with a high aspect ratio, the deposition is still highly conformal, so that the deposited In2O3 has good uniformity and low roughness, which effectively improves the interface quality during contact. In addition, the atomic layer deposition growth can be carried out at a low temperature of 90~150℃, which does not increase the thermal budget of the field effect transistor and is beneficial to the back-end process.

[0019] (3) The present invention uses an atomic layer deposition (ALD) method to deposit an In2O3 contact layer, and the specific steps are to introduce (3-(dimethylamino)propyl)-dimethylindium (DADI) into the atomic deposition device to allow the precursor to react with the surface active sites, and then introduce nitrogen or argon for purging to remove the incompletely reacted DADI and the reaction byproduct methane, and then introduce a water pulse as an oxidant to further oxidize the DADI on the channel layer, and oxidize the (3-(dimethylamino)propyl)-dimethylindium on the channel layer to generate In2O3, and then introduce nitrogen or argon for purging again to remove excess water pulses and the reaction byproduct methane, and repeat these four steps. By controlling the number of cycles, the thickness of the indium oxide film can be controlled and adjusted, thereby controlling the size of the transistor and optimizing the contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention is a flowchart of the preparation of an indium oxide interface layer field effect transistor with improved contact resistance.

[0021] Figures 2 to 6 A structural schematic diagram of the preparation process of the indium oxide interface layer field effect transistor with improved back gate structure contact resistance provided by the present invention.

[0022] Figure 7 A schematic structural diagram of an indium oxide interface layer field effect transistor with improved top gate structure contact resistance provided by the present invention.

[0023] Figure 8 Schematic diagram of the structure of the field effect transistor without In2O3 contact layer prepared in Comparative Example 1.

[0024] Fig. 9 Schematic diagram of improvement of the output characteristic curve of the field effect transistor of Example 1 and Comparative Example 1.

[0025] In the figure: 11, gate electrode; 21, gate dielectric; 31, channel layer; 41, drain-source contact layer; 51, metal electrode; 61, substrate. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] According to a first aspect of the present invention, there is provided an indium oxide interface layer field effect transistor with improved contact resistance, wherein the structure is a back-gate structure, specifically comprising, from bottom to top, a gate electrode 11, a gate dielectric layer 21, a channel layer 31, a drain-source contact layer 41, and a metal electrode 51, wherein the channel layer 31 is located in the middle region of the gate dielectric layer 21 and the edges of the gate dielectric layer 21 are not covered by the channel layer 31, the drain-source contact layers 41 are arranged at intervals at both ends of the channel layer 31, the metal electrodes 51 are arranged on the top of the drain-source contact layers 41, and the material of the drain-source contact layers 41 is indium trioxide.

[0028] According to another aspect of the present invention, there is provided an indium oxide interface layer field effect transistor with improved contact resistance, wherein the structure is a top gate structure, specifically comprising, from bottom to top, a substrate 61, a channel layer 31, a drain-source region contact layer 41, and a metal electrode 51, wherein the channel layer 31 is located in the middle region of the substrate 61 and the edges of the substrate 61 are not covered with the channel layer 31, the drain-source region contact layer 41 is arranged at intervals at both ends of the channel layer 31, the metal electrode 51 is arranged on the top of the drain-source region contact layer 41, and the channel layer 31 , the drain-source contact layer 41, and the surface not covered by the metal electrode 51 are all covered with the gate dielectric layer 21, the area of ​​the gate dielectric layer 21 between the spaced metal electrodes 51 is a recessed area, the area of ​​the gate dielectric layer 21 on the top of the metal electrode 51 is a raised area, the gate electrode 11 is arranged on the top of the gate dielectric layer 21, the gate electrode 11 completely covers the recessed area and continues to the raised area, and the gate electrode 11 does not completely cover the raised area, and the material of the drain-source contact layer 41 is indium trioxide.

[0029] In some embodiments, the thickness of the drain-source contact layer 41 is 0.4-2 nm.

[0030] In some embodiments, the material of the gate electrode 11 is selected from one or more of silicon, platinum, and gold.

[0031] In some embodiments, the material of the gate dielectric layer 21 is selected from one or more of silicon oxide, hafnium oxide, aluminum oxide, lanthanum oxide, antimony oxide, zirconium oxide, hafnium aluminum oxide, hafnium oxide silicate, and hafnium lanthanum oxide; In some embodiments, the material of the channel layer 31 is selected from amorphous oxides, preferably one or more of zinc oxide, indium oxide, gallium oxide, indium gallium zinc oxide, indium tin oxide, indium gallium tin oxide, and indium gallium oxide; the channel layer 31 is an n-type channel.

[0032] In some embodiments, the material of the metal electrode is selected from one or two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron.

[0033] According to another aspect of the present invention, a method for preparing an indium oxide interface layer field effect transistor with improved contact resistance is provided, which specifically comprises the following steps: (1) selecting a gate electrode and preparing a gate dielectric layer on the gate electrode by atomic layer deposition technology; (2) preparing a channel layer on the gate dielectric layer by atomic layer deposition technology, and then performing electron beam exposure and isolation region etching on the channel layer to obtain a channel region; (3) using an atomic deposition device to atomically deposit an indium trioxide material on the channel region to obtain a contact layer, and then performing electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; (4) Then, electron beam exposure and metal deposition are performed on the source-drain contact layer to prepare a metal electrode, thereby obtaining an indium oxide interface layer field effect transistor with improved contact resistance.

[0034] According to another aspect of the present invention, a method for preparing an indium oxide interface layer field effect transistor with improved contact resistance is provided, which specifically comprises the following steps: S1: selecting a substrate, preparing a channel layer on the substrate by atomic layer deposition technology, and then performing electron beam exposure and isolation region etching on the channel layer to obtain a channel region; S2 uses an atomic deposition device to atomically deposit an indium trioxide material on the channel region to obtain a contact layer, and then performs electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; S3 then performs electron beam exposure and metal deposition on the source and drain contact layer to prepare a metal electrode; S4: using an atomic layer deposition technique to coat the substrate, the channel layer, the drain-source contact layer, and the side and top of the metal electrode with a gate dielectric layer; S5: preparing a gate electrode on the gate dielectric layer by electron beam evaporation, thereby obtaining the indium oxide interface layer field effect transistor.

[0035] In some embodiments, in step (1), the gate electrode is pre-treated, and the pre-treatment specifically comprises placing the gate electrode in a mixed solution of ammonia water and hydrogen peroxide, heating it, and then cleaning it.

[0036] In some embodiments, the cleaning is performed using an aqueous hydrofluoric acid solution.

[0037] In some embodiments, in step (3) or step S2, the step of preparing the source-drain contact layer is specifically as follows: (3-(dimethylamino)propyl)-dimethylindium is introduced into the atomic deposition device, and then nitrogen or argon is introduced for a first purge, and then a water pulse is introduced to oxidize the (3-(dimethylamino)propyl)-dimethylindium on the substrate to generate indium trioxide, and nitrogen or argon is introduced again for a second purge.

[0038] In some embodiments, in step (3) or step S2, the temperature of the In2O3 deposition reaction is 90~150°C, the source temperature of the (3-(dimethylamino)propyl)-dimethylindium is 65~80°C, the time of the water pulse is 0.4~1 s, and the time of the first and second nitrogen purges is 20~40s.

[0039] Example 1 A contact resistance improved indium oxide interface layer field effect transistor, the specific structure of which is: from bottom to top, it includes a gate electrode 11, a gate dielectric layer 21, a channel layer 31, a drain-source region contact layer 41, and a metal electrode 51, the channel layer 31 partially covers the gate dielectric layer 21, the drain-source region contact layer 41 is arranged at intervals at both ends of the channel layer 31, the upper end of the drain-source region contact layer 41 covers the metal electrode 51, the material of the drain-source region contact layer 41 is indium trioxide, the gate electrode 11 is silicon, the gate dielectric layer 21 is hafnium oxide, the material of the channel layer 31 is selected from amorphous oxide IZO, the metal contact is Ni, and its structure is as follows Figure 6 shown.

[0040] The steps for preparing an indium oxide interface layer field effect transistor with improved contact resistance specifically include: Preparation of S1 gate electrode 11: Prepare silicon with a resistivity of 0.05 Ω·cm, mix 150 mL of deionized water and 30 mL of ammonia water in a beaker, heat at 110 ℃ for 10 min until the solution is 70 ℃, then add 30 mL of hydrogen peroxide and heat at 110 ℃ for 8 min, then place the silicon wafer and clean it for 10 min. Then use a buffered oxide etchant solution to clean it for 30 s until there are no water droplets attached to the surface, blow it dry with a nitrogen gun, and let it stand.

[0041] S2 Preparation of marking pattern: In order to facilitate the alignment and overlay between different structural layers later, it is necessary to prepare the marking pattern on the Si gate electrode 11 in advance. This process is completed by electron beam exposure (EBL). First, spin-coat the electron beam glue on the cleaned silicon wafer, and use a glue spreader to spread the glue for 60 s at a speed of 3000 r / min, and then bake the glue to solidify the glue. The condition is to bake on a hot plate at 180 ℃ for 90 s. Use EBL equipment to expose so that the marking pattern is transferred to the electron beam glue. Then, it is developed by developer, which is a mixed solution of methyl isobutyl ketone (MIBK) and isopropyl alcohol (IPA) with a mass ratio of 1 to 3. The exposed substrate is immersed in the developer for 50 s, and then fixed with IPA for 30 s to obtain a substrate with a marking pattern. Metal 20 nm nickel and 40 nm gold are deposited by electron beam evaporation (EBE). The deposited metal substrate is peeled off with NMP solution, heated at 120°C for 30 min, and then rinsed and peeled off with a syringe to obtain the marked gate electrode 11.

[0042] S3 deposition of gate dielectric layer 21: Atomic layer deposition equipment is used to grow hafnium dioxide as the gate dielectric. The precursors are tetra(ethylmethylamine)hafnium (TEMAHf) and ozone (O3). The reaction temperature is set to 250°C. The thickness increases by approximately 0.1 nm in each growth cycle. The total growth cycle is 100 times. The thickness of the final grown hafnium dioxide dielectric is 10 nm.

[0043] S4 deposits an indium zinc oxide (IZO) channel layer 31: IZO is selected as the channel layer material and is prepared by atomic layer deposition. Since there are usually many oxygen vacancies in In2O3 materials, the threshold of In2O3 channel devices is negative and the device is difficult to turn off. ZnO is also an amorphous oxide with relatively low oxygen vacancies. When mixed with In2O3 for deposition, it can reduce the carrier concentration and increase the device threshold to a certain extent. Therefore, a thickness ratio of In:Zn=3:1 is selected to obtain the IZO channel. At a reaction temperature of 225 ℃, trimethyl indium (TMIn), diethyl zinc (DEZn) and water are used as precursors, and the In and Zn cycles are grown in a large cycle of 6:1. The specific parameters of the In and Zn small cycles are In / H2O / N2 / H2O=0.5 / 20 / 0.5 / 20 s, Zn / H2O / N2 / H2O=0.2 / 20 / 0.2 / 20 s, and the total thickness of the deposition is about 4 nm. Then, the same steps as in S2 are repeated, including spin coating of electron beam photoresist, baking, electron beam photolithography, development, etching and other process flows to obtain the channel region of the device.

[0044] S5 deposits the drain-source contact layer 41. Using the same steps as S4, In2O3 is deposited using atomic layer deposition (ALD). At a reaction temperature of 150°C, (3-(dimethylamino)propyl)-dimethylindium (DADI) and water are used as precursors for cyclic growth. The specific parameters of In are In / H2O / N2 / H2O=0.5 / 40 / 0.5 / 40 s, and the total thickness of the deposition is about 1 nm. Afterwards, in order to improve the contact resistance without affecting the channel characteristics, it is necessary to etch In2O3 except the contact area. Therefore, the electron beam exposure process is also used to spin-coat electron beam photoresist, bake the glue, electron beam lithography, and develop to obtain the pattern except the contact area. After etching with 0.1 mol / L hydrochloric acid for 6 minutes, a device with In2O3 as contact in the source and drain regions is obtained. After that, the excess glue on the top is removed, heated with NMP at 120°C for 120 minutes, and rinsed with IPA. S6, depositing metal electrodes 51: first expose the source and drain electrode patterns, then deposit metal through EBE equipment, the steps are spin coating electron beam photoresist, baking, electron beam lithography, development, EBE, stripping and other process flows, the metal is 20 nm nickel and 40 nm gold. That is, the indium oxide interface layer field effect transistor with improved contact resistance is completed.

[0045] Comparative Example 1 A field effect transistor, the specific structure of which is: from bottom to top, it includes a gate electrode 11, a gate dielectric layer 21, a channel layer 31, and a metal electrode 51, wherein the channel layer 31 partially covers the gate dielectric layer 21, and the metal electrodes 51 are arranged at intervals at both ends of the channel layer 31, the gate electrode 11 is silicon, the gate dielectric layer 21 is hafnium oxide, the channel layer 31 material is selected from amorphous oxide IZO, and the metal contact is Ni. The structure is as follows Figure 8 shown.

[0046] A preparation step of a field effect transistor specifically includes: S1 gate electrode 11 preparation: prepare low-resistance silicon with a resistivity of 0.05 Ω·cm, invert 150 mL of deionized water and 30 mL of ammonia water in a beaker, heat at 110 ℃ for 10 min until the solution is 70 ℃, then add 30 mL of hydrogen peroxide and heat at 110 ℃ for 8 min, then place the silicon wafer and clean it for 10 min. Then use a buffered oxide etchant solution to clean it for 30 s until there are no water droplets attached to the surface, blow it dry with a nitrogen gun, and let it stand.

[0047] S2 Preparation of marking pattern: To facilitate the alignment and overlay between different structural layers, it is necessary to prepare the marking pattern on the Si gate electrode 11 in advance. This process is completed by EBL. First, spin-coat the cleaned silicon wafer with electron beam glue, and use a glue spreader to spread the glue for 60 s at a speed of 3000 r / min, and then bake the glue to solidify the PMMAA4 glue. The condition is to bake on a hot plate at 180 ℃ for 90 s. Use EBL equipment to expose so that the marking pattern is transferred to the electron beam glue. Then, it is developed with a developer, which is a mixed solution of MIBK and IPA with a mass ratio of 1 to 3. The exposed substrate is immersed in the developer for 50 s, and then fixed with IPA for 30 s to obtain a substrate with a marking pattern. Metal 20 nm nickel and 40 nm gold are deposited by EBE. The deposited metal substrate is peeled off with NMP solution, heated at 120 ℃ for 30 min, and then rinsed and peeled with a syringe to obtain a marked gate electrode 11.

[0048] S3 deposits the gate dielectric layer 21: an atomic layer deposition device is used to grow hafnium dioxide as the gate dielectric. The precursors are TEMAHf and O3. The reaction temperature is set to 250 °C. The thickness increases by about 0.1 nm in each growth cycle. The total growth cycle is 100 times. The thickness of the final grown hafnium dioxide dielectric is 10 nm.

[0049] S4 deposition of indium zinc oxide (IZO) channel layer 31: IZO was selected as the channel layer material and prepared by atomic layer deposition. Since there are usually many oxygen vacancies in In2O3 materials, the threshold of In2O3 channel devices is negative and the devices are difficult to turn off. ZnO is also an amorphous oxide with relatively low oxygen vacancies. When mixed with In2O3 for deposition, it can reduce the carrier concentration and increase the device threshold to a certain extent. Therefore, the thickness ratio of In:Zn=3:1 is selected to obtain the IZO channel. At a reaction temperature of 225 ℃, trimethyl indium, diethyl zinc and water are used as precursors, and the In and Zn cycles are 6:1 for growth. The specific parameters of the In and Zn small cycles are In / H2O / N2 / H2O=0.5 / 20 / 0.5 / 20 s, Zn / H2O / N2 / H2O=0.2 / 20 / 0.2 / 20 s, and the total thickness of the deposition is about 4 nm. Then, the same steps as in S2 are repeated, including spin coating of PMMA A4 electron beam photoresist, baking, electron beam photolithography, development, etching and other process steps to obtain the channel region of the device.

[0050] S5 Deposition of metal electrodes 51: First, the source and drain electrode patterns are exposed, and then metal is deposited through EBE equipment. The steps include spin coating of electron beam photoresist, baking, electron beam lithography, development, EBE deposition, stripping and other process flows. The metal is 20 nm nickel and 40 nm gold. That is, the preparation of field effect transistors is completed.

[0051] Fig. 9 The output characteristic curves of transistors with two different contact structures (with or without In2O3 contact layer) were tested. The horizontal axis is the drain-source voltage V DS (unit V), the vertical axis is the drain-source current I DS (unit: µA / µm) to evaluate the effect of the In2O3 contact layer on device performance. BG = 3 V, L ch = 60 nm, the same V DS , the device with In2O3 contact layer (solid line) shows a higher drain-source current I DS , indicating better contact performance. And at V DS = 1 V, device I with In2O3 contact layer (solid line) DS It reaches 832 μA / μm, which is 1.7 times that of the 487 μA / μm device without In2O3 contact layer (dashed line), indicating that the present invention effectively improves the contact resistance and enhances the current injection capability by introducing the In2O3 contact layer in the source and drain regions, thereby improving the output current of the device. Compared with Comparative Example 1 (without In2O3 contact layer), the present invention significantly improves the device performance, proving that the technical solution effectively improves the electrical characteristics of the source and drain regions.

[0052] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An indium oxide interface layer field effect transistor with improved contact resistance, characterized in that: The structure is a back-gate structure, specifically comprising, from bottom to top, a gate electrode (11), a gate dielectric layer (21), a channel layer (31), a drain-source region contact layer (41), and a metal electrode (51); the channel layer (31) is located in the middle region of the gate dielectric layer (21), and the edges of the gate dielectric layer (21) are not covered by the channel layer (31); the drain-source region contact layer (41) is arranged at intervals at both ends of the channel layer (31); the metal electrode (51) is arranged on the top of the drain-source region contact layer (41); and the material of the drain-source region contact layer (41) is indium trioxide.

2. An indium oxide interface layer field effect transistor with improved contact resistance, characterized in that: The structure is a top gate structure, specifically comprising: from bottom to top, a substrate (61), a channel layer (31), a drain-source region contact layer (41), and a metal electrode (51), wherein the channel layer (31) is located in the middle area of ​​the substrate (61) and the edges of the substrate (61) are not covered by the channel layer (31), the drain-source region contact layer (41) is arranged at intervals at both ends of the channel layer (31), the metal electrode (51) is arranged on the top of the drain-source region contact layer (41), and the channel layer (31), the drain-source region contact layer (41) and the metal electrode (51) are arranged on the top of the drain-source region contact layer (41). , and the surfaces not covered by the metal electrodes (51) are covered with a gate dielectric layer (21), the area of ​​the gate dielectric layer (21) between the metal electrodes (51) arranged at intervals is recorded as a recessed area, the area of ​​the gate dielectric layer (21) on the top of the metal electrodes (51) is recorded as a raised area, a gate electrode (11) is arranged on the top of the gate dielectric layer (21), the gate electrode (11) completely covers the recessed area and extends to the raised area, and the gate electrode (11) does not completely cover the raised area, and the material of the drain-source contact layer (41) is indium trioxide.

3. The indium oxide interface layer field effect transistor with improved contact resistance according to claim 1 or 2, characterized in that: The thickness of the drain-source region contact layer (41) is 0.4-2 nm.

4. The indium oxide interface layer field effect transistor with improved contact resistance according to claim 1 or 2, characterized in that: The material of the gate electrode (11) is selected from one or more of silicon, platinum and gold; the material of the gate dielectric layer (21) is selected from one or more of silicon oxide, hafnium oxide, aluminum oxide, lanthanum oxide, antimony oxide, zirconium oxide, hafnium aluminum oxide, hafnium oxide silicate and hafnium lanthanum oxide.

5. The indium oxide interface layer field effect transistor with improved contact resistance according to claim 1 or 2, characterized in that: The material of the channel layer (31) is selected from amorphous oxides, preferably one or more of zinc oxide, indium oxide, gallium oxide, indium gallium zinc oxide, indium tin oxide, indium gallium tin oxide, and indium gallium oxide; the channel layer (31) is an n-type channel.

6. A method for preparing an indium oxide interface layer field effect transistor with improved contact resistance according to any one of claims 1, 3-5, characterized in that: The specific steps include: (1) selecting a gate electrode and preparing a gate dielectric layer on the gate electrode by atomic layer deposition technology; (2) preparing a channel layer on the gate dielectric layer by atomic layer deposition technology, and then performing electron beam exposure and isolation region etching on the channel layer to obtain a channel region; (3) using an atomic deposition device to atomically deposit an indium trioxide material on the channel region to obtain a contact layer, and then performing electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; (4) Then, electron beam exposure and metal deposition are performed on the source-drain contact layer to prepare a metal electrode, thereby obtaining the indium oxide interface layer field effect transistor.

7. A method for preparing an indium oxide interface layer field effect transistor with improved contact resistance according to any one of claims 2, 3-5, characterized in that: The specific steps include: S1: selecting a substrate, preparing a channel layer on the substrate by atomic layer deposition technology, and then performing electron beam exposure and isolation region etching on the channel layer to obtain a channel region; S2 uses an atomic deposition device to atomically deposit an indium trioxide material on the channel region to obtain a contact layer, and then performs electron beam exposure and etching on the contact layer to obtain a drain-source region contact layer; S3 then performs electron beam exposure and metal deposition on the source and drain contact layer to prepare a metal electrode; S4: coating the substrate, the channel layer, the drain-source contact layer, and the metal electrode with a gate dielectric layer by atomic layer deposition technology; S5: preparing a gate electrode on the gate dielectric layer by electron beam evaporation, thereby obtaining the indium oxide interface layer field effect transistor.

8. The method for preparing an indium oxide interface layer field effect transistor with improved contact resistance according to claim 7, characterized in that: In step (1), the gate electrode is pre-treated, and the pre-treatment specifically comprises placing the gate electrode in a mixed solution of ammonia water and hydrogen peroxide, heating it, and then cleaning it.

9. The method for preparing an indium oxide interface layer field effect transistor with improved contact resistance according to claim 7 or 8, characterized in that: In step (3) or step S2, the preparation step of the contact layer is specifically as follows: (3-(dimethylamino)propyl)-dimethylindium is introduced into the atomic deposition device, and then nitrogen or argon is introduced for a first purge, and then a water pulse is introduced to oxidize the (3-(dimethylamino)propyl)-dimethylindium on the channel layer to generate indium trioxide, and nitrogen or argon is introduced again for a second purge.

10. The method for preparing an indium oxide interface layer field effect transistor with improved contact resistance according to claim 9, characterized in that: In step (3) or step S2, the temperature of the indium trioxide deposition reaction is 90-150°C, the source temperature of the (3-(dimethylamino)propyl)-dimethylindium is 65-80°C, the time of the water pulse is 0.4-1 s, and the time of the first and second nitrogen purges is 20-40 s.

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