Semiconductor structure and preparation method thereof
By forming an ion implantation barrier layer and an isolation structure in the semiconductor structure, the problem of lowering the ion concentration in the well region caused by ion migration in small-sized NMOS devices is solved, and the improvement of the device threshold voltage and performance are achieved.
Patent Information
- Application Number
- CN202510080986.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-04-25
AI Technical Summary
When a small-size NMOS device implants ions into a well region to form a well region, due to compression stress and thermal stress, ions are easily migrated into the STI, resulting in a decrease in the ion concentration in the well region, which in turn affects the threshold voltage and performance of the device.
An ion implantation barrier layer is formed on the side walls, bottom portions and side walls of the first liner layer of the isolation trench, and the isolation trench is filled to form an isolation structure. The dielectric constant of the ion implantation barrier layer is large, and ions are prevented from migrating to the isolation structure.
The formation conditions of the inverted layer at the conductive channel of the semiconductor structure are effectively controlled, the threshold voltage of the device is improved, and the normal opening of the device is ensured under the set voltage conditions, which improves performance and reliability.
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Figure CN119894079A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] With the development of semiconductor devices, the size of CMOS devices is getting smaller and smaller. However, the reduction in the size of CMOS devices may cause short channel effects, resulting in a decrease in transistor threshold voltage and an increase in leakage current, which in turn affects the performance of the device.
[0003] For small-sized NMOS devices, when ions are injected into a specific area of the substrate to form a well region, the compressive stress of shallow trench isolation (STI) and the thermal stress in the subsequent process will cause the ions to migrate to the STI, causing the ions in the well region to precipitate into the STI. After the ions are precipitated into the STI region, the ion concentration in the well region of the NMOS device decreases. At this time, the small-sized NMOS is more likely to form an inversion layer in the channel, making it easier to turn on the subsequent device, which in turn leads to a decrease in the threshold voltage of the NMOS device. Summary of the invention
[0004] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same to address the above problems.
[0005] In order to achieve the above object, on the one hand, the present invention provides a method for preparing a semiconductor structure, comprising:
[0006] Providing a substrate, the substrate comprising a substrate and a first liner layer, the first liner layer being located at one side of the substrate, the first liner layer having a first opening, and the substrate exposed by the first opening having an isolation trench;
[0007] forming an ion implantation barrier layer on the sidewalls of the isolation trench, the bottom of the isolation trench, and the sidewalls of the first liner layer, and forming an isolation structure filling the isolation trench;
[0008] Ions are implanted into the substrate between two adjacent isolation structures to form a well region.
[0009] In one embodiment, the base further includes a second liner layer, the second liner layer is located on a side of the first liner layer away from the substrate, the second liner layer has a second opening, and the second opening is arranged corresponding to the first opening.
[0010] The ion implantation barrier layer is formed on the sidewall of the isolation trench, the bottom of the isolation trench and the sidewall of the first liner layer, and an isolation structure filling the isolation trench is formed, including:
[0011] forming a first injection blocking intermediate layer in the isolation trench, the first opening and at least a portion of the second opening, and forming the isolation structure filling the isolation trench;
[0012] The second liner layer and the first implantation blocking intermediate layer located on the sidewall of the second liner layer are removed, and the remaining first implantation blocking intermediate layer forms the ion implantation blocking layer.
[0013] In one embodiment, forming a first injection blocking intermediate layer in the isolation trench, the first opening, and at least a portion of the second opening, and forming the isolation structure filling the isolation trench, comprises:
[0014] forming a second injection blocking intermediate layer and the isolation intermediate structure in the isolation trench, the first opening and the second opening, wherein the isolation intermediate structure fills the second opening;
[0015] Part of the second injection blocking intermediate layer and part of the isolation intermediate structure in the second opening are removed to expose part of the side wall of the second liner layer, and the remaining second injection blocking intermediate layer forms the first injection blocking intermediate layer, and the remaining isolation intermediate structure forms the isolation structure.
[0016] In one embodiment, forming a second injection blocking intermediate layer and the isolation intermediate structure in the isolation trench, the first opening, and the second opening includes:
[0017] forming a barrier material layer on the bottom of the isolation trench, the sidewalls of the isolation trench, the sidewalls of the first opening, the sidewalls of the second opening, and the top of the substrate;
[0018] forming the isolation intermediate structure filling the isolation trench, the first opening and the second opening on the surface of the barrier material layer;
[0019] The barrier material layer located on the top of the substrate is removed to form the second implantation barrier interlayer.
[0020] In one embodiment, forming a barrier material layer on the bottom of the isolation trench, the sidewalls of the isolation trench, the sidewalls of the first opening, the sidewalls of the second opening, and the top of the substrate includes:
[0021] forming an initial barrier material layer on the bottom of the isolation trench, the sidewalls of the isolation trench, the sidewalls of the first opening, the sidewalls of the second opening, and the top of the substrate;
[0022] The initial barrier material layer is doped with a first reaction gas to form the barrier material layer having first doping ions.
[0023] In one embodiment, an ion implantation barrier layer is formed on the sidewalls of the isolation trench, the bottom of the isolation trench, and the sidewalls of the first liner layer, and while forming an isolation structure filling the isolation trench, a first dielectric layer and a second dielectric layer are formed between the ion implantation barrier layer and the substrate and between the ion implantation barrier layer and the first liner layer;
[0024] The first dielectric layer covers the sidewalls and the bottom of the isolation trench, and the second dielectric layer covers the sidewalls of the first dielectric layer and the first liner layer.
[0025] In another aspect, a semiconductor structure is provided, comprising:
[0026] A substrate, the substrate comprising a substrate and a first liner layer, the first liner layer being located at one side of the substrate and having a first opening therein, the substrate exposed by the first opening having an isolation trench therein; the substrate between two adjacent isolation trenches comprising an ion-doped well region;
[0027] an ion implantation barrier layer, covering the sidewalls of the isolation trench, the bottom of the isolation trench and the sidewalls of the first liner layer;
[0028] An isolation structure fills the isolation trench.
[0029] In one embodiment, the isolation structure protrudes from the first opening toward a side of the first liner layer away from the substrate.
[0030] In one embodiment, the semiconductor structure further comprises:
[0031] A first dielectric layer, located between the isolation trench and the ion implantation barrier layer, covering the sidewall and bottom of the isolation trench;
[0032] The second dielectric layer is located between the first dielectric layer and the ion implantation blocking layer, and covers the sidewalls of the first dielectric layer and the first liner layer.
[0033] In one embodiment, the ion implantation barrier layer is a HfO2 material having a first doping ion, the first doping ion is a N ion, and the doping ion of the well region is a B ion.
[0034] Compared with the prior art, the above technical solution has the following advantages:
[0035] In the above-mentioned semiconductor structure and preparation method thereof, a substrate is first provided, which includes a substrate and a first liner layer, wherein the first liner layer is located on one side of the substrate, and the first liner layer has a first opening, and the substrate exposed by the first opening has an isolation groove. Then, an ion implantation barrier layer is formed on the sidewall of the isolation groove, the bottom of the isolation groove and the sidewall of the first liner layer, and an isolation structure filling the isolation groove is formed. When ion implantation is performed in the substrate between two adjacent isolation structures to form a well region, since the dielectric constant of the ion implantation barrier layer is large and the bandgap width is relatively large, when the ions diffuse, the ion implantation barrier layer can prevent the migration of ions to the isolation structure. The ions cannot penetrate the ion implantation barrier layer, so that the conditions for the formation of the inversion layer at the conductive channel of the semiconductor structure are controlled within a predetermined range, that is, the subsequent device will be turned on under the set voltage condition, which improves the problem of the threshold voltage reduction of the semiconductor structure. In addition, since the ion implantation barrier layer also covers the sidewall of the first liner layer, the possibility of ions entering the isolation structure from the sidewall of the first liner layer during implantation is avoided. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0037] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure is provided for an embodiment of the present application;
[0038] Figure 2-Figure 8 A schematic diagram of a partial structure of a semiconductor structure is provided for an embodiment of the present application.
[0039] Explanation of the figure markings: 01-base; 011-substrate; 012-first liner layer; 013-isolation groove; 014-second liner layer; 02-ion implantation blocking layer; 021-first implantation blocking intermediate layer; 022-second implantation blocking intermediate layer; 023-blocking material layer; 03-isolation structure; 031-isolation intermediate structure; 04-well region; 05-first dielectric layer; 06-second dielectric layer; 061-second dielectric material layer; A-first opening; a-second opening. DETAILED DESCRIPTION
[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0045] Please refer to Figure 1 , Figure 1 A schematic diagram of a method for preparing a semiconductor structure is provided for reference. Figure 2-Figure 8 , Figure 2-Figure 8 A schematic diagram of a semiconductor structure portion is provided for an embodiment of the present application, comprising the following steps:
[0046] Step S101: providing a substrate 01, the substrate 01 comprising a substrate 011 and a first liner layer 012, the first liner layer 012 being located on one side of the substrate 011, the first liner layer 012 having a first opening A, the substrate 011 exposed by the first opening A having an isolation trench 013 (such as Figure 2 as shown).
[0047] like Figure 2 As shown, the substrate 011 may be a silicon substrate, and the first liner layer 012 may be a pad oxide layer (Pad Oxide). The material of the first liner layer 012 may be a silicon dioxide material.
[0048] An isolation trench 013 is provided on the substrate 011 . The isolation trench 013 may include a shallow trench. The isolation trench 013 may be formed by etching. The first liner layer 012 may be formed by, but not limited to, chemical vapor deposition (CVD).
[0049] Step S102: forming an ion implantation barrier layer 02 on the sidewalls of the isolation trench 013, the bottom of the isolation trench 013 and the sidewalls of the first liner layer 012, and forming an isolation structure 03 (such as Figure 8 as shown).
[0050] The ion implantation blocking layer 02 may be formed by deposition, including but not limited to atomic layer deposition.
[0051] The material of the isolation structure 03 can be silicon dioxide material, and the isolation structure 03 can effectively isolate adjacent transistors. The isolation structure 03 can be formed using the High-Density Plasma (HDP) technology, and the plasma generated by HDP can promote the deposition of silicon dioxide. During the deposition process, the active particles in the plasma can enhance the chemical reaction between the reaction precursors, thereby achieving high-quality and high-filling-rate silicon dioxide deposition.
[0052] Step S103: Perform ion implantation into the substrate 011 between two adjacent isolation structures 03 to form a well region 04 (eg Figure 8 as shown).
[0053] The semiconductor structure may be an NMOS structure, in which a P-type well region needs to be formed. Ions are implanted into the substrate 011 between two adjacent isolation structures 03, and the ions diffuse to form a well region 04. In some embodiments, the ions may be B ions. The well region 04 can effectively isolate different types of transistors, reduce leakage, and improve device performance and reliability.
[0054] In this embodiment, when ion implantation is performed in the substrate 011 between two adjacent isolation structures 03 to form a well region 04, since the dielectric constant of the ion implantation barrier layer 02 is relatively large and the bandgap width is relatively large, when the ions diffuse, the ion implantation barrier layer 02 can prevent the ions from migrating to the isolation structure 03. The ions cannot penetrate the ion implantation barrier layer 02, so that the conditions for the formation of the inversion layer at the conductive channel of the semiconductor structure are controlled within a predetermined range, that is, the subsequent device will be turned on under the set voltage conditions, which improves the problem of the threshold voltage reduction of the semiconductor structure. In addition, since the ion implantation barrier layer 02 also covers the side wall of the first liner layer 012, the possibility of ions entering the isolation structure 03 from the side wall of the first liner layer 012 during implantation is avoided.
[0055] In one embodiment, Figure 2 As shown, the substrate 01 further includes a second liner layer 014, which is located on the side of the first liner layer 012 away from the substrate 011. The first liner layer 012 has a second opening a, and the first opening A is arranged corresponding to the second opening a. Step S102 includes:
[0056] Step S1021: forming a first injection blocking intermediate layer 021 in the isolation trench 013, the first opening A and at least a portion of the second opening a, forming an isolation structure 03 (such as Figure 7 as shown).
[0057] Specifically, the substrate 01 further includes a second liner layer 014. The material of the second liner layer 014 may be a pad nitride layer (Pad Nitride). The material of the second liner layer 014 may be a silicon nitride material.
[0058] The second liner layer 014 includes but is not limited to being formed by chemical vapor deposition (CVD), and the second opening a of the second liner layer 014 corresponds to the first opening A one-to-one, and both expose the isolation structure 03. It should be noted that, if Figure 2 As shown, the orthographic projection area of the first opening A on the substrate 011 may be larger than the orthographic projection area of the isolation trench 013 on the substrate 011, and the orthographic projection area of the second opening a on the substrate 011 may be larger than the orthographic projection area of the first opening A on the substrate 011, as shown in FIG. Figure 2 The illustration is only taken as an example and is not a specific limitation.
[0059] Step S1022: remove the second liner layer 014 and the first injection blocking intermediate layer 021 located on the sidewall of the second liner layer 014, and the remaining first injection blocking intermediate layer 021 forms an ion injection blocking layer 02 (such as Figure 8 as shown).
[0060] The second liner layer 014 and the first implantation blocking intermediate layer 021 on the sidewall of the second liner layer 014 may be removed by wet etching to be suitable for subsequent preparation processes.
[0061] In this embodiment, the isolation structure 03 not only fills the isolation trench 013, but also fills the first opening A and at least a portion of the second opening a, that is, the isolation structure 03 protrudes toward the upper surface, higher than the height of the first liner layer 012, so that the isolation effect can be enhanced to prevent leakage and signal interference. In addition, the capacitive coupling between adjacent transistors can also be reduced.
[0062] In one embodiment, step S1021 includes:
[0063] Step S1121: forming a second injection blocking intermediate layer 022 and an isolation intermediate structure 031 in the isolation trench 013, the first opening A and the second opening a, and the isolation intermediate structure 031 fills the second opening a (such as Figure 6 as shown).
[0064] Specifically, the second injection blocking intermediate layer 022 and the isolation intermediate structure 031 can be formed by deposition.
[0065] Step S1221: remove part of the second injection blocking intermediate layer 022 and part of the isolation intermediate structure 031 in the second opening a to expose part of the side wall of the second liner layer 014 , and the remaining second injection blocking intermediate layer 022 forms the first injection blocking intermediate layer 021 , and the remaining isolation intermediate structure 031 forms the isolation structure 03 .
[0066] In this step, wet etching is required to remove part of the second injection blocking intermediate layer 022 and part of the isolation intermediate structure 031 in the second opening a, and expose part of the sidewall of the second liner layer 014. For example, hydrofluoric acid is used to remove a certain thickness of the isolation intermediate structure 031. Hydrofluoric acid has a relatively high selectivity for the isolation structure 03, and the amount of etching can be well controlled, thereby ensuring that the isolation structure 03 formed in the end at least fills part of the second opening a, that is, the isolation structure 03 at least covers part of the sidewall of the second liner layer 014. The second injection blocking intermediate layer 022 can also react with the hydrofluoric acid and be removed.
[0067] In this embodiment, the second injection blocking intermediate layer 022 and the isolation intermediate structure 031 are first formed, and then the second injection blocking intermediate layer 022 and the isolation intermediate structure 031 are etched to realize the first injection blocking intermediate layer 021 and the isolation structure 03 of the required morphology.
[0068] In one embodiment, step S1121 includes:
[0069] Step S2121: forming a barrier material layer 023 (such as a barrier material layer 023) on the bottom of the isolation trench 013, the sidewalls of the isolation trench 013, the sidewalls of the first opening A, the sidewalls of the second opening a, and the top of the substrate 01. Figure 3 as shown).
[0070] In this step, the base 01 includes a substrate 011 , a first liner layer 012 and a second liner layer 014 .
[0071] The barrier material layer 023 may cover the sidewalls of the isolation trench 013 , the bottom of the isolation trench 013 , the sidewalls of the first liner layer 012 , the sidewalls of the second liner layer 014 , and the upper surface of the second liner layer 014 .
[0072] The barrier material layer 023 may be formed by atomic layer deposition. The barrier material layer 023 may be made of HfO2.
[0073] Step S2221: forming an isolation intermediate structure 031 (such as Figure 4 , Figure 5 as shown).
[0074] In some practical examples, the isolation intermediate structure 031 may cover the second liner layer 014 to achieve a better filling structure, such as Figure 4 shown.
[0075] After the isolation intermediate structure 031 covering the second liner layer 014 is formed, it is necessary to thin it so that the isolation intermediate structure is flush with the second liner layer 014. Figure 5 As shown. For example, chemical mechanical polishing (CMP) is used to grind the isolation intermediate structure 031 to form an isolation intermediate structure 031 flush with the second liner layer 014, so as to facilitate subsequent process preparation. At this time, the barrier material layer 023 can be used as a stop layer. When grinding to the barrier material layer 023, grinding stops.
[0076] Step S2321: removing the barrier material layer 023 located on the top of the substrate 01 to form a second injection barrier intermediate layer 022 (eg Figure 6 as shown).
[0077] In this step, a concentrated sulfuric acid solution with a high selectivity ratio may be used to remove the barrier material layer 023 on the top of the substrate 01 by wet etching within a certain appropriate time.
[0078] In this embodiment, the barrier material layer 023 on the top of the substrate 01 is first removed to form the second injection barrier intermediate layer 022 , which can ensure more accurate etching when subsequently forming the isolation structure 03 and the first injection barrier intermediate layer 021 .
[0079] In one embodiment, step S2121 includes:
[0080] Step S3121 : forming an initial barrier material layer on the bottom of the isolation trench 013 , the sidewalls of the isolation trench 013 , the sidewalls of the first opening A, the sidewalls of the second opening a, and the top of the substrate 01 .
[0081] In this step, the initial barrier material layer can be formed by atomic layer deposition. The material of the initial barrier material layer can be undoped HfO2 material.
[0082] Step S3221: using a first reaction gas to perform a doping treatment on the initial barrier material layer to form a barrier material layer 023 having first doping ions.
[0083] In this step, a first reaction gas may be introduced into the reaction chamber to perform an annealing process. The first reaction gas may be nitrogen gas, and the first doping ions may be N ions.
[0084] The material of the barrier material layer 023 may be HfO 2 material. Doping the HfO 2 material with N element may increase the density of the HfO 2 material.
[0085] In this embodiment, doping is performed in the barrier material layer 023 , so as to improve the density of the barrier material layer 023 and further prevent the migration of isolators from the well region 04 to the isolation structure 03 .
[0086] In one embodiment, Figure 3 As shown, an ion implantation barrier layer 02 is formed on the sidewall of the isolation trench 013, the bottom of the isolation trench 013 and the sidewall of the first liner layer 012, and an isolation structure 03 filling the isolation trench 013 is formed, and a first dielectric layer 05 and a second dielectric layer 06 are formed between the ion implantation barrier layer 02 and the substrate 011 and between the ion implantation barrier layer 02 and the first liner layer 012;
[0087] The first dielectric layer 05 covers the sidewalls and the bottom of the isolation trench 013 , and the second dielectric layer 06 covers the sidewalls of the first dielectric layer 05 and the first liner layer 012 .
[0088] Specifically, the first dielectric layer 05 may be a linear oxide layer, and the material of the first dielectric layer 05 may be a silicon dioxide material.
[0089] The first dielectric layer 05 can play an insulating role and can also block the diffusion of some impurity ions.
[0090] The second dielectric layer 06 may be a linear nitride layer, and the material of the second dielectric layer 06 may be a silicon nitride material.
[0091] The second dielectric layer 06 can improve the migration characteristics of carriers and significantly improve the reliability of the structure. At the same time, the second dielectric layer 06 can also serve as an effective barrier layer for atomic diffusion to maintain the stability and electrical properties of the interface.
[0092] It should be noted that the second dielectric layer 06 can be formed into the second dielectric material layer 061 first, and then removed by etching in a synchronous manner in step S1221.
[0093] In this embodiment, the first dielectric layer 05 and the second dielectric layer 06 can also block the migration of ions from the well region 04 to the isolation structure 03 to a certain extent.
[0094] In one embodiment, Figure 8 As shown, the present application also provides a semiconductor structure, which includes:
[0095] A substrate 01, the substrate 01 comprises a substrate 011 and a first liner layer 012, the first liner layer 012 is located at one side of the substrate 011, the first liner layer 012 has a first opening A, and the substrate 011 exposed by the first opening A has an isolation trench 013; the substrate 011 between two adjacent isolation trenches 013 comprises an ion-doped well region 04;
[0096] An ion implantation barrier layer 02 covers the sidewalls of the isolation trench 013 , the bottom of the isolation trench 013 , and the sidewalls of the first liner layer 012 ;
[0097] The isolation structure 03 fills the isolation trench 013 .
[0098] Specifically, the substrate 011 may be a silicon substrate 011 , and the first liner layer 012 may be a pad oxide layer (Pad Oxide). The material of the first liner layer 012 may be a silicon dioxide material.
[0099] An isolation trench 013 is disposed on the substrate 011 , and the isolation trench 013 may include a shallow trench. The isolation trench 013 may be formed by etching, and the first liner layer 012 may be formed by, but not limited to, chemical vapor deposition (CVD).
[0100] The material of the isolation structure 03 may be silicon dioxide material, and the isolation structure 03 may effectively isolate adjacent transistors.
[0101] In this embodiment, since an ion implantation barrier layer 02 is provided in the semiconductor structure, and the dielectric constant of the ion implantation barrier layer 02 is relatively large, and the band gap is relatively large, when the ions diffuse, the ion implantation barrier layer 02 can prevent the ions from migrating to the isolation structure 03. The ions cannot penetrate the ion implantation barrier layer 02, so that the conditions for the formation of the inversion layer at the conductive channel of the semiconductor structure are controlled within a predetermined range, that is, the subsequent device will be turned on under the set voltage condition, which improves the problem of the threshold voltage reduction of the semiconductor structure. In addition, since the ion implantation barrier layer 02 also covers the side wall of the first liner layer 012, the possibility of ions entering the isolation structure 03 from the side wall of the first liner layer 012 during ion implantation is avoided.
[0102] In one embodiment, Figure 8 As shown, the isolation structure 03 protrudes from the first opening A toward the side of the first liner layer 012 facing away from the substrate 011 .
[0103] In this embodiment, the isolation structure 03 not only fills the isolation trench 013, but also fills the first opening A and extends outward, protruding from the first opening A to the side of the first liner layer 012 away from the substrate 011. In other words, the isolation structure 03 is higher than the height of the first liner layer 012. The isolation structure 03 can enhance the isolation effect to prevent leakage and signal interference. In addition, the capacitive coupling between adjacent transistors can be reduced.
[0104] In one embodiment, Figure 8 As shown, the semiconductor structure further includes:
[0105] The first dielectric layer 05 is located between the isolation trench 013 and the ion implantation barrier layer 02 and covers the sidewall and bottom of the isolation trench 013;
[0106] The second dielectric layer 06 is located between the first dielectric layer 05 and the ion implantation blocking layer 02 , and covers the first dielectric layer 05 and the sidewalls of the first liner layer 012 .
[0107] Specifically, the first dielectric layer 05 may be a linear oxide layer, and the material of the first dielectric layer 05 may be a silicon dioxide material. The second dielectric layer 06 may be a linear nitride layer, and the material of the second dielectric layer 06 may be a silicon nitride material.
[0108] In this embodiment, the first dielectric layer 05 and the second dielectric layer 06 can also block the migration of ions from the well region 04 to the isolation structure 03 to a certain extent.
[0109] In one embodiment, the ion implantation blocking layer 02 is made of HfO 2 material having first doping ions, the first doping ions are N ions, and the doping ions of the well region 04 are B ions.
[0110] HfO2 material has a large dielectric constant and a relatively large bandgap, so when B ions diffuse, the ion implantation barrier layer 02 can prevent the B ions from migrating to the isolation structure 03. B ions cannot penetrate the ion implantation barrier layer 02, so that the conditions for the formation of the inversion layer at the conductive channel of the semiconductor structure are controlled within a predetermined range, that is, the subsequent device will be turned on under the set voltage conditions, which improves the problem of lowering the threshold voltage of the semiconductor structure. In addition, since the ion implantation barrier layer 02 also covers the side wall of the first liner layer 012, the possibility of B ions entering the isolation structure 03 from the side wall of the first liner layer 012 during implantation is avoided.
[0111] N doping in the HfO 2 material can improve the density of the HfO 2 material, and the ion implantation barrier layer 02 can further block the migration of B ions from the well region 04 to the isolation structure 03 .
[0112] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0113] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0114] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a first liner layer, the first liner layer being located at one side of the substrate, the first liner layer having a first opening, and the substrate exposed by the first opening having an isolation trench; forming an ion implantation barrier layer on the sidewalls of the isolation trench, the bottom of the isolation trench, and the sidewalls of the first liner layer, and forming an isolation structure filling the isolation trench; Ions are implanted into the substrate between two adjacent isolation structures to form a well region.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The base also includes a second liner layer, the second liner layer is located on a side of the first liner layer away from the substrate, the second liner layer has a second opening, and the second opening is arranged corresponding to the first opening. The ion implantation barrier layer is formed on the sidewall of the isolation trench, the bottom of the isolation trench and the sidewall of the first liner layer, and an isolation structure filling the isolation trench is formed, including: forming a first injection blocking intermediate layer in the isolation trench, the first opening and at least a portion of the second opening, and forming the isolation structure filling the isolation trench; The second liner layer and the first implantation blocking intermediate layer located on the sidewall of the second liner layer are removed, and the remaining first implantation blocking intermediate layer forms the ion implantation blocking layer.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The step of forming a first injection blocking intermediate layer in the isolation trench, the first opening, and at least a portion of the second opening, and forming the isolation structure filling the isolation trench, comprises: forming a second injection blocking intermediate layer and the isolation intermediate structure in the isolation trench, the first opening and the second opening, wherein the isolation intermediate structure fills the second opening; Part of the second injection blocking intermediate layer and part of the isolation intermediate structure in the second opening are removed to expose part of the side wall of the second liner layer, and the remaining second injection blocking intermediate layer forms the first injection blocking intermediate layer, and the remaining isolation intermediate structure forms the isolation structure.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The forming of a second injection blocking intermediate layer and the isolation intermediate structure in the isolation trench, the first opening and the second opening comprises: forming a barrier material layer on the bottom of the isolation trench, the sidewalls of the isolation trench, the sidewalls of the first opening, the sidewalls of the second opening, and the top of the substrate; forming the isolation intermediate structure filling the isolation trench, the first opening and the second opening on the surface of the barrier material layer; The barrier material layer located on the top of the substrate is removed to form the second implantation barrier interlayer.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The barrier material layer is formed on the bottom of the isolation trench, the sidewall of the isolation trench, the sidewall of the first opening, the sidewall of the second opening and the top of the substrate, comprising: forming an initial barrier material layer on the bottom of the isolation trench, the sidewalls of the isolation trench, the sidewalls of the first opening, the sidewalls of the second opening, and the top of the substrate; The initial barrier material layer is doped with a first reaction gas to form the barrier material layer having first doping ions.
6. The method for preparing a semiconductor structure according to claim 1, characterized in that: An ion implantation barrier layer is formed on the sidewall of the isolation trench, the bottom of the isolation trench and the sidewall of the first liner layer, and while forming an isolation structure filling the isolation trench, a first dielectric layer and a second dielectric layer are formed between the ion implantation barrier layer and the substrate and between the ion implantation barrier layer and the first liner layer; The first dielectric layer covers the sidewalls and the bottom of the isolation trench, and the second dielectric layer covers the sidewalls of the first dielectric layer and the first liner layer.
7. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a substrate and a first liner layer, the first liner layer is located at one side of the substrate, and the first liner layer has a first opening, and the substrate exposed by the first opening has an isolation trench; The substrate between two adjacent isolation trenches includes an ion-doped well region; an ion implantation barrier layer, covering the sidewalls of the isolation trench, the bottom of the isolation trench and the sidewalls of the first liner layer; An isolation structure fills the isolation trench.
8. The semiconductor structure according to claim 7, characterized in that: The isolation structure protrudes from the first opening toward a side of the first liner layer away from the substrate.
9. The semiconductor structure according to claim 7, characterized in that: The semiconductor structure further comprises: A first dielectric layer, located between the isolation trench and the ion implantation barrier layer, covering the sidewall and bottom of the isolation trench; The second dielectric layer is located between the first dielectric layer and the ion implantation blocking layer, and covers the sidewalls of the first dielectric layer and the first liner layer.
10. The semiconductor structure according to claim 7, characterized in that: The ion implantation barrier layer is made of HfO2 material having first doping ions, the first doping ions are N ions, and the doping ions in the well region are B ions.