Cascode cascade device
By designing parallel adjustment capacitance and adjustment resistance in cascaded cascaded devices and adjusting the Vmn voltage value, the problem that the co-source cascaded devices in the prior art is prone to avalanche at zero voltage, and the effect of reducing the risk of avalanche without increasing the chip area is achieved.
Patent Information
- Application Number
- CN202411948371.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-25
AI Technical Summary
Existing cascaded cascade devices are difficult to maintain a normal off-operation mode at zero voltage, which can easily lead to MOSFET avalanche or DGaN gate damage, and increasing the source and drain voltage or chip size of the MOSFET will affect device performance.
A cascade cascade device is designed, including a cascaded depletion transistor and an enhancement transistor, and a regulating component is provided in parallel between the first source and the second source, the regulating component includes a series-connected regulating capacitor and a regulating resistor to adjust the Vmn voltage value.
By increasing the charge loss generated by the regulation resistance, a lower Vmn voltage value is obtained, the risk of avalanche of the enhanced transistor is avoided, and this effect is achieved without increasing the chip area.
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Figure CN119894084A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a common-source and common-gate cascade device. Background Art
[0002] Gallium nitride (GaN)'s large bandgap, high breakdown voltage, and fast switching properties make it an ideal candidate for use in high-power semiconductor devices and at high temperatures. GaN high electron mobility transistors (HEMTs) are almost always normally-on devices, also known as depletion-mode devices. This means that when zero voltage is applied to the control terminal or gate, the depletion-mode device is highly conductive, or in the on state.
[0003] Normally-on devices are difficult to apply to many power conversion or switching applications. The cascode circuit includes a low voltage normally-off metal oxide semiconductor field effect transistor connected in series with a high voltage normally-on HEMT, and thus provides a cascode cascode structure having a normally-off mode of operation when zero voltage is applied to its control terminal, the gate of the MOSFET. Specifically, the gate and source of the GaN device are individually connected to the source and drain of the MOSFET in a cascode configuration, and when the MOSFET is turned off, a negative gate voltage is generated in the GaN device, thereby turning off the high voltage device. However, C between the GaN device and the MOSFET often occurs. ds_GaN The capacitor and Coss_Si capacitor do not match, which may cause MOSFET avalanche or DGaN gate damage. In the prior art, the source-drain voltage (V DS-MOSFET ) rating reduces the risk of MOSFET avalanche or DGaN gate damage. However, increasing the VDS voltage of the MOSFET often also leads to an increase in the on-resistance Rds(on), which can lead to a decrease in overall device performance. Another solution is to increase the chip size of the MOSFET, increase its Coss_Si junction capacitance and thus reduce Vmn, which will result in a significant increase in chip area. Summary of the invention
[0004] The purpose of the present application is to provide a common-source and common-gate cascade device, which can reduce the risk of MOSFET avalanche without increasing the chip area.
[0005] On the one hand, an embodiment of the present application provides a common-source and common-gate cascade device, including a cascaded depletion-mode transistor and an enhancement-mode transistor, wherein the depletion-mode transistor has a first source, a first drain and a first gate, and the enhancement-mode transistor has a second source, a second drain and a second gate, the first source is connected to the second drain, and the first gate is connected to the second source to form a cascade structure, and an adjustment component is also arranged in parallel between the first source and the second source, and the adjustment component includes an adjustment capacitor and an adjustment resistor connected in series.
[0006] As an implementable manner, the adjusting capacitor and the adjusting resistor are integrated inside the cascade structure.
[0007] As an implementable manner, the adjusting capacitor and the adjusting resistor are passive components connected inside the enhancement transistor.
[0008] As an implementable manner, the regulating capacitor is a junction capacitance of an enhancement mode transistor.
[0009] As an implementable manner, the cascade structure is formed with connection ends corresponding to the second source and the first source respectively, and the regulating component is arranged between the two connection ends.
[0010] As an implementable manner, auxiliary adjustment capacitors are also provided in parallel at both ends of the adjustment component.
[0011] As an implementable manner, a second resistor is connected between the first gate and the second source.
[0012] As an practicable manner, when the enhancement mode transistor is turned off, the voltage between the second source and the second drain rises to the turn-off voltage of the depletion mode transistor, and a negative voltage is generated at the first gate, turning off the depletion mode transistor.
[0013] As an implementable manner, after the depletion transistor is turned off, the junction capacitances of the depletion transistor and the enhancement transistor are charged. At this time, the gate-source voltage of the depletion transistor is the product of the ratio of the parasitic capacitance of the enhancement transistor and the junction capacitance of the depletion transistor and the voltage of the first drain.
[0014] As an implementable manner, the depletion mode transistor is a depletion gallium nitride device, and the enhancement mode transistor is a silicon MOS transistor.
[0015] The beneficial effects of the embodiments of the present application include:
[0016] The common-source and common-gate cascade device provided in the present application comprises a cascaded depletion-mode transistor and an enhancement-mode transistor, wherein the depletion-mode transistor has a first source, a first drain and a first gate, and the enhancement-mode transistor has a second source, a second drain and a second gate, the first source is connected to the second drain, the first gate is connected to the second source to form a cascade structure, and an adjustment component is also arranged in parallel between the first source and the second source, and the adjustment component comprises an adjustment capacitor and an adjustment resistor connected in series. The parasitic capacitance C of the depletion-mode transistor DS-1 and the junction capacitance C of the enhancement mode transistor DS-2When charging continues, the charge will be lost on the regulating resistor. The present application can obtain a lower Vmn voltage value by increasing the charge loss generated by the regulating resistor, thereby avoiding reducing the risk of avalanche of the enhancement transistor. In addition, there is also a technical solution in the prior art to set a simple capacitor in parallel between the first source and the second source. In this way, a larger capacitance value is required to obtain a lower Vmn voltage value, and a larger capacitance value needs to occupy a larger area. Therefore, the regulating component of the embodiment of the present application includes a regulating capacitor and a regulating resistor in series, which avoids the large chip area caused by simply relying on increasing the capacitance to reduce the Vmn voltage value. Therefore, the common source and common gate cascade device of the embodiment of the present application can reduce the risk of avalanche of the enhancement transistor without increasing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1 A circuit diagram of the structure of a common-source common-gate cascade device in the prior art;
[0019] Figure 2 The voltage variation curve of the common-source and common-gate cascade device in the prior art during the shutdown process;
[0020] Figure 3 One of the circuit diagrams of the structure of the common-source and common-gate device provided in the embodiment of the present application;
[0021] Figure 4 An equivalent circuit diagram of the structure of a common-source and common-gate device provided in an embodiment of the present application;
[0022] Figure 5 A second circuit diagram of the structure of a common-source and common-gate device provided in an embodiment of the present application;
[0023] Figure 6 A third circuit diagram of the structure of a common-source and common-gate device provided in an embodiment of the present application;
[0024] Figure 7 The fourth circuit diagram of the structure of the common-source and common-gate device provided in an embodiment of the present application.
[0025] Icon: 110 - depletion mode transistor; 111 - first source; 112 - first drain; 113 - first gate; 120 - enhancement mode transistor; 121 - second source; 122 - second drain; 123 - second gate; 130 - adjustment component; 131 - adjustment resistor; 132 - adjustment capacitor; 133 - auxiliary adjustment capacitor; 141 - junction capacitor; 142 - parasitic capacitor; 151 - second resistor. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0029] Common source and common gate cascade devices in the prior art are as follows: Figure 1 As shown, it includes a cascaded depletion-type transistor and an enhancement-type transistor. In practical applications, the depletion-type transistor has parasitic capacitance, and the enhancement-type transistor has junction capacitance. The shut-off process of the cascaded common-source and common-gate devices in the prior art is as follows: Figure 2 As shown, at time t1, the enhancement transistor is turned off, and the source-drain voltage V DS-2 Gradually increases until the source-drain voltage V DS-2When the depletion transistor is turned off, a negative voltage is generated at the first gate of the depletion transistor, thereby turning off the depletion transistor. After the depletion transistor is turned off, at time t2, the parasitic capacitance of the depletion transistor and the junction capacitance of the enhancement transistor continue to charge. According to the law of conservation of charge, the voltage value of Vmn is determined by the ratio of the parasitic capacitance to the junction capacitance, wherein the greater the ratio of the parasitic capacitance to the junction capacitance, the smaller the voltage value of Vmn. Wherein, Vmn is the drain-source voltage of the enhancement transistor and the gate-source voltage of the depletion transistor. At this time, if the ratio of the parasitic capacitance to the junction capacitance does not match, it will cause the enhancement transistor to avalanche. At time t3, the drain-source voltage Vmn of the enhancement transistor has reached the avalanche voltage, while the source-drain voltage VB of the depletion transistor has not yet reached a stable value, causing the depletion transistor to avalanche.
[0030] The present application provides a common-source common-gate cascade device, such as Figure 3 and Figure 4 As shown, it includes a cascaded depletion-mode transistor 110 and an enhancement-mode transistor 120, wherein the depletion-mode transistor 110 has a first source 111, a first drain 112 and a first gate 113, and the enhancement-mode transistor 120 has a second source 121, a second drain 122 and a second gate 123, the first source 111 is connected to the second drain 122, the first gate 113 is connected to the second source 121 to form a cascade structure, and an adjustment component 130 is also arranged in parallel between the first source 111 and the second source 121, and the adjustment component 130 includes an adjustment capacitor 132 and an adjustment resistor 131 connected in series.
[0031] The common-source common-gate cascade device of the embodiment of the present application includes a cascaded depletion-mode transistor 110 and an enhancement-mode transistor 120, wherein the depletion-mode transistor 110 is used as a main transistor to amplify an input signal; the enhancement-mode transistor 120 is used as an auxiliary transistor to control the on and off of the main transistor, and is used to increase the output impedance of the circuit, and to increase the gain and bandwidth. Specifically, the depletion-mode transistor 110 has a first source 111, a first drain 112, and a first gate 113, and the enhancement-mode transistor 120 has a second source 121, a second drain 122, and a second gate 123, wherein the first source 111 is connected to the second drain 122, and the first gate 113 is connected to the second source 121 to form a cascade structure.
[0032] In order to prevent the enhancement mode transistor 120 from avalanching, the embodiment of the present application sets a regulating component 130 between the source of the depletion mode transistor 110 (i.e., the first source 111) and the enhancement mode transistor 120 (i.e., the second source 121). The regulating component 130 includes a regulating capacitor 132 and a regulating resistor 131 connected in series. Figure 3 As shown, Figure 4 for Figure 3The equivalent circuit diagram is as follows, that is, the depletion-mode transistor 110 includes a tube body and a parasitic capacitor 142 connected in parallel with the tube body, and the enhancement-mode transistor 120 includes a tube body and a junction capacitor 141 connected in parallel with the tube body. Figure 4 in Figure 2 After time t2, the parasitic capacitance 142 of the depletion transistor 110 -1 The junction capacitance 141 of the enhancement mode transistor 120 continues to charge. At this time, the regulating resistor 131 will lose charge. According to the charge conservation law, the charge amount on the parasitic capacitance 142 of the depletion mode transistor 110 is equal to the sum of the charge amounts consumed by the junction capacitance 141 of the enhancement mode transistor 120 and the regulating resistor 131. At this time, the drain-source voltage Vmn of the enhancement mode transistor 120 satisfies the following equation:
[0033]
[0034]
[0035] Wherein, Cx is the capacitance value of the adjustment capacitor 132, Q is the total charge, and Qx is the charge consumed by the adjustment resistor 131. It can be seen from the above formula that the adjustment resistor 131 will generate charge loss. By increasing the charge loss generated by the adjustment resistor 131, a lower Vmn voltage value can be obtained, thereby avoiding the risk of reducing the avalanche of the enhancement transistor 120. In addition, there is also a technical solution in the prior art to set a simple capacitor in parallel between the first source 111 and the second source 121. In this way, a larger capacitance value is required to obtain a lower Vmn voltage value, and a larger capacitance value requires a larger area. The adjustment component 130 of the embodiment of the present application includes an adjustment capacitor 132 and an adjustment resistor 131 connected in series, which avoids the large chip area caused by simply relying on increasing the capacitance to reduce the Vmn voltage value. Therefore, the common source and common gate cascade device of the embodiment of the present application can reduce the risk of avalanche of the enhancement transistor 120 without increasing the chip area.
[0036] In the embodiment of the present application, the specific structures of the depletion-mode transistor 110 and the enhancement-mode transistor 120 are not limited in the embodiment of the present application, as long as the depletion-mode transistor 110 (also called the normally-on transistor) is in the on state in the natural state; the enhancement-mode transistor 120 (also called the normally-off transistor) is in the off state in the natural state.
[0037] In addition, the cascode device is a device such as Figure 3 As shown, the first drain 112 of the depletion mode transistor 110 is led out as the drain of the cascade device, the second source 121 of the enhancement mode transistor 120 is led out as the source of the cascade device, and the second gate 123 of the enhancement mode transistor 120 is led out as the gate of the cascade device.
[0038] The common-source common-gate cascade device provided in the present application includes a cascaded depletion-mode transistor 110 and an enhancement-mode transistor 120. After the enhancement-mode transistor 120 is turned off, during the depletion-mode transistor 110 being turned off, the parasitic capacitance 142 of the depletion-mode transistor 110 -1 and the junction capacitance 141 of the enhancement mode transistor 120 -2 When charging continues, the regulating resistor 131 will lose charge. The present application can obtain a lower Vmn voltage value by increasing the charge loss generated by the regulating resistor 131, thereby avoiding reducing the risk of avalanche of the enhancement mode transistor 120. In addition, there is also a technical solution in the prior art to set a simple capacitor in parallel between the first source 111 and the second source 121. In this way, a larger capacitance value is required to obtain a lower Vmn voltage value, and a larger capacitance value needs to occupy a larger area. Therefore, the regulating component 130 of the embodiment of the present application includes a regulating capacitor 132 and a regulating resistor 131 connected in series, avoiding the large chip area caused by simply relying on increasing the capacitance to reduce the Vmn voltage value. Therefore, the common source and common gate cascade device of the embodiment of the present application can reduce the risk of avalanche of the enhancement mode transistor 120 without increasing the chip area.
[0039] Optionally, the adjustment capacitor 132 and the adjustment resistor 131 are integrated inside the cascade structure.
[0040] The regulating capacitor 132 and the regulating resistor 131 are integrated into the cascade structure, so that the common-source and common-gate cascade device functions as a whole.
[0041] In one implementable manner of the embodiment of the present application, the adjustment capacitor 132 and the adjustment resistor 131 are passive components connected inside the enhancement mode transistor 120 .
[0042] The adjustment capacitor 132 and the adjustment resistor 131 are connected inside the enhancement mode transistor 120, and the adjustment capacitor 132 occupies the area of the enhancement mode transistor 120. The present application can reduce the area of the enhancement mode transistor 120. In this way, on the basis of the chip area of the same cascade structure, after reducing the area of the enhancement mode transistor 120, the chip area of the depletion mode transistor 110 can be increased.
[0043] Optional, such as Figure 6 As shown, the adjustment capacitor 132 is the junction capacitor 141 of the enhancement mode transistor 120 .
[0044] The adjustment capacitor 132 is the junction capacitor 141 of the enhancement transistor 120. In this way, the junction capacitor 141 of the enhancement transistor 120 can be fully utilized, or on the basis of the original junction capacitor 141, only a smaller value of the junction capacitor 141 needs to be increased, that is, the area occupied by the junction capacitor 141 needs to be increased, without increasing the adjustment capacitor 132, thereby reducing the chip area occupied by the adjustment capacitor 132.
[0045] In addition, by using the junction capacitor 141 as the adjustment capacitor 132 , the number of components of the cascode device can be reduced.
[0046] In one implementable manner of the embodiment of the present application, the cascade structure is formed with connection ends corresponding to the first drain 112 and the first source 111 , respectively, and the regulating component 130 is disposed between the two connection ends.
[0047] In practical applications, the depletion-mode transistor 110 and the enhancement-mode transistor 120 are usually packaged together. The depletion-mode transistor 110 and the enhancement-mode transistor 120 of the embodiment of the present application are usually packaged together to form a package body, and the package body forms connection ends corresponding to the second source 121 and the first source 111, respectively. The adjustment component 130 is arranged between the two connection ends, that is, the adjustment capacitor 132 and the adjustment resistor 131 of the adjustment component 130 are discrete components independent of the package body. When the adjustment capacitor 132 or the adjustment resistor 131 fails or is damaged, it can be easily replaced.
[0048] Optional, such as Figure 5 As shown, an auxiliary adjustment capacitor 133 is also connected in parallel at both ends of the adjustment component 130 .
[0049] An auxiliary adjustment capacitor 133 is arranged in parallel at both ends of the adjustment component 130. The combination of the adjustment capacitor 132, the adjustment resistor 131 and the auxiliary adjustment capacitor 132 can reduce the capacitance value of the adjustment capacitor 132. When the capacitor is integrated inside the cascade structure, the area occupied by the adjustment capacitor 132 can be reduced, thereby reducing the area of the chip.
[0050] In one possible implementation of the embodiment of the present application, Figure 7 As shown, a second resistor 151 is connected between the first gate 113 and the second source 121 .
[0051] exist Figure 7 In the embodiment, a second resistor 151 is arranged between the first gate 113 and the second source 121, wherein the second resistor 151 serves as a gate resistor of the first gate 113 and can adjust the voltage at the gate, thereby adjusting the switching speed of the depletion-mode transistor 110 to avoid excessive temperature of the common-source and common-gate cascade device due to excessive switching speed.
[0052] It should be noted that the setting of the second resistor 151 may result in a risk of a higher Vmn voltage value. In this case, the temperature and the Vmn voltage value are balanced by adjusting the parameters of the regulating component 130 .
[0053] Optionally, when the enhancement mode transistor 120 is turned off, the voltage between the second source 121 and the second drain 122 rises to the turn-off voltage of the depletion mode transistor 110 , and a negative voltage is generated at the first gate 113 , turning off the depletion mode transistor 110 .
[0054] In one implementable method of the embodiment of the present application, after the depletion-mode transistor 110 is turned off, the parasitic capacitance 142 of the depletion-mode transistor 110 and the junction capacitance 141 of the enhancement-mode transistor 120 are charged. At this time, the gate-source voltage of the depletion-mode transistor 110 is the product of the ratio of the junction capacitance 141 of the enhancement-mode transistor 120 and the depletion-mode transistor 110 and the voltage of the first drain 112.
[0055] Optionally, the depletion mode transistor 110 is a depletion gallium nitride device, and the enhancement mode transistor 120 is a silicon MOS transistor.
[0056] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A common source and common gate cascade device, characterized in that: It includes a cascaded depletion-mode transistor and an enhancement-mode transistor, wherein the depletion-mode transistor has a first source, a first drain and a first gate, and the enhancement-mode transistor has a second source, a second drain and a second gate, the first source is connected to the second drain, the first gate is connected to the second source to form a cascade structure, and an adjustment component is also arranged in parallel between the first source and the second source, and the adjustment component includes an adjustment capacitor and an adjustment resistor connected in series.
2. The cascode device according to claim 1, characterized in that: The regulating capacitor and the regulating resistor are integrated inside the cascade structure.
3. The cascode device according to claim 2, characterized in that: The regulating capacitor and regulating resistor are passive components connected inside the enhancement transistor.
4. The cascode device according to claim 2, characterized in that: The adjustment capacitor is the junction capacitance of the enhancement mode transistor.
5. The cascode device according to claim 1, characterized in that: The cascade structure is formed with connection ends corresponding to the first source and the second source respectively, and the regulating component is arranged between the two connection ends.
6. The cascode device according to claim 1, characterized in that: Auxiliary adjustment capacitors are also arranged in parallel at both ends of the adjustment component.
7. The cascode device according to claim 1, characterized in that: A second resistor is connected between the first gate and the second source.
8. The cascode device according to claim 1, characterized in that: When the enhancement-mode transistor is turned off, the voltage between the second source and the second drain rises to a turn-off voltage of the depletion-mode transistor, and a negative voltage is generated at the first gate, turning off the depletion-mode transistor.
9. The cascode device according to claim 1, characterized in that: After the depletion transistor is turned off, the junction capacitance of the depletion transistor and the enhancement transistor is charged. At this time, the gate-source voltage of the depletion transistor is the product of the ratio of the parasitic capacitance of the enhancement transistor and the junction capacitance of the depletion transistor and the voltage of the first drain.
10. The cascode device according to claim 1, characterized in that: The depletion mode transistor is a depleted gallium nitride device, and the enhancement mode transistor is a silicon MOS transistor.