A passivated contact back contact solar cell and a method of making the same

Abstract

The application discloses a kind of passivated contact type back contact solar cell and its preparation method, and the cell includes crystalline silicon base, the positive side of crystalline silicon base is passivation antireflection layer, and the back side is sequentially first tunneling layer, first polysilicon layer, second tunneling layer, second polysilicon layer, passivation layer and metal electrode from inside to outside, wherein, first polysilicon layer includes first n+ polysilicon area, first p+ polysilicon area and first isolation area, second polysilicon layer includes second n+ polysilicon area, second p+ polysilicon area and second isolation area, and the doping concentration of boron element in first p+ polysilicon area is lower than the doping concentration of boron element in second p+ polysilicon area, and the doping concentration of phosphorus element in first n+ polysilicon area is lower than the doping concentration of phosphorus element in second n+ polysilicon area.The cell of the application adopts double-layer tunneling polysilicon structure on the back side, which can simultaneously meet low metal contact recombination, low non-metal contact area recombination and low contact resistivity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a passivated contact back contact solar cell and a preparation method thereof. BACKGROUND

[0002] Back contact cell is a kind of cell in which p+ doped region and n+ doped region are both placed on the back surface (non-light receiving surface) of the cell, and the light receiving surface of the cell is not blocked by any metal electrode, thereby effectively increasing the short-circuit current of the cell sheet and improving the energy conversion efficiency of the cell sheet. Passivated contact technology is a technology that has emerged in recent years and has excellent contact without damaging the passivation film. The technology is to set an ultrathin oxide layer as a tunneling layer on the surface of a silicon substrate, and then set a doped polysilicon layer on the oxide layer, and then set a passivation film and a metal electrode on the doped polysilicon layer. The advantage of this structure is that the carriers can be transmitted freely through the oxide layer, and the oxide layer can also provide good surface passivation for the surface of the silicon substrate.

[0003] Passivated contact back contact cell (IBC cell) refers to a passivated contact structure formed by an ultrathin oxide layer and a doped polysilicon layer on the back surface. One of the difficulties of this structure is to prepare N-type diffusion region and P-type diffusion region in a comb-shaped cross distribution on the back surface of the cell. Usually, two high-temperature diffusion processes, intermediate high-temperature diffusion mask preparation, pattern etching, and cleaning processes are required, and the preparation process is relatively complex, and the yield of the cell is relatively low. Moreover, the existing IBC cell structure is a passivated contact structure formed by a single tunneling oxide layer and a single doped polysilicon layer. In this structure, the metal semiconductor recombination and the non-metal contact area recombination loss are large, and the contact resistivity is large, thereby resulting in low conversion efficiency of the cell.

[0004] Therefore, how to obtain an IBC cell with low metal semiconductor recombination, low non-metal contact area recombination, and low contact resistivity through optimization of the structure and preparation process has become a research focus. SUMMARY

[0005] In view of the above problems, the present application aims to provide a passivated contact back contact solar cell and a preparation method thereof. A double-layer tunneling polysilicon structure comprising a first tunneling oxide layer, a first polysilicon layer, a second tunneling oxide layer and a second polysilicon layer is sequentially deposited on the back surface of the solar cell, a certain thickness of phosphorus ions and boron ions are respectively injected into the surface of the second polysilicon layer by ion implantation technology, and under the action of high-temperature annealing, boron and phosphorus are diffused inwardly to the first polysilicon layer by controlling the annealing temperature and time, so as to complete the doping of the second polysilicon layer and the first polysilicon layer. Due to the blocking effect of the second tunneling oxide layer, a certain concentration difference of phosphorus and boron is formed between the doped second polysilicon layer and the doped first polysilicon layer in the finally formed cell structure, which reduces the contact resistivity and also reduces the recombination of the metal contact area and the non-metal contact area, so that the cell meets the requirements of low metal contact recombination, low non-metal contact area recombination and low contact resistivity, thereby improving the open-circuit voltage and conversion efficiency of the cell.

[0006] In order to achieve the above-mentioned purposes, the present application first provides a preparation method of a passivated contact back contact solar cell, comprising the following steps:

[0007] (1) performing a texturing treatment on a crystalline silicon substrate to remove a damage layer and form a pyramid light-trapping structure;

[0008] (2) depositing a mask layer on the front surface of the crystalline silicon substrate treated in step (1);

[0009] (3) placing the crystalline silicon substrate treated in step (2) in a polishing solution so that the back surface is etched into a polished surface;

[0010] (4) sequentially depositing a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer and a second intrinsic amorphous silicon layer on the back surface of the crystalline silicon substrate etched in step (3);

[0011] (5) performing phosphorus injection and boron injection on the back surface of the crystalline silicon substrate treated in step (4) by ion implantation to form an n+ injection region and a p+ injection region, respectively, and leaving a gap between the n+ injection region and the p+ injection region;

[0012] (6) Put the crystal silicon substrate processed in step (5) into an annealing furnace for high-temperature annealing treatment. Under the action of high-temperature annealing, the boron element in the p+ injection region and the phosphorus element in the n+ injection region will respectively perform boron doping and phosphorus doping on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, so as to finally form the first p+ polysilicon region and the second p+ polysilicon region and the first n+ polysilicon region and the second n+ polysilicon region, wherein the doping concentration of the boron element in the first p+ polysilicon region is lower than the doping concentration of the boron element in the second p+ polysilicon region, and the doping concentration of the phosphorus element in the first n+ polysilicon region is lower than the doping concentration of the phosphorus element in the second n+ polysilicon region;

[0013] (7) Put the crystal silicon substrate processed in step (6) into a cleaning machine for cleaning and drying, so that the mask layer and the oxide layer generated in the annealing are completely removed;

[0014] (8) Make a passivation anti-reflection layer and a passivation layer on the front surface and the back surface of the crystal silicon substrate processed in step (7), respectively;

[0015] (9) Print a metal electrode on the back surface of the crystal silicon substrate processed in step (8) by a screen printing method, and then transfer the crystal silicon substrate into a belt sintering furnace for sintering to form an ohmic contact.

[0016] In an embodiment of the present application, the crystal silicon substrate in step (1) includes an N-type crystal silicon substrate and a P-type crystal silicon substrate, the resistivity of the crystal silicon substrate is 0.3-10 Ω·cm, preferably 1-5 Ω·cm, and the thickness of the crystal silicon substrate is 50-300 μm, preferably 80-200 μm.

[0017] In an embodiment of the present application, the mask layer in step (2) is at least one of SiO2, SiN x , SiN x O y , and the deposition method of the mask layer is plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), and the thickness of the mask is 20-100 nm.

[0018] In an embodiment of the present application, the polishing solution in step (3) is at least one of heated NaOH, KOH and TMAH solution, the heating temperature is 75-85 ℃, and the etching time is 50-120 s. After the crystal silicon substrate is placed in the polishing solution, the front surface will not react with the polishing solution due to the presence of the mask layer, and the back surface will be etched into a polished surface, and the mask layer is still retained after polishing.

[0019] In one embodiment of the present application, the first tunneling oxide layer in step (4) is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the first tunneling layer is 0.8-3 nm, preferably 1-1.5 nm.

[0020] In one embodiment of the present application, the deposition method of the first intrinsic amorphous silicon layer in step (4) includes at least one of low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and plasma-enhanced chemical vapor deposition (PECVD). The thickness of the first intrinsic amorphous silicon layer is 10-30 nm.

[0021] In one embodiment of the present application, the second tunneling oxide layer in step (4) is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the second tunneling layer is 0.8-3 nm, preferably 0.8-1.0 nm.

[0022] The thickness of the second tunneling oxide layer is preferably 0.8-1.0 nm. If the thickness is too thin, the chemical passivation effect is not good. If the thickness is too thick, it exceeds the penetration ability of the electron, resulting in a loss of current. According to experimental simulation data, the optimal thickness of the second tunneling oxide layer is 0.9 nm.

[0023] In one embodiment of the present application, the deposition method of the second intrinsic amorphous silicon layer in step (4) includes at least one of low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and plasma-enhanced chemical vapor deposition (PECVD). The thickness of the second intrinsic amorphous silicon layer is 50-80 nm.

[0024] In one embodiment of the present application, in step (5), two ion sources are used to realize phosphorus and boron implantation. A mask clamp is arranged between the back surface of the silicon wafer and the ion source when the phosphorus implantation or boron implantation is performed, so as to realize selective implantation of boron ions or phosphorus ions. The material of the mask clamp is graphite.

[0025] In one embodiment of the present application, in step (5), when boron implantation is performed, linear openings are provided on the mask holder, the linear openings are 1950-2050 um wide, and after implantation, a patterned p+ implantation layer is formed on the second intrinsic amorphous silicon layer; when phosphorus implantation is performed, linear openings are provided on the mask holder, the linear openings are 1950-2050 um wide, and after implantation, a patterned n+ implantation layer is formed on the second intrinsic amorphous silicon layer. The p+ implantation layer and the n+ implantation layer do not directly contact each other, and there is an area between them that is not implanted by ions. The opening pattern on the mask holder can also be other arbitrary periodic or quasi-periodic arrays, and the pattern can be selected in multiple ways according to needs, which is not limited here and is only listed as an example.

[0026] In one embodiment of the present application, in step (5), the dose of boron implantation is 0.5×10 15 cm -2 -3×10 15 cm -2 , preferably 1.5×10 15 cm -2 -2.5×10 15 cm -2 , and the dose of phosphorus implantation is 3×10 15 cm -2 -8×10 15 cm -2 , preferably 4×10 15 cm -2 -6×10 15 cm -2 .

[0027] In one embodiment of the present application, in step (5), when boron and phosphorus implantation is performed, the power supply voltage is 105-300 V, preferably 150-250 V, and more preferably 180-220 V, and the material delivery rate is 0.8-1.2 m / min.

[0028] In one embodiment of the present application, in step (6), the peak temperature of annealing is 800-1100℃, preferably 850-1000℃, the annealing time is 30-200 min, preferably 60-200 min, and the environmental gas source is preferably N2 and O2.

[0029] In the present application, the depth of boron and phosphorus implantation into the second intrinsic polysilicon layer is realized by regulating the power voltage and the material conveying rate, so that the ion implantation depth is 25-45 nm, and the ion concentration distribution is Gaussian distribution outside the core implantation depth. By implanting a certain dose of boron and phosphorus into the surface of the second intrinsic polysilicon layer, an ion implantation layer with a certain depth is formed on the surface of the second intrinsic polysilicon layer. Under the action of high-temperature annealing, the implanted boron or phosphorus will diffuse to the inside. By controlling the annealing temperature and time, the phosphorus and boron in the second polysilicon layer are activated, and at the same time, part of the boron or phosphorus is doped into the first intrinsic polysilicon layer through the second tunnel oxide layer, forming a concentration difference between the second intrinsic polysilicon layer and the first intrinsic polysilicon layer, so as to improve the recombination loss of the solar cell and improve the conversion efficiency of the solar cell.

[0030] Under the action of high-temperature annealing, the boron element in the p+ implantation layer will dope the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer below, and finally form a first p+ polysilicon layer and a second p+ polysilicon layer, wherein the doping concentration of boron element in the first p+ polysilicon layer is lower than that in the second p+ polysilicon layer. Under the action of high-temperature annealing, the phosphorus element in the n+ implantation layer will dope the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer below, and finally form a first n+ polysilicon layer and a second n+ polysilicon layer, wherein the doping concentration of phosphorus element in the first n+ polysilicon layer is lower than that in the second n+ polysilicon layer. The region of the first intrinsic amorphous silicon layer which is not ion implanted is converted into a first isolation layer after annealing, and the region of the second intrinsic amorphous silicon layer which is not ion implanted is converted into a second isolation layer after annealing.

[0031] In an embodiment of the present application, the passivation anti-reflection layer of step (8) comprises AlO x dielectric film, SiN x dielectric film and / or SiN x O y dielectric film, the AlO x dielectric film is deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), and the film thickness is 3-10 nm; the SiN x dielectric film or SiN x O y dielectric film is deposited by plasma enhanced chemical vapor deposition (PECVD), and the SiN x dielectric film has a thickness of 5-30 nm, and the SiN x O y dielectric film has a thickness of 40-80 nm.

[0032] In one embodiment of the present application, the passivation layer in step (8) comprises AlO x dielectric film and SiN x dielectric film x The deposition method of the dielectric film is plasma enhanced chemical vapor deposition (PECVD), and the SiN x The thickness of the dielectric film is 50-90 nm.

[0033] In one embodiment of the present application, in step (8), a layer of AlO x dielectric film with a thickness of 3-10 nm is first prepared on the front surface and the back surface of the crystalline silicon substrate, then a layer of SiN x dielectric film with a thickness of 5-30 nm is deposited on the front surface by PECVD, then a layer of SiN x dielectric film is deposited on the SiN x O y dielectric film, and finally a layer of SiN x dielectric film is deposited on the surface of the back AlO x dielectric film.

[0034] In one embodiment of the present application, in step (10), the metal electrode is silver.

[0035] The present application also discloses a passivated contact back contact solar cell prepared by the above method.

[0036] In one embodiment of the present application, the solar cell comprises a crystalline silicon substrate, the front surface of the crystalline silicon substrate is a passivation anti-reflection layer, and the passivation anti-reflection layer comprises, from inside to outside, a first AlO x dielectric film, a first SiN x dielectric film and / or SiN x O y dielectric film, and the back surface of the crystalline silicon substrate comprises, from inside to outside, a first tunneling layer, a first polysilicon layer, a second tunneling layer, a second polysilicon layer, a passivation layer and a metal electrode, wherein the passivation layer comprises, from inside to outside, a second AlO x dielectric film and a second SiN x dielectric film, and the metal electrode is a silver electrode; wherein the first polysilicon layer comprises a first n+ polysilicon region, a first p+ polysilicon region and a first isolation region, the second polysilicon layer comprises a second n+ polysilicon region, a second p+ polysilicon region and a second isolation region, the doping concentration of boron in the first p+ polysilicon region is lower than that in the second p+ polysilicon region, and the doping concentration of phosphorus in the first n+ polysilicon region is lower than that in the second n+ polysilicon region.

[0037] In one embodiment of the present application, the first AlO xDielectric film and second AlO x The thickness of the dielectric film is 3~10nm. The first SiN x The thickness of the dielectric film is 5~30nm, and the SiN x O y The thickness of the dielectric film is 40-80 nm, and the second SiN x The thickness of the dielectric film is 50~90nm.

[0038] Beneficial effects:

[0039] (1) The back of the back-contact solar cell of the present invention adopts a double-layer tunneling polysilicon structure, which can simultaneously meet the requirements of low metal contact recombination, low non-metal contact area recombination and low contact resistivity. On the one hand, the metal electrode only partially burns through the second n+ polysilicon layer and the second p+ polysilicon layer, and does not contact the crystalline silicon substrate, thereby reducing metal semiconductor recombination; on the other hand, the second n+ polysilicon layer and the second p+ polysilicon layer in contact with the metal electrode are heavily doped, which can greatly reduce the contact resistivity and reduce resistance loss; while the first n+ polysilicon layer and the first p+ polysilicon layer close to the crystalline silicon substrate are lightly doped, which reduces the recombination of the non-metal contact area and reduces the current loss caused by free carrier absorption.

[0040] (2) The double-layer tunneling polysilicon structure of the present invention can overcome the shortcomings of the single-layer tunneling polysilicon structure used in the prior art, meet the requirements of low metal area contact recombination, non-metal contact area recombination and resistance loss, and at the same time improve the open circuit voltage and conversion efficiency of the battery by controlling the concentration difference of boron and phosphorus between the doped second polysilicon layer and the first polysilicon layer. The process technologies used in the preparation method are all mature technologies and are suitable for mass production and promotion.

[0041] (3) The present invention uses ion implantation technology to dope phosphorus and boron ions. The doping concentration of phosphorus and boron ions is easy to control. By controlling the implantation thickness and amount of phosphorus and boron, the thickness of the second intrinsic amorphous silicon layer, and the diffusion temperature and time, the concentration of boron and phosphorus ions doped in the first intrinsic polycrystalline silicon layer can be effectively controlled, thereby effectively improving the performance of the solar cell and improving the conversion efficiency. In addition, compared with the traditional method of diffusion using a diffusion furnace, the present invention uses an ion implantation method to implant boron or phosphorus into the surface of the second intrinsic polycrystalline silicon layer. Under the drive of high temperature, phosphorus and boron will be selectively and directionally doped into the first intrinsic polycrystalline silicon layer. When the same concentration difference is achieved, the ion implantation method of the present invention can effectively reduce the implantation amount of boron and phosphorus. Moreover, the method of ion implantation combined with high temperature annealing can improve the doping uniformity of phosphorus and boron in the intrinsic polycrystalline silicon layer, further improving the performance of the cell.

[0042] (4) The open circuit voltage of the passivated contact back contact solar cell prepared by the method can reach 749mV, the current density reaches 42mA / cm 2 , the fill factor reaches 85.5%, and the conversion efficiency of the cell is as high as 26.8%. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 It is the battery structure cross section schematic diagram after step (1) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0044] Figure 2 It is the battery structure cross section schematic diagram after step (2) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0045] Figure 3 It is the battery structure cross section schematic diagram after step (3) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0046] Figure 4 It is the battery structure cross section schematic diagram after step (4) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0047] Figure 5 It is the battery structure cross section schematic diagram after step (5) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0048] Figure 6 It is the battery structure cross section schematic diagram after step (6) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0049] Figure 7 It is the battery structure cross section schematic diagram after step (7) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0050] Figure 8 It is the battery structure cross section schematic diagram after step (8) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0051] Figure 9 It is the battery structure cross section schematic diagram after step (9) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0052] Figure 10 It is the flow chart of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0053] Figure 11 It is the schematic diagram of the mask 41 used in step (5) of the preparation method of the passivated contact back contact solar cell of the embodiment of the application.

[0054] Figure 12 A schematic view of the mask 42 used in step (5) of the method for preparing a passivated contact back junction solar cell according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] The present application will be described in detail below with reference to examples.

[0056] Example 1

[0057] A method for preparing a passivated contact back junction solar cell, comprising the following steps:

[0058] (1) A texturized treatment is performed on the N-type crystalline silicon substrate 1 to remove the damaged layer and form a pyramid light-trapping structure. The resistivity of the N-type crystalline silicon substrate 1 is 1-1.5 Ω•cm, and the thickness of the N-type crystalline silicon substrate 1 is 130-170 μm. The structure of the cell after this step is shown in FIG. 1. Figure 1

[0059] (2) A layer of SiN X mask 31 is deposited on the front surface of the N-type crystalline silicon substrate 1 after step (1) using a plasma enhanced chemical vapor deposition (PECVD) method. The thickness of the mask 31 is 35-45 nm. The structure of the cell after this step is shown in FIG. 2. Figure 2

[0060] (3) The N-type crystalline silicon substrate 1 is placed in a polishing solution, and the front surface will not react with the polishing solution due to the presence of the mask 31, while the back surface will be etched into a polished surface. The polishing solution is a heated NaOH solution (solution temperature 78-82 °C, polishing time 60 s). The mask 31 is still retained after polishing. The structure of the cell after this step is shown in FIG. 3. Figure 3

[0061] (4) A first tunneling layer 201 is first grown on the back surface of the N-type crystalline silicon substrate 1 using a high-temperature thermal oxidation method. The first tunneling layer 201 is SiO2, and the thickness is 1.0-1.5 nm. A first intrinsic amorphous silicon layer 701 with a thickness of 15-25 nm is grown on the first tunneling layer 201 using an LPCVD device (low pressure chemical vapor deposition). A second tunneling layer 202 is then grown on the first intrinsic amorphous silicon layer 701 using a high-temperature thermal oxidation method. The second tunneling layer 202 is SiO2, and the thickness is 1.0-1.5 nm. A second intrinsic amorphous silicon layer 702 with a thickness of 75-85 nm is grown on the second tunneling layer 202 using an LPCVD device (low pressure chemical vapor deposition). The structure of the cell after this step is shown in FIG. 4. Figure 4

[0062] ​​​​(5) Ion implantation is used to perform back surface doping on the back surface of the N-type crystalline silicon substrate 1 after treatment in step (4), wherein two ion sources are provided, which can respectively implement boron implantation and phosphorus implantation. A mask fixture is provided between the back surface of the silicon wafer and the ion source for selectively implanting boron ions or phosphorus ions. During boron ion implantation, the power supply voltage is 200V, the material transport speed is 1m / min, and a mask 41 is provided between the back surface of the N-type crystalline silicon substrate 1 and the ion beam. The material of the mask 41 is graphite, such as Figure 11 As shown, a linear opening 411 is provided on the mask 41, and the width of the linear opening 411 is 1950-2050 μm, and the boron implantation dose is 1.5×10 15 ~2.5×10 15 cm -2 After the implantation is completed, a patterned p+ implantation layer 500 is formed on the second intrinsic amorphous silicon layer 702; during the phosphorus ion implantation, the power supply voltage is 200V, the material transport speed is 0.95m / min, and a mask 42 is set between the back surface of the N-type crystalline silicon substrate 1 and the ion beam. The material of the mask 42 is graphite, such as Figure 12 As shown, a linear opening 421 is provided on the mask 42, and the width of the linear opening 421 is 1950-2050 μm. The phosphorus implantation dose is 4.5×10 15 ~5.5×10 15 cm -2 After the implantation is completed, a patterned n+ implantation layer 400 is formed on the second intrinsic amorphous silicon layer 702. The p+ implantation layer 500 and the n+ implantation layer 400 do not directly contact each other, and there is an area between them that is not implanted with ions. The opening pattern on the mask 41 and the mask 42 can also be a periodic or quasi-periodic array with any other arrangement. There are many options for the pattern as needed, which are not limited here and are only listed as examples. The battery structure after completing this step is as follows Figure 5 shown.

[0063] (6) Put the N-type crystalline silicon substrate 1 treated in step (5) into an annealing furnace for high-temperature annealing treatment, with a peak temperature of 888-892°C, an annealing time of 120 min, and N2 as the environmental gas source. Under the action of high temperature in the annealing process, the boron element in the p+ implantation layer 500 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form the first p+ polysilicon layer 501 and the second p+ polysilicon layer 502, wherein the doping concentration of boron element in the first p+ polysilicon layer 501 is lower than that in the second p+ polysilicon layer 502. Under the action of high temperature in the annealing process, the phosphorus element in the n+ implantation layer 400 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form the first n+ polysilicon layer 401 and the second n+ polysilicon layer 402, wherein the doping concentration of phosphorus element in the first n+ polysilicon layer 401 is lower than that in the second n+ polysilicon layer 402. The region in the first intrinsic amorphous silicon layer 701 that is not ion implanted is converted into the first isolation layer 301 after annealing, and the region in the second intrinsic amorphous silicon layer 702 that is not ion implanted is converted into the second isolation layer 302 after annealing. Thus, a double-layer tunneling polysilicon structure is formed on the back surface of the N-type crystalline silicon substrate 1. The structure of the battery after completion of this step is shown in FIG. 6. Figure 6

[0064] (7) Put the N-type crystalline silicon substrate 1 treated in step (6) into a cleaning machine for cleaning and drying. After cleaning, the mask 31 and the oxide layer generated in the annealing process are completely removed. The structure of the battery after completion of this step is shown in FIG. 7. Figure 7

[0065] (8) On the front surface of the N-type crystalline silicon substrate 1 treated in step (7), an AlO x dielectric film 12 with a thickness of 4.5-5.5 nm is prepared by ALD (atomic layer deposition); and on the back surface, an AlO x dielectric film 11 with a thickness of 4.5-5.5 nm is prepared by ALD (atomic layer deposition). On the front surface, a SiN x dielectric film 13 with a thickness of 28-32 nm is first deposited by PECVD, and then a SiN x O x dielectric film 14 with a thickness of 48-52 nm is deposited on the SiN y dielectric film 13; and finally, a SiN x O x dielectric film 15 with a thickness of 83-87 nm is deposited on the surface of the AlO x dielectric film 11 on the back surface.

[0066] The AlO​​x Dielectric film 12, SiN x Dielectric film 13, SiN x O y Dielectric film 14 serves to passivate the front surface of the silicon substrate and reduce reflection of light; AlO x Dielectric film 11 and SiN x Dielectric film 15 serves to passivate the back surface of the silicon substrate, while SiN x Dielectric film 15 also serves to protect the AlO x Dielectric film 11. The structure of the battery after this step is shown in Figure 8 .

[0067] (9) A metal electrode 22 is printed on the second n+ polysilicon layer 402 on the back surface of the N-type crystalline silicon substrate 1 after step (8) by a screen printing method, and a metal electrode 21 is printed on the second p+ polysilicon layer 502 on the back surface. The metal electrode 21 and the metal electrode 22 are silver. After printing, the N-type crystalline silicon substrate 1 is transferred into a belt sintering furnace for sintering to form an ohmic contact. The structure of the battery after this step is shown in Figure 9 . Thus, the preparation of the passivated contact back contact solar cell is completed.

[0068] The open-circuit voltage of the solar cell prepared by the method of Example 1 is 749 mV, the current density is 42 mA / cm 2 , the fill factor is 85.5%, and the conversion efficiency of the battery is 26.8%.

[0069] Example 2:

[0070] A preparation method of a passivated contact back contact solar cell, comprising the following steps:

[0071] (1) The P-type crystalline silicon substrate 1 is subjected to texturing treatment to remove the damage layer and form a pyramid light-trapping structure. The resistivity of the P-type crystalline silicon substrate 1 is 1-1.5 Ω•cm; the thickness of the P-type crystalline silicon substrate 1 is 130-170 μm. The structure of the battery after this step is shown in Figure 1 .

[0072] (2) A layer of SiN X mask 31 with a thickness of 35-45 nm is deposited on the front surface of the P-type crystalline silicon substrate 1 after step (1) by a plasma enhanced chemical vapor deposition (PECVD) method. The structure of the battery after this step is shown in Figure 2 .

[0073] (3) Put the P-type crystalline silicon substrate 1 into a polishing solution, the front surface will not react with the polishing solution due to the presence of the mask 31, while the back surface will be etched into a polished surface. The polishing solution is a heated NaOH solution (78-82℃, time 60s). The mask 31 is still retained after the polishing is completed. The battery structure after this step is shown in Figure 3 .

[0074] (4) First, a first tunneling layer 201 is grown on the back surface of the P-type crystalline silicon substrate 1, the first tunneling layer 201 is SiO2, and the growth method is high-temperature thermal oxidation. The thickness of the first tunneling layer 201 is 1.0-1.5nm. An LPCVD device (low pressure chemical vapor deposition) is used to grow a first intrinsic amorphous silicon layer 701 with a thickness of 15-25nm on the first tunneling layer 201. Then a high-temperature thermal oxidation method is used to grow a second tunneling layer 202 on the first intrinsic amorphous silicon layer 701, the second tunneling layer 202 is SiO2, and the thickness is 0.8-1.0nm. An LPCVD device (low pressure chemical vapor deposition) is used to grow a second intrinsic amorphous silicon layer 702 with a thickness of 75-85nm on the second tunneling layer 202. The battery structure after this step is shown in Figure 4 .

[0075] (5) Back surface doping is performed on the back surface of the P-type crystalline silicon substrate 1 after step (4) by ion implantation, two ion sources are used to achieve boron implantation and phosphorus implantation, respectively. A mask clamp is provided between the back surface of the silicon wafer and the ion source to achieve selective implantation of boron ions or phosphorus ions. When boron ions are implanted, the power supply voltage is 200V, the material transfer speed is 1m / min, and a mask 41 is provided between the back surface of the P-type crystalline silicon substrate 1 and the ion beam. The mask 41 is made of graphite, as shown in Figure 11 , a line-shaped opening 411 is provided on the mask 41, the line-shaped opening 411 is 1950-2050um wide, the boron implantation dose is 1.5×10 15 ~2.5×10 15 cm -2 , and a patterned p+ implantation layer 500 is formed on the second intrinsic amorphous silicon layer 702 after implantation is completed; when phosphorus ions are implanted, the power supply voltage is 200V, the material transfer speed is 0.95m / min, and a mask 42 is provided between the back surface of the P-type crystalline silicon substrate 1 and the ion beam. The mask 42 is made of graphite, as shown in Figure 12 , a line-shaped opening 421 is provided on the mask 42, the line-shaped opening 421 is 1950-2050um wide, the phosphorus implantation dose is 4.5×10 15 ~5.5×10 15 cm -2, after the implantation, a patterned n+ implantation layer 400 is formed on the second intrinsic amorphous silicon layer 702. The p+ implantation layer 500 and the n+ implantation layer 400 do not directly contact each other, and there is an area not implanted by ions between them. The opening pattern on the mask 41 and the mask 42 can also be other periodic or quasi-periodic arrays arranged in any manner, and the pattern can be selected in various manners as needed, which is not limited herein and is only listed as an example. The battery structure after this step is shown in Figure 5 .

[0076] (6) The P-type crystalline silicon substrate 1 after step (5) is placed in an annealing furnace for high-temperature annealing treatment, the peak temperature of the annealing is 888-892°C, the annealing time is 120 min, and the environmental gas source is N2. Under the action of the high temperature of the annealing, the boron element in the p+ implantation layer 500 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form a first p+ polysilicon layer 501 and a second p+ polysilicon layer 502, wherein the doping concentration of the boron element in the first p+ polysilicon layer 501 is lower than that in the second p+ polysilicon layer 502. Under the action of the high temperature of the annealing, the phosphorus element in the n+ implantation layer 400 will dope the first intrinsic amorphous silicon layer 701 and the second intrinsic amorphous silicon layer 702 below, and finally form a first n+ polysilicon layer 401 and a second n+ polysilicon layer 402, wherein the doping concentration of the phosphorus element in the first n+ polysilicon layer 401 is lower than that in the second n+ polysilicon layer 402. The area not implanted by ions in the first intrinsic amorphous silicon layer 701 is converted into a first isolation layer 301 after the annealing, and the area not implanted by ions in the second intrinsic amorphous silicon layer 702 is converted into a second isolation layer 302 after the annealing. Thus, a double-layer tunneling polysilicon structure is formed on the back surface of the P-type crystalline silicon substrate 1. The battery structure after this step is shown in Figure 6 .

[0077] (7) The P-type crystalline silicon substrate 1 after step (6) is placed in a cleaning machine for cleaning and drying. After the cleaning, the mask 31 and the oxide layer generated in the annealing are completely removed. The battery structure after this step is shown in Figure 7 .

[0078] (8) An AlO x dielectric film 12 with a thickness of 4.5-5.5 nm is prepared on the front surface of the P-type crystalline silicon substrate 1 after step (7) by ALD (atomic layer deposition), and an AlO x dielectric film 11 with a thickness of 4.5-5.5 nm is prepared on the back surface by ALD (atomic layer deposition). Then, a SiN x dielectric film 13 with a thickness of 28-32 nm is first deposited on the front surface by PECVD, and then a SiO xDepositing a layer of SiN on the dielectric film 13 x O y Dielectric film 14, film thickness 48-52 nm; finally, AlO x Depositing a layer of SiN on the surface of the dielectric film 11 x Dielectric film 15, SiN x The thickness of the dielectric film 15 is 83-87 nm.

[0079] AlO on the front surface of the silicon substrate x Dielectric film 12, SiN x Dielectric film 13, SiN x O y The dielectric film 14 serves to passivate the front surface of the silicon substrate and reduce the reflection of light; AlO on the back surface of the silicon substrate x Dielectric film 11 and SiN x The dielectric film 15 serves to passivate the back surface of the silicon substrate, and the SiN x Dielectric film 15 also serves to protect the AlO x Dielectric film 11. The structure of the battery after this step is shown in Figure 8 .

[0080] (9) Printing a metal electrode 22 on the second n+ polysilicon layer 402 on the back surface of the P-type crystalline silicon substrate 1 after step (8) and printing a metal electrode 21 on the second p+ polysilicon layer 502 on the back surface by a screen printing method. The metal electrode 21 and the metal electrode 22 are silver. After printing, the P-type crystalline silicon substrate 1 is transferred into a belt sintering furnace for sintering to form an ohmic contact. The structure of the battery after this step is shown in Figure 9 . Thus, the preparation of the passivated contact back contact solar cell is completed.

[0081] The open circuit voltage of the solar cell prepared in this example is 746 mV, the current density is 41 mA / cm 2 , the fill factor is 85.5%, and the conversion efficiency of the battery is 26.15%.

[0082] Comparative Example 1

[0083] Comparative Example 1 differs from Example 1 in that, in step (4), only a first tunneling layer and a first intrinsic amorphous silicon layer are sequentially deposited on the back surface of the N-type crystalline silicon substrate 1, wherein the thickness of the first tunneling layer is 1-1.5 nm, the thickness of the first intrinsic amorphous silicon layer is 115-125 nm, the initial doping concentration is the same as in Example 1, and the other auxiliary materials used are the same as in Example 1.

[0084] The open circuit voltage of the solar cell prepared in Comparative Example 1 is 742 mV, the current density is 42 mA / cm 2, the fill factor is 84.5%, and the conversion efficiency of the battery is 26.33%.

[0085] Comparative Example 2

[0086] Comparative Example 2 differs from Example 1 in that the thickness of the second intrinsic poly-silicon layer is 23-27 nm.

[0087] The open circuit voltage of the solar cell prepared in Comparative Example 2 is 735 mV, the current density is 41 mA / cm 2 , the fill factor is 82%, and the conversion efficiency of the battery is 24.7%.

[0088] Comparative Example 3

[0089] Comparative Example 3 differs from Example 1 in that the thickness of the second intrinsic poly-silicon layer is 115-125 nm.

[0090] The open circuit voltage of the solar cell prepared in Comparative Example 3 is 747 mV, the current density is 41.5 mA / cm 2 , the fill factor is 85.0%, and the conversion efficiency of the battery is 26.4%.

[0091] Comparative Example 4

[0092] Comparative Example 4 differs from Example 1 in that the implantation amount of boron and phosphorus is reduced, the implantation amount of boron is 1.5 x 10 14 ~ 2.5 x 10 14 cm -2 , and the implantation amount of phosphorus is 4.5 x 10 14 ~ 5.5 x 10 14 cm -2 .

[0093] The short circuit current density of the solar cell prepared in Comparative Example 4 is 42 mA / cm 2 , the open circuit voltage is 748 mV, which does not change much, the fill factor is reduced to 80%, and the conversion efficiency is reduced from 26.8% to 25.1%.

[0094] Comparative Example 5

[0095] Comparative Example 5 differs from Example 1 in that the implantation amount of boron and phosphorus is increased, the implantation amount of boron is 1.5 x 10 17 ~ 2.5 x 10 17 cm -2 , and the implantation amount of phosphorus is 4.5 x 10 17 ~ 5.5 x 10 17 cm -2 .

[0096] The short circuit current density of the solar cell prepared in Comparative Example 5 is 41 mA / cm 2The open circuit voltage is 740 mV, the fill factor remains unchanged at 85.5%, and the conversion efficiency of the battery is reduced from 26.8% to 25.9%.

[0097] As can be seen from the experimental data of Example 1 and Comparative Example 1, the open circuit voltage, fill factor and conversion efficiency of the solar cell with the double-layer tunneling oxide layer and the double-layer intrinsic polysilicon layer prepared by the method of the present application are all greater than those of the structure with the single-layer tunneling oxide layer and the single-layer intrinsic polysilicon layer. The main reason is that, in the structure with the single-layer tunneling oxide layer and the single-layer intrinsic polysilicon layer, the concentration difference of phosphorus and boron ions on both sides of the tunneling oxide layer is large during annealing, slow activation at low temperature and easy penetration of phosphorus atoms / boron atoms through the tunneling oxide layer at high temperature, thereby causing conflict in conductivity and passivation. Increasing the doping concentration helps the metal grid to draw out the current and reduce the contact resistance, but is easy to cause recombination, thereby reducing the short-circuit current; reducing the doping concentration helps to improve the passivation of the interface and protect the tunneling oxide layer, but is easy to cause the increase of the contact resistance, thereby affecting the output characteristics of the battery and reducing the conversion efficiency.

[0098] The thickness of the second intrinsic polysilicon layer also has a great influence on the performance of the solar cell of the present application. The main reason is that the metal paste is in direct contact with the second intrinsic polysilicon layer, and the metal paste will form an alloy with the polysilicon when sintered at high temperature. If the thickness of the second intrinsic polysilicon layer is low, part of the alloy layer will melt through the tunneling oxide layer and enter the first layer of polysilicon layer with low concentration, thereby increasing the contact resistance and affecting the output efficiency of the battery. In addition, the penetration of the alloy layer through the tunneling oxide layer and the high-concentration polysilicon layer will cause the loss of the open voltage of the battery and affect the output efficiency of the battery. If the thickness of the second intrinsic polysilicon layer is thick, it is easy to cause the increase of recombination in this region, thereby affecting the output characteristics of the battery voltage and current.

[0099] In the present application, the injection amount of boron and phosphorus has a great influence on the performance of the solar cell. The injection amount of boron in the present application is preferably 1.5×10 15 ~2.5×10 15 cm -2 , and the injection amount of phosphorus is preferably 4.5×10 15 ~5.5×10 15 cm -2 . If the injection amount is too low (10 14 cm -2 ), the injection amount at this time only maintains the passivation effect, which leads to the increase of the current transmission resistance of the battery, thereby causing the obvious deterioration of the output characteristics, which is reflected in the increase of the series resistance Rs and the decrease of the fill factor from 85.5% to 80%, thereby reducing the conversion efficiency of the battery. If the injection amount is too high (10 17 cm -2), at this time the increase of the injection amount will bring negative effects, i.e. Auger recombination increases, which affects the open circuit voltage and short circuit current, thus leading to the decrease of the conversion efficiency of the battery.

[0100] The above provided examples are not intended to limit the scope of the present application, nor are the described steps intended to limit the order of their execution. The obvious modifications made by those skilled in the art in light of the prior art knowledge, fall within the scope of protection defined by the claims of the present application.

Claims

1. A method for preparing a passivated contact back contact solar cell, characterized in that: The following steps are involved: (1) performing a texturing treatment on a crystalline silicon substrate to remove a damaged layer and form a pyramid light trapping structure, wherein the crystalline silicon substrate is an N-type crystalline silicon substrate or a P-type crystalline silicon substrate, the resistivity of the crystalline silicon substrate is 0.3 to 10 Ω·cm, and the thickness of the crystalline silicon substrate is 50 to 300 μm; (2) depositing a mask layer on the front surface of the crystalline silicon substrate treated in step (1); (3) placing the crystalline silicon substrate treated in step (2) in a polishing solution so that the back surface is etched into a polished surface, wherein the polishing solution comprises at least one of heated NaOH, KOH, and TMAH solutions, the heating temperature is 75-85° C., and the etching time is 50-120 s; (4) depositing a first tunneling oxide layer, a first intrinsic amorphous silicon layer, a second tunneling oxide layer, and a second intrinsic amorphous silicon layer in sequence on the back surface of the crystalline silicon substrate after etching in step (3); (5) Phosphorus implantation and boron implantation are performed on the back surface of the crystalline silicon substrate treated in step (4) by ion implantation to form an n+ implantation region and a p+ implantation region, respectively, with a gap left between the n+ implantation region and the p+ implantation region; (6) placing the crystalline silicon substrate after the treatment in step (5) into an annealing furnace for high-temperature annealing treatment. Under the action of high-temperature annealing, the boron element in the p+ implantation region and the phosphorus element in the n+ implantation region respectively dope the first intrinsic amorphous silicon layer with boron and dope the second intrinsic amorphous silicon layer with phosphorus, thereby finally forming a first p+ polycrystalline silicon region and a second p+ polycrystalline silicon region as well as a first n+ polycrystalline silicon region and a second n+ polycrystalline silicon region, wherein the doping concentration of the boron element in the first p+ polycrystalline silicon region is lower than the doping concentration of the boron element in the second p+ polycrystalline silicon region, and the doping concentration of the phosphorus element in the first n+ polycrystalline silicon region is lower than the doping concentration of the phosphorus element in the second n+ polycrystalline silicon region; (7) placing the crystalline silicon substrate treated in step (6) into a cleaning machine for cleaning and drying, so that the mask layer and the oxide layer generated during annealing are completely removed; (8) forming a passivation anti-reflection layer and a passivation layer on the front surface and the back surface of the crystalline silicon substrate treated in step (7); (9) Printing a metal silver electrode on the back surface of the crystalline silicon substrate treated in step (8) by screen printing. After printing, the crystalline silicon substrate is transferred to a belt sintering furnace for sintering to form an ohmic contact.

2. The preparation method according to claim 1, characterized in that The mask layer in step (2) includes SiO2, SiN x 、SiN x O y At least one of the methods, wherein the mask layer is deposited by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition, and the thickness of the mask layer is 20-100 nm.

3. The preparation method according to claim 1, characterized in that The first tunneling oxide layer described in step (4) is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the first tunneling layer is 0.8~3nm; the deposition method of the first intrinsic amorphous silicon layer includes at least one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and plasma-enhanced chemical vapor deposition. The thickness of the first intrinsic amorphous silicon layer is 10~30nm; the second tunneling oxide layer is SiO2, and the deposition method includes one of high-temperature thermal oxidation, nitric acid oxidation, ozone oxidation, and CVD deposition. The thickness of the second tunneling layer is 0.8~3nm; the deposition method of the second intrinsic amorphous silicon layer includes at least one of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, and plasma-enhanced chemical vapor deposition. The thickness of the second intrinsic amorphous silicon layer is 50~80nm.

4. The preparation method according to claim 1, characterized in that In step (5), two ion sources are used to implant phosphorus and boron, respectively. When implanting phosphorus or boron, a mask fixture is set between the back surface of the silicon wafer and the ion source to selectively implant boron ions or phosphorus ions, wherein the mask fixture is made of graphite.

5. The preparation method according to claim 1, characterized in that In step (5), when boron is injected, a linear opening is set on the mask fixture, the width of the linear opening is 1950~2050um, and the dose of boron injection is 0.5×10 15 cm -2 ~3×10 15 cm -2 After the implantation is completed, a patterned p+ implantation layer is formed on the second intrinsic amorphous silicon layer; when phosphorus implantation is performed, a linear opening is set on the mask fixture, and the width of the linear opening is 1950~2050um, 3×10 15 cm -2 ~8×10 15 cm -2 After the implantation is completed, a patterned n+ implantation layer is formed on the second intrinsic amorphous silicon layer; the p+ implantation layer and the n+ implantation layer do not directly contact each other, and an area not implanted by ions is left between them.

6. The preparation method according to claim 1, characterized in that In step (6), the peak annealing temperature is 800-1100°C, the annealing time is 30-200 min, and the ambient gas source is N2 and / or O2.

7. The preparation method according to claim 1, characterized in that The passivation anti-reflection layer in step (8) comprises AlO deposited on the front surface of the crystalline silicon substrate in sequence. x Dielectric film, SiN x Dielectric film and / or SiN x O y dielectric film, the AlO x The dielectric film is deposited by plasma enhanced chemical vapor deposition or atomic layer deposition, with a film thickness of 3 to 10 nm. x Dielectric film or SiN x O y The dielectric film is deposited by plasma enhanced chemical vapor deposition. x The thickness of the dielectric film is 5~30nm, SiN x O y The thickness of the dielectric film is 40~80nm.

8. The preparation method according to claim 1, characterized in that The passivation layer in step (8) comprises AlO x Dielectric film and SiN x dielectric film, the SiN x The dielectric film is deposited by plasma enhanced chemical vapor deposition. x The thickness of the dielectric film is 50~90nm.

9. A passivated back-contact solar cell prepared by the preparation method according to any one of claims 1 to 8, wherein the solar cell comprises a crystalline silicon substrate, a passivation anti-reflection layer on the front side of the crystalline silicon substrate, and the passivation anti-reflection layer is sequentially composed of a first AlO x Dielectric film, first SiN x Dielectric film and / or SiN x O y The back of the crystalline silicon substrate is composed of a first tunneling layer, a first polysilicon layer, a second tunneling layer, a second polysilicon layer, a passivation layer and a metal electrode from the inside to the outside. The passivation layer is composed of a second AlO x Dielectric film and second SiN x dielectric film, the metal electrode is a silver electrode; wherein, The first polysilicon layer includes a first n+ polysilicon region, a first p+ polysilicon region and a first isolation region, the second polysilicon layer includes a second n+ polysilicon region, a second p+ polysilicon region and a second isolation region, and the doping concentration of the boron element in the first p+ polysilicon region is lower than the doping concentration of the boron element in the second p+ polysilicon region, and the doping concentration of the phosphorus element in the first n+ polysilicon region is lower than the doping concentration of the phosphorus element in the second n+ polysilicon region.

10. The passivated contact back contact solar cell according to claim 9, characterized in that: The first AlO x Dielectric film and second AlO x The thickness of the dielectric film is 3~10nm. The first SiN x The thickness of the dielectric film is 5~30nm, and the SiN x O y The thickness of the dielectric film is 40-80 nm, and the second SiN x The thickness of the dielectric film is 50~90nm.

Images