High-reliability LED chip, its preparation method, and display screen

Abstract

The present invention relates to the technical field of light-emitting diode manufacturing, and particularly to a high-reliability LED chip, a preparation method thereof, and a display screen. The preparation method includes: providing an epitaxial wafer; forming a conductive step and an etching groove; forming a first passivation layer and a second passivation layer; patterning the second passivation layer so that the second passivation layer covers the side wall of the etching groove and extends a first preset distance L1 along the bottom wall of the conductive step and a second preset distance L2 along the bottom wall of the etching groove; forming a third passivation layer; opening holes and forming a first electrode and a second electrode. Wherein, the deposition rates of the third passivation layer and the first passivation layer are the same and less than the deposition rate of the second passivation layer. L1≥1.5μm, L2≥1.5μm; implementing the present invention can improve the reliability of the LED chip.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diode manufacturing, and particularly to a high-reliability LED chip, a preparation method thereof, and a display screen. Background Art

[0002] In recent years, the display screen market based on red, green, and blue LED chips has expanded rapidly, with strong demand. Such LED chips for display screens need to be used under outdoor conditions in different regions and environments, which poses relatively high requirements for their high-temperature resistance performance. Further, as the LED chips for display screens are gradually miniaturized, more and more LED chips are integrated in a single display screen device, and their heat generation is also increasing, which further poses higher requirements for the high-temperature resistance performance of a single LED chip.

[0003] The high-temperature and high-humidity resistance performance of an LED chip mainly depends on the insulating protective film on its surface, which is generally one or a combination of at least two of an Al2O3 film, a SiN x film, and a SiO2 film. For the currently most widely used SiO2 film, it is generally prepared by the PECVD method. In order to optimize the high-temperature and high-humidity resistance performance of the SiO2 film, it is often required to have a relatively high density. Therefore, a relatively low deposition rate is generally used for deposition to increase the crystal size, crystal quality, and improve the film density. At the same time, a high film density also means higher film transparency and higher light extraction efficiency. However, when the grain size of the SiO2 film is relatively large, it is difficult to form a good bond with the etched sidewall, that is, there will be a gap between the two, which causes moisture to enter the interior of the LED chip from the gap during high-temperature and high-humidity use, resulting in chip failure. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-reliability LED chip and a preparation method thereof, which have strong high-temperature and high-humidity resistance performance and high reliability.

[0005] To solve the above technical problem, the present invention provides a preparation method of a high-reliability LED chip, which includes the following steps:

[0006] (1) Provide an epitaxial wafer; wherein, the epitaxial wafer includes a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked on the substrate;

[0007] (2) Remove the second semiconductor layer, the active layer, and the first semiconductor layer in a preset area on the epitaxial wafer to form a conductive step; the included angle between the sidewall of the conductive step and the surface of the epitaxial wafer is α1;

[0008] (3) Remove the conductive steps in the preset area on the epitaxial wafer obtained in step (2) to form an etching groove; the included angle between the side wall of the etching groove and the surface of the epitaxial wafer is α2, and α2 > α1;

[0009] (4) Deposit a first passivation layer on the epitaxial wafer obtained in step (3) at a first deposition rate;

[0010] (5) Deposit a second passivation layer on the first passivation layer at a second deposition rate; the second deposition rate is greater than the first deposition rate;

[0011] (6) Pattern the second passivation layer so that the second passivation layer covers the side wall of the etching groove and extends a first preset distance L1 along the bottom wall of the conductive step and a second preset distance L2 along the bottom wall of the etching groove to obtain an intermediate; wherein, L1 ≥ 1.5 μm, L2 ≥ 1.5 μm;

[0012] (7) Deposit a third passivation layer on the intermediate at a first deposition rate, the third passivation layer covers the first passivation layer and the second passivation layer; and the thickness of the third passivation layer is greater than the thickness of the first passivation layer;

[0013] (8) Form a first electrode hole penetrating through the third passivation layer and the second passivation layer on the conductive step, and form a second electrode hole penetrating through the third passivation layer and the second passivation layer on the second semiconductor layer;

[0014] (9) Form a first electrode and a second electrode, the first electrode is electrically connected to the first semiconductor layer through the first electrode hole, and the second electrode is electrically connected to the second semiconductor layer through the second electrode hole.

[0015] As an improvement of the above technical solution, the first passivation layer, the second passivation layer, and the third passivation layer are all SiO2 layers and are all deposited by PECVD method; and / or

[0016] The first deposition rate is 1.5 - 2.5 Å / s; the second deposition rate is 3 - 5 Å / s.

[0017] As an improvement of the above technical solution, the deposition temperature of the second passivation layer is lower than the deposition temperature of the first passivation layer;

[0018] The flow ratio of SiH4 to N2O during the deposition of the second passivation layer is greater than the flow ratio of SiH4 to N2O during the deposition of the first passivation layer;

[0019] The RF power during the deposition of the second passivation layer is less than the RF power during the deposition of the first passivation layer.

[0020] As an improvement of the above technical solution, the process conditions for depositing the first passivation layer include: RF power of 80 - 100 W, SiH4 flow rate of 60 - 100 sccm, N2O flow rate of 1800 - 2000 sccm, and temperature of 270 - 300 °C.

[0021] As an improvement of the above technical solution, the process conditions for depositing the second passivation layer include: RF power of 60 - 80 W, SiH4 flow rate of 120 - 200 sccm, N2O flow rate of 1000 - 1800 sccm, and temperature of 80 - 120 °C.

[0022] As an improvement of the above technical solution, the process conditions for depositing the third passivation layer include: RF power of 80 - 100 W, SiH4 flow rate of 60 - 100 sccm, N2O flow rate of 1800 - 2000 sccm, and temperature of 270 - 300 °C.

[0023] As an improvement of the above technical solution, the thickness of the second passivation layer is greater than the sum of the thicknesses of the first passivation layer and the third passivation layer.

[0024] As an improvement of the above technical solution, the first electrode and the second electrode both include a Cr layer, an Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer, and an Au layer that are stacked in sequence;

[0025] The thickness of the Cr layer is 30 - 50 Å, the thickness of the Al layer is 1200 - 2000 Å, the thickness of the first Ti layer is 1000 - 2000 Å, the thickness of the first Pt layer is 1000 - 2000 Å, the thickness of the second Ti layer is 1000 - 2000 Å, the thickness of the second Pt layer is 1000 - 2000 Å, and the thickness of the Au layer is 15000 - 20000 Å.

[0026] Correspondingly, the present invention also discloses a high - reliability LED chip, which is prepared by the preparation method of the above high - reliability LED chip.

[0027] Correspondingly, the present invention also discloses a display screen, which includes the above high - reliability LED chip.

[0028] Implementing the present invention has the following beneficial effects:

[0029] In the method for preparing a highly reliable LED chip according to an embodiment of the present invention, a first passivation layer obtained by deposition at a low deposition rate, a second passivation layer obtained by deposition at a high deposition rate, and a third passivation layer obtained by deposition at a low deposition rate are sequentially provided on the sidewall of the etching groove at a large inclination angle. Moreover, both sides of the second passivation layer extend a preset distance along the bottom wall of the conductive step and the bottom wall of the etching groove respectively. This greatly optimizes the connection effect between the first passivation layer and the sidewall of the etching groove, effectively prevents the first passivation layer from separating from the sidewall of the etching groove under high temperature and high humidity conditions, and improves the reliability of the LED chip. At the same time, the first passivation layer and the third passivation layer are sequentially covered on the sidewall of the conductive step at a small inclination angle, which can play a good passivation role and ensure sufficient transparency, improving the light extraction efficiency of the LED chip and the luminous efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 FIG. is a schematic structural diagram of an epitaxial wafer after step S3 in an embodiment of the present invention;

[0031] Figure 2 FIG. is a schematic structural diagram of an epitaxial wafer after step S4 in an embodiment of the present invention;

[0032] Figure 3 FIG. is a schematic structural diagram of an intermediate obtained after step S6 in an embodiment of the present invention;

[0033] Figure 4 FIG. is a schematic structural diagram of an intermediate after step S7 in an embodiment of the present invention;

[0034] Figure 5 FIG. is a schematic structural diagram of a highly reliable LED chip obtained after step S9 in an embodiment of the present invention;

[0035] In the figure, 1 is an epitaxial wafer, 11 is a substrate, 12 is a first semiconductor layer, 13 is an active layer, 14 is a second semiconductor layer, 15 is a conductive step, 151 is the sidewall of the conductive step, 16 is an etching groove, 161 is the sidewall of the etching groove, 2 is a transparent conductive layer, 3 is a first passivation layer, 4 is a second passivation layer, 41 is a first electrode hole, 42 is a second electrode hole, 5 is a third passivation layer, 6 is a first electrode, and 7 is a second electrode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] To make the objectives, technical solutions and advantages of this application more clear and understandable, the following further details this application in conjunction with the accompanying drawings and embodiments. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain this application and should not be construed as a limitation to this application. In addition, it should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0037] In the description of this application, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to this application.

[0038] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, "a plurality" means two or more unless otherwise specifically defined.

[0039] The present invention discloses a method for preparing a highly reliable LED chip, which comprises the following steps:

[0040] S1: Provide an epitaxial wafer;

[0041] Among them, the epitaxial wafer 1 includes a substrate 11 and an epitaxial layer. Among them, the epitaxial layer includes a first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14 that are sequentially stacked on the substrate 11. The substrate 11 is a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. The first semiconductor layer 12 can be an N-type GaN layer, an N-type AlGaN layer, an N-type GaAs layer, but is not limited thereto. The active layer 13 can be an InGaN-GaN type MQW layer, an InGaN-AlGaN type MQW layer, or an AlGaN-AlGaN type MQW layer, but is not limited thereto. The second semiconductor layer 14 can be a P-type GaN layer, a P-type AlGaN layer, a P-type GaAs layer, but is not limited thereto.

[0042] Preferably, in an embodiment of the present invention, the epitaxial layer may further include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer that are common in the art, but is not limited thereto.

[0043] S2: Remove the second semiconductor layer, the active layer, and the first semiconductor layer within a preset area on the epitaxial wafer to form a conductive step;

[0044] Specifically, a mask (such as a photoresist layer, a SiO2 layer, etc.) can be formed on the epitaxial wafer 1 obtained in step S1 first, and then the second semiconductor layer 14, the active layer 13, and a part of the first semiconductor layer 12 in the preset area are removed by wet etching or dry etching to form a conductive step 15, but this is not limited thereto.

[0045] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S1. After patterning it by exposure and development, the inductively coupled plasma etching process (ICP) is used to etch away the second semiconductor layer 14, the active layer 13, and a part of the first semiconductor layer 12 to obtain a conductive step 15.

[0046] Specifically, referring to Figure 1 , the included angle α1 between the sidewall 151 of the conductive step and the surface of the epitaxial wafer 1 ranges from 20° to 50°. In the present invention, the inclination angle of the sidewall 151 of the conductive step is relatively small, which is convenient for the first passivation layer 3 and the third passivation layer 5 formed at a low deposition rate to form a good bond thereon, thereby achieving saturation of sidewall dangling bonds, reducing leakage channels and non-radiative recombination centers, and improving the luminous efficiency and reliability of the LED chip. It should be noted that the inclination angle of the sidewall 151 of the traditional conductive step reaches 60° to 90°.

[0047] Preferably, in some embodiments, step S2 includes:

[0048] S21: Etch the epitaxial wafer obtained in step S1 to form a conductive step;

[0049] S22: Form a transparent conductive layer on the epitaxial wafer obtained in step S21;

[0050] Among them, the transparent conductive layer 2 can be a common ITO layer, IZO layer, AZO layer, ATO layer, or FTO layer in the art, but this is not limited thereto. Preferably, the transparent conductive layer 2 is an ITO layer. The thickness of the transparent conductive layer 2 is 5 - 150 nm, preferably 50 - 150 nm.

[0051] The transparent conductive layer 2 can be formed by processes such as magnetron sputtering method, electron beam evaporation method, etc., but this is not limited thereto. Preferably, in one embodiment, after the transparent conductive layer 2 is formed, it is annealed. The annealing temperature is 500°C - 600°C, and the annealing time is 3 min - 10 min. By annealing, its light transmittance can be optimized, and the ohmic contact between it and the second semiconductor layer 14 can be optimized.

[0052] S23: Etch away the transparent conductive layer in the preset area and retain the transparent conductive layer on the second semiconductor layer;

[0053] Specifically, a mask (such as a photoresist layer, a SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S22, and then the transparent conductive layer 2 in a preset area can be removed by wet etching or dry etching, leaving only the transparent conductive layer 2 on the second semiconductor layer 14, but not limited thereto.

[0054] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S22. After exposure and development to pattern it, the transparent conductive layer 2 in the preset area is etched away using an etching solution, and then the photoresist layer is removed.

[0055] S3: Remove the conductive steps in the preset area on the epitaxial wafer obtained in step S2 to form an etching groove;

[0056] Specifically, a mask (such as a photoresist layer, a SiO2 layer, etc.) can be first formed on the epitaxial wafer 1 obtained in step S2, and then the conductive steps 15 in the preset area are removed by wet etching or dry etching to form an etching groove 16 exposing the substrate 11, but not limited thereto.

[0057] Preferably, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S2. After exposure and development to pattern it, the conductive steps 15 are etched by ICP process to form an etching groove 16.

[0058] Specifically, the included angle between the sidewall 161 of the etching groove and the surface of the epitaxial wafer 1 is α2, and α2 > α1. Specifically, the value range of α2 is 70° - 90°. In the present invention, the inclination angle of the sidewall 161 of the etching groove is relatively large, which can reduce the occupation of the light-emitting area of the LED chip and improve the light-emitting efficiency. At the same time, by subsequently covering the second passivation layer 4 on the sidewall 16 of the etching groove, the sidewall 161 of the etching groove can also be effectively passivated, ensuring that the LED chip has better reliability.

[0059] S4: Deposit a first passivation layer on the epitaxial wafer obtained in step S3 at a first deposition rate;

[0060] Among them, referring to Figure 2 , the first passivation layer 3 can be made of one or several of SiO2, Al2O3, SiN x , SiO x N y , but not limited thereto. The thickness of the first passivation layer 3 is 200 - 1500 Å, exemplarily 300 Å, 400 Å, 600 Å, 800 Å, 1100 Å or 1400 Å, but not limited thereto. Preferably, it is 300 - 1000 Å.

[0061] Among them, the first passivation layer 3 can be deposited by PECVD, ALD or MOCVD, but not limited thereto.

[0062] Preferably, in some embodiments, the first passivation layer 3 is a SiO2 layer deposited by PECVD. The deposition process conditions include: RF power of 80 - 100 W, SiH4 flow rate of 60 - 100 sccm, N2O flow rate of 1800 - 2000 sccm, and temperature of 270 - 300 °C. Based on these process conditions, the deposition rate of the first passivation layer 3 can be controlled to 1.5 - 2.5 Å / s, thereby effectively improving the density and light transmittance of the first passivation layer 3, and enhancing the passivation effect on positions such as the sidewall 151 of the conductive step.

[0063] S5: Deposit a second passivation layer on the first passivation layer at a second deposition rate;

[0064] Among them, the second passivation layer 4 can be made of one or more of SiO2, Al2O3, SiN x , SiO x N y , but not limited thereto. The thickness of the second passivation layer 4 is 800 - 3500 Å, exemplarily 900 Å, 1400 Å, 1900 Å, 2300 Å, 2700 Å or 3100 Å, but not limited thereto. Preferably it is 1000 - 2000 Å.

[0065] Among them, the second passivation layer 4 can be deposited by PECVD, ALD or MOCVD, but not limited thereto. The second deposition rate is greater than the first deposition rate to form a looser second passivation layer 4 on the first passivation layer 3, which will introduce tensile stress, prompting the first passivation layer 3 to better adhere to the sidewall 161 of the etching groove with a larger inclination angle, thereby enhancing the high-temperature and high-humidity resistance and improving the reliability of the LED chip. It should be noted that the first passivation layer 3 deposited at a lower deposition rate is mainly under compressive stress, which drives the first passivation layer 3 to separate from the surface of the epitaxial wafer 1, especially from the surface of the sidewall 161 of the etching groove with a larger inclination angle. By introducing the second passivation layer 4 with a higher deposition rate, tensile stress is introduced, which can effectively balance the compressive stress, and thus make the first passivation layer 3 adhere more tightly to the sidewall 161 of the etching groove, improving the reliability of the LED chip.

[0066] Preferably, in some embodiments, the second passivation layer 4 is a SiO2 layer deposited by PECVD. The deposition temperature of the second passivation layer 4 is lower than that of the first passivation layer 3, which can reduce the breaking and decomposition of Si - H bonds and increase the tensile stress. The flow rate ratio of SiH4 to N2O during the deposition of the second passivation layer 4 is greater than that during the deposition of the first passivation layer 3 to weaken the densification of the SiO2 network, inhibit the formation of large grains, and at the same time promote the formation of Si - H bonds and increase the tensile stress. The RF power during the deposition of the second passivation layer 4 is less than that during the deposition of the first passivation layer 3.

[0067] More specifically, the process conditions for depositing the second passivation layer 4 include: RF power of 80 - 100 W, SiH4 flow rate of 60 - 100 sccm, N2O flow rate of 1800 - 2000 sccm, and temperature of 270 - 300 °C. Based on these process conditions, the deposition rate of the second passivation layer 4 can be controlled to 3 - 5 Å / s, thereby effectively improving the adhesion of the first passivation layer 3 to the sidewall 161 of the etching groove and enhancing the reliability of the LED chip.

[0068] S6: Pattern the second passivation layer to obtain an intermediate.

[0069] Specifically, in some embodiments, a photoresist layer is first formed on the epitaxial wafer 1 obtained in step S5. After patterning it by exposure and development, the inductively coupled plasma etching process (ICP) is used to etch and remove the second passivation layer 4 in a preset area. Specifically, referring to Figure 3 , after removal, the second passivation layer 4 covers the sidewall 161 of the etching groove, its top extends a first preset distance L1 along the bottom wall of the conductive step 15, and its bottom extends a second preset distance L2 along the bottom wall of the etching groove 16. L1 ≥ 1.5 μm, L2 ≥ 1.5 μm. With the second passivation layer 4 of this structure, the combination of the first passivation layer 3 and the sidewall 161 of the etching groove can be greatly optimized, enhancing the reliability. It should be noted that in traditional LED chips, the inclination angles of the sidewall 151 of the conductive step and the sidewall 161 of the etching groove are not very different, both being 60° - 90°. In the present invention, the angles between the two are quite different. One is the sidewall 151 of the conductive step with a small inclination angle, which strengthens the connection with the first passivation layer 3. Therefore, there is no need to further provide a second passivation layer 4 with a porous structure above it to avoid the second passivation layer 4 reducing the light extraction efficiency. Second, the sidewall 161 of the etching groove with a large inclination angle is adopted, and the second passivation layer 4 is provided thereon. This not only expands the light-emitting area but also ensures the reliability of the LED chip.

[0070] More specifically, L1 is 1.5 - 2.5 μm, and L2 is 1.8 - 3 μm.

[0071] Preferably, in some embodiments, the thickness of the second passivation layer 4 is greater than the sum of the thicknesses of the first passivation layer 3 and the third passivation layer 5. Based on this embodiment, the reliability of the LED chip can be further improved.

[0072] S7: Deposit the third passivation layer on the intermediate obtained in step S6 at a first deposition rate.

[0073] Among them, referring to Figure 4 , the third passivation layer 5 can be composed of SiO2, Al2O3, SiN x , SiO x Ny made of one or more of the following, but not limited thereto.

[0074] Among them, the thickness of the third passivation layer 5 is greater than that of the first passivation layer 3. Specifically, the thickness of the third passivation layer 5 is 300 - 1500 Å, and exemplarily it is 300 Å, 400 Å, 600 Å, 800 Å, 1100 Å or 1400 Å, but not limited thereto. Preferably it is 500 - 1200 Å.

[0075] Among them, the third passivation layer 5 can be deposited by PECVD, ALD or MOCVD, but not limited thereto.

[0076] Preferably, in some embodiments, the third passivation layer 5 is a SiO2 layer, which is deposited by PECVD method. The deposition process conditions include: RF power is 80 - 100 W, SiH4 flow rate is 60 - 100 sccm, N2O flow rate is 1800 - 2000 sccm, and the temperature is 270 - 300 °C. Based on these process conditions, the deposition rate of the third passivation layer 5 can be controlled to 1.5 - 2.5 Å / s, thereby effectively improving the density and light transmittance of the third passivation layer 5, enhancing the passivation effect, and enhancing the reliability of the LED chip.

[0077] S8: Form a first electrode hole penetrating the third passivation layer and the second passivation layer on the conductive step, and form a second electrode hole penetrating the third passivation layer and the second passivation layer on the second semiconductor layer;

[0078] Specifically, in some embodiments, first form a photoresist layer on the epitaxial wafer 1 obtained in step S5. After patterning it by exposure and development, use inductively coupled plasma etching process (ICP) to etch away the first passivation layer 3 and the second passivation layer 4 in the preset area to form the first electrode hole 41 and the second electrode hole 42. The bottom of the first electrode hole 41 exposes the first semiconductor layer 12, and the bottom of the second electrode hole 42 exposes the second semiconductor layer 14 or the transparent conductive layer 2.

[0079] S9: Form the first electrode and the second electrode;

[0080] Specifically, the first electrode and the second electrode can be formed by PVD or evaporation process, but not limited thereto. The first electrode and the second electrode can be formed simultaneously or step by step, but not limited thereto. Among them, referring to Figure 5 , the first electrode 6 is electrically connected to the first semiconductor layer 12 through the first electrode hole 41, and the second electrode 7 is electrically connected to the second semiconductor layer 14 through the second electrode hole 42.

[0081] Specifically, both the first electrode 6 and the second electrode 7 are made of one or several of Al, Cr, Ti, Ni, Pt, and Au, but are not limited thereto. Preferably, in some embodiments, both the first electrode 6 and the second electrode 7 include a Cr layer, an Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer, and an Au layer stacked in sequence; the thickness of the Cr layer is 30-50 Å, the thickness of the Al layer is 1200-2000 Å, the thickness of the first Ti layer is 1000-2000 Å, the thickness of the first Pt layer is 1000-2000 Å, the thickness of the second Ti layer is 1000-2000 Å, the thickness of the second Pt layer is 1000-2000 Å, and the thickness of the Au layer is 15000-20000 Å.

[0082] In summary, in the method for manufacturing a high-reliability LED chip in this embodiment, a first passivation layer 3 obtained by low deposition rate deposition, a second passivation layer 4 obtained by high deposition rate deposition, and a third passivation layer 5 obtained by low deposition rate deposition are sequentially covered on the sidewall 161 of the etching groove at a large inclination angle, and both sides of the second passivation layer 4 extend a preset distance along the bottom wall of the conductive step and the bottom wall of the etching groove respectively, which greatly optimizes the connection effect between the first passivation layer 3 and the sidewall 161 of the etching groove, effectively prevents it from separating from the sidewall of the etching groove under high temperature and high humidity conditions, and improves the reliability of the LED chip. At the same time, a first passivation layer 3 and a third passivation layer 5 are sequentially covered on the sidewall 151 of the conductive step at a small inclination angle, which can play a good passivation role and ensure sufficient transparency, improve the light extraction efficiency of the LED chip, and improve the luminous efficiency of the LED chip.

[0083] Specifically, based on the technical solution in this embodiment, the high temperature and high humidity aging failure duration can reach more than 2000 h, and the maximum can reach 3250 h. For traditional LED chips (the inclination angles of the sidewalls of the conductive step and the etching groove are both 75°, and only the first passivation layer 3 and the third passivation layer 5 are formed), it can only reach about 680 h. Specifically, the aging process is as follows: the prepared LED chip is subjected to high temperature and high humidity aging, and the reverse current of the LED chip is tested every 24 hours. The test reverse voltage is 10 V, and when the reverse current value is less than 0.5 μA, the LED chip is regarded as failed. Among them, the aging temperature is 85 °C and the aging humidity is 90%RH.

[0084] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0085] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a high-reliability LED chip, characterized in that: The following steps are involved: (1) Providing an epitaxial wafer; wherein the epitaxial wafer comprises a substrate and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate; (2) removing the second semiconductor layer, the active layer and the first semiconductor layer in a preset area on the epitaxial wafer to form a conductive step; the angle between the side wall of the conductive step and the surface of the epitaxial wafer is α1; (3) removing the conductive step in a predetermined area on the epitaxial wafer obtained in step (2) to form an etched groove; the angle between the sidewall of the etched groove and the surface of the epitaxial wafer is α2, α2>α1; (4) depositing a first passivation layer on the epitaxial wafer obtained in step (3) at a first deposition rate; (5) depositing a second passivation layer on the first passivation layer at a second deposition rate; the second deposition rate is greater than the first deposition rate; (6) patterning the second passivation layer so that the second passivation layer covers the sidewalls of the etching groove and extends a first preset distance L1 along the bottom wall of the conductive step and a second preset distance L2 along the bottom wall of the etching groove, to obtain an intermediate; wherein L1 ≥ 1.5 μm, L2 ≥ 1.5 μm; (7) depositing a third passivation layer on the intermediate body at a first deposition rate, wherein the third passivation layer covers the first passivation layer and the second passivation layer; and the thickness of the third passivation layer is greater than the thickness of the first passivation layer; (8) forming a first electrode hole on the conductive step that penetrates the third passivation layer and the second passivation layer, and forming a second electrode hole on the second semiconductor layer that penetrates the third passivation layer and the second passivation layer; (9) A first electrode and a second electrode are formed, wherein the first electrode is electrically connected to the first semiconductor layer through the first electrode hole, and the second electrode is electrically connected to the second semiconductor layer through the second electrode hole.

2. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The first passivation layer, the second passivation layer, and the third passivation layer are all SiO2 layers, and are deposited by PECVD method; and / or The first deposition rate is 1.5-2.5 Å / s; the second deposition rate is 3-5 Å / s.

3. The method for preparing a high-reliability LED chip according to claim 2, characterized in that: The deposition temperature of the second passivation layer is lower than the deposition temperature of the first passivation layer; The flow ratio of SiH4 to N2O during the deposition of the second passivation layer is greater than the flow ratio of SiH4 to N2O during the deposition of the first passivation layer; The RF power during the deposition of the second passivation layer is less than the RF power during the deposition of the first passivation layer.

4. The method for preparing a high-reliability LED chip according to claim 2, characterized in that: The process conditions for depositing the first passivation layer include: RF power of 80-100 W, SiH4 flow rate of 60-100 sccm, N2O flow rate of 1800-2000 sccm, and temperature of 270-300°C.

5. The method for preparing a high-reliability LED chip according to claim 4, characterized in that: The process conditions for depositing the second passivation layer include: RF power of 60-80 W, SiH4 flow rate of 120-200 sccm, N2O flow rate of 1000-1800 sccm, and temperature of 80-120°C.

6. The method for preparing a high-reliability LED chip according to claim 5, characterized in that: The process conditions for depositing the third passivation layer include: RF power of 80-100 W, SiH4 flow rate of 60-100 sccm, N2O flow rate of 1800-2000 sccm, and temperature of 270-300°C.

7. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The thickness of the second passivation layer is greater than the sum of the thickness of the first passivation layer and the thickness of the third passivation layer.

8. The method for preparing a high-reliability LED chip according to claim 1, characterized in that: The first electrode and the second electrode each include a Cr layer, an Al layer, a first Ti layer, a first Pt layer, a second Ti layer, a second Pt layer and an Au layer stacked in sequence; The thickness of the Cr layer is 30~50Å, the thickness of the Al layer is 1200~2000Å, the thickness of the first Ti layer is 1000~2000Å, the thickness of the first Pt layer is 1000~2000Å, the thickness of the second Ti layer is 1000~2000Å, the thickness of the second Pt layer is 1000~2000Å, and the thickness of the Au layer is 15000~20000Å.

9. A high reliability LED chip, characterized in that: The LED chip is prepared by the method for preparing a high-reliability LED chip as described in any one of claims 1 to 8.

10. A display screen, characterized in that: Comprising the high-reliability LED chip as claimed in claim 9.

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