Display apparatus and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate including an emission area and a sensing area; a light emitting element on the substrate and overlapping the emission region; a lower bank layer having a lower opening defining the emission region, the lower bank layer including a first conductive layer and a second conductive layer on the first conductive layer; a light receiving element on the lower bank layer and overlapping the sensing region; and an upper bank layer including an upper opening defining the sensing region, in which the light emitting element and the light receiving element are located at different layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0142430 filed in the Korean Intellectual Property Office on October 23, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] A display device displays data visually. A display device may include a substrate divided into a display area and a peripheral area. In the display area, scan lines and data lines insulated from each other may be formed. A plurality of pixels may be included in the display area. In addition, the display area may include thin film transistors corresponding to the plurality of pixels, respectively, and pixel electrodes electrically connected to the thin film transistors, respectively. In addition, the display area may include a counter electrode shared by the plurality of pixels. The peripheral area may include various wiring lines configured to transmit electrical signals to the display area, a scan driver, a data driver, a controller, and a pad unit.

[0005] The use of display devices has been diversified. Therefore, various designs have been tried to improve the quality of display devices. Summary of the invention

[0006] One or more embodiments provide a display device capable of displaying an image with excellent quality at an improved resolution.The embodiments set forth herein are examples, and the scope of the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments presented in the disclosure.

[0008] According to one or more embodiments, a display device includes: a substrate including an emission area and a sensing area; a light-emitting element on the substrate and overlapping the emission area; a lower embankment layer having a lower opening defining the emission area, the lower embankment layer including a first conductive layer and a second conductive layer on the first conductive layer; a light-receiving element on the lower embankment layer and overlapping the sensing area; and an upper embankment layer including an upper opening defining the sensing area, wherein the light-emitting element and the light-receiving element are located at different layers.

[0009] The light emitting element may include: a pixel electrode in the emission region; an emission layer in the lower opening of the lower bank layer and overlapping the pixel electrode; and a counter electrode in the lower opening of the lower bank layer and overlapping the emission layer.

[0010] The light receiving element may include: a sensing electrode in the sensing region; an active layer in the upper opening of the upper bank layer and overlapping the sensing electrode; and a sensing counter electrode on the active layer and an entire surface of the substrate.

[0011] The light emitting element and the upper bank layer overlap each other, and the light receiving element and the lower bank layer overlap each other.

[0012] The second conductive layer may include a tip extending toward the lower opening from a point where a bottom surface of the second conductive layer and a side surface of the first conductive layer contact each other.

[0013] The lower bank layer may further include a groove between lower openings arranged adjacent to each other among the plurality of lower openings.

[0014] The lower bank layer may include a first portion and a second portion spaced apart from each other, with the trench interposed between the first portion and the second portion, wherein the first portion and the second portion may be electrically disconnected from each other.

[0015] The second portion may include a side of the lower bank layer facing the lower opening, and the first portion may be located between second portions facing different lower openings among the plurality of lower openings among the plurality of second portions.

[0016] The second portion may surround the first portion in a plan view, and the first portion may have an island shape.

[0017] The first portion may be electrically connected to the light receiving element, and the second portion may be electrically connected to the light emitting element.

[0018] The counter electrode of the light emitting element may directly contact a side surface of the second portion facing the lower opening.

[0019] The display device may further include an emission driving circuit electrically connected to the light emitting element and a sensing driving circuit electrically connected to the light receiving element, wherein the emission driving circuit and the sensing driving circuit may be driven independently of each other.

[0020] The sensing drive circuit and the light receiving element may be electrically connected to each other via the first portion.

[0021] The display device may further include a bridging electrode between the sensing drive circuit and the lower bank layer, wherein a lower surface of the first conductive layer of the first portion may contact the bridging electrode, and an upper surface of the second conductive layer of the first portion may contact the sensing electrode of the light receiving element.

[0022] The bridge electrode may be located at the same layer as a pixel electrode of the light emitting element, and the bridge electrode may include the same material as the pixel electrode.

[0023] The display device may further include a lower encapsulation layer covering the light emitting element and an upper encapsulation layer covering the light receiving element, wherein the lower encapsulation layer and the upper encapsulation layer may be located at different layers.

[0024] The lower encapsulation layer may encapsulate the light emitting element, and may include a plurality of encapsulation layer units spaced apart from each other.

[0025] Each of the plurality of encapsulation layer units may include: a first lower inorganic encapsulation layer on the light emitting element and extending to cover the lower opening; a lower organic encapsulation layer on the first lower inorganic encapsulation layer and filling the lower opening; and a second lower inorganic encapsulation layer on the lower organic encapsulation layer.

[0026] The first lower inorganic encapsulating layer and the second lower inorganic encapsulating layer may contact each other on the lower bank layer.

[0027] The upper encapsulation layer may include: a first upper inorganic encapsulation layer on the light receiving element and extending to cover the upper opening; an upper organic encapsulation layer on the first upper inorganic encapsulation layer; and a second upper inorganic encapsulation layer on the upper organic encapsulation layer.

[0028] The first upper inorganic encapsulating layer and the second upper inorganic encapsulating layer may be spaced apart from each other with the upper organic encapsulating layer interposed therebetween.

[0029] The first upper inorganic encapsulation layer may be integrally formed as one body over the entire surface of the substrate.

[0030] The first upper inorganic encapsulation layer may encapsulate each of the plurality of light receiving elements, and the plurality of first upper inorganic encapsulation layers may be spaced apart from each other.

[0031] The upper organic encapsulation layer may include a plurality of air cavities, wherein the plurality of air cavities may overlap the light receiving element.

[0032] According to one or more embodiments, a method for manufacturing a display device includes: forming a pixel electrode on a substrate; forming a lower bank layer on the pixel electrode, the lower bank layer including a first conductive layer and a second conductive layer on the first conductive layer; forming a lower opening overlapping the pixel electrode in the lower bank layer; forming an emission layer overlapping the pixel electrode in the lower opening of the lower bank layer; forming a counter electrode overlapping the emission layer in the lower opening of the lower bank layer; forming a sensing electrode on the lower bank layer; forming an upper bank layer on the sensing electrode; forming an upper opening overlapping the sensing electrode in the upper bank layer; forming an active layer arranged in the upper opening of the upper bank layer and overlapping the sensing electrode; and forming a sensing counter electrode on the upper bank layer and the active layer.

[0033] The method may further include forming a trench in the lower bank layer between lower openings arranged adjacent to each other among the plurality of lower openings, wherein the trench may be formed through the same etching process as the lower openings.

[0034] The lower bank layer may include a first portion and a second portion spaced apart from each other with the trench interposed therebetween, wherein the first portion may contact the sensing electrode, and the second portion may contact the counter electrode.

[0035] The method may further include forming a lower encapsulation layer between the forming of the counter electrode and the forming of the sensing electrode, wherein the forming of the lower encapsulation layer may include: forming a first lower inorganic encapsulation layer on the counter electrode and the lower bank layer; forming a lower organic encapsulation layer on the first lower inorganic encapsulation layer to fill the lower opening; and forming a second lower inorganic encapsulation layer on the lower organic encapsulation layer.

[0036] The method may further include: etching a portion of the first lower inorganic encapsulation layer on the lower bank layer between the forming of the lower organic encapsulation layer and the forming of the second lower inorganic encapsulation layer; and etching a portion of the second lower inorganic encapsulation layer on the lower bank layer between the forming of the second lower inorganic encapsulation layer and the forming of the sensing electrode.

[0037] The sensing electrode may be electrically connected to the lower bank layer through a contact hole formed by etching a portion of each of the first lower inorganic encapsulation layer and the second lower inorganic encapsulation layer.

[0038] The method may further include: after forming the sensing counter electrode, forming an upper encapsulation layer, wherein the forming of the upper encapsulation layer may include: forming a first upper inorganic encapsulation layer on the sensing counter electrode over the entire surface of the substrate; forming an upper organic encapsulation layer on the first upper inorganic encapsulation layer, the upper organic encapsulation layer filling the upper opening and on the upper bank layer; and forming a second upper inorganic encapsulation layer on the upper organic encapsulation layer.

[0039] The method may further include forming a plurality of air cavities in the upper organic encapsulation layer between the forming of the upper organic encapsulation layer and the forming of the second upper inorganic encapsulation layer, wherein the plurality of air cavities overlap the sensing electrode.

[0040] The method may further include: before forming the pixel electrode, forming an emission driving circuit electrically connected to the light emitting element including the pixel electrode, the emission layer and the counter electrode; and forming a sensing driving circuit electrically connected to the light receiving element including the sensing electrode, the active layer and the sensing counter electrode.

[0041] The method may further include forming a bridge electrode between the sensing driving circuit and the lower bank layer, wherein the bridge electrode may be formed through a same deposition process as the pixel electrode.

[0042] The sensing driving circuit may be electrically connected to the sensing electrode via the bridge electrode and the lower bank layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other aspects and features of the embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0044] Figure 1A and Figure 1B is a schematic perspective view of a display device according to one or more embodiments;

[0045] Figure 2A and Figure 2B is an equivalent circuit diagram schematically illustrating a light emitting diode corresponding to one pixel of a display device and a pixel circuit electrically connected to the light emitting diode according to one or more embodiments;

[0046] Figure 3 is a schematic cross-sectional view of a portion of a display device according to one or more embodiments;

[0047] Figure 4 is a schematic plan view of a portion of a display device according to one or more embodiments;

[0048] Figure 5 is a display device according to one or more embodiments Figure 4 A schematic cross-sectional view of a portion taken along line II' of FIG.

[0049] FIG. 6A to FIG. 6O is a cross-sectional view schematically illustrating a state according to a process of manufacturing a display device according to one or more embodiments;

[0050] Figure 7 is a display device according to one or more embodiments Figure 4 A schematic cross-sectional view of a portion taken along line II' of FIG.

[0051] Figure 8 is a display device according to one or more embodiments Figure 4 Schematic cross-sectional view of a portion taken along line II'. DETAILED DESCRIPTION

[0052] Now will refer to embodiment in detail, the example of embodiment is shown in the accompanying drawings, in which the same reference numerals always refer to the same elements. In this respect, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following only describes the embodiment with reference to the accompanying drawings to illustrate the various aspects of the present disclosure. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the present disclosure, the statement "at least one of a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or their variants.

[0053] The present disclosure may be variously modified and may have many embodiments, specific embodiments of which are shown in the drawings and further described in the detailed description. The effects, aspects and features of the embodiments of the present disclosure and the methods for achieving these effects, aspects and features will become clear with reference to the embodiments described in detail below in conjunction with the drawings. However, the present disclosure is not limited to the embodiments described herein and may be implemented in various forms.

[0054] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and when describing with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals, and their repeated description will be omitted.

[0055] In the following embodiments, the terms “first”, “second”, etc. are not intended to be limiting but are used to distinguish one component from another.

[0056] In the following embodiments, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0057] In the following embodiments, the terms “including” or “having” and the like are intended to imply the presence of the features or components described, and do not exclude the possibility of adding one or more other features or components.

[0058] In the following embodiments, when a portion of a membrane, region, component, etc. is above or on top of another portion, this includes not only when the portion is directly on top of the other portion, but also when other membranes, regions, components, etc. are arranged between the portion and the other portion.

[0059] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each configuration are arbitrarily shown in the drawings for the purpose of explanation, and the present disclosure is not necessarily limited to those shown.

[0060] In some embodiments, a particular process sequence may be performed in a different order than described. For example, two processes described in succession may be performed in parallel (eg, substantially simultaneously), or may be performed in a reverse order than described.

[0061] In the following embodiments, when layers, regions, or components are connected to each other, the layers, regions, or components may be directly connected to each other, or another layer, another region, or another component may be interposed between the layers, regions, or components, and thus the layers, regions, or components may be indirectly connected to each other. For example, in the following embodiments, when layers, regions, or components are electrically connected to each other, the layers, regions, or components may be directly electrically connected to each other, or another layer, another region, or another component may be interposed between the layers, regions, or components, and thus the layers, regions, or components may be indirectly electrically connected to each other.

[0062] Figure 1A and Figure 1B is a schematic perspective view of a display device 1 according to one or more embodiments.

[0063] Reference Figure 1A and Figure 1B , the display device 1 may include a display area DA and a non-display area NDA arranged outside the display area DA along an edge or periphery of the display area DA. The display area DA may display an image via a plurality of pixels P arranged in the display area DA. The non-display area NDA in which the image is not displayed is arranged outside the display area DA and may be around the display area DA (or may completely surround the display area DA). A driver for providing an electrical signal or power to the display area DA, etc. may be arranged in the non-display area NDA. A pad (i.e., an area to which an electronic component or a printed circuit board (PCB), etc. may be electrically connected) may be arranged in the non-display area NDA.

[0064] In one or more embodiments, although Figure 1A The display area DA is shown to have a polygonal planar shape (eg, a rectangle in which the length in the x direction is smaller than the length in the y direction), but the present disclosure is not limited thereto. Figure 1B As shown in , the display area DA may have a polygonal planar shape (eg, a rectangle in which the length in the y direction is smaller than the length in the x direction). Figure 1A and Figure 1B The display area DA is shown to be approximately rectangular in planar shape, but the present disclosure is not limited thereto. In one or more embodiments, the display area DA may have various planar shapes such as other N-gons (where N is a natural number of 3 or more), circles, or ellipses. Figure 1A and Figure 1B The display area DA is shown to have a planar shape in which a corner portion of the display area DA includes a vertex at which a straight line and another straight line intersect, but in another embodiment, the display area DA may have a polygonal planar shape having rounded corner portions.

[0065] In the following description, for the convenience of explanation, the case where the display device 1 is a smart phone is described, but the display device 1 according to one or more embodiments is not limited thereto. The display device 1 can be applied to various products, including not only portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs), but also televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices, etc. In addition, the display device 1 according to one or more embodiments can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device 1 according to one or more embodiments can be applied to a dashboard of a vehicle and a central information display (CID) arranged in a central dashboard or instrument panel of the vehicle, an in-vehicle mirror display instead of a side mirror of the vehicle, and a display screen arranged on the back of the front seat as entertainment for rear seat passengers of the vehicle.

[0066] Figure 2A and Figure 2B is an equivalent circuit diagram schematically illustrating a light emitting diode corresponding to one pixel of a display device and a pixel circuit PC electrically connected to the light emitting diode according to one or more embodiments.

[0067] Reference Figure 2A, the light emitting element ED may be electrically connected to a pixel circuit PC that may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. A pixel electrode (e.g., an anode) of the light emitting element ED may be electrically connected to the first transistor T1, a counter electrode (e.g., a cathode) of the light emitting element ED may be electrically connected to an auxiliary wiring line VSL, and a voltage corresponding to the common voltage ELVSS may be received via the auxiliary wiring line VSL.

[0068] The second transistor T2 is configured to transmit the data signal Dm input through the data line DL to the first transistor T1 in response to the scan signal Sgw input through the scan line GW.

[0069] The storage capacitor Cst is connected to the second transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the second transistor T2 and a driving voltage ELVDD supplied through the driving voltage line PL.

[0070] The first transistor T1 is connected to the driving voltage line PL, the storage capacitor Cst and the light emitting element ED, and may be configured to control a driving current I flowing from the driving voltage line PL into the light emitting element ED. d , the driving current I d The light emitting element ED can be driven by the driving current I d Emits light of a specific brightness.

[0071] although Figure 2A A case is shown in which the pixel circuit PC includes two transistors and one storage capacitor, but the present disclosure is not limited thereto.

[0072] Reference Figure 2B , the pixel circuit PC may include seven transistors and two capacitors.

[0073] The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a boost capacitor Cbt. In another embodiment, the pixel circuit PC may not include the boost capacitor Cbt. The pixel electrode (e.g., anode) of the light emitting element ED may be electrically connected to the first transistor T1 via the sixth transistor T6, the counter electrode (e.g., cathode) may be connected to the auxiliary wiring line VSL, and a voltage corresponding to the common voltage ELVSS may be received via the auxiliary wiring line VSL.

[0074] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N-channel metal oxide semiconductor field effect transistors (MOSFET) (NMOS), and the remaining transistors may be P-channel MOSFETs (PMOS). In one or more embodiments, as Figure 2B As shown in , the third transistor T3 and the fourth transistor T4 may be N-channel MOSFETs (NMOS), and the remaining transistors may be P-channel MOSFETs (PMOS). For example, the third transistor T3 and the fourth transistor T4 may be N-channel MOSFETs (NMOS) including oxide-based semiconductor materials, and the remaining transistors may be P-channel MOSFETs (PMOS) including silicon-based semiconductor materials. In another embodiment, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-channel MOSFETs (NMOS), and the remaining transistors may be P-channel MOSFETs (PMOS).

[0075] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, the storage capacitor Cst and the boost capacitor Cbt may be connected to the signal line. The signal line may include a scan line GW, an emission control line EM, a compensation gate line GC, a first initialization gate line GI1, a second initialization gate line GI2 and a data line DL. The pixel circuit PC may be electrically connected to a voltage line, for example, a driving voltage line PL, a first initialization voltage line VL1 and a second initialization voltage line VL2.

[0076] The first transistor T1 may be a driving transistor. The first gate electrode of the first transistor T1 is connected to the storage capacitor Cst, the first electrode of the first transistor T1 is electrically connected to the driving voltage line PL via the fifth transistor T5, and the second electrode of the first transistor T1 may be electrically connected to the pixel electrode (e.g., anode) of the light emitting element ED via the sixth transistor T6. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode, and the other may be a drain electrode. The first transistor T1 may be configured to supply a driving current I to the light emitting element ED according to a switching operation of the second transistor T2. d .

[0077] The second transistor T2 may be a switching transistor. The second gate electrode of the second transistor T2 is connected to the scan line GW, the first electrode of the second transistor T2 is connected to the data line DL, and the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1 and is electrically connected to the driving voltage line PL via the fifth transistor T5. One of the first electrode and the second electrode of the second transistor T2 may be a source electrode, and the other may be a drain electrode. The second transistor T2 may be configured to be turned on in response to a scan signal Sgw received via the scan line GW, and to perform a switching operation of transmitting a data signal Dm transmitted via the data line DL to the first electrode of the first transistor T1.

[0078] The third transistor T3 may be a compensation transistor for compensating for the threshold voltage of the first transistor T1. The third gate electrode of the third transistor T3 is connected to the compensation gate line GC. The first electrode of the third transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst and is connected to the first gate electrode of the first transistor T1 via the node connection line 166. The first electrode of the third transistor T3 may be connected to the fourth transistor T4. The second electrode of the third transistor T3 is connected to the second electrode of the first transistor T1 and is electrically connected to the pixel electrode (e.g., anode) of the light emitting element ED via the sixth transistor T6. One of the first electrode and the second electrode of the third transistor T3 may be a source electrode, and the other may be a drain electrode.

[0079] The third transistor T3 can be configured to be turned on in response to the compensation signal Sgc received via the compensation gate line GC and electrically connect the first gate electrode and the second electrode (e.g., the drain electrode) of the first transistor T1 to each other, thereby connecting the first transistor T1 in a diode manner (e.g., the first transistor T1 can be connected in a diode manner).

[0080] The fourth transistor T4 may be a first initialization transistor that initializes the first gate electrode of the first transistor T1. The fourth gate electrode of the fourth transistor T4 is connected to the first initialization gate line GI1. The first electrode of the fourth transistor T4 is connected to the first initialization voltage line VL1. The second electrode of the fourth transistor T4 may be connected to the lower electrode CE1 of the storage capacitor Cst, the first electrode of the third transistor T3, and the first gate electrode of the first transistor T1. One of the first electrode and the second electrode of the fourth transistor T4 may be a source electrode, and the other may be a drain electrode. The fourth transistor T4 may be configured to be turned on in response to a first initialization signal Sgi1 received via the first initialization gate line GI1, and to send a first initialization voltage Vint to the first gate electrode of the first transistor T1, thereby performing an initialization operation to initialize the voltage of the first gate electrode of the first transistor T1.

[0081] The fifth transistor T5 may be an operation control transistor. A fifth gate electrode of the fifth transistor T5 is connected to the emission control line EM, a first electrode of the fifth transistor T5 is connected to the driving voltage line PL, and a second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2. One of the first electrode and the second electrode of the fifth transistor T5 may be a source electrode, and the other may be a drain electrode.

[0082] The sixth transistor T6 may be an emission control transistor. A sixth gate electrode of the sixth transistor T6 is connected to the emission control line EM, a first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the second electrode of the third transistor T3, and a second electrode of the sixth transistor T6 is electrically connected to the second electrode of the seventh transistor T7 and a pixel electrode (e.g., an anode) of the light emitting element ED. One of the first electrode and the second electrode of the sixth transistor T6 may be a source electrode, and the other may be a drain electrode.

[0083] The fifth transistor T5 and the sixth transistor T6 may be configured to be turned on in parallel (eg, simultaneously) in response to an emission control signal Sem received via the emission control line EM and transmit the driving voltage ELVDD to the light emitting element ED, thereby causing the driving current I d Flows into the light emitting element ED.

[0084] The seventh transistor T7 may be a second initialization transistor that initializes the pixel electrode (e.g., anode) of the light emitting element ED. The seventh gate electrode of the seventh transistor T7 is connected to the second initialization gate line GI2. The first electrode of the seventh transistor T7 is connected to the second initialization voltage line VL2. The second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 and the pixel electrode (e.g., anode) of the light emitting element ED. The seventh transistor T7 may be configured to be turned on in response to a second initialization signal Sgi2 received via the second initialization gate line GI2, and to send the second initialization voltage Vaint to the pixel electrode (e.g., anode) of the light emitting element ED, thereby initializing the pixel electrode of the light emitting element ED.

[0085] In one or more embodiments, the second initialization gate line GI2 may be used as a subsequent scan line. For example, the second initialization gate line GI2 connected to the seventh transistor T7 of the pixel circuit PC arranged in the i-th row may correspond to the scan line connected to the pixel circuit PC arranged in the (i+1)-th row, where "i" is a natural number greater than 0. In one or more embodiments, the second initialization gate line GI2 may be used as an emission control line EM. For example, the emission control line EM may be electrically connected to the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0086] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst is connected to the first gate electrode of the first transistor T1, and the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may store charges corresponding to the difference between the voltage of the first gate electrode of the first transistor T1 and the driving voltage ELVDD.

[0087] The boosting capacitor Cbt may include a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 is connected to the second gate electrode of the second transistor T2 and the scan line GW, and the fourth electrode CE4 may be connected to the first electrode of the third transistor T3 and the node connection line 166. When the scan signal Sgw supplied via the scan line GW is turned off, the boosting capacitor Cbt may increase the voltage of the first node N1, and when the voltage of the first node N1 increases, the black gradation may be clearly expressed.

[0088] The first node N1 may be a region where the first gate electrode of the first transistor T1 , the first electrode of the third transistor T3 , the second electrode of the fourth transistor T4 , and the fourth electrode CE4 of the boosting capacitor Cbt are connected to each other.

[0089] In one or more embodiments, Figure 2B It is shown that the third transistor T3 and the fourth transistor T4 are N-channel MOSFETs (NMOS), and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-channel MOSFETs (PMOS). The first transistor T1 directly affects the brightness of the display device for displaying an image and is configured to include a semiconductor layer including polysilicon with high reliability, and therefore, a high-resolution display device can be realized.

[0090] although Figure 2B Some transistors are shown to be N-channel MOSFETs (NMOS) and the rest are P-channel MOSFETs (PMOS), but the disclosure is not limited thereto. In one or more embodiments, the pixel circuit PC may include three transistors, and the three transistors may all be N-channel MOSFETs (NMOS).

[0091] Figure 3 is a schematic cross-sectional view of a portion of a display device 1 according to one or more embodiments.

[0092] Reference Figure 3According to one or more embodiments, the display device 1 may include a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3, and a light receiving element PD. The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may emit light of different colors. For example, the first light emitting element ED1 may emit red light, the second light emitting element ED2 may emit green light, and the third light emitting element ED3 may emit blue light.

[0093] like Figure 3 As shown in , the display device 1 may have a function of sensing an object (e.g., a fingerprint of a finger F) in contact with the cover window CW. Among the light emitted from at least one of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3, at least a portion of the reflected light reflected from the fingerprint of the user may be re-incident to the light receiving element PD, and thus, the light receiving element PD may detect the reflected light. For example, the red light emitted by the first light emitting element ED1 may be reflected by the object in contact with the cover window CW and re-incident to the light receiving element PD, and thus, the light receiving element PD may detect the re-incident red light.

[0094] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 and the light receiving element PD may be disposed on different layers (e.g., at different layers). In one or more embodiments, the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be disposed on the substrate 100, and the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be encapsulated with the lower encapsulation layer 400. A plurality of light receiving elements PD may be disposed on the flat upper surface of the lower encapsulation layer 400, and a plurality of light receiving elements PD may be encapsulated with the upper encapsulation layer 600. Figure 3 As shown in , when the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3 and the light receiving element PD are arranged on different layers (for example, at different layers), the emission area of ​​each of the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3 can be increased, and therefore, the resolution of the display device 1 can be improved.

[0095] Figure 4 is a schematic plan view of a portion of a display device according to one or more embodiments. Specifically, Figure 4 yes Figure 1A For convenience, Figure 4 A plan view of the upper bank layer 117 is shown.

[0096] Reference Figure 4, the display device may include a plurality of light emitting elements and a plurality of light receiving elements PD. The plurality of light emitting elements may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3, and the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may emit light of different colors. For example, the first light emitting element ED1 may emit red light, the second light emitting element ED2 may emit green light, and the third light emitting element ED3 may emit blue light. The red light may be light belonging to a band of about 600nm to about 780nm, the green light may be light belonging to a band of about 495nm to about 600nm, and the blue light may be light belonging to a band of about 380nm to about 495nm. In one or more embodiments, the light receiving element PD may sense an object by detecting light emitted from the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 and reflected by the object. In one or more embodiments, the light receiving element PD may sense an object by detecting light emitted from a near-infrared light emitting unit and reflected by the object.

[0097] Each light emitting element ED may include a pixel electrode, a counter electrode, and an emission layer disposed between the pixel electrode and the counter electrode, and each light receiving element PD may include a sensing electrode, a sensing counter electrode, and an active layer disposed between the sensing electrode and the sensing counter electrode. Therefore, the first light emitting element ED1 may include a first pixel electrode 1210, the second light emitting element ED2 may include a second pixel electrode 2210, the third light emitting element ED3 may include a third pixel electrode 3210, and the light receiving element PD may include a sensing electrode 510. The first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 and the sensing electrode 510 may be arranged on the substrate 100 (see Figure 5 ) are spaced apart from each other on a plane. In this specification, “in a plan view” means a plane observed in a direction perpendicular to the substrate 100. That is, “A and B spaced apart from each other in a plan view” means “A and B spaced apart from each other when observed in a direction perpendicular to the substrate 100”.

[0098] The bank layer may be disposed on the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 or the sensing electrode 510, and may cover an edge of each of the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 or an edge of the sensing electrode 510. However, in one or more embodiments, the bank layer may include a lower bank layer 300 (see Figure 5 ) and the upper bank layer 117 (see Figure 5 ) double bank layer. As previously mentioned Figure 3As described, when the light emitting element ED and the light receiving element PD are disposed on different layers, the lower bank layer 300 may be disposed above the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210, and the upper bank layer 117 may be disposed above the sensing electrode 510. That is, the lower bank layer 300 may have a first lower opening LOP1 exposing a central portion of the first pixel electrode 1210, a second lower opening LOP2 exposing a central portion of the second pixel electrode 2210, and a third lower opening LOP3 exposing a central portion of the third pixel electrode 3210. Similarly, the upper bank layer 117 may have an upper opening UOP exposing a central portion of the sensing electrode 510.

[0099] although Figure 4 Although not shown in the figure, the emission layer that emits light can be respectively located in the first lower opening LOP1, the second lower opening LOP2 and the third lower opening LOP3 of the lower bank layer 300, and the active layer that detects light can be located in the upper opening UOP of the upper bank layer 117. The counter electrode can be arranged on the emission layer, and the sensing counter electrode can be arranged on the active layer. As described above, the structure in which the pixel electrode, the emission layer and the counter electrode are stacked can form a light-emitting element ED. In addition, as described above, the stacked structure including the sensing electrode, the active layer and the sensing counter electrode can form a light-receiving element PD. An opening in the lower bank layer 300 corresponds to a light-emitting element ED and can define an emission area. Alternatively, an opening in the upper bank layer 117 can correspond to a light-receiving element PD and define a sensing area SA.

[0100] For example, an emission layer emitting red light may be arranged in the first lower opening LOP1, and the first lower opening LOP1 may define a first emission area EA1. Similarly, an emission layer emitting green light may be arranged in the second lower opening LOP2, and the second lower opening LOP2 may define a second emission area EA2. An emission layer emitting blue light may be arranged in the third lower opening LOP3, and the third lower opening LOP3 may define a third emission area EA3. An active layer for detecting light may be arranged in the upper opening UOP, and the upper opening UOP may define a sensing area SA.

[0101] Therefore, the size of the area of ​​the first lower opening LOP1 is the same as the size of the area of ​​the first emission area EA1. In addition, the size of the area of ​​the second lower opening LOP2 is the same as the size of the area of ​​the second emission area EA2, and the size of the area of ​​the third lower opening LOP3 is the same as the size of the area of ​​the third emission area EA3. The size of the area of ​​the upper opening UOP is the same as the size of the area of ​​the sensing area SA.

[0102] When the substrate 100 is perpendicular to the substrate 100 (see Figure 5), each of the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 and the upper opening UOP may have a polygonal shape. In other words, when viewed in a direction perpendicular to the substrate 100 (z direction), each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 and the sensing area SA may have a polygonal shape. Figure 4 It is shown that when viewed in a direction (z direction) perpendicular to the substrate 100, each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the sensing area SA has a quadrilateral shape (specifically, a quadrilateral shape with rounded corners). However, the present disclosure is not limited thereto. For example, when viewed in a direction (z direction) perpendicular to the substrate 100, each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the sensing area SA may have a circular or elliptical shape.

[0103] Figure 5 is a display device 1 according to one or more embodiments. Figure 4 Schematic cross-sectional view of a portion taken along line II'.

[0104] Reference Figure 5 , the display device 1 may include a light emitting element ED, an emission driving circuit electrically connected to the light emitting element ED (i.e., a first emission driving circuit PC1, a second emission driving circuit PC2, and a third emission driving circuit PC3), a light receiving element PD, and a sensing driving circuit PC' electrically connected to the light receiving element PD. First, the emission driving circuit and the sensing driving circuit PC' may be formed on a substrate 100. The emission driving circuit may include a first emission driving circuit PC1 connected to the first light emitting element ED1, a second emission driving circuit PC2 connected to the second light emitting element ED2, and a third emission driving circuit PC3 connected to the third light emitting element ED3. The first emission driving circuit PC1, the second emission driving circuit PC2, the third emission driving circuit PC3, and the sensing driving circuit PC' may have the same structure. However, the first emission driving circuit PC1, the second emission driving circuit PC2, the third emission driving circuit PC3, and the sensing driving circuit PC' may be driven independently of each other. The first emission driving circuit PC1, the second emission driving circuit PC2, the third emission driving circuit PC3, and the sensing driving circuit PC' may each include as described above with reference to Figure 2A and Figure 2B In one or more embodiments, Figure 5The first transistor T1 , the sixth transistor T6 , and the storage capacitor Cst of each of the first, second, and third emission driving circuits PC1 , PC2 , and PC3 are shown, and the transistor TFT′ of each sensing driving circuit PC′ is shown.

[0105] The substrate 100 may include glass or a polymer resin. The substrate 100 may include a structure in which a base layer including a polymer resin and an inorganic barrier layer are stacked. The polymer resin may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, triacetyl cellulose (TAC) and / or cellulose acetate propionate (CAP).

[0106] The buffer layer 101 may be disposed on the upper surface of the substrate 100. The buffer layer 101 may prevent impurities from penetrating into the semiconductor layer of the transistor. The buffer layer 101 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and / or silicon oxide, and may be a single layer or multiple layers including the aforementioned inorganic insulating material.

[0107] The first transistor T1 may include a first semiconductor layer A1 on the buffer layer 101 and a first gate electrode G1 overlapping a channel region of the first semiconductor layer A1 in the z direction. The first semiconductor layer A1 may include a silicon-based semiconductor material (e.g., polycrystalline silicon). The first semiconductor layer A1 may include a channel region and a first region and a second region disposed at both sides of the channel region. The first region and the second region are regions including impurities having a higher concentration than impurities of the channel region, and any one of the first region and the second region may correspond to a source region, and the other may correspond to a drain region.

[0108] The sixth transistor T6 may include a sixth semiconductor layer A6 on the buffer layer 101 and a sixth gate electrode G6 overlapping the channel region of the sixth semiconductor layer A6 in the z direction. The sixth semiconductor layer A6 may include a silicon-based semiconductor material (e.g., polycrystalline silicon). The sixth semiconductor layer A6 may include a channel region and a first region and a second region arranged at both sides of the channel region. The first region and the second region are regions including impurities having a higher concentration than the impurities of the channel region, and any one of the first region and the second region may correspond to a source region, and the other may correspond to a drain region.

[0109] The first gate electrode G1 and the sixth gate electrode G6 may each include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti), etc., and may have a single-layer or multi-layer structure including the foregoing materials. A first gate insulating layer 103 for electrically insulating the first semiconductor layer A1 and the sixth semiconductor layer A6 may be arranged below the first gate electrode G1 and the sixth gate electrode G6, covering the buffer layer 101 and the semiconductor layer. The first gate insulating layer 103 may include an inorganic insulating material such as silicon nitride, silicon oxynitride and / or silicon oxide, and may be a single layer or a multilayer including the foregoing inorganic insulating material.

[0110] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 overlapping each other in the z direction. In one or more embodiments, the lower electrode CE1 of the storage capacitor Cst may include the first gate electrode G1. In other words, the first gate electrode G1 may include the lower electrode CE1 of the storage capacitor Cst. For example, the first gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst may be integrally formed.

[0111] The first interlayer insulating layer 105 may be disposed between the lower electrode CE1 and the upper electrode CE2 of the storage capacitor Cst, and may cover the first gate insulating layer 103 and the gate electrode. The first interlayer insulating layer 105 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0112] The upper electrode CE2 of the storage capacitor Cst may include a low-resistance conductive material such as Mo, Al, Cu, and / or Ti, and may have a single-layer or multi-layer structure including the foregoing materials.

[0113] The second interlayer insulating layer 107 may be disposed between the upper electrode CE2 of the storage capacitor Cst and the source electrode S1, and may cover the first interlayer insulating layer 105 and the upper electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 107 may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0114] A source electrode S1 and / or a drain electrode D1 electrically connected to the first semiconductor layer A1 of the first transistor T1 may be disposed on the second interlayer insulating layer 107. A source electrode S6 and / or a drain electrode D6 electrically connected to the sixth semiconductor layer A6 of the sixth transistor T6 may be disposed on the second interlayer insulating layer 107. The source electrodes S1 and S6 and / or the drain electrodes D1 and D6 may each include Al, Cu, and / or Ti, and may be a single layer or a multilayer including the foregoing materials.

[0115] The first organic insulating layer 109 may be disposed on the emission driving circuits PC1, PC2 and PC3 and the sensing driving circuit PC'. The first organic insulating layer 109 may include an organic insulating material such as acrylic resin, benzocyclobutene (BCB), polyimide and / or hexamethyldisiloxane (HMDSO).

[0116] The connection metals CM and CM' may be disposed on the first organic insulating layer 109. The connection metals CM and CM' may include Al, Cu, and / or Ti, and may be a single layer or a multilayer including the foregoing materials.

[0117] The second organic insulating layer 111 may be disposed between the connection metals CM and CM′ and the pixel electrode 210 (e.g., the pixel electrode 210 including the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210). The second organic insulating layer 111 may include an organic insulating material such as acrylic resin, BCB, polyimide, and / or HMDSO. Figure 5 In the described embodiments, the emission drive circuits PC1, PC2 and PC3 and the pixel electrode 210 are electrically connected to each other via the connection metal CM. However, according to one or more embodiments, the connection metal CM may be omitted, and one organic insulating layer may be located between the emission drive circuits PC1, PC2 and PC3 and the pixel electrode 210. Alternatively, three or more organic insulating layers may be located between the emission drive circuits PC1, PC2 and PC3 and the pixel electrode 210, and the emission drive circuits PC1, PC2 and PC3 and the pixel electrode 210 may be connected to each other via a plurality of connection metals. In addition, these embodiments may be similarly applied to the connection metal CM' that electrically connects the sensing drive circuit PC' to the bridge electrode BE to be described later.

[0118] Each of the first, second and third light emitting elements ED1, ED2 and ED3 electrically connected to the first, second and third emission driving circuits PC1, PC2 and PC3, respectively, may have a structure in which a pixel electrode, an emission layer and a counter electrode are stacked.

[0119] For example, the first light emitting element ED1 may include a first pixel electrode 1210, a first emission layer 1220, and a first pair of electrodes 1230. The first pixel electrode 1210 may be electrically connected to the first emission driving circuit PC1. The second light emitting element ED2 may include a second pixel electrode 2210, a second emission layer 2220, and a second pair of electrodes 2230. The second pixel electrode 2210 may be electrically connected to the second emission driving circuit PC2. The third light emitting element ED3 may include a third pixel electrode 3210, a third emission layer 3220, and a third pair of electrodes 3230. The third pixel electrode 3210 may be electrically connected to the third emission driving circuit PC3.

[0120] The pixel electrode 210 may be formed on the second organic insulating layer 111. The pixel electrode 210 may be a (semi) transparent electrode or a reflective electrode. When the pixel electrode 210 is a (semi) transparent electrode, the pixel electrode 210 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum-doped zinc oxide (AZO). When the pixel electrode 210 is a reflective electrode, the pixel electrode 210 may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof, and may include ITO, IZO, ZnO and / or In 2 O 3 The layer may be formed on the reflective layer. In one or more embodiments, the pixel electrode 210 may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked. The pixel electrode 210 may be electrically connected to the connection metal CM through a contact hole in the second organic insulating layer 111.

[0121] A bridge electrode BE that electrically connects the sensing driving circuit PC' to the light receiving element PD may also be formed on the second organic insulating layer 111. The bridge electrode BE may be disposed on the same layer (e.g., at the same layer) as the pixel electrode 210, and may include the same material as the pixel electrode 210. In one or more embodiments, the bridge electrode BE may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked. The bridge electrode BE may be electrically connected to the connection metal CM' through a contact hole in the second organic insulating layer 111.

[0122] The insulating layer 115 may be formed on the pixel electrode 210 and the bridging electrode BE. The insulating layer 115 may be disposed on the pixel electrode 210 and the bridging electrode BE to cover an outer portion of each of the pixel electrode 210 and the bridging electrode BE. For example, the insulating layer 115 may overlap the pixel electrode 210 and may be in direct contact with the upper surface of the second organic insulating layer 111 where the pixel electrode 210 does not exist. The insulating layer 115 may cover the side surface of each of the pixel electrode 210 and the bridging electrode BE. The insulating layer 115 may include an inorganic insulating material. Compared to a case where the insulating layer 115 includes an organic insulating material, when the insulating layer 115 includes an inorganic insulating material, quality degradation of the light emitting diode caused by gas emitted from the insulating layer including the organic insulating material during a process of manufacturing a display device may be prevented or reduced.

[0123] The insulating layer 115 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned inorganic insulating material. In one or more embodiments, the insulating layer 115 may have a two-layer structure including a silicon oxide layer and a silicon nitride layer. The thickness of the silicon oxide layer may be less than the thickness of the silicon nitride layer.

[0124] The insulating layer 115 may be disposed around the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210, and the bridge electrode BE (e.g., surround the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210, and the bridge electrode BE). Specifically, the insulating layer 115 may surround the pixel electrode 210 while including an opening that exposes a central portion of the pixel electrode 210. Similarly, the insulating layer 115 may surround the bridge electrode BE (e.g., surround the bridge electrode BE) while including an opening that exposes a central portion of the bridge electrode BE.

[0125] The first protective layer 113 may be formed between the pixel electrode 210 and the insulating layer 115. The first protective layer 113 may be deposited to overlap the pixel electrode 210, and then may be etched to expose the central portion of the pixel electrode 210, thereby leaving only a portion of the first protective layer 113. The first protective layer 113 may prevent the pixel electrode 210 from being damaged by a gas or liquid substance used in various etching processes or ashing processes included in the process of manufacturing the display device 1. The first protective layer 113 may include a conductive oxide such as ITO, IZO, indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), ZnO, aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO) and / or fluorine-doped tin oxide (FTO).

[0126] The lower bank layer 300 may be disposed on the insulating layer 115. The lower bank layer 300 may include a first conductive layer 310 and a second conductive layer 320 on the first conductive layer 310. The first conductive layer 310 and the second conductive layer 320 include conductive materials and may include different metals. For example, the first conductive layer 310 and the second conductive layer 320 may include metals having different etching selectivities. In one or more embodiments, the first conductive layer 310 may be a layer including Al, and the second conductive layer 320 may be a layer including Ti.

[0127] The thickness of the first conductive layer 310 may be greater than the thickness of the second conductive layer 320. In one or more embodiments, the thickness of the first conductive layer 310 may be approximately 5 times greater than the thickness of the second conductive layer 320. For example, the first conductive layer 310 may have a thickness of approximately 4000 angstroms. To date The second conductive layer 320 may have a thickness of about To date Thickness.

[0128] The lower bank layer 300 may have a first lower opening LOP1, a second lower opening LOP2, and a third lower opening LOP3 respectively overlapping the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210. Each of the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 may pass from the top surface of the lower bank layer 300 to the bottom surface of the lower bank layer 300, and may have an undercut cross-sectional structure. The side of the corresponding opening among the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 of the first conductive layer 310 facing the lower bank layer 300 may have a positive tapered shape, and may have an inclination angle greater than or equal to about 60° and less than about 90°. The second conductive layer 320 of the lower bank layer 300 may include a portion protruding toward the lower opening. Specifically, the second conductive layer 320 may include a tip extending from a point where a bottom surface of the second conductive layer 320 and a side surface of the first conductive layer 310 contact each other toward a corresponding one of the first, second, and third lower openings LOP1, LOP2, and LOP3.

[0129] In the display device 1 according to one or more embodiments, due to the structure of the lower bank layer 300 including the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 having an undercut structure, the emission layer 220 (for example, the emission layer 220 including the first emission layer 1220, the second emission layer 2220, and the third emission layer 3220) and the counter electrode 230 (for example, the counter electrode 230 including the first counter electrode 1230, the second counter electrode 2230, and the third counter electrode 3230) can be deposited without using a separate mask. Therefore, damage to the display device 1 caused by the mask can be prevented, and since an area for placing the mask is not required, the resolution can be improved.

[0130] Specifically, the emission layer 220 and the counter electrode 230 may be arranged in the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 to overlap with the pixel electrode 210. The emission layer 220 may overlap and contact with the inner portion of the pixel electrode 210, and the counter electrode 230 may overlap with the emission layer 220. The structure in which the pixel electrode 210, the emission layer 220, and the counter electrode 230 are stacked corresponds to a light emitting element ED as a light emitting diode (LED). The emission layer 220 may include a first emission layer 1220 arranged in the first lower opening LOP1, a second emission layer 2220 arranged in the second lower opening LOP2, and a third emission layer 3220 arranged in the third lower opening LOP3. The counter electrode 230 may include a first counter electrode 1230 disposed on the first emission layer 1220, a second counter electrode 2230 disposed on the second emission layer 2220, and a third counter electrode 3230 disposed on the third emission layer 3220.

[0131] The emission layer 220 may include a polymer or low-molecular organic material that emits light of a specific color (red, green, or blue). In one or more embodiments, the emission layer 220 may include an inorganic material or a quantum dot. In this case, the first emission layer 1220, the second emission layer 2220, and the third emission layer 3220 may emit light of different colors. The emission layer 220 may have a single stacked structure including a single emission layer or a series structure as a multi-stacked structure including a plurality of emission layers.

[0132] The emission layer 220 may overlap the pixel electrode 210 via the first, second, and third lower openings LOP1, LOP2, and LOP3 of the lower bank layer 300. Therefore, the width of the emission region of the light emitting element ED may be substantially the same as the widths of the first, second, and third lower openings LOP1, LOP2, and LOP3.

[0133] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a transparent layer (e.g., a semi-transparent layer) containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and / or an alloy thereof. Alternatively, the counter electrode 230 may also include a conductive material such as ITO, IZO, ZnO, and / or In on the transparent layer (e.g., semi-transparent layer) including the aforementioned materials. 2 O 3 A transparent conductive oxide (TCO) layer.

[0134] The first pair of electrodes 1230 arranged in the first lower opening LOP1, the second pair of electrodes 2230 arranged in the second lower opening LOP2, and the third pair of electrodes 3230 arranged in the third lower opening LOP3 may be spatially separated or spaced apart from each other. The first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may be electrically connected to each other, and the voltages supplied to the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may have the same voltage level. For example, the voltages supplied to the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may each have the same voltage level as the voltage (e.g., common voltage) provided by the auxiliary wiring line VSL. Each of the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may be electrically connected to the auxiliary wiring line VSL via the lower bank layer 300.

[0135] For example, the outer portion of the first pair of electrodes 1230 may be electrically connected to (e.g., directly contact) the side of the lower bank layer 300 facing the first lower opening LOP1 (e.g., the side of the first conductive layer 310), and since the lower bank layer 300 is electrically connected to a portion of the auxiliary wiring line VSL, the first pair of electrodes 1230 may receive a common voltage. Similarly, the outer portion of the second pair of electrodes 2230 and the outer portion of the third pair of electrodes 3230 may also directly contact the side of the lower bank layer 300 facing the second lower opening LOP2 and the third lower opening LOP3, respectively, and since the lower bank layer 300 is electrically connected to a portion of the auxiliary wiring line VSL, the second pair of electrodes 2230 and the third pair of electrodes 3230 may also receive a common voltage.

[0136] In one or more embodiments, the common layer may be arranged between the pixel electrode 210 and the emission layer 220 and / or between the emission layer 220 and the counter electrode 230. Specifically, the first common layer may be arranged between the pixel electrode 210 and the emission layer 220, and the second common layer may be arranged between the emission layer 220 and the counter electrode 230. The first common layer may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second common layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first common layer and the second common layer may each include an organic material.

[0137] In addition, in one or more embodiments, since the emission layer 220 and the counter electrode 230 are deposited in the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 through the undercut structure of the lower bank layer 300 without a mask, the emission layer 220 and the counter electrode 230 may be partially deposited on the lower bank layer 300. For example, a deposition material for forming the emission layer 220 and a deposition material for forming the counter electrode 230 may be used to form a dummy emission layer and a dummy counter electrode on the lower bank layer 300. The emission layer 220 and the dummy emission layer may include the same material and may be separated and spaced apart from each other, and the counter electrode 230 and the dummy counter electrode may include the same material and may be separated and spaced apart from each other.

[0138] In addition to the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3, the lower bank layer 300 may further include a trench TR. The trench TR may be arranged between the lower openings arranged adjacent to each other. For example, the trench TR may be arranged between the first lower opening LOP1 and the second lower opening LOP2 or between the second lower opening LOP2 and the third lower opening LOP3. In other words, the trench TR may be arranged between the light emitting elements ED arranged adjacent to each other.

[0139] The trench TR may have a shape similar to the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 passing through the lower bank layer 300. The trench TR may have a concave shape relative to the upper surface of the lower bank layer 300. In addition, the trench TR may have an undercut shape similar to the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3. A portion of the second conductive layer 320 of the lower bank layer 300 may include a tip protruding toward the trench TR. Because the trench TR may be formed by etching the first conductive layer 310 and the second conductive layer 320, the trench TR may expose the insulating layer 115. That is, the bottom surface of the trench TR may be substantially the same as the top surface of the insulating layer 115.

[0140] The lower bank layer 300 may be divided into a first portion P31 and a second portion P32 by a trench TR formed by etching a portion of the lower bank layer 300. The first portion P31 and the second portion P32 of the lower bank layer 300 may be arranged to be spaced apart from each other with the trench TR interposed between the first portion P31 and the second portion P32. Since the first portion P31 and the second portion P32 are separated and spaced apart from each other, the first portion P31 and the second portion P32 may not be electrically connected to each other.

[0141] The second portion P32 may be a portion of the side of the corresponding lower opening among the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 of the lower bank layer 300 facing the lower bank layer 300. The first portion P31 may be arranged between the second portions P32 facing different lower openings. For example, in a cross-sectional view in a direction perpendicular to the substrate 100, the first portion P31 may be arranged between the second portion P32 adjacent to the first lower opening LOP1 and the second portion P32 adjacent to the second lower opening LOP2. In addition, the trench TR and the second portion P32 may have a shape that surrounds (e.g., surrounds) the first portion P31 in a plan view. In this case, the first portion P31 may have an island shape.

[0142] As described above, the lower bank layer 300 may transmit the common voltage to the counter electrode 230. Since the counter electrode 230 is in direct contact with the side of the second portion P32 of the lower bank layer 300, the lower bank layer 300 that transmits the voltage to the counter electrode 230 may be the second portion P32. In other words, the second portion P32 of the lower bank layer 300 may be connected to the auxiliary wiring line VSL (see Figure 2A ), and the common voltage can be transmitted to the opposite electrode 230.

[0143] Because the first portion P31 separated from the second portion P32 by the trench TR is not electrically connected to the second portion P32, the first portion P31 can transmit another electrical signal to the light receiving element PD. In other words, the first portion P31 can be electrically connected to the light receiving element PD, and the second portion P32 can be electrically connected to the light emitting element ED.

[0144] Specifically, the first portion P31 can be used as a connection electrode that electrically connects the sensing drive circuit PC' to the light receiving element PD. Because the first portion P31 includes a first conductive layer 310 and a second conductive layer 320, each including a conductive material, the first portion P31 can be used as a connection electrode for transmitting a signal, which is different from a bank layer (or a pixel defining layer) that generally includes an inorganic insulating material or an organic insulating material. Specifically, the lower surface of the first conductive layer 310 of the first portion P31 can be in direct contact with the bridge electrode BE connected to the sensing drive circuit PC', and the upper surface of the second conductive layer 320 of the first portion P31 can be in contact with the sensing electrode 510 through the contact hole CNT1. Therefore, the signal output from the sensing drive circuit PC' can be transmitted to the sensing electrode 510 of the light receiving element PD via the bridge electrode BE and the first portion P31.

[0145] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be encapsulated by the lower encapsulation layer 400. The lower encapsulation layer 400 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the lower encapsulation layer 400 may include a first lower inorganic encapsulation layer 410 (for example, a first lower inorganic encapsulation layer 410 including a 1-1 lower inorganic encapsulation layer 1410, a 1-2 lower inorganic encapsulation layer 2410, and a 1-3 lower inorganic encapsulation layer 3410), a lower organic encapsulation layer 420 on the first lower inorganic encapsulation layer 410 (for example, a lower organic encapsulation layer 420 including a first lower organic encapsulation layer 1420, a second lower organic encapsulation layer 2420, and a third lower organic encapsulation layer 3420), and a second lower inorganic encapsulation layer 430 on the lower organic encapsulation layer 420 (for example, a second lower inorganic encapsulation layer 430 including a 2-1 lower inorganic encapsulation layer 1430, a 2-2 lower inorganic encapsulation layer 2430, and a 2-3 lower inorganic encapsulation layer 3430).

[0146] The first lower inorganic encapsulation layer 410 and the second lower inorganic encapsulation layer 430 may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first lower inorganic encapsulation layer 410 and the second lower inorganic encapsulation layer 430 may each include a single layer or multiple layers containing the aforementioned materials. The lower organic encapsulation layer 420 may include a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. In one or more embodiments, the lower organic encapsulation layer 420 may include acrylates. The lower organic encapsulation layer 420 may be formed by curing a monomer or applying a polymer. The lower organic encapsulation layer 420 may be transparent.

[0147] The first lower inorganic encapsulation layer 410 having relatively excellent step coverage may cover at least a portion of the inner surface of each of the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 of the lower bank layer 300 having an undercut structure and at least a portion of the inner surface of the trench TR. For example, the first lower inorganic encapsulation layer 410 may be continuously formed to overlap with the upper and side surfaces of the lower bank layer 300 and the upper surface of the counter electrode 230. The lower organic encapsulation layer 420 may be located on the first lower inorganic encapsulation layer 410, and may fill at least a portion of each of the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 of the lower bank layer 300 and at least a portion of the inner surface of the trench TR. The second lower inorganic encapsulation layer 430 may be disposed on the lower organic encapsulation layer 420.

[0148] In one or more embodiments, the lower encapsulation layer 400 may encapsulate each of the light emitting elements ED, and may include a plurality of encapsulation layer units arranged to be spaced apart from each other. Specifically, the lower encapsulation layer 400 may include a first encapsulation layer unit encapsulating the first light emitting element ED1, a second encapsulation layer unit encapsulating the second light emitting element ED2, and a third encapsulation layer unit encapsulating the third light emitting element ED3.

[0149] For example, the first encapsulation layer unit may include a 1-1 lower inorganic encapsulation layer 1410 covering the first light emitting element ED1, a first lower organic encapsulation layer 1420 filling the first lower opening LOP1, and a 2-1 lower inorganic encapsulation layer 1430 on the first lower organic encapsulation layer 1420. The second encapsulation layer unit may include a 1-2 lower inorganic encapsulation layer 2410 covering the second light emitting element ED2, a second lower organic encapsulation layer 2420 filling the second lower opening LOP2, and a 2-2 lower inorganic encapsulation layer 2430 on the second lower organic encapsulation layer 2420. The third encapsulation layer unit may include a 1-3 lower inorganic encapsulation layer 3410 covering the third light emitting element ED3, a third lower organic encapsulation layer 3420 filling the third lower opening LOP3, and a 2-3 lower inorganic encapsulation layer 3430 on the third lower organic encapsulation layer 3420.

[0150] Due to the contact hole CNT1 formed on the lower bank layer 300, the first encapsulation layer unit, the second encapsulation layer unit, and the third encapsulation layer unit may be arranged to be spaced apart from each other. The contact hole CNT1 may be a contact hole formed in a layer arranged between the lower bank layer 300 and the sensing electrode 510 to connect the sensing driving circuit PC' to the sensing electrode 510. Specifically, the first lower inorganic encapsulation layer 410 and the second lower inorganic encapsulation layer 430 may be separated from each other by etching a portion thereof to form the contact hole CNT1. For example, the first lower inorganic encapsulation layer 410 may include a 1-1 lower inorganic encapsulation layer 1410, a 1-2 lower inorganic encapsulation layer 2410, and a 1-3 lower inorganic encapsulation layer 3410, and the 1-1 lower inorganic encapsulation layer 1410, the 1-2 lower inorganic encapsulation layer 2410, and the 1-3 lower inorganic encapsulation layer 3410 are separated from each other by the contact hole CNT1. Similarly, the second lower inorganic encapsulation layer 430 may include a 2-1st lower inorganic encapsulation layer 1430 , a 2-2nd lower inorganic encapsulation layer 2430 , and a 2-3rd lower inorganic encapsulation layer 3430 , which are separated from one another by the contact hole CNT1 .

[0151] The lower organic encapsulation layer 420 may not be formed on the lower bank layer 300, but may be formed to fill only the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 and at least a portion of the inner surface of the trench TR. Therefore, the first lower inorganic encapsulation layer 410 and the second lower inorganic encapsulation layer 430 may directly contact each other on the lower bank layer 300.

[0152] Since the lower encapsulation layer 400 has the above-mentioned structure including a plurality of encapsulation layer units spaced apart from each other, a structure in which the corresponding light emitting element ED is sealed for each pixel unit can be formed. Since the lower encapsulation layer 400 can seal each light emitting element ED, even when defects such as dark spots occur due to penetration of contaminants from the outside, an effect of suppressing the increase of defects can be provided. Therefore, the display device 1 according to one or more embodiments can improve the resolution by using the lower bank layer 300 having an undercut structure, and can produce an image of excellent quality by sealing each light emitting element ED.

[0153] Return to reference Figure 5 , the light receiving element PD may be disposed on the lower encapsulation layer 400. As previously described, the light emitting element ED and the light receiving element PD may be disposed on different layers (e.g., at different layers). Since the light receiving element PD is arranged to overlap with the lower bank layer 300 as a non-emitting region, the emission region may be ensured and the resolution may be improved. The light receiving element PD may have a structure in which a sensing electrode 510, an active layer 520, and a sensing counter electrode 530 may be stacked.

[0154] The sensing electrode 510 may be disposed on the second lower inorganic encapsulation layer 430. The sensing electrode 510 may be arranged to overlap with the lower bank layer 300 and not overlap with the emission region of the light emitting element ED. The sensing electrode 510 may be connected to the first portion P31 of the lower bank layer 300 via a contact hole CNT1 passing through the first lower inorganic encapsulation layer 410 and the second lower inorganic encapsulation layer 430. Therefore, the light receiving element PD may be connected to the sensing driving circuit PC' via the first portion P31 and receive a signal.

[0155] The sensing electrode 510 may include the same material as the pixel electrode 210. The sensing electrode 510 may be a transparent electrode, a semi-transparent electrode, or a reflective electrode. When the sensing electrode 510 is a transparent electrode or a semi-transparent electrode, the sensing electrode 510 may include, for example, ITO, IZO, ZnO, In 2 O 3 , IGO and / or AZO. When the sensing electrode 510 is a reflective electrode, the sensing electrode 510 may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or a compound thereof, and may include ITO, IZO, ZnO and / or In 2 O 3 The layer may be formed on the reflective layer. In one or more embodiments, the sensing electrode 510 may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked.

[0156] The upper bank layer 117 may be formed on the sensing electrode 510. The upper bank layer 117 may be disposed on the sensing electrode 510 to cover an outer portion of the sensing electrode 510. For example, the upper bank layer 117 may overlap the sensing electrode 510 and may be in direct contact with an upper surface of the second lower inorganic encapsulation layer 430 where the sensing electrode 510 does not exist. The upper bank layer 117 may cover a side surface of the sensing electrode 510.

[0157] The upper bank layer 117 may be arranged around the sensing electrode 510 (e.g., surrounding the sensing electrode 510). Specifically, the upper bank layer 117 may include an upper opening UOP exposing a central portion of the sensing electrode 510 and covering an edge of the sensing electrode 510. The upper opening UOP may pass from the top surface of the upper bank layer 117 to the bottom surface of the upper bank layer 117, and the side surface of the upper bank layer 117 may have a positive tapered shape. The upper opening UOP may define a sensing area SA.

[0158] The upper bank layer 117 may include an inorganic insulating layer and / or an organic insulating layer. In one or more embodiments, when the upper bank layer 117 includes an inorganic insulating layer, the upper bank layer 117 may include the same material as the insulating layer 115. For example, the upper bank layer 117 may include an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned inorganic insulating material. In one or more embodiments, the upper bank layer 117 may have a two-layer structure including a silicon oxide layer and a silicon nitride layer. In one or more embodiments, when the upper bank layer 117 includes an organic insulating layer, the upper bank layer 117 may include an organic insulating layer including a material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO) and / or phenolic resin.

[0159] The second protective layer 119 may be formed between the sensing electrode 510 and the upper bank layer 117. The second protective layer 119 may be deposited to overlap the sensing electrode 510, and then may be etched to expose the central portion of the sensing electrode 510, thereby leaving only a portion of the second protective layer 119. The second protective layer 119 may prevent the sensing electrode 510 from being damaged by gas or liquid substances used in various etching processes or ashing processes included in the process of manufacturing the display device 1. The second protective layer 119 may include a conductive oxide such as ITO, IZO, IGZO, ITZO, ZnO, AZO, GZO, ZTO, GTO, and / or FTO.

[0160] The active layer 520 may be disposed in the upper opening UOP of the upper bank layer 117 to overlap the sensing electrode 510. The active layer 520 may include a P-type organic semiconductor and an N-type organic semiconductor. In this case, the P-type organic semiconductor may act as an electron donor, and the N-type organic semiconductor may act as an electron acceptor.

[0161] In one or more embodiments, the active layer 520 may be a mixed layer in which a P-type organic semiconductor and an N-type organic semiconductor are mixed. In this case, the active layer 520 may be formed by co-depositing a P-type organic semiconductor and an N-type organic semiconductor. When the active layer 520 is a mixed layer, excitons may be generated from a donor-acceptor interface within a diffusion length.

[0162] In one or more embodiments, the P-type organic semiconductor may be a compound that acts as an electron donor to supply electrons. For example, the P-type organic semiconductor may include, but is not limited to, chloroboron subphthalocyanine (SubPc), copper (II) phthalocyanine (CuPc), tetraphenyldiphenylene (DBP), and / or any combination thereof.

[0163] In one or more embodiments, the N-type organic semiconductor may be a compound that acts as an electron acceptor to accept electrons. For example, the N-type organic semiconductor may include, but is not limited to, C60 fullerene, C70 fullerene, or any combination thereof.

[0164] The active layer 520 may receive light from the outside to generate excitons, and then separate the generated excitons into holes and electrons. When a (+) potential is applied to the sensing electrode 510 and a (-) potential is applied to the sensing counter electrode 530, the holes separated in the active layer 520 may move toward the sensing counter electrode 530, and the electrons separated in the active layer 520 may move toward the sensing electrode 510. Therefore, a photocurrent may be formed in a direction from the sensing electrode 510 to the sensing counter electrode 530.

[0165] When a bias is applied between the sensing electrode 510 and the sensing counter electrode 530, a dark current may flow in the light receiving element PD. In addition, when light is incident on the light receiving element PD, a photocurrent may flow in the light receiving element PD. In one or more embodiments, the light receiving element PD may detect the amount of light from the ratio of the photocurrent to the dark current.

[0166] The sensing counter electrode 530 may be disposed on the active layer 520 to overlap with the active layer 520. However, the sensing counter electrode 530 may not only be arranged in the upper opening UOP, but may also be continuously formed on the upper bank layer 117. That is, the sensing counter electrode 530 may be formed over the entire surface of the substrate 100 and formed as a whole. In one or more embodiments, the sensing counter electrode 530 may include the same material as the counter electrode 230. The sensing counter electrode 530 may be a transparent electrode or a semi-transparent electrode, and may include a transparent layer or a semi-transparent layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca and / or alloys thereof. Alternatively, the sensing counter electrode 530 may also include a transparent layer or a semi-transparent layer including the aforementioned materials such as ITO, IZO, ZnO and / or In. 2 O 3 layer of TCO layer.

[0167] In one or more embodiments, the common layer may be arranged between the sensing electrode 510 and the active layer 520 and / or between the active layer 520 and the sensing counter electrode 530. Specifically, the first common layer may be arranged between the sensing electrode 510 and the active layer 520, and the second common layer may be arranged between the active layer 520 and the sensing counter electrode 530. The first common layer may include an HTL and / or a HIL. The second common layer may include an ETL and / or an EIL. The first common layer and the second common layer may each include an organic material.

[0168] Through the structure of the light receiving element PD as described above, the display device 1 according to one or more embodiments can also improve the resolution. When the light emitting element ED and the light receiving element PD are arranged on the same layer (for example, at the same layer), a separate area where the light receiving element PD other than the light emitting element ED can be arranged must be ensured on the same plane, and therefore, the emission area of ​​the light emitting element ED may be relatively reduced. On the other hand, in the case of Figure 5 In the display device 1 shown in FIG, the light receiving element PD is not only provided on a different layer from the light emitting element ED, but also the light receiving element PD is provided above the lower bank layer 300 which is a non-emitting region, and therefore, the resolution can be significantly improved by effectively utilizing the space. In addition, since the light receiving element PD can receive a signal from the sensing drive circuit PC' by using the lower bank layer 300 including a conductive material, it is not necessary to separately arrange a signal transmission wiring line, and therefore, it is easier to ensure an emission region and improve the resolution.

[0169] The light receiving element PD may be encapsulated by an upper encapsulation layer 600. The upper encapsulation layer 600 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the upper encapsulation layer 600 may include a first upper inorganic encapsulation layer 610, an upper organic encapsulation layer 620 on the first upper inorganic encapsulation layer 610, and a second upper inorganic encapsulation layer 630 on the upper organic encapsulation layer 620.

[0170] The first upper inorganic encapsulation layer 610 and the second upper inorganic encapsulation layer 630 may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first upper inorganic encapsulation layer 610 and the second upper inorganic encapsulation layer 630 may each include a single layer or multiple layers containing the aforementioned materials. The upper organic encapsulation layer 620 may include a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimides, and / or polyethylene. In one or more embodiments, the upper organic encapsulation layer 620 may include acrylates. The upper organic encapsulation layer 620 may be formed by curing a monomer or applying a polymer. The upper organic encapsulation layer 620 may be transparent.

[0171] The first upper inorganic encapsulation layer 610 having relatively excellent step coverage may cover at least a portion of the inner surface of the upper opening UOP of the upper bank layer 117. For example, the first upper inorganic encapsulation layer 610 may be continuously formed to overlap the upper surface and side surface of the upper bank layer 117 and the upper surface of the sensing electrode 530. However, the first upper inorganic encapsulation layer 610 may not only cover the upper opening UOP, but also cover the upper surface of the upper bank layer 117. That is, the first upper inorganic encapsulation layer 610 may be integrally formed over the entire surface of the substrate 100. The upper organic encapsulation layer 620 may be located on the first upper inorganic encapsulation layer 610, fill the upper opening UOP, and may also be formed on the upper bank layer 117 to flatten the upper surface of the display device 1. The second upper inorganic encapsulation layer 630 may be disposed on the upper organic encapsulation layer 620. Thus, the first upper inorganic encapsulating layer 610 and the second upper inorganic encapsulating layer 630 may be arranged to be spaced apart from each other with the upper organic encapsulating layer 620 interposed therebetween.

[0172] The input sensing layer 700 may be disposed on the upper encapsulation layer 600. The input sensing layer 700 may acquire coordinate information according to an external input (eg, a touch event). The input sensing layer 700 may include a plurality of touch electrodes and a touch insulating layer.

[0173] FIG. 6A to FIG. 6O is a cross-sectional view schematically illustrating a state according to a process of manufacturing a display device according to one or more embodiments.

[0174] Refer to Figure 5 and FIG. 6A to FIG. 6O First, refer to Fig. 6A , the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 and the bridge electrode BE may be formed on the substrate 100. The first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 may be arranged for each pixel and spaced apart from each other. The bridge electrode BE may be arranged between the pixel electrodes arranged adjacent to each other. The first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 and the bridge electrode BE may be formed together in the same process. The first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 and the bridge electrode BE may include the same material.

[0175] Before forming the first pixel electrode 1210, the second pixel electrode 2210, the third pixel electrode 3210 and the bridging electrode BE, the first emission driving circuit PC1, the second emission driving circuit PC2, the third emission driving circuit PC3, the sensing driving circuit PC' and the connecting metals CM and CM' may be formed between the substrate 100 and the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210.

[0176] Each of the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and / or compounds thereof, and a reflective layer including ITO, IZO, ZnO, and / or In 2 O 3 In one or more embodiments, each of the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 may have a structure in which an ITO layer, an Ag layer, and an ITO layer are sequentially stacked.

[0177] The first protective layer 113 may be formed to overlap each of the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210. The first protective layer 113 may include a conductive oxide such as ITO, IZO, IGZO, ITZO, ZnO, AZO, GZO, ZTO, GTO, and / or FTO. The first protective layer 113 and the first pixel electrode 1210, the second pixel electrode 2210, and the third pixel electrode 3210 may be patterned together in the same process.

[0178] The insulating layer 115 may be formed on the first protective layer 113. The insulating layer 115 may be integrally formed over the entire surface of the substrate 100. Therefore, the insulating layer 115 may not only cover the first protective layer 113 and the bridge electrode BE, but also cover the exposed upper surface of the second organic insulating layer 111. The material of the insulating layer 115 is the same as that described above with reference to Figure 5 The material of the insulating layer 115 is the same as described.

[0179] A material layer corresponding to the lower bank layer 300 (eg, a first conductive layer 310 and a second conductive layer 320 on the first conductive layer 310) may be formed on the insulating layer 115. The properties such as material and thickness of the first conductive layer 310 and the second conductive layer 320 are similar to those described above with reference to FIG. Figure 5 The first conductive layer 310 and the second conductive layer 320 are described to be the same in properties such as material and thickness. For example, the thickness of the first conductive layer 310 may be greater than the thickness of the second conductive layer 320.

[0180] Next, refer to Figure 6B , first, second, and third lower openings LOP1, LOP2, and LOP3 and a trench TR may be formed in the lower bank layer 300. The first, second, and third lower openings LOP1, LOP2, and LOP3 may overlap each pixel electrode 210, and a trench TR may be formed between the lower openings disposed adjacent to each other.

[0181] The first lower opening LOP1, the second lower opening LOP2, the third lower opening LOP3 and the trench TR may be formed via an etching process. Specifically, a photoresist may be formed on the second conductive layer 320 in the remaining regions except for the regions where the first lower opening LOP1, the second lower opening LOP2, the third lower opening LOP3 and the trench TR are to be formed. Using the photoresist as a mask, portions of the first conductive layer 310 and the second conductive layer 320 may be removed to form the first lower opening LOP1, the second lower opening LOP2, the third lower opening LOP3 and the trench TR. The first lower opening LOP1, the second lower opening LOP2 and the third lower opening LOP3 may have the shape of a through hole passing through the lower bank layer 300 and the insulating layer 115. The process of removing portions of the lower bank layer 300 and the insulating layer 115 may be performed via dry etching.

[0182] In addition, because the first conductive layer 310 and the second conductive layer 320 of the lower bank layer 300 have different etching selectivities, the first conductive layer 310 may be etched more than the second conductive layer 320 even if the same etching process is performed. Therefore, the second conductive layer 320 may include a tip PT1 that protrudes more toward the lower opening than the first conductive layer 310, and each of the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 may have an undercut structure. Similarly, the second conductive layer 320 may include a tip PT2 that protrudes more toward the trench TR than the first conductive layer 310. The process of removing a portion of the first conductive layer 310 and a portion of the first protective layer 113 may be performed via wet etching.

[0183] By forming the trench TR in the lower bank layer 300, the lower bank layer 300 may be divided into a first portion P31 and a second portion P32. The second portion P32 may be a portion including the side of the lower bank layer 300 facing the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3, and the first portion P31 may have an island shape around the second portion P32 (e.g., surrounded by the second portion P32) in a plan view. The first portion P31 and the second portion P32 may be spaced apart from each other, and the trench TR is interposed between the first portion P31 and the second portion P32, the first portion P31 may be electrically connected to the light receiving element PD, and the second portion P32 may be electrically connected to the light emitting element ED.

[0184] Next, refer to Figure 6C , the emission layer 220 (see Figure 5 ) and the counter electrode 230 (see Figure 5 ) may be formed in the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3. The emission layer 220 (see Figure 5 ) may include a first emission layer 1220 disposed in the first lower opening LOP1, a second emission layer 2220 disposed in the second lower opening LOP2, and a third emission layer 3220 disposed in the third lower opening LOP3. The counter electrode 230 (see Figure 5 ) may include a first pair of electrodes 1230 disposed on the first emission layer 1220 , a second pair of electrodes 2230 disposed on the second emission layer 2220 , and a third pair of electrodes 3230 disposed on the third emission layer 3220 .

[0185] The first emission layer 1220, the second emission layer 2220 and the third emission layer 3220 may be formed via a deposition method such as thermal evaporation. The first emission layer 1220, the second emission layer 2220 and the third emission layer 3220 may be patterned and deposited in the first lower opening LOP1, the second lower opening LOP2 and the third lower opening LOP3 by the undercut structure of the lower bank layer 300 without a separate mask. Similarly, the first pair of electrodes 1230, the second pair of electrodes 2230 and the third pair of electrodes 3230 may be formed via a deposition method such as thermal evaporation. The first pair of electrodes 1230, the second pair of electrodes 2230 and the third pair of electrodes 3230 may be patterned and deposited in the first lower opening LOP1, the second lower opening LOP2 and the third lower opening LOP3 by the undercut structure of the lower bank layer 300 without a separate mask. However, during the deposition process, the formation of the pair of electrodes 230 (see Figure 5 ) may be different from the incident angle of the material forming the emission layer 220 (see Figure 5 Therefore, the first pair of electrodes 1230, the second pair of electrodes 2230, and the third pair of electrodes 3230 may be deposited such that their outer portions directly contact the side of the first conductive layer 310.

[0186] Next, refer to Fig.6D , the first lower inorganic encapsulation layer 410 may be formed on Figure 6C . The first lower inorganic encapsulation layer 410 may include one or more inorganic materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be deposited using a chemical vapor deposition method. The first lower inorganic encapsulation layer 410 having excellent step coverage may continuously cover the inner surfaces of the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3 and the inner surface of the trench TR.

[0187] Can be evaluated at room temperature, high temperature and high humidity Fig.6D The reliability of the display device 1 is evaluated based on the structure shown in FIG. Fig.6D In the structure shown in FIG, the light emitting element ED is covered with the first lower inorganic encapsulation layer 410, so an environmental reliability evaluation can be performed to check whether there are any abnormal problems in the processes performed so far. When an environmental reliability evaluation is performed at an intermediate stage like this, it can be checked whether the process can be further performed, thereby avoiding sending defective products to subsequent processes, thereby improving yield and reducing costs.

[0188] Next, refer to Fig. 6E , the lower organic encapsulation layer 420 may be formed in the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3. The lower organic encapsulation layer 420 may be arranged not only in the first lower opening LOP1, the second lower opening LOP2, and the third lower opening LOP3, but also in the trench TR, and thus the upper surface of the display device 1 may be flattened. The material of the lower organic encapsulation layer 420 is the same as that described above with reference to FIG. Figure 5 The material of the lower organic encapsulation layer 420 is the same as described.

[0189] Thereafter, a hard mask HM and a mask protection layer MP may be formed on the first lower inorganic encapsulation layer 410 and the lower organic encapsulation layer 420. The hard mask HM may be formed on an area other than a partial area of ​​the upper surface of the first portion P31 of the lower bank layer 300. That is, the hard masks HM may be arranged to be spaced apart from each other, and a portion of the upper surface of the first portion P31 is between the hard masks HM. Unlike a photoresist, the hard mask HM may include a metal such as chromium (Cr). In addition, compared to a photoresist, the hard mask HM may include a relatively hard metal material, and therefore, when the hard mask HM is used as a mask layer for forming a small diameter hole, a pattern may be formed without using a high-resolution semiconductor device. Therefore, the manufacturing process may be facilitated by forming a small hole in the first lower inorganic encapsulation layer 410 using a hard mask HM.

[0190] However, in order to prevent damage to the lower structure during the etching process for the first lower inorganic encapsulation layer 410, a mask protection layer MP may be formed under the hard mask HM. The mask protection layer MP may be deposited to overlap with the hard mask HM. Like the hard mask HM, the mask protection layer MP may be formed on an area other than a partial area of ​​the upper surface of the first portion P31 of the lower bank layer 300. The mask protection layer MP may include the same material as the first protective layer 113. For example, the mask protection layer MP may include a conductive oxide such as ITO, IZO, IGZO, ITZO, ZnO, AZO, GZO, ZTO, GTO and / or FTO.

[0191] Next, refer to Fig. 6F , a portion of the first lower inorganic encapsulation layer 410 may be etched using the hard mask HM. Since the hard mask HM is not disposed on a partial region of the first portion P31 of the lower bank layer 300, when the dry etching process is performed, a portion of the first lower inorganic encapsulation layer 410 that does not overlap with the hard mask HM may be etched. That is, the hole H' may be formed in a portion of the first lower inorganic encapsulation layer 410 that overlaps with the first portion P31, and the hole H' may be a portion of the light receiving element PD (see Figure 5 ) is connected to a preliminary contact hole of the lower bank layer 300.

[0192] In addition, since the hole H' is formed in the first lower inorganic encapsulation layer 410, the first lower inorganic encapsulation layer 410 may be divided into a 1-1 lower inorganic encapsulation layer 1410, a 1-2 lower inorganic encapsulation layer 2410, and a 1-3 lower inorganic encapsulation layer 3410. The 1-1 lower inorganic encapsulation layer 1410, the 1-2 lower inorganic encapsulation layer 2410, and the 1-3 lower inorganic encapsulation layer 3410 may be arranged to be spaced apart from each other with the hole H' interposed therebetween.

[0193] Next, refer to Figure 6G , the hard mask HM and the mask protection layer MP may be removed, and a second lower inorganic encapsulation layer 430 may be formed on the first lower inorganic encapsulation layer 410 and the lower organic encapsulation layer 420. The second lower inorganic encapsulation layer 430 may include one or more inorganic materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be deposited using a chemical vapor deposition method. The second lower inorganic encapsulation layer 430 may be integrally formed over the entire surface of the substrate 100.

[0194] Next, refer to Figure 6H , a hard mask HM and a mask protection layer MP may be formed on the second lower inorganic encapsulation layer 430. The material of each of the hard mask HM and the mask protection layer MP is the same as that of the reference Fig. 6E The material of each of the hard mask HM and the mask protection layer MP described is the same. The hard mask HM and the mask protection layer MP may be formed on an area other than a partial area of ​​the upper surface of the first portion P31 of the lower bank layer 300. That is, a plurality of hard masks HM may be arranged to be spaced apart from each other and a plurality of mask protection layers MP may be arranged to be spaced apart from each other, and a partial area of ​​the upper surface of the first portion P31 is between the plurality of hard masks HM and between the plurality of mask protection layers MP. Fig. 6FIn the embodiment, a region where the hard mask HM and the mask protection layer MP are not formed may overlap a region where the hole H′ of the first lower inorganic encapsulation layer 410 is formed.

[0195] Next, refer to Fig.6I , a portion of the second lower inorganic encapsulation layer 430 may be etched using the hard mask HM. Through the dry etching process, a portion of the second lower inorganic encapsulation layer 430 that does not overlap with the hard mask HM may be etched. A hole H' may be formed in a portion of the second lower inorganic encapsulation layer 430 that overlaps with the first portion P31, and the hole H' may be a portion of the light receiving element PD (see Figure 5 ) is connected to a preliminary contact hole of the lower bank layer 300.

[0196] Next, refer to Figure 6J , the hard mask HM and the mask protection layer MP formed on the second lower inorganic encapsulation layer 430 may be removed. The hard mask HM and the mask protection layer MP may be removed through an etching process.

[0197] The hole H′ (see FIG. 1 ) formed in the portion of the first lower inorganic encapsulation layer 410 overlapping the first portion P31. Fig. 6F ) may be formed in a portion of the second lower inorganic encapsulating layer 430 overlapping the first portion P31 (see Fig.6I ) overlap. That is, the contact hole CNT1 may be formed in a portion of the first lower inorganic encapsulation layer 410 and the second lower inorganic encapsulation layer 430 that overlaps the first portion P31, and thus, a portion of the upper surface of the first portion P31 may be exposed. As described above, the contact hole CNT1 may be formed to connect the light receiving element PD (see Figure 5 ) is connected to the sensing drive circuit PC'.

[0198] Next, refer to Figure 6K , the sensing electrode 510 and the second protective layer 119 may be formed on the lower encapsulation layer 400. The sensing electrodes 510 may be arranged in the non-emission region and may be spaced apart from each other. The sensing electrode 510 may include the same material as the pixel electrode 210. In one or more embodiments, the sensing electrode 510 may have a structure in which an ITO layer, an Ag layer, and / or an ITO layer are sequentially stacked.

[0199] The second protective layer 119 may overlap the sensing electrode 510. The second protective layer 119 may include the same material as the first protective layer 113. The second protective layer 119 may include a conductive oxide such as ITO, IZO, IGZO, ITZO, ZnO, AZO, GZO, ZTO, GTO and / or FTO. The second protective layer 119 and the sensing electrode 510 may be patterned together in the same process.

[0200] Next, refer to Figure 6L , the upper bank layer 117 may be formed on the sensing electrode 510 and the second protection layer 119. The material of the upper bank layer 117 is similar to that of the reference Figure 5 The upper bank layer 117 may be patterned to include an opening overlapping the sensing electrode 510 . Specifically, the upper bank layer 117 may overlap the sensing electrode 510 and include a preliminary upper opening UOP′ exposing a central portion of an upper surface of the second protection layer 119 .

[0201] Next, refer to Figure 6M , a portion of the second protective layer 119 may be etched to expose the central portion of the sensing electrode 510. The process of removing a portion of the second protective layer 119 may be performed by wet etching. As the portion of the second protective layer 119 overlapping the central portion of the sensing electrode 510 is removed, an upper opening UOP may be formed.

[0202] Next, refer to Figure 6N , the active layer 520 and the sensing counter electrode 530 can be formed in the upper opening UOP. The active layer 520 can be formed via a deposition method such as thermal evaporation. The active layer 520 can be patterned and formed to be deposited in the upper opening UOP. Similarly, the sensing counter electrode 530 can be formed via a deposition method such as thermal evaporation. However, the sensing counter electrode 530 can be deposited not only in the upper opening UOP, but also on the upper bank layer 117. That is, the sensing counter electrode 530 can be integrally formed over the entire surface of the substrate 100. The material of each of the active layer 520 and the sensing counter electrode 530 is the same as the reference Figure 5 The material of each of the active layer 520 and the sensing counter electrode 530 is described to be the same.

[0203] Next, refer to Fig.6O , the upper encapsulation layer 600 may be formed on Figure 6N The upper encapsulation layer 600 may include a first upper inorganic encapsulation layer 610 , an upper organic encapsulation layer 620 on the first upper inorganic encapsulation layer 610 , and a second upper inorganic encapsulation layer 630 on the upper organic encapsulation layer 620 .

[0204] The first upper inorganic encapsulation layer 610 may be formed on the sensing electrode 530 and may be integrally formed over the entire surface of the substrate 100. Because the first upper inorganic encapsulation layer 610 has excellent step coverage, the first upper inorganic encapsulation layer 610 may extend to cover the inner surface of the upper opening UOP. The upper organic encapsulation layer 620 may not only fill the upper opening UOP, but may also be disposed above the upper bank layer 117 to flatten the upper surface of the display device 1. The second upper inorganic encapsulation layer 630 may be formed on the upper organic encapsulation layer 620 and may be integrally formed over the entire surface of the substrate 100. That is, the first upper inorganic encapsulation layer 610 and the second upper inorganic encapsulation layer 630 may be arranged to be spaced apart from each other, and the upper organic encapsulation layer 620 is disposed between the first upper inorganic encapsulation layer 610 and the second upper inorganic encapsulation layer 630.

[0205] In one or more embodiments, the first upper inorganic encapsulation layer 610 may include the same material as the first lower inorganic encapsulation layer 410, the upper organic encapsulation layer 620 may include the same material as the lower organic encapsulation layer 420, and the second upper inorganic encapsulation layer 630 may include the same material as the second lower inorganic encapsulation layer 430. However, the present disclosure is not limited thereto, and the upper encapsulation layer 600 may include a different material from the lower encapsulation layer 400.

[0206] Figure 7 is a display device 1 according to one or more embodiments. Figure 4 A schematic cross-sectional view of a portion taken along line II' of FIG. Figure 7 , except for the features of the upper organic encapsulation layer 620, the other features are the same as those of reference Figure 5 The characteristics described are the same. Figure 7 In, with Figure 5 The same reference numerals as those in the reference numerals in FIG. Figure 5 The components in FIG. 1 are the same components, and therefore, the differences will be mainly described below.

[0207] Reference Figure 7 , also refer to Figure 5 , a plurality of air cavities AC may be formed in the upper organic encapsulation layer 620. The plurality of air cavities AC are air gaps formed in the upper organic encapsulation layer 620, and may have a tunnel shape extending in a direction perpendicular to the substrate 100. The plurality of air cavities AC may overlap the sensing electrode 510 of the light receiving element PD.

[0208] The input sensing layer 700 may be disposed on the upper encapsulation layer 600, and parasitic capacitance generated by the light receiving element PD as the lower structure closest to the input sensing layer 700 may be formed in the input sensing layer 700. However, the dielectric constant of the upper organic encapsulation layer 620 has a value of about 3.0 to about 3.2, and the dielectric constant of the air cavity has a value of about 1.0, and therefore, when a plurality of air cavities AC are formed in the upper organic encapsulation layer 620, the density of the upper organic encapsulation layer 620 may be reduced. Therefore, the parasitic capacitance caused by the light receiving element PD formed in the input sensing layer 700 may be reduced, and therefore, the touch sensitivity of the touch electrode included in the input sensing layer 700 may be effectively improved. That is, the display device 1 according to one or more embodiments may not only improve the resolution by placing the light receiving element PD and the light emitting element ED on different layers, but also improve the touch sensitivity of the input sensing layer 700.

[0209] Figure 8 is a display device 1 according to one or more embodiments. Figure 4 A schematic cross-sectional view of a portion taken along line II' of FIG. Figure 8 , except for the features of the sensing electrode 530 and the upper encapsulation layer 600, the other features are the same as those of the reference Figure 5 The characteristics described are the same. Figure 8 In, with Figure 5 The same reference numerals as those in the reference numerals in FIG. Figure 5 The components in FIG. 1 are the same components, and therefore, the differences will be mainly described below.

[0210] Reference Figure 8 , the sensing counter electrode 530 may be arranged not only in the upper opening UOP, but also on the upper bank layer 117. However, the sensing counter electrode 530 may not be integrally formed as a whole over the entire surface of the substrate 100, but a plurality of sensing counter electrodes 530 may be arranged to be spaced apart from each other. That is, the sensing counter electrode 530 may be individually provided for each of the plurality of light receiving elements PD.

[0211] The first upper inorganic encapsulation layer 610 may be disposed on the sensing electrode 530. The first upper inorganic encapsulation layer 610 having excellent step coverage may cover at least a portion of the inner surface of the upper opening UOP. The first upper inorganic encapsulation layer 610 may be continuously formed to overlap with the upper surface and side surface of the upper bank layer 117 and the upper surface of the sensing electrode 530. However, like the sensing electrode 530, a plurality of first upper inorganic encapsulation layers 610 may be arranged to be spaced apart from each other. Specifically, the first upper inorganic encapsulation layer 610 may be arranged to encapsulate each of the plurality of light receiving elements PD, respectively, while being arranged to be spaced apart from each other.

[0212] The upper organic encapsulating layer 620 may be disposed on the first upper inorganic encapsulating layer 610 to flatten the upper surface of the display device 1. Therefore, the upper organic encapsulating layer 620 may cover the upper surface of the upper bank layer 117 exposed due to the absence of the sensing counter electrode 530 and the first upper inorganic encapsulating layer 610.

[0213] In the upper encapsulation layer 600 having the above-described structure, since the plurality of first upper inorganic encapsulation layers 610 are arranged to be spaced apart from each other, a structure in which the corresponding light receiving element PD is sealed for each device unit can be formed. Since the upper encapsulation layer 600 can seal each light receiving element PD, even when defects such as dark spots occur due to penetration of contaminants from the outside, an effect of suppressing the increase of defects can be provided. Therefore, the display device 1 according to one or more embodiments can not only improve the resolution by arranging the light emitting element ED and the light receiving element PD on different layers, but also produce an image of excellent quality by sealing both the light emitting element ED and the light receiving element PD for each device unit.

[0214] The display device according to one or more embodiments as described above can improve resolution by arranging the light emitting element and the light receiving element on different layers.The aforementioned effects are examples, and the scope of the present disclosure is not limited by these effects.

[0215] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: a substrate including an emitting region and a sensing region; a light emitting element on the substrate and overlapping the emission region; a lower bank layer having a lower opening defining the emission region, the lower bank layer comprising a first conductive layer and a second conductive layer on the first conductive layer; a light receiving element on the lower bank layer and overlapping the sensing area; and an upper bank layer including an upper opening defining the sensing area, The light emitting element and the light receiving element are located at different layers.

2. The display device according to claim 1, wherein: The light emitting element comprises: A pixel electrode in the emission region; an emission layer in the lower opening of the lower bank layer and overlapping the pixel electrode; and A counter electrode is in the lower opening of the lower bank layer and overlaps the emission layer.

3. The display device according to claim 1, wherein: The light receiving element comprises: a sensing electrode in the sensing region; an active layer in the upper opening of the upper bank layer and overlapping the sensing electrode; and A sensing counter electrode is disposed on the active layer and the entire surface of the substrate.

4. The display device according to claim 1, wherein: The light emitting element and the upper bank layer overlap each other, and the light receiving element and the lower bank layer overlap each other.

5. The display device according to claim 1, wherein: The second conductive layer includes a tip extending toward the lower opening from a point where a bottom surface of the second conductive layer and a side surface of the first conductive layer contact each other.

6. The display device according to claim 1, wherein: The lower bank layer further includes a groove between lower openings adjacent to each other among the plurality of lower openings.

7. The display device according to claim 6, wherein: The lower bank layer includes a first portion and a second portion spaced apart from each other, and the trench is between the first portion and the second portion. Wherein, the first part and the second part are electrically disconnected from each other.

8. The display device according to claim 7, wherein: The second portion includes a side of the lower bank layer facing the lower opening, and the first portion is located between second portions of the plurality of second portions facing different lower openings of the plurality of lower openings.

9. The display device according to claim 8, wherein: The second portion surrounds the first portion in a plan view, and the first portion has an island shape.

10. The display device according to claim 7, wherein: The first portion is electrically connected to the light receiving element, and the second portion is electrically connected to the light emitting element.

11. The display device according to claim 7, wherein: The counter electrode of the light emitting element directly contacts a side surface of the second portion facing the lower opening.

12. The display device according to claim 7, wherein: The display device further includes: an emission drive circuit electrically connected to the light emitting element; and a sensing driving circuit, electrically connected to the light receiving element, The emission driving circuit and the sensing driving circuit are driven independently of each other.

13. The display device according to claim 12, wherein: The sensing drive circuit and the light receiving element are electrically connected to each other via the first portion.

14. The display device according to claim 13, wherein: The display device further includes a bridge electrode between the sensing driving circuit and the lower bank layer, The lower surface of the first conductive layer of the first portion contacts the bridge electrode, and the upper surface of the second conductive layer of the first portion contacts the sensing electrode of the light receiving element.

15. The display device according to claim 14, wherein: The bridge electrode is located at the same layer as the pixel electrode of the light emitting element, and the bridge electrode and the pixel electrode include the same material.

16. The display device according to claim 1, wherein: The display device further includes: a lower encapsulation layer covering the light emitting element; and an upper encapsulation layer, covering the light receiving element, Wherein, the lower encapsulation layer and the upper encapsulation layer are located at different layers.

17. The display device according to claim 16, wherein: The lower encapsulation layer encapsulates the light emitting element and includes a plurality of encapsulation layer units spaced apart from each other.

18. The display device according to claim 17, wherein: Each of the plurality of encapsulation layer units comprises: a first lower inorganic encapsulation layer on the light emitting element and extending to cover the lower opening; a lower organic encapsulation layer on the first lower inorganic encapsulation layer and filling the lower opening; and A second lower inorganic encapsulation layer is on the lower organic encapsulation layer.

19. The display device according to claim 18, wherein: The first lower inorganic encapsulating layer and the second lower inorganic encapsulating layer contact each other on the lower bank layer.

20. The display device according to claim 16, wherein: The upper encapsulation layer comprises: a first upper inorganic encapsulation layer on the light receiving element and extending to cover the upper opening; an upper organic encapsulation layer on the first upper inorganic encapsulation layer; and A second upper inorganic encapsulation layer is on the upper organic encapsulation layer.

21. The display device according to claim 20, wherein: The first upper inorganic encapsulating layer and the second upper inorganic encapsulating layer are spaced apart from each other, and the upper organic encapsulating layer is interposed between the first upper inorganic encapsulating layer and the second upper inorganic encapsulating layer.

22. The display device according to claim 20, wherein: The first upper inorganic encapsulation layer is integrally formed as one body over the entire surface of the substrate.

23. The display device according to claim 20, wherein: The first upper inorganic encapsulation layer encapsulates each of the plurality of light receiving elements, and the plurality of first upper inorganic encapsulation layers are spaced apart from each other.

24. The display device according to claim 20, wherein: The upper organic encapsulation layer includes a plurality of air cavities, Wherein, the plurality of air cavities overlap with the light receiving element.

25. A method of manufacturing a display device, wherein: The method comprises: forming a pixel electrode on a substrate; forming a lower bank layer on the pixel electrode, wherein the lower bank layer comprises a first conductive layer and a second conductive layer on the first conductive layer; forming a lower opening in the lower bank layer overlapping the pixel electrode; forming an emission layer overlapping the pixel electrode in the lower opening of the lower bank layer; forming a counter electrode overlapping the emission layer in the lower opening of the lower bank layer; forming a sensing electrode on the lower bank layer; forming an upper bank layer on the sensing electrode; forming an upper opening in the upper bank layer overlapping the sensing electrode; forming an active layer disposed in the upper opening of the upper bank layer and overlapping the sensing electrode; and A sensing counter electrode is formed on the upper bank layer and the active layer.

26. The method according to claim 25, wherein: The method further includes: forming a groove in the lower bank layer between lower openings arranged adjacent to each other among the plurality of lower openings, The trench and the lower opening are formed by the same etching process.

27. The method according to claim 26, wherein: The lower bank layer includes a first portion and a second portion spaced apart from each other, and the trench is between the first portion and the second portion. The first portion is in contact with the sensing electrode, and the second portion is in contact with the counter electrode.

28. The method according to claim 25, wherein: The method further includes: forming a lower encapsulation layer between the forming of the counter electrode and the forming of the sensing electrode, Wherein, forming the lower encapsulation layer comprises: forming a first lower inorganic encapsulation layer on the counter electrode and the lower bank layer; forming a lower organic encapsulation layer on the first lower inorganic encapsulation layer to fill the lower opening; and A second lower inorganic encapsulation layer is formed on the lower organic encapsulation layer.

29. The method according to claim 28, wherein: The method further comprises: Between the forming of the lower organic encapsulation layer and the forming of the second lower inorganic encapsulation layer, etching a portion of the first lower inorganic encapsulation layer on the lower bank layer; and Between the forming of the second lower inorganic encapsulating layer and the forming of the sensing electrode, a portion of the second lower inorganic encapsulating layer on the lower bank layer is etched.

30. The method of claim 29, wherein: The sensing electrode is electrically connected to the lower bank layer through a contact hole formed by etching a portion of each of the first lower inorganic encapsulation layer and the second lower inorganic encapsulation layer.

31. The method of claim 25, wherein: The method further comprises: after forming the sensing counter electrode, forming an upper encapsulation layer, Wherein, forming the upper encapsulation layer comprises: forming a first upper inorganic encapsulation layer on the sensing counter electrode over the entire surface of the substrate; forming an upper organic encapsulation layer on the first upper inorganic encapsulation layer, the upper organic encapsulation layer filling the upper opening and on the upper bank layer; and A second upper inorganic encapsulation layer is formed on the upper organic encapsulation layer.

32. The method according to claim 31, wherein: The method further includes: between the forming of the upper organic encapsulation layer and the forming of the second upper inorganic encapsulation layer, forming a plurality of air cavities in the upper organic encapsulation layer, Wherein, the plurality of air cavities overlap with the sensing electrodes.

33. The method of claim 25, wherein: The method further comprises: before forming the pixel electrode, forming an emission driving circuit electrically connected to a light emitting element including the pixel electrode, the emission layer and the counter electrode; and A sensing driving circuit electrically connected to a light receiving element including the sensing electrode, the active layer, and the sensing counter electrode is formed.

34. The method of claim 33, wherein: The method further includes: forming a bridge electrode between the sensing driving circuit and the lower bank layer, Wherein, the bridge electrode and the pixel electrode are formed through the same deposition process.

35. The method of claim 34, wherein: The sensing driving circuit is electrically connected to the sensing electrode via the bridge electrode and the lower bank layer.

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