Display substrate and display method thereof, pixel driving circuit and driving method thereof, and display device

Abstract

The invention provides a display substrate. The display substrate comprises a substrate body; the driving circuit layer is located on the substrate, and the driving circuit layer comprises a plurality of pixel driving circuits; the light-emitting device layer is located on the side, away from the substrate, of the driving circuit layer, the light-emitting device layer comprises a plurality of light-emitting devices, and the light-emitting devices are electrically connected with the pixel driving circuits respectively; wherein the at least one light-emitting device comprises a laminated light-emitting device; the laminated light-emitting device comprises a first electrode, a first light-emitting unit located on the side, away from the substrate, of the first electrode, a second electrode located on the side, away from the substrate, of the first light-emitting unit, a second light-emitting unit located on the side, away from the substrate, of the second electrode and a third electrode located on the side, away from the substrate, of the second light-emitting unit. The pixel driving circuit includes a plurality of transistors, the first electrode is electrically connected to at least one transistor, the second electrode is electrically connected to at least one transistor, and the transistor electrically connected to the first electrode is different from the transistor electrically connected to the second electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display method thereof, a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display products have become the mainstream display products in the smart terminal sector due to their advantages such as high brightness, long life and low power consumption. As consumers demand higher and higher display quality, double-layer OLED devices and multi-layer OLED devices are gaining more and more attention. However, how to solve the problems of high power consumption and poor low grayscale image quality of double-layer OLED devices and multi-layer OLED devices is one of the topics that display product developers are concerned about.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display substrate is provided, comprising:

[0005] substrate substrate;

[0006] A driving circuit layer, located on the base substrate, the driving circuit layer comprising a plurality of pixel driving circuits; and

[0007] A light emitting device layer is located on a side of the driving circuit layer away from the base substrate, the light emitting device layer includes a plurality of light emitting devices arranged at intervals, and the plurality of light emitting devices are electrically connected to a plurality of pixel driving circuits respectively;

[0008] Wherein, at least one light-emitting device comprises a stacked light-emitting device, wherein the stacked light-emitting device comprises a first electrode, a first light-emitting unit located on a side of the first electrode away from the substrate, a second electrode located on a side of the first light-emitting unit away from the substrate, a second light-emitting unit located on a side of the second electrode away from the substrate, and a third electrode located on a side of the second light-emitting unit away from the substrate;

[0009] The pixel driving circuit includes a plurality of transistors, the first electrode is electrically connected to at least one of the transistors, the second electrode is electrically connected to at least one of the transistors, and the transistor electrically connected to the first electrode is different from the transistor electrically connected to the second electrode.

[0010] According to some exemplary embodiments, the display substrate further includes a pixel defining layer, the pixel defining layer is located between the first electrode and the first light emitting unit, the pixel defining layer includes a plurality of openings, the plurality of openings respectively expose a portion of a plurality of the first electrodes; and

[0011] An orthographic projection of at least one of the second electrodes on the base substrate covers an orthographic projection of at least one of the openings on the base substrate.

[0012] According to some exemplary embodiments, the display substrate further includes a pixel defining layer, the pixel defining layer is located between the first electrode and the first light emitting unit, the pixel defining layer includes a plurality of openings, the plurality of openings respectively expose a portion of a plurality of the first electrodes; and

[0013] An orthographic projection of at least one of the second electrodes on the base substrate partially overlaps with an orthographic projection of at least one of the openings on the base substrate.

[0014] According to some exemplary embodiments, an overlapping portion of an orthographic projection of at least one of the second electrodes on the substrate and an orthographic projection of at least one of the openings on the substrate is annular; and / or,

[0015] The orthographic projection of at least one of the second electrodes on the substrate falls within the orthographic projection of at least one of the openings on the substrate; and / or,

[0016] The orthographic projection of at least one of the second electrodes on the base substrate covers a portion of an edge of the orthographic projection of at least one of the openings on the base substrate.

[0017] According to some exemplary embodiments, the plurality of light emitting devices include a plurality of first light emitting devices, a plurality of second light emitting devices, and a plurality of third light emitting devices, and the first light emitting devices, the second light emitting devices, and the third light emitting devices all include the stacked light emitting device.

[0018] According to some exemplary embodiments, the plurality of light emitting devices include a plurality of first light emitting devices, a plurality of second light emitting devices, and a plurality of third light emitting devices, at least one of the first light emitting devices, the second light emitting devices, and the third light emitting devices includes the stacked light emitting device; and

[0019] At least one of the first light-emitting device, the second light-emitting device and the third light-emitting device comprises a single-layer light-emitting device, the single-layer light-emitting device comprising a fourth electrode, a third light-emitting unit located on a side of the fourth electrode away from the substrate, and a fifth electrode located on a side of the third light-emitting unit away from the substrate, the fourth electrode being electrically connected to at least one of the transistors.

[0020] According to some exemplary embodiments, the first light emitting device includes the stacked light emitting device, the second light emitting device includes the stacked light emitting device, and the third light emitting device includes the single-layer light emitting device; and

[0021] The first light emitting device emits red light, the second light emitting device emits green light, and the third light emitting device emits blue light.

[0022] According to some exemplary embodiments, the first light emitting device includes the single-layer light emitting device, the second light emitting device includes the single-layer light emitting device, and the third light emitting device includes the stacked-layer light emitting device; and

[0023] The first light emitting device emits red light, the second light emitting device emits green light, and the third light emitting device emits blue light.

[0024] According to some exemplary embodiments, the pixel defining layer includes a first via hole, the first via hole being spaced apart from the opening; and

[0025] The array substrate further includes a second electrode lead, the second electrode lead and the second electrode are connected to form an integral structure, and the second electrode lead is electrically connected to the transistor of the pixel driving circuit through the first via hole.

[0026] According to some exemplary embodiments, in at least two adjacent stacked light emitting devices, a first light emitting unit of one stacked light emitting device is spaced apart from a first light emitting unit of another stacked light emitting device; and

[0027] The orthographic projection of the first via hole on the base substrate is located in a spacing area between orthographic projections of two adjacent first light emitting units on the base substrate.

[0028] According to some exemplary embodiments, in at least two adjacent stacked light emitting devices, the second light emitting unit of one stacked light emitting device is spaced apart from the second light emitting unit of another stacked light emitting device.

[0029] According to some exemplary embodiments, the third electrodes of the plurality of stacked light-emitting devices are connected to form a third electrode layer of an integrated structure, the third electrode layer having a hollow portion, the orthographic projection of the hollow portion on the base substrate at least partially overlaps with the orthographic projection of the second electrode lead on the base substrate, and the third electrode layer and the second electrode lead are spaced apart.

[0030] In another aspect, a display method of a display substrate is provided, which is applied to the display substrate as described in any one of the above items, and the display method comprises:

[0031] Obtaining image information to be displayed;

[0032] dividing the plurality of stacked light emitting devices into at least one first stacked light emitting device and at least one second stacked light emitting device according to image information to be displayed; and

[0033] In response to the image information to be displayed, the first light emitting unit and the second light emitting unit in the first stacked light emitting device both emit light and reach target brightness, and the first light emitting unit or the second light emitting unit in the second stacked light emitting device emits light and reaches target brightness.

[0034] In another aspect, a pixel driving circuit is provided, the pixel driving circuit being configured to drive a light-emitting device to emit light, the light-emitting device comprising a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on a side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on a side of the second electrode away from the first electrode, and a third electrode located on a side of the second light-emitting unit away from the first electrode; the pixel driving circuit comprising:

[0035] a driving subcircuit, electrically connected to the light emitting device;

[0036] a data writing sub-circuit, electrically connected to the data signal terminal, the scan signal terminal and the driving sub-circuit, wherein the data writing sub-circuit is configured to write the data signal from the data signal terminal into the driving sub-circuit under the control of the scan signal from the scan signal terminal;

[0037] a first light emitting control subcircuit electrically connected to the driving subcircuit, the first light emitting control signal terminal and the first electrode of the light emitting device; and

[0038] The second light emitting control sub-circuit is electrically connected to the driving sub-circuit, the second light emitting control signal terminal and the second electrode of the light emitting device.

[0039] According to some exemplary embodiments, the driving subcircuit includes a third transistor;

[0040] The first light emitting control subcircuit comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to a second electrode of the third transistor, a second electrode of the fifth transistor is electrically connected to a first electrode of the light emitting device, and a gate of the fifth transistor is electrically connected to the first light emitting signal control terminal;

[0041] The second light-emitting control subcircuit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the second electrode of the third transistor, a second electrode of the eighth transistor is electrically connected to the second electrode of the light-emitting device, and a gate of the eighth transistor is electrically connected to the second light-emitting signal control terminal.

[0042] In another aspect, a driving method of a pixel driving circuit is provided, the driving method comprising:

[0043] Under the control of the scan signal, the data writing subcircuit writes the data signal into the driving subcircuit;

[0044] In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned off, the second light-emitting control subcircuit is turned on, and the second light-emitting control subcircuit controls the driving subcircuit to output a driving current only to the second light-emitting unit; and

[0045] In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned on, the second light-emitting control subcircuit is turned off, and the first light-emitting control subcircuit controls the driving subcircuit to output a driving current to the first light-emitting unit and the second light-emitting unit.

[0046] In another aspect, a pixel driving circuit is provided, the pixel driving circuit being configured to drive a light-emitting device to emit light, the light-emitting device comprising a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on a side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on a side of the second electrode away from the first electrode, and a third electrode located on a side of the second light-emitting unit away from the first electrode; the pixel driving circuit comprising:

[0047] a driving subcircuit, electrically connected to the light emitting device;

[0048] a data writing sub-circuit, electrically connected to the data signal terminal, the scan signal terminal and the driving sub-circuit, wherein the data writing sub-circuit is configured to write the data signal from the data signal terminal into the driving sub-circuit under the control of the scan signal from the scan signal terminal;

[0049] a first light emitting control subcircuit electrically connected to the driving subcircuit, the first light emitting control signal terminal and the first electrode of the light emitting device; and

[0050] The second light emitting control subcircuit is electrically connected to the second electrode, the second power supply terminal and the second light emitting control signal terminal of the light emitting device.

[0051] According to some exemplary embodiments, the driving subcircuit includes a third transistor;

[0052] The first light emitting control subcircuit comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to a second electrode of the third transistor, a second electrode of the fifth transistor is electrically connected to a first electrode of the light emitting device, and a gate of the fifth transistor is electrically connected to the first light emitting signal control terminal; and

[0053] The second light-emitting control subcircuit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the second electrode of the light-emitting device, a second electrode of the eighth transistor is electrically connected to the second power supply terminal, and a gate of the eighth transistor is electrically connected to the second light-emitting signal control terminal.

[0054] In another aspect, a driving method of a pixel driving circuit is provided, the driving method comprising:

[0055] Under the control of the scan signal, the data writing subcircuit writes the data signal into the driving subcircuit;

[0056] In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned on, the second light-emitting control subcircuit is turned on, and the first light-emitting control subcircuit and the second light-emitting control subcircuit control the driving subcircuit to output the driving current only to the first light-emitting unit; and

[0057] In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned on, the second light-emitting control subcircuit is turned off, and the first light-emitting control subcircuit controls the driving subcircuit to output a driving current to the first light-emitting unit and the second light-emitting unit.

[0058] On the other hand, a display device is provided, wherein the display device comprises the display substrate as described in any one of the above items, or comprises the pixel driving circuit as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0060] Figure 1 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0061] Figure 2 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0062] Figure 3 A cross-sectional schematic diagram of a stacked light emitting device in a display substrate according to some embodiments of the present disclosure is schematically shown.

[0063] Figure 4 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0064] Figure 5 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0065] Figure 6 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0066] Figure 7 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0067] Figure 8A-8E A plan view schematically shows a second electrode of a display substrate according to some embodiments of the present disclosure.

[0068] Fig. 9 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0069] Fig.10 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0070] Fig.11 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0071] Figure 12A-12C The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0072] Fig.13 The flowchart of a display method of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0073] Fig.14 The structure diagram of the pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0074] Fig.15 An equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0075] Figure 16A-16B The figure schematically shows a signal timing diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0076] Fig.17 The structure diagram of the pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0077] Fig.18 An equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0078] Figure 19A-19B The figure schematically shows a signal timing diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0079] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0080] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0081] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of the individual elements are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiments may be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0082] When an element is described as "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on another element, directly connected to another element or directly coupled to another element, or there may be an intermediate element. However, when an element is described as "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and 1 such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0083] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, a first element may be named a second element, and similarly, a second element may be named a first element.

[0084] Figure 1 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown. Figure 2 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown. Figure 3 A cross-sectional schematic diagram of a stacked light emitting device in a display substrate according to some embodiments of the present disclosure is schematically shown.

[0085] Combined with reference Figure 1 and Figure 2The display substrate includes a base substrate 100 and a driving circuit layer 200 and a light-emitting device layer 300 located on the base substrate 100. The driving circuit layer 200 includes a plurality of pixel driving circuits, and the pixel driving circuit may include a plurality of transistors TFT and at least one storage capacitor. The light-emitting device layer 300 is located on a side of the driving circuit layer 200 away from the base substrate 100, and the light-emitting device layer 300 includes a plurality of light-emitting devices 310 distributed at intervals, and the plurality of light-emitting devices 310 are electrically connected to the plurality of pixel driving circuits, respectively, and independently emit light under the drive of the plurality of pixel driving circuits to display.

[0086] Figure 1 A method of arranging a plurality of light emitting devices 310 is illustrated in FIG. 1 . According to actual display requirements, the plurality of light emitting devices 310 may also be arranged in other ways, which is not limited in the embodiments of the present disclosure.

[0087] Combined with reference Figure 1 , Figure 2 and Figure 3 Among the plurality of light-emitting devices 310, at least one light-emitting device 310 is a stacked light-emitting device 400, and the stacked light-emitting device 400 includes a first electrode 410, a first light-emitting unit 420 located on a side of the first electrode 410 away from the substrate 100, a second electrode 430 located on a side of the first light-emitting unit 420 away from the substrate 100, a second light-emitting unit 440 located on a side of the second electrode 430 away from the substrate 100, and a third electrode 450 located on a side of the second light-emitting unit 440 away from the substrate 100. The first electrode 410 is electrically connected to at least one transistor TFT, the second electrode 430 is electrically connected to at least one transistor TFT, and the transistor TFT electrically connected to the first electrode 410 and the transistor TFT electrically connected to the second electrode 430 are different.

[0088] With such a configuration, the pixel driving circuit can control the potential of the first electrode 410 and the second electrode 430 respectively, so that the stacked light-emitting device 400 can realize the switching between a single-layer device and a double-layer device. In some cases, such as when the luminous brightness is low, the stacked device can use a single-layer device to emit light (one of the first light-emitting unit 420 and the second light-emitting unit 440 emits light), thereby reducing power consumption. In addition, when only a single-layer device is used to emit light, the light-emitting current is larger, thereby effectively improving the crosstalk problem, thereby improving the display effect under low grayscale display images. In some cases, such as when the luminous brightness is high, the stacked device can use a double-layer device to emit light (both the first light-emitting unit 420 and the second light-emitting unit 440 emit light), thereby facilitating the realization of a higher luminous brightness, thereby improving the display contrast of the display substrate.

[0089] According to some exemplary embodiments, the first light emitting unit 420 may include a first hole transport layer HTL1 located on the first electrode 410, a first light emitting layer EML1 located on a side of the first hole transport layer HTL1 away from the first electrode 410, and a first charge generation layer CGL1 located on a side of the first light emitting layer EML1 away from the first electrode 410. Of course, according to actual needs, the first light emitting unit 420 may also include other functional film layers.

[0090] According to some exemplary embodiments, the second light emitting unit 440 may include a second charge generation layer CGL2 located on the second electrode 430, a second light emitting layer EML2 located on a side of the second charge generation layer CGL2 away from the second electrode 430, and a first electron transport layer ETL1 located on a side of the second light emitting layer EML2 away from the second electrode 430. Of course, according to actual needs, the second light emitting unit 440 may also include other functional film layers.

[0091] According to some exemplary embodiments, the material of the first electrode 410 may include a conductive metal oxide material. For example, the material of the first electrode 410 includes indium tin oxide.

[0092] According to some exemplary embodiments, the material of the third electrode 450 may include a metal material, for example, the material of the third electrode 450 includes magnesium and silver.

[0093] According to some exemplary embodiments, the material of the second electrode 430 may include at least one of a metal material and a conductive metal oxide material. For example, the material of the second electrode 430 includes indium tin oxide, or the material of the second electrode 430 includes magnesium and silver. The material of the second electrode 430 may be consistent with the material of the first electrode 410 or the third electrode 450, or the material of the second electrode 430 may also be selected to have both the material properties of the first electrode 410 and the third electrode 450.

[0094] According to some exemplary embodiments, referring to Figure 1 The plurality of light emitting devices 310 may include a plurality of first light emitting devices 311, a plurality of second light emitting devices 312, and a plurality of third light emitting devices 313. The first light emitting devices 311, the second light emitting devices 312, and the third light emitting devices 313 emit different light colors, for example, the first light emitting device 311 emits red light, the second light emitting device 312 emits green light, and the third light emitting device 313 emits blue light.

[0095] Figure 4 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0096] According to some exemplary embodiments, in combination with reference Figure 2 and Figure 4 , the first light emitting device 311, the second light emitting device 312 and the third light emitting device 313 all include a stacked light emitting device 400. In this way, when displaying, the plurality of first light emitting devices 311, the plurality of second light emitting devices 312 and the plurality of third light emitting devices 313 can be independently controlled to display using a single-layer device or a double-layer device according to the image to be displayed.

[0097] Figure 5 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown. Figure 6 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0098] According to some exemplary embodiments, in combination with reference Figure 2 , Figure 5 and Figure 6 , at least one of the first light emitting device 311, the second light emitting device 312 and the third light emitting device 313 includes a stacked light emitting device 400, and at least one of the first light emitting device 311, the second light emitting device 312 and the third light emitting device 313 includes a single-layer light emitting device 500. According to the performance difference of different light emitting devices 310, only a part of the light emitting devices 310 can be set as the stacked light emitting device 400, and the other part of the light emitting devices 310 can be set as the single-layer light emitting device 500. In this way, when displaying, according to the image to be displayed, the multiple stacked light emitting devices 400 can be independently controlled to display using a single-layer device or a double-layer device, and the multiple single-layer light emitting devices 500 are always displayed as single-layer devices.

[0099] Reference Figure 5 The single-layer light-emitting device 500 may include a fourth electrode 510, a third light-emitting unit 520 located on a side of the fourth electrode 510 away from the substrate 100, and a fifth electrode 530 located on a side of the third light-emitting unit 520 away from the substrate 100, and the fourth electrode 510 is electrically connected to at least one transistor TFT.

[0100] For example, the third light emitting unit 520 may include a second hole transport layer HTL2 on the fourth electrode 510 , a third light emitting layer EML3 on a side of the second hole transport layer HTL2 away from the fourth electrode 510 , and a second electron transport layer ETL2 on a side of the third light emitting layer EML3 away from the fourth electrode 510 .

[0101] For example, the fourth electrode 510 of the single-layer light-emitting device 500 may be located at the same layer as the first electrode 410 of the stacked light-emitting device 400 .

[0102] For example, the fifth electrode 530 of the single-layer light-emitting device 500 may be located at the same layer as the third electrode 450 of the stacked light-emitting device 400, and a plurality of fifth electrodes 530 and a plurality of third electrodes 450 may be connected into an integrated structure.

[0103] For example, some functional layers in the third light-emitting unit 520 of the single-layer light-emitting device 500 can be located on the same layer as some functional layers in the first light-emitting unit 420 and the second light-emitting unit 440 of the stacked light-emitting device 400. For example, the first hole transport layer HTL1 and the second hole transport layer HTL2 can be located on the same layer, and the first electron transport layer ETL1 and the second electron transport layer ETL2 can be located on the same layer.

[0104] It should be noted that being located in the same layer should be understood as two (or more) structures formed by the same deposition process and patterned by the same patterning process, and their materials may be the same or different.

[0105] According to some exemplary embodiments, in combination with reference Figure 2 , Figure 5 and Figure 6 , the first light emitting device 311 includes a single-layer light emitting device 500, the second light emitting device 312 includes a single-layer light emitting device 500, and the third light emitting device 313 includes a stacked light emitting device 400. That is, only the blue light emitting device is set as the stacked light emitting device 400. The blue light emitting device has a low luminous efficiency. By setting it as the stacked light emitting device 400, the luminous efficiency of the blue light emitting device can be increased. The green light emitting device and the red light emitting device have a high luminous efficiency, and they can still be set as the single-layer light emitting device 500, which is conducive to reducing the power consumption of the display substrate.

[0106] Figure 7 The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0107] According to some exemplary embodiments, in combination with reference Figure 2 , Figure 5 and Figure 7 , the first light emitting device 311 includes a stacked light emitting device 400, the second light emitting device 312 includes a stacked light emitting device 400, and the third light emitting device 313 includes a single-layer light emitting device 500. That is, the blue light emitting device is set as the single-layer light emitting device 500, and the red light emitting device and the green light emitting device are set as the stacked light emitting device 400.

[0108] Of course, according to actual display requirements, part of the first light-emitting device 311, the second light-emitting device 312 and the third light-emitting device 313 can be set as the stacked light-emitting device 400, and the other part can be set as the single-layer light-emitting device 500 in other ways.

[0109] Figure 8A-8E A plan view schematically shows a second electrode of a display substrate according to some embodiments of the present disclosure.

[0110] According to some exemplary embodiments, in combination with reference Figure 2 and Fig. 8A The display substrate further includes a pixel defining layer PDL, which is located between the first electrode 410 and the first light emitting unit 420. The pixel defining layer PDL includes a plurality of openings KK, which respectively expose a portion of the plurality of first electrodes 410, and the first light emitting unit 420 contacts the first electrode 410 through the openings KK. The orthographic projection of a second electrode 430 on the base substrate 100 covers the orthographic projection of an opening KK on the base substrate 100, and the second electrode 430 is arranged to fully cover the area where the opening KK of the pixel defining layer PDL is located.

[0111] It should be noted that, in the manner in which the second electrode 430 is fully covered in the area where the opening KK of the pixel definition layer PDL is located, the plurality of second electrodes 430 in the plurality of stacked light-emitting devices 400 are arranged at intervals, and the plurality of second electrodes 430 are respectively arranged to cover the plurality of openings KK.

[0112] It should be noted that in Figures 8A-8E In FIG. 4 , a bold black outline is used to illustrate the edge of the opening KK of the pixel defining layer PDL, so as to more clearly illustrate the projection relationship between the second electrode 430 and the opening KK of the pixel defining layer PDL.

[0113] In addition, since the process of forming the second electrode 430 may have a certain degree of fluctuation, it is difficult for the second electrode 430 to be completely formed within the area where the opening KK of the pixel definition layer PDL is located. In other words, a portion of the second electrode 430 is located outside the area where the opening KK of the pixel definition layer PDL is located. Figure 2 As shown, when the second electrode 430 is disposed to fully cover the area where the opening KK of the pixel definition layer PDL is located, the edge of the orthographic projection of the second electrode 430 on the base substrate 100 surrounds the outer side of the orthographic projection of the opening KK on the base substrate 100. Figure 8A-8E In order to more clearly illustrate the projection relationship between the second electrode 430 and the opening KK of the pixel defining layer PDL, only the portion of the second electrode 430 located in the opening KK region of the pixel defining layer PDL is illustrated.

[0114] Fig. 9 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0115] According to some exemplary embodiments, in combination with reference Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig. 9 , the orthographic projection of a second electrode 430 on the base substrate 100 partially overlaps with the orthographic projection of an opening KK on the base substrate 100, and the second electrode 430 only covers a portion of the opening KK of the pixel defining layer PDL, so that the problem of blocking light and reducing light extraction efficiency due to the provision of the second electrode 430 can be effectively avoided. In addition, referring to Fig. 9 In the area not covered by the second electrode 430, a portion of the first charge generation layer CGL1 in the first light emitting unit 420 is in direct contact with the second charge generation layer CGL2 in the second light emitting unit 440, which is beneficial to improving the efficiency when using a stacked device for display.

[0116] According to some exemplary embodiments, in combination with reference Figure 8B and Fig. 9 , the orthographic projection of the second electrode 430 on the base substrate is annular, and the outer edge of the second electrode 430 on the base substrate surrounds the outer side of the edge of the orthographic projection of the opening KK on the base substrate, and the inner edge of the second electrode 430 on the base substrate is located within the orthographic projection of the opening KK on the base substrate. In other words, the overlapping portion of the orthographic projection of the second electrode 430 on the base substrate and the orthographic projection of the opening KK on the base substrate is annular, and the second electrode 430 only covers the edge area of ​​the opening KK of the pixel defining layer PDL.

[0117] Fig.10 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0118] According to some exemplary embodiments, in combination with reference Figure 8C , Fig.8D and Fig.10 , a positive projection of a second electrode 430 on the base substrate falls within the positive projection of at least one opening KK on the base substrate, the second electrode 430 only covers a portion of the interior of the opening KK of the pixel defining layer PDL, and the edge area of ​​the opening KK of the pixel defining layer PDL is not covered by the second electrode 430.

[0119] For example, refer to Figure 8C The shape of the second electrode 430 (referring to the shape of the orthographic projection on the substrate) may be consistent with the shape of the opening KK of the pixel defining layer PDL, and the edge of the second electrode 430 may be extended and arranged in the opening KK along the edge of the opening KK of the pixel defining layer PDL. Exemplarily, the shape of the opening KK is a rounded rectangle, and the shape of the second electrode 430 located in the opening KK is also a rounded rectangle.

[0120] For example, refer to Fig.8DThe shape of the second electrode 430 may be different from the shape of the opening KK of the pixel defining layer PDL. For example, when the shape of the opening KK is a rectangle or other polygon, the shape of the second electrode 430 may be a circle.

[0121] According to some exemplary embodiments, referring to Fig. 8E The orthographic projection of the second electrode 430 on the substrate covers a portion of the edge of the orthographic projection of the opening KK on the substrate. The orthographic projection of the second electrode 430 on the substrate only covers a portion of the orthographic projection of the opening KK on the substrate that is located in a specific direction. For example, Fig. 8E In FIG. 4 , the orthographic projection of the second electrode 430 on the substrate covers the right half of the orthographic projection of the opening KK on the substrate.

[0122] Of course, the position and coverage area ratio of the second electrode 430 covering the opening KK can be set according to actual process requirements, and the embodiments of the present disclosure are not limited to this.

[0123] According to some exemplary embodiments, referring to Figure 2 The pixel defining layer PDL includes a first via hole V01, which is spaced apart from the opening KK. The array substrate also includes a second electrode lead 431, which is connected to the second electrode 430 as an integrated structure. The second electrode lead 431 is electrically connected to the transistor TFT of the pixel driving circuit through the first via hole V01.

[0124] The "integrated structure" in the embodiments of the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process to form a structure connected to each other, and their materials may be the same or different.

[0125] According to some exemplary embodiments, referring to Fig.10 When the second electrode 430 is located in the opening KK of the pixel definition layer PDL, the second electrode lead 431 needs to extend into the opening KK to be connected to the second electrode 430 .

[0126] It should be noted that the second electrode 430 and the second electrode lead 431 are formed by the same deposition process and patterning process. In actual products, there is no obvious dividing line between the second electrode 430 and the second electrode lead 431, but the width of the second electrode lead 431 (the dimension perpendicular to its extension direction) is smaller than the dimension of the second electrode 430 (the side length of the second electrode 430 or the diameter of the second electrode 430). For example, the width of the second electrode lead 431 is less than or equal to one-half of the dimension of the second electrode 430. It should be considered that the location where the dimension suddenly changes is the boundary between the second electrode 430 and the second electrode lead 431. Figure 2In the cross-sectional view, the first electrode lead 431 and the second electrode lead 431 are schematically distinguished by the density of the filling pattern.

[0127] According to some exemplary embodiments, referring to Figure 2 The driving circuit layer 200 may include a buffer layer Buf located on the base substrate 100, an active layer ACT located on a side of the buffer layer Buf away from the base substrate 100, a first gate insulating layer GI1 located on a side of the active layer ACT away from the base substrate 100, a first gate metal layer Gatel located on a side of the first gate insulating layer GI1 away from the base substrate 100, a second gate insulating layer GI2 located on a side of the first gate metal layer Gatel away from the base substrate 100, a second gate metal layer located on a side of the second gate insulating layer GI2 away from the base substrate 100, and a The second gate metal layer is located on a side of the third gate insulating layer GI3 away from the substrate substrate 100, the third gate metal layer is located on a side of the third gate insulating layer GI3 away from the substrate substrate 100, the interlayer dielectric layer ILD is located on a side of the third gate metal layer away from the substrate substrate 100, the first source and drain metal layer SD1 is located on a side of the interlayer dielectric layer ILD away from the substrate substrate 100, the first planarization layer PLN1 is located on a side of the first source and drain metal layer SD1 away from the substrate substrate 100, and the second source and drain metal layer SD2 is located on a side of the first planarization layer PLN1 away from the substrate substrate 100.

[0128] Because in Figure 2 The intercepted position does not have the related structures of the second gate metal layer and the third gate metal layer. Figure 2 The second gate metal layer and the third gate metal layer are not shown.

[0129] The pixel driving unit includes a transistor TFT, and the transistor TFT includes an active portion A, a gate G, a source S, and a drain D. The active portion A is located in the active layer ACT, and the active portion A includes a channel portion A1 and two conductive portions A2 connected to both sides of the channel portion A1. The gate G is located in the first gate metal layer Gate1, and the orthographic projection of the gate G on the base substrate 100 covers the orthographic projection of the channel portion A1 on the base substrate 100. The source S and the drain D are located in the first source-drain metal layer SD1, and the source S and the drain D are electrically connected to the two conductive portions A2 respectively.

[0130] According to some exemplary embodiments, referring to Figure 2The display substrate further includes a first transition portion L01 and a second transition portion L02. The first transition portion L01 and the first electrode 410 are located in the same layer. The first transition portion L01 and the first electrode 410 are arranged at intervals. The second electrode lead 431 is electrically connected to the first transition portion L01 through a first via hole V01. The second transition portion L02 is located in the second source-drain metal layer SD2. The first transition portion L01 is electrically connected to the second transition portion L02 through a second via hole V02 located in the second planarization layer PLN2. The second transition portion L02 is then electrically connected to the drain electrode D of the corresponding transistor TFT through a third via hole V03 located in the first planarization layer PLN1. The second electrode lead 431 is electrically connected to the transistor TFT through the first transition portion L01 and the second transition portion L02 in sequence. In this way, the hole depth of a single connection via hole can be reduced, which is conducive to improving the connection reliability between the second electrode lead 431 and the transistor TFT.

[0131] According to some exemplary embodiments, referring to Figure 2 In at least two adjacent stacked light emitting devices 400, the first light emitting unit 420 of one stacked light emitting device 400 is spaced apart from the first light emitting unit 420 of another stacked light emitting device 400, Figure 2 The first light-emitting unit 420 of a stacked light-emitting device 400 is schematically shown, and the first light-emitting unit 420 of another adjacent stacked light-emitting device 400 has the same structure and is arranged at intervals. The orthographic projection of the first via hole V01 on the base substrate 100 is located in the interval area between the orthographic projections of two adjacent first light-emitting units 420 on the base substrate 100. In other words, each layer in the first light-emitting unit 420 is formed by fine metal mask (FMM) evaporation. Multiple first light-emitting units 420 are independently spaced apart, and the interval area of ​​the first light-emitting unit 420 exposes the first via hole V01, so that the second electrode lead 431 can be electrically connected to the transistor TFT of the lower layer through the first via hole V01.

[0132] Fig.11 A cross-sectional schematic diagram of a display substrate according to some embodiments of the present disclosure is schematically shown.

[0133] According to some exemplary embodiments, referring to Fig.11 In at least two adjacent stacked light emitting devices 400 , the second light emitting unit 440 of one stacked light emitting device 400 is spaced apart from the second light emitting unit 440 of another stacked light emitting device 400 . Fig.11The second light-emitting unit 440 of a stacked light-emitting device 400 is schematically shown, and the second light-emitting unit 440 of another adjacent stacked light-emitting device 400 has the same structure and is arranged at intervals. That is, each layer in the second light-emitting unit 440 is formed by fine FMM evaporation, and multiple first light-emitting units 420 are independently spaced and distributed, which can effectively avoid the crosstalk problem of adjacent stacked light-emitting devices 400.

[0134] According to some exemplary embodiments, referring to Fig.11 The third electrodes 450 of the plurality of stacked light-emitting devices 400 are connected to form a third electrode layer 450A of an integrated structure, the third electrode layer 450A has a hollow portion 451, the orthographic projection of the hollow portion 451 on the base substrate 100 at least partially overlaps with the orthographic projection of the second electrode lead 431 on the base substrate 100, and the third electrode layer 450A is spaced from the second electrode lead 431. The third electrode layer 450A is patterned, and the hollow portion 451 is provided in the third electrode layer 450A to prevent the third electrode 450 and the second electrode 430 from being short-circuited.

[0135] Figure 12A-12C The planar distribution diagram of the light emitting devices in the display substrate according to some embodiments of the present disclosure is schematically shown.

[0136] The above-described scheme of setting the first part of the light-emitting device 310 as a stacked light-emitting device 400 and setting the other part of the light-emitting device 310 as a single-layer light-emitting device 500, as well as the scheme of the second electrode 430 fully or partially covering the opening KK of the pixel defining layer PDL, can be arbitrarily combined according to actual needs, as illustrated below.

[0137] For example, refer to Figure 4The first light emitting device 311, the second light emitting device 312 and the third light emitting device 313 are all stacked light emitting devices 400. The openings KK of the pixel defining layer PDL include a first opening KK1, a second opening KK2 and a third opening KK3. The first opening KK1 serves as a pixel opening KK of the first light emitting device 311, the second opening KK2 serves as a pixel opening KK of the second light emitting device 312, and the third opening KK3 serves as a pixel opening KK of the third light emitting device 313. The second electrodes 430 in the first light-emitting device 311, the second light-emitting device 312 and the third light-emitting device 313 only cover a portion of the area inside the opening KK of the pixel defining layer PDL. Specifically, the orthographic projection of the second electrode 430 of the first light-emitting device 311 on the substrate substrate 100 falls within the orthographic projection of the first opening KK1 on the substrate substrate 100, the orthographic projection of the second electrode 430 of the second light-emitting device 312 on the substrate substrate 100 falls within the orthographic projection of the second opening KK2 on the substrate substrate 100, and the orthographic projection of the second electrode 430 of the third light-emitting device 313 on the substrate substrate 100 falls within the orthographic projection of the third opening KK3 on the substrate substrate 100.

[0138] For example, refer to Fig. 12A , the first light-emitting device 311, the second light-emitting device 312 and the third light-emitting device 313 are all stacked light-emitting devices 400. The second electrodes 430 in the first light-emitting device 311, the second light-emitting device 312 and the third light-emitting device 313 only cover the edge area of ​​the opening KK of the pixel defining layer PDL. Specifically, the overlapping part of the orthographic projection of the second electrode 430 of the first light-emitting device 311 on the substrate substrate 100 and the orthographic projection of the first opening KK1 on the substrate substrate 100 is annular, the overlapping part of the orthographic projection of the second electrode 430 of the second light-emitting device 312 on the substrate substrate 100 and the orthographic projection of the second opening KK2 on the substrate substrate 100 is annular, and the overlapping part of the orthographic projection of the second electrode 430 of the third light-emitting device 313 on the substrate substrate 100 and the orthographic projection of the third opening KK3 on the substrate substrate 100 is annular.

[0139] For example, refer to Figure 6 The first light emitting device 311 and the second light emitting device 312 are single-layer light emitting devices 500, and the third light emitting device 313 is a stacked light emitting device 400. The orthographic projection of the second electrode 430 of the third light emitting device 313 on the substrate 100 falls within the orthographic projection of the third opening KK3 on the substrate 100.

[0140] For example, refer to Fig. 12BThe first light emitting device 311 and the second light emitting device 312 are single-layer light emitting devices 500, and the third light emitting device 313 is a stacked light emitting device 400. The overlapped portion of the orthographic projection of the second electrode 430 of the third light emitting device 313 on the substrate 100 and the orthographic projection of the third opening KK3 on the substrate 100 is annular.

[0141] For example, refer to Figure 7 , the first light emitting device 311 and the second light emitting device 312 are stacked light emitting devices 400, and the third light emitting device 313 is a single-layer light emitting device 500. The orthographic projection of the second electrode 430 of the first light emitting device 311 on the substrate 100 falls within the orthographic projection of the first opening KK1 on the substrate 100, and the orthographic projection of the second electrode 430 of the second light emitting device 312 on the substrate 100 falls within the orthographic projection of the second opening KK2 on the substrate 100.

[0142] For example, refer to Fig. 12C The first light emitting device 311 and the second light emitting device 312 are stacked light emitting devices 400, and the third light emitting device 313 is a single-layer light emitting device 500. The overlapping portion of the orthographic projection of the second electrode 430 of the first light emitting device 311 on the substrate 100 and the orthographic projection of the first opening KK1 on the substrate 100 is in a ring shape, and the overlapping portion of the orthographic projection of the second electrode 430 of the second light emitting device 312 on the substrate 100 and the orthographic projection of the second opening KK2 on the substrate 100 is in a ring shape.

[0143] The above is only a schematic illustration, and other combination settings can be made according to actual process requirements, and the embodiments of the present disclosure are not limited to this.

[0144] Fig.13 The flowchart of the display method of the display substrate according to some embodiments of the present disclosure is schematically shown.

[0145] At least some embodiments of the present disclosure further provide a display method for a display substrate, which is applied to the display substrate as described above, referring to Fig.13 , the display method includes steps S11 to S13.

[0146] In step S11, image information to be displayed is obtained.

[0147] In step S12, a plurality of stacked light emitting devices are divided into at least one first stacked light emitting device and at least one second stacked light emitting device according to image information to be displayed.

[0148] For example, a critical brightness value may be set, and the stacked light-emitting devices with a target brightness less than or equal to the critical brightness value may be classified as second stacked light-emitting devices, and the stacked light-emitting devices with a target brightness greater than or equal to the critical brightness value may be classified as first stacked light-emitting devices. For example, the critical brightness value may be 300 nit. Of course, other methods may also be used to classify the first stacked light-emitting devices and the second stacked light-emitting devices, and the embodiments of the present disclosure are not limited thereto.

[0149] In step S13, in response to the image information to be displayed, the first light emitting unit and the second light emitting unit in the first stacked light emitting device both emit light and reach the target brightness, and the first light emitting unit or the second light emitting unit in the second stacked light emitting device emits light and reaches the target brightness.

[0150] For the display substrate, when performing gamma debugging, a gamma debugging is performed once when both the first light-emitting unit and the second light-emitting unit emit light to obtain a first gamma curve, and a gamma debugging is performed once when only the first light-emitting unit or the second light-emitting unit emits light to obtain a second gamma curve, and the first gamma curve and the second gamma curve are burned into the driver chip. When displaying, for the first stacked light-emitting device, the driver chip outputs a corresponding data signal according to the first gamma curve, and for the second stacked light-emitting device, the driver chip outputs a corresponding data signal according to the second gamma curve.

[0151] Fig.14 The structure diagram of the pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0152] According to some exemplary embodiments, referring to Fig.14 The pixel circuit includes a pixel driving circuit 210 and a light emitting device 310. The pixel driving circuit 210 is configured to drive the light emitting device 310 to emit light. The cross-sectional structure of the light emitting device 310 can be referred to Figure 3 The light emitting device 310 includes a first electrode 410, a first light emitting unit 420 located on the first electrode 410, a second electrode 430 located on a side of the first light emitting unit 420 away from the first electrode 410, a second light emitting unit 440 located on a side of the second electrode 430 away from the first electrode 410, and a third electrode 450 located on a side of the second light emitting unit 440 away from the first electrode 410. The pixel driving circuit 210 includes a driving subcircuit 211, a data writing subcircuit 212, a first light emitting control subcircuit 213, and a second light emitting control subcircuit 214.

[0153] The third electrode 450 of the light emitting device 310 is electrically connected to the second power supply terminal VSS. The driving sub-circuit 211 is electrically connected to the light emitting device 310 and the first power supply terminal VDD, and the driving sub-circuit 211 is configured to control the driving current that drives the light emitting device 310 to emit light. The data writing sub-circuit 212 is electrically connected to the data signal terminal Data, the scan signal terminal Gate and the driving sub-circuit 211, and the data writing sub-circuit 212 is configured to write the data signal from the data signal terminal Data into the driving sub-circuit 211 under the control of the scan signal from the scan signal terminal Gate.

[0154] The first light control subcircuit 213 is electrically connected to the driving subcircuit 211, the first light control signal terminal EM1 and the first electrode 410 of the light emitting device 310. The second light control subcircuit 214 is electrically connected to the driving subcircuit 211, the second light control signal terminal EM2 and the second electrode 430 of the light emitting device 310.

[0155] The first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214 are configured to control the driving subcircuit 211 to output the driving current only to the second light-emitting unit 440, or to control the driving subcircuit 211 to output the driving current to the first light-emitting unit 420 and the second light-emitting unit 440, under the control of the first light-emitting control signal from the first light-emitting control signal terminal EM1 and the second light-emitting control signal from the second light-emitting control signal terminal EM2. Through the configuration of the first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214, the light-emitting mode of the light-emitting device 310 can be controlled to realize dynamic switching of single-layer light-emitting or double-layer light-emitting.

[0156] According to an embodiment of the present disclosure, the pixel driving circuit 210 includes a first driving mode and a second driving mode.

[0157] Reference Fig.14 In the first driving mode, the driving method includes: under the control of the scan signal, the data writing subcircuit 212 writes the data signal into the driving subcircuit 211; under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit 213 is turned off, the second light-emitting control subcircuit 214 is turned on, and the second light-emitting control subcircuit 214 controls the driving subcircuit 211 to output the driving current only to the second light-emitting unit 440, so that the second light-emitting unit 440 emits light.

[0158] Reference Fig.14In the second driving mode, the driving method includes: under the control of the scan signal, the data writing subcircuit 212 writes the data signal into the driving subcircuit 211; under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit 213 is turned on, and the second light-emitting control subcircuit 214 is turned off, and the first light-emitting control subcircuit 213 controls the driving subcircuit 211 to output a driving current to the first light-emitting unit 420 and the second light-emitting unit 440, so that the first light-emitting unit 420 and the second light-emitting unit 440 both emit light.

[0159] Fig.15 An equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0160] According to some exemplary embodiments, in combination with reference Fig.14 and Fig.15 The driving sub-circuit 211 includes a third transistor T3 (i.e., a driving transistor) and a storage capacitor C. The gate of the third transistor T3 is electrically connected to the first electrode of the storage capacitor C at the fourth node N4, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VDD at the fifth node N5, and the second electrode of the storage capacitor C is electrically connected to the first power supply terminal VDD.

[0161] The data writing subcircuit 212 includes a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is electrically connected to the scan signal terminal Gate, the first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3 at the sixth node N6, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The gate of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5.

[0162] The first light emitting control subcircuit 213 includes a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected to the first light emitting control signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to a sixth node N6, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode 410 of the light emitting device 310 at the first node N1.

[0163] The second light-emitting control subcircuit 214 includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the second light-emitting control signal terminal EM2, a first electrode of the eighth transistor T8 is electrically connected to a sixth node N6, and a second electrode of the eighth transistor T8 is electrically connected to the second electrode 430 of the light-emitting device 310 at the second node N2.

[0164] The third electrode 450 of the light emitting device 310 is electrically connected to the second power supply terminal VSS at the third node N3.

[0165] According to some exemplary embodiments, in combination with reference Fig.14 and Fig.15 , the pixel driving circuit 210 may further include a first transistor T1, a sixth transistor T6, and a seventh transistor T7. The gate of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4. The gate of the sixth transistor T6 is electrically connected to the third light emitting control signal terminal EM3, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The gate of the seventh transistor T7 is electrically connected to the scan signal terminal Gate, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0166] Figure 16A-16B The figure schematically shows a signal timing diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0167] Next, combine Figure 16A-16B , a driving process of the pixel driving circuit 210 according to an embodiment of the present disclosure is described in detail.

[0168] Reference Fig.16A , illustrates a signal timing diagram of the pixel driving circuit 210 in the first driving mode. The display process of each frame of image may include an initialization phase, a data writing phase and a light emitting phase.

[0169] In the initialization stage, the low level of the reset signal terminal Reset is an effective level, and the scanning signal terminal Gate, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the reset signal terminal Reset, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0170] In the data writing stage, the low level of the scanning signal terminal Gate is an effective level, and the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the scanning signal terminal Gate, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data via the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit via the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0171] In the light-emitting stage, the low levels of the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are effective levels, and the reset signal terminal Reset, the scanning signal terminal Gate, and the first light-emitting control signal terminal EM1 are high levels. The eighth transistor T8 is turned on under the control of the second light-emitting control signal terminal EM2, the sixth transistor T6 is turned on under the control of the third light-emitting control signal terminal EM3, and the fifth transistor T5 is turned off by the high level of the first light-emitting control signal terminal EM1. The third transistor T3 is turned on by the voltage signal stored in the storage capacitor C. The driving current is applied to the second light-emitting unit 440 along the path from the sixth transistor T6, the third transistor T3, and the eighth transistor T8, so that the second light-emitting unit 440 emits light.

[0172] Reference Fig. 16B , illustrates a signal timing diagram of the pixel driving circuit 210 in the second driving mode.

[0173] In the initialization stage, the low level of the reset signal terminal Reset is an effective level, and the scanning signal terminal Gate, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the reset signal terminal Reset, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0174] In the data writing stage, the low level of the scanning signal terminal Gate is an effective level, and the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the scanning signal terminal Gate, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data via the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit via the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0175] In the light-emitting stage, the low levels of the first light-emitting control signal terminal EM1 and the third light-emitting control signal terminal EM3 are effective levels, and the reset signal terminal Reset, the scanning signal terminal Gate, and the second light-emitting control signal terminal EM2 are high levels. The fifth transistor T5 is turned on under the control of the first light-emitting control signal terminal EM1, the sixth transistor T6 is turned on under the control of the third light-emitting control signal terminal EM3, and the eighth transistor T8 is turned off by the high level of the second light-emitting control signal terminal EM2. The third transistor T3 is turned on by the voltage signal stored in the storage capacitor C. The driving current is applied to the second light-emitting unit 440 and the first light-emitting unit 420 along the path from the sixth transistor T6, the third transistor T3, and the fifth transistor T5, so that the first light-emitting unit 420 and the second light-emitting unit 440 emit light.

[0176] Fig.17 The structure diagram of the pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0177] According to some exemplary embodiments, referring to Fig.17 The pixel circuit includes a pixel driving circuit 210 and a light emitting device 310. The pixel driving circuit 210 is configured to drive the light emitting device 310 to emit light. The cross-sectional structure of the light emitting device 310 can be referred to Figure 3 The light emitting device 310 includes a first electrode 410, a first light emitting unit 420 located on the first electrode 410, a second electrode 430 located on a side of the first light emitting unit 420 away from the first electrode 410, a second light emitting unit 440 located on a side of the second electrode 430 away from the first electrode 410, and a third electrode 450 located on a side of the second light emitting unit 440 away from the first electrode 410. The pixel driving circuit 210 includes a driving subcircuit 211, a data writing subcircuit 212, a first light emitting control subcircuit 213, and a second light emitting control subcircuit 214.

[0178] The third electrode 450 of the light emitting device 310 is electrically connected to the second power supply terminal VSS. The driving sub-circuit 211 is electrically connected to the light emitting device 310 and the first power supply terminal VDD, and the driving sub-circuit 211 is configured to control the driving current that drives the light emitting device 310 to emit light. The data writing sub-circuit 212 is electrically connected to the data signal terminal Data, the scan signal terminal Gate and the driving sub-circuit 211, and the data writing sub-circuit 212 is configured to write the data signal from the data signal terminal Data into the driving sub-circuit 211 under the control of the scan signal from the scan signal terminal Gate.

[0179] The first light control subcircuit 213 is electrically connected to the driving subcircuit 211, the first light control signal terminal EM1 and the first electrode 410 of the light emitting device 310. The second light control subcircuit 214 is electrically connected to the second electrode 430 of the light emitting device 310, the second power terminal VSS and the second light control signal terminal EM2.

[0180] The first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214 are configured to control the driving subcircuit 211 to output the driving current only to the first light-emitting unit 420, or to control the driving subcircuit 211 to output the driving current to the first light-emitting unit 420 and the second light-emitting unit 440, under the control of the first light-emitting control signal from the first light-emitting control signal terminal EM1 and the second light-emitting control signal from the second light-emitting control signal terminal EM2. Through the configuration of the first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214, the dynamic switching of the light-emitting mode of the light-emitting device 310 between single-layer light-emitting and double-layer light-emitting can be realized.

[0181] According to an embodiment of the present disclosure, the pixel driving circuit 210 includes a first driving mode and a second driving mode.

[0182] Reference Fig.17 In the first driving mode, the driving method includes: under the control of the scan signal, the data writing subcircuit 212 writes the data signal into the driving subcircuit 211; under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit 213 is turned on, and the second light-emitting control subcircuit 214 is turned on, and the first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214 control the driving subcircuit 211 to output the driving current only to the first light-emitting unit 420, so that the first light-emitting unit 420 emits light.

[0183] Reference Fig.17In the second driving mode, the driving method includes: under the control of the scan signal, the data writing subcircuit 212 writes the data signal into the driving subcircuit 211; under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit 213 is turned on, and the second light-emitting control subcircuit 214 is turned off, and the first light-emitting control subcircuit 213 controls the driving subcircuit 211 to output a driving current to the first light-emitting unit 420 and the second light-emitting unit 440, so that the first light-emitting unit 420 and the second light-emitting unit 440 emit light.

[0184] Fig.18 An equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure is schematically shown.

[0185] According to some exemplary embodiments, in combination with reference Fig.17 and Fig.18 The driving sub-circuit 211 includes a third transistor T3 (i.e., a driving transistor) and a storage capacitor C. The gate of the third transistor T3 is electrically connected to the first electrode of the storage capacitor C at the fourth node N4, the first electrode of the third transistor T3 is electrically connected to the first power supply terminal VDD at the fifth node N5, and the second electrode of the storage capacitor C is electrically connected to the first power supply terminal VDD.

[0186] The data writing subcircuit 212 includes a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is electrically connected to the scan signal terminal Gate, the first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3 at the sixth node N6, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4. The gate of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5.

[0187] The first light emitting control subcircuit 213 includes a fifth transistor T5, a gate of the fifth transistor T5 is electrically connected to the first light emitting control signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to a sixth node N6, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode 410 of the light emitting device 310 at the first node N1.

[0188] The second light-emitting control subcircuit 214 includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the second light-emitting control signal terminal EM2, a first electrode of the eighth transistor T8 is electrically connected to the second electrode 430 of the light-emitting device 310 at the second node N2, and a second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VSS at the third node N3.

[0189] The third electrode 450 of the light emitting device 310 is electrically connected to the second power supply terminal VSS at the third node N3.

[0190] According to some exemplary embodiments, in combination with reference Fig.17 and Fig.18 , the pixel driving circuit 210 may further include a first transistor T1, a sixth transistor T6, and a seventh transistor T7. The gate of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4. The gate of the sixth transistor T6 is electrically connected to the first light emission control signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The gate of the seventh transistor T7 is electrically connected to the scan signal terminal Gate, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0191] Figure 19A-19B The figure schematically shows a signal timing diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0192] Next, combine Figure 19A-19B , a driving process of the pixel driving circuit 210 according to an embodiment of the present disclosure is described in detail.

[0193] Reference Fig.19A , illustrates a signal timing diagram of the pixel driving circuit 210 in the first driving mode. The display process of each frame of image may include an initialization phase, a data writing phase and a light emitting phase.

[0194] In the initialization stage, the low level of the reset signal terminal Reset is an effective level, and the scanning signal terminal Gate, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the reset signal terminal Reset, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0195] In the data writing stage, the low level of the scanning signal terminal Gate is an effective level, and the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the scanning signal terminal Gate, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data via the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit via the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0196] In the light-emitting stage, the second light-emitting control signal terminal EM2 and the low level of the second light-emitting control signal terminal EM2 are effective levels, and the reset signal terminal Reset and the scanning signal terminal Gate are high levels. Under the control of the second light-emitting control signal terminal EM2, the eighth transistor T8 is turned on, and under the control of the first light-emitting control signal terminal EM1, the sixth transistor T6 and the fifth transistor T5 are turned on. The third transistor T3 is turned on under the drive of the voltage signal stored in the storage capacitor C. The eighth transistor T8 is turned on so that the potentials of the second node N2 and the third node N3 are the same, that is, the second light-emitting unit 440 is short-circuited, and the driving current is applied to the first light-emitting unit 420 along the path from the sixth transistor T6, the third transistor T3, the fifth transistor T5, the first light-emitting unit 420 and the eighth transistor T8 to make the first light-emitting unit 420 emit light.

[0197] Reference Fig.19B , illustrates a signal timing diagram of the pixel driving circuit 210 in the second driving mode.

[0198] In the initialization stage, the low level of the reset signal terminal Reset is an effective level, and the scanning signal terminal Gate, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the reset signal terminal Reset, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0199] In the data writing stage, the low level of the scanning signal terminal Gate is an effective level, and the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are high levels. Under the control of the scanning signal terminal Gate, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data via the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit via the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0200] In the light-emitting stage, the low level of the first light-emitting control signal terminal EM1 is an effective level, and the reset signal terminal Reset, the scanning signal terminal Gate, and the second light-emitting control signal terminal EM2 are high levels. Under the control of the first light-emitting control signal terminal EM1, the fifth transistor T5 and the sixth transistor T6 are turned on, and the eighth transistor T8 is turned off by the high level of the second light-emitting control signal terminal EM2. The third transistor T3 is turned on by the voltage signal stored in the storage capacitor C. The driving current is applied to the second light-emitting unit 440 and the first light-emitting unit 420 along the path from the sixth transistor T6, the third transistor T3, and the fifth transistor T5, so that the first light-emitting unit 420 and the second light-emitting unit 440 emit light.

[0201] At least some embodiments of the present disclosure also provide a display device, which includes a display substrate as described above. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0202] At least some embodiments of the present disclosure also provide a display device, which includes the pixel driving circuit as described above.

[0203] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate, and these features and advantages can be referred to the above description of the display substrate, which will not be repeated here.

[0204] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0205] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate substrate; A driving circuit layer, located on the base substrate, the driving circuit layer comprising a plurality of pixel driving circuits; and A light emitting device layer is located on a side of the driving circuit layer away from the base substrate, the light emitting device layer includes a plurality of light emitting devices arranged at intervals, and the plurality of light emitting devices are electrically connected to a plurality of pixel driving circuits respectively; Wherein, at least one light-emitting device comprises a stacked light-emitting device, wherein the stacked light-emitting device comprises a first electrode, a first light-emitting unit located on a side of the first electrode away from the substrate, a second electrode located on a side of the first light-emitting unit away from the substrate, a second light-emitting unit located on a side of the second electrode away from the substrate, and a third electrode located on a side of the second light-emitting unit away from the substrate; The pixel driving circuit includes a plurality of transistors, the first electrode is electrically connected to at least one of the transistors, the second electrode is electrically connected to at least one of the transistors, and the transistor electrically connected to the first electrode is different from the transistor electrically connected to the second electrode.

2. The display substrate according to claim 1, wherein: The display substrate further includes a pixel defining layer, the pixel defining layer is located between the first electrode and the first light emitting unit, the pixel defining layer includes a plurality of openings, and the plurality of openings respectively expose a portion of the plurality of first electrodes; as well as An orthographic projection of at least one of the second electrodes on the base substrate covers an orthographic projection of at least one of the openings on the base substrate.

3. The display substrate according to claim 1, wherein: The display substrate further includes a pixel defining layer, the pixel defining layer is located between the first electrode and the first light emitting unit, the pixel defining layer includes a plurality of openings, and the plurality of openings respectively expose a portion of the plurality of first electrodes; as well as An orthographic projection of at least one of the second electrodes on the base substrate partially overlaps with an orthographic projection of at least one of the openings on the base substrate.

4. The display substrate according to claim 3, wherein: The overlapping portion of the orthographic projection of at least one of the second electrodes on the substrate and the orthographic projection of at least one of the openings on the substrate is in a ring shape; and / or, An orthographic projection of at least one of the second electrodes on the substrate falls within an orthographic projection of at least one of the openings on the substrate; and / or, The orthographic projection of at least one of the second electrodes on the base substrate covers a portion of an edge of the orthographic projection of at least one of the openings on the base substrate.

5. The display substrate according to any one of claims 1 to 4, wherein: The plurality of light emitting devices include a plurality of first light emitting devices, a plurality of second light emitting devices, and a plurality of third light emitting devices, and the first light emitting devices, the second light emitting devices, and the third light emitting devices all include the stacked light emitting device.

6. The display substrate according to any one of claims 1 to 4, wherein: The plurality of light emitting devices include a plurality of first light emitting devices, a plurality of second light emitting devices, and a plurality of third light emitting devices, at least one of the first light emitting devices, the second light emitting devices, and the third light emitting devices includes the stacked light emitting device; and At least one of the first light-emitting device, the second light-emitting device and the third light-emitting device comprises a single-layer light-emitting device, the single-layer light-emitting device comprising a fourth electrode, a third light-emitting unit located on a side of the fourth electrode away from the substrate, and a fifth electrode located on a side of the third light-emitting unit away from the substrate, the fourth electrode being electrically connected to at least one of the transistors.

7. The display substrate according to claim 6, wherein: The first light emitting device includes the stacked light emitting device, the second light emitting device includes the stacked light emitting device, and the third light emitting device includes the single-layer light emitting device; and The first light emitting device emits red light, the second light emitting device emits green light, and the third light emitting device emits blue light.

8. The display substrate according to claim 6, wherein: The first light emitting device includes the single-layer light emitting device, the second light emitting device includes the single-layer light emitting device, and the third light emitting device includes the stacked-layer light emitting device; and The first light emitting device emits red light, the second light emitting device emits green light, and the third light emitting device emits blue light.

9. The display substrate according to any one of claims 2 to 4, wherein: The pixel defining layer comprises a first via hole, and the first via hole is spaced apart from the opening; as well as The array substrate further includes a second electrode lead, the second electrode lead and the second electrode are connected to form an integral structure, and the second electrode lead is electrically connected to the transistor of the pixel driving circuit through the first via hole.

10. The display substrate according to claim 9, wherein: In at least two adjacent stacked light-emitting devices, a first light-emitting unit of one stacked light-emitting device is spaced apart from a first light-emitting unit of another stacked light-emitting device; as well as The orthographic projection of the first via hole on the base substrate is located in a spacing area between orthographic projections of two adjacent first light emitting units on the base substrate.

11. The display substrate according to claim 10, wherein: In at least two adjacent stacked light-emitting devices, the second light-emitting unit of one stacked light-emitting device is spaced apart from the second light-emitting unit of another stacked light-emitting device.

12. The display substrate according to claim 11, wherein: The third electrodes of the plurality of stacked light-emitting devices are connected to form a third electrode layer of an integrated structure, the third electrode layer having a hollow portion, the orthographic projection of the hollow portion on the base substrate at least partially overlaps with the orthographic projection of the second electrode lead on the base substrate, and the third electrode layer and the second electrode lead are spaced apart.

13. A display method for a display substrate, wherein: Applied to the display substrate according to any one of claims 1 to 12, the display method comprises: Obtaining image information to be displayed; dividing the plurality of stacked light emitting devices into at least one first stacked light emitting device and at least one second stacked light emitting device according to image information to be displayed; and In response to the image information to be displayed, the first light emitting unit and the second light emitting unit in the first stacked light emitting device both emit light and reach target brightness, and the first light emitting unit or the second light emitting unit in the second stacked light emitting device emits light and reaches target brightness.

14. A pixel driving circuit, wherein: The pixel driving circuit is configured to drive the light-emitting device to emit light, wherein the light-emitting device includes a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on a side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on a side of the second electrode away from the first electrode, and a third electrode located on a side of the second light-emitting unit away from the first electrode; The pixel driving circuit comprises: a driving subcircuit, electrically connected to the light emitting device; a data writing sub-circuit, electrically connected to the data signal terminal, the scan signal terminal and the driving sub-circuit, wherein the data writing sub-circuit is configured to write the data signal from the data signal terminal into the driving sub-circuit under the control of the scan signal from the scan signal terminal; a first light emitting control subcircuit electrically connected to the driving subcircuit, the first light emitting control signal terminal and the first electrode of the light emitting device; and The second light emitting control sub-circuit is electrically connected to the driving sub-circuit, the second light emitting control signal terminal and the second electrode of the light emitting device.

15. The pixel driving circuit according to claim 14, wherein: The driving subcircuit includes a third transistor; The first light emitting control subcircuit comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to a second electrode of the third transistor, a second electrode of the fifth transistor is electrically connected to a first electrode of the light emitting device, and a gate of the fifth transistor is electrically connected to the first light emitting signal control terminal; The second light-emitting control subcircuit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the second electrode of the third transistor, a second electrode of the eighth transistor is electrically connected to the second electrode of the light-emitting device, and a gate of the eighth transistor is electrically connected to the second light-emitting signal control terminal.

16. A driving method for a pixel driving circuit, wherein: Applied to the pixel driving circuit according to claim 14 or 15, the driving method comprises: Under the control of the scan signal, the data writing subcircuit writes the data signal into the driving subcircuit; In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned off, the second light-emitting control subcircuit is turned on, and the second light-emitting control subcircuit controls the driving subcircuit to output a driving current only to the second light-emitting unit; and In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned on, the second light-emitting control subcircuit is turned off, and the first light-emitting control subcircuit controls the driving subcircuit to output a driving current to the first light-emitting unit and the second light-emitting unit.

17. A pixel driving circuit, wherein: The pixel driving circuit is configured to drive the light-emitting device to emit light, wherein the light-emitting device includes a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on a side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on a side of the second electrode away from the first electrode, and a third electrode located on a side of the second light-emitting unit away from the first electrode; The pixel driving circuit comprises: a driving subcircuit, electrically connected to the light emitting device; a data writing sub-circuit, electrically connected to the data signal terminal, the scan signal terminal and the driving sub-circuit, wherein the data writing sub-circuit is configured to write the data signal from the data signal terminal into the driving sub-circuit under the control of the scan signal from the scan signal terminal; a first light emitting control subcircuit electrically connected to the driving subcircuit, the first light emitting control signal terminal and the first electrode of the light emitting device; and The second light emitting control subcircuit is electrically connected to the second electrode, the second power supply terminal and the second light emitting control signal terminal of the light emitting device.

18. The pixel driving circuit according to claim 17, wherein: The driving subcircuit includes a third transistor; The first light emitting control subcircuit comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to a second electrode of the third transistor, a second electrode of the fifth transistor is electrically connected to a first electrode of the light emitting device, and a gate of the fifth transistor is electrically connected to the first light emitting signal control terminal; as well as The second light-emitting control subcircuit includes an eighth transistor, a first electrode of the eighth transistor is electrically connected to the second electrode of the light-emitting device, a second electrode of the eighth transistor is electrically connected to the second power supply terminal, and a gate of the eighth transistor is electrically connected to the second light-emitting signal control terminal.

19. A driving method for a pixel driving circuit, wherein: Applied to the pixel driving circuit according to claim 17 or 18, the driving method comprises: Under the control of the scan signal, the data writing subcircuit writes the data signal into the driving subcircuit; In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned on, the second light-emitting control subcircuit is turned on, and the first light-emitting control subcircuit and the second light-emitting control subcircuit control the driving subcircuit to output the driving current only to the first light-emitting unit; and In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control subcircuit is turned on, the second light-emitting control subcircuit is turned off, and the first light-emitting control subcircuit controls the driving subcircuit to output a driving current to the first light-emitting unit and the second light-emitting unit.

20. A display device, wherein: The display device comprises the display substrate according to any one of claims 1 to 12, or comprises the pixel driving circuit according to any one of claims 14 to 15 and 17 to 18.

Images