Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a display panel including a display area and a non-display area adjacent to one side of the display area; and a residual trace disposed on the display panel and disposed on the display area and the non-display area, in which an outer boundary of the residual trace is adjacent to an edge portion of the display panel and disposed closer to a central portion of the display panel than the edge portion of the display panel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0143011 filed in the Korean Intellectual Property Office on October 24, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] As the information-oriented society develops, more and more demands are placed on display devices for displaying images in various ways. The display device may be a flat panel display device such as a liquid crystal display, a field emission display, and a light emitting display.

[0005] The display device includes a display area for displaying an image and a non-display area disposed around the display area, for example, to surround the display area. Recently, the width of the non-display area has gradually decreased to increase immersion in the display area and enhance the aesthetics of the display device.

[0006] In a manufacturing process of the display device, the display device may be formed by cutting a mother substrate along a display unit formed on the mother substrate including the display unit.

[0007] The non-display area may include a first non-display area in which lines and circuits for driving the display area are arranged, and a second non-display area corresponding to a margin of a cutting process in a manufacturing process of the display device. Since there is a limitation in reducing the lines and circuits in the first non-display area, a method of reducing the width of the second non-display area is being studied. Summary of the invention

[0008] Aspects of the present disclosure provide a display device capable of minimizing the width of a non-display area and a method of manufacturing the display device.

[0009] Aspects of the present disclosure also provide a display device capable of improving process efficiency and process yield, and a method of manufacturing the display device.

[0010] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0011] According to aspects of the present disclosure, a display device is provided, comprising: a display panel including a display area and a non-display area adjacent to one side of the display area; and a residual trace disposed on the display panel and disposed on the display area and the non-display area, wherein an outer boundary of the residual trace may be adjacent to an edge portion of the display panel and disposed closer to a center portion of the display panel than the edge portion of the display panel.

[0012] In an embodiment, an outer boundary of the residual trace may be surrounded by an outer boundary of the display panel in a plan view.

[0013] In an embodiment, the display panel may include a crack dam adjacent to an edge portion of the display panel, and an outer boundary of the residual trace is closer to a central portion of the display panel than the crack dam.

[0014] In an embodiment, the display panel may include a through hole penetrating the display panel and disposed in the display area, and the residual trace may include an opening surrounding the through hole.

[0015] In an implementation, an opening of the residual trace may be larger than a through hole of the display panel in a plan view.

[0016] In an embodiment, in a plan view, the opening of the residual trace and the through hole of the display panel may have different sizes and the same shape.

[0017] According to aspects of the present disclosure, a display device is provided, comprising: a display panel comprising at least one conductive layer and at least one non-conductive layer disposed on the conductive layer; and a residual trace disposed on at least a portion of the non-conductive layer, wherein a transmittance of the non-conductive layer in a first region in which the residual trace is disposed may be different from a transmittance of the non-conductive layer in a second region in which the residual trace is not disposed.

[0018] In an embodiment, the residual trace may be smaller than the display panel in plan view.

[0019] In an implementation, the residual trace may include at least one of an acrylic resin, an epoxy resin, and a polyurethane resin.

[0020] In an implementation, the residual traces may be formed in a process in which a portion of the non-conductive layer is removed.

[0021] In an embodiment, the display panel may include a substrate, a light emitting element layer disposed on the substrate, and an encapsulation layer disposed on the light emitting element layer, wherein the residual trace may be disposed on the encapsulation layer.

[0022] In an embodiment, the encapsulation layer may include a first encapsulation inorganic layer, an encapsulation organic layer disposed on the first encapsulation inorganic layer, and a second encapsulation inorganic layer disposed on the encapsulation organic layer, and the residual trace may be disposed on the second encapsulation inorganic layer.

[0023] In an embodiment, the display panel may include a substrate, a light emitting element layer disposed on the substrate, an encapsulation layer disposed on the light emitting element layer, and a sensor electrode layer disposed on the encapsulation layer, wherein the residual trace may be disposed on the sensor electrode layer.

[0024] In an embodiment, the sensor electrode layer may include a sensor electrode and a sensor insulating layer, and the residual trace may be disposed on the sensor insulating layer.

[0025] According to aspects of the present disclosure, a method for manufacturing a display device is provided, the method comprising: forming a plurality of display units on a mother substrate; forming a coating on each of the plurality of display units; forming a plurality of first laser irradiation areas by irradiating a first laser to the mother substrate; attaching a protective film to the mother substrate; and cutting the mother substrate along the plurality of first laser irradiation areas by spraying an etchant on the mother substrate without a mask.

[0026] In an embodiment, forming the coating may include applying a resin and curing the resin.

[0027] In an embodiment, the resin may be applied by a printing process.

[0028] In an embodiment, the coating may include an inclined surface at the end of the coating.

[0029] In an embodiment, at the end of the coating, the angle of the tangent line relative to the inclined surface may be equal to or less than about 30 degrees.

[0030] In an embodiment, the coating layer may include an inclined portion adjacent to an end of the coating layer and a flat portion disposed on one side of the inclined portion.

[0031] In an embodiment, the method may further include removing the coating, wherein, when removing the coating, adhesion of the coating in the inclined portion may be greater than adhesion of the coating in the flat portion.

[0032] In an embodiment, the adhesion of the coating in the inclined portion may be about 10 gf / inch to about 150 gf / inch, and the adhesion of the coating in the flat portion may be about 5 gf / inch to about 10 gf / inch.

[0033] In an embodiment, the coating layer may include at least one of an acrylic resin, an epoxy resin, and a polyurethane resin.

[0034] In an embodiment, the coating may have an average thickness of about 40 μm to about 150 μm.

[0035] In an implementation, the protective film may include at least one of polyethylene terephthalate (PET), polypropylene (PP), polycarbonate, polyethylene (PE), and polyvinyl chloride (PVC).

[0036] In an implementation, the protection film may include an adhesive layer, and the adhesive layer may include at least one of a silicone-based, a polyurethane-based, and an acrylic-based material.

[0037] According to the display device and the method of manufacturing the display device according to embodiments, the width of the non-display area may be minimized.

[0038] In the display device and the method of manufacturing the display device according to the embodiments, process efficiency and process yield may be improved.

[0039] However, the effects according to the embodiments are not limited to those examples above, and various other effects are combined herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0041] Figure 1 is a schematic perspective view showing a display device according to an embodiment;

[0042] Figure 2 is a schematic plan view showing a display panel and a driving integrated circuit (IC) according to an embodiment;

[0043] Figure 3 It is along Figure 1 A schematic cross-sectional view taken along line X1-X1';

[0044] Figure 4 is shown in a bent state Figure 3 A schematic cross-sectional view of a display device;

[0045] Figure 5 is a schematic cross-sectional view showing an example of a display area of ​​a display device according to an embodiment;

[0046] Figure 6 yes Figure 2 An enlarged schematic diagram of region A;

[0047] Figure 7 It is along Figure 6 A schematic cross-sectional view taken along line X2-X2';

[0048] Figure 8 yes Figure 7 An enlarged schematic diagram of region C;

[0049] Fig. 9 yes Figure 2 An enlarged schematic diagram of region B;

[0050] Fig.10 It is along Fig. 9 A schematic cross-sectional view taken along line X3-X3';

[0051] Fig.11 yes Fig.10 An enlarged schematic diagram of region D;

[0052] Fig.12 is a photograph showing a process by which a residual trace of a display device according to an embodiment is formed;

[0053] Fig.13 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0054] Fig.14 is a schematic diagram showing the depth of a laser irradiation area formed by a laser processing apparatus according to an embodiment;

[0055] Fig.15 It is shown Fig.13 A schematic three-dimensional diagram of step S110;

[0056] Fig.16 It is shown Fig.13 A schematic three-dimensional diagram of step S120;

[0057] Fig.17 It is shown Fig.13 A schematic three-dimensional diagram of step S130;

[0058] Fig.18 It is shown Fig.13 A schematic three-dimensional diagram of step S140;

[0059] Fig.19 It is shown Fig.13 A schematic three-dimensional diagram of step S160;

[0060] Fig. 20 It is shown Fig.13 A schematic plan view of step S140;

[0061] Fig.21 It is shown Fig.13 A schematic three-dimensional diagram of step S160;

[0062] Fig. 22 It is shown Fig.13A schematic three-dimensional diagram of step S170;

[0063] Fig.23 It is shown Fig.13 A schematic cross-sectional view of step S120;

[0064] Fig.24 is a schematic cross-sectional view showing a coating layer according to an embodiment;

[0065] Fig.25 It is shown Fig.13 A schematic cross-sectional view of step S130;

[0066] Fig.26 It is shown Fig.13 A schematic cross-sectional view of step S160;

[0067] Fig. 27 It is shown Fig.13 A schematic cross-sectional view of step S160;

[0068] Fig.28 It is shown Fig.13 A schematic cross-sectional view of step S170;

[0069] Fig.29 It is shown Fig.13 A schematic cross-sectional view of step S120;

[0070] Fig.30 It is shown Fig.13 A schematic cross-sectional view of step S140;

[0071] Fig.31 It is shown Fig.13 A schematic cross-sectional view of step S160;

[0072] Fig.32 It is shown Fig.13 A schematic cross-sectional view of step S160;

[0073] Fig.33 It is shown Fig.13 A schematic cross-sectional view of step S170;

[0074] Fig.34 is a photograph showing a through hole and its vicinity according to a comparative example; and

[0075] Fig.35 is a photograph showing a through hole and its vicinity according to an embodiment. DETAILED DESCRIPTION

[0076] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or embodiments of the present invention. As used herein, "embodiment" and "embodiment" are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0077] Unless otherwise specified, the embodiments shown will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments, etc. (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0078] The use of cross hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise specified. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0079] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or directly coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there may be no intervening element or layer. For this purpose, the term "connection" may refer to a physical connection, electrical connection and / or fluid connection with or without an intervening element. In addition, the axis of the first direction, the axis of the second direction and the axis of the third direction are not limited to the three axes of a rectangular coordinate system, such as an X-axis, a Y-axis and a Z-axis, and may be interpreted in a broader sense. For example, the axis of the first direction, the axis of the second direction and the axis of the third direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0080] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0081] For the purpose of description, spatial relative terms such as "below", "below", "below", "lower", "above", "upper", "above", "higher", "side", (e.g., as in "sidewall"), etc. may be used herein, and thereby describe the relationship of one element to another (multiple) element as shown in the drawings. In addition to the orientation depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use, operation and / or manufacture. For example, if the device in the drawings is flipped, the elements described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the term "below" can include both the orientation above and below. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relative descriptors used herein should be interpreted accordingly.

[0082] The terms used herein are used to describe the purpose of a particular embodiment and are not intended to be limiting. As used herein, the singular forms "one", "a kind of" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include", "comprise", "include", "include" and / or "include" illustrate the existence of the features, integral bodies, steps, operations, elements, components and / or groups described, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as degree terms, and therefore, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0083] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein are not necessarily interpreted as being limited to the shapes of the specifically illustrated regions, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0084] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings according to function blocks, units and / or modules. It will be appreciated by those skilled in the art that these function blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the function blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each function block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. In addition, each function block, unit and / or module of some embodiments can be physically divided into two or more interactive and discrete function blocks, units and / or modules without departing from the scope of the present invention. Furthermore, the functional blocks, units and / or modules of some embodiments may be physically combined into more complex functional blocks, units and / or modules without departing from the scope of the present invention.

[0085] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0086] Figure 1 is a schematic perspective view showing a display device 10 according to an embodiment. Figure 2 2 is a schematic plan view showing a display panel 100 and a driving integrated circuit (IC) 200 according to an embodiment.

[0087] refer to Figure 1 and Figure 2 The display device 10 may be a device for displaying a moving image or a still image. The display device 10 may be used as a display screen of various devices such as a television, a laptop computer, a monitor, a billboard, and an Internet of Things (IOT) device, and portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC).

[0088] The display device 10 according to the embodiment may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, a micron light-emitting display using a micron light-emitting diode (LED), and a nano light-emitting display using a nano light-emitting diode (LED). In the following description, the display device 10 may be an organic light-emitting display device, but the embodiment is not limited thereto.

[0089] The display device 10 according to the embodiment may include a display panel 100 , a driving integrated circuit (IC) 200 , and a circuit board 300 .

[0090] In a plan view, the display panel 100 may be formed in a rectangular shape having a long side in a first direction (e.g., an X-axis direction) and a short side in a second direction (e.g., a Y-axis direction) intersecting the first direction (e.g., the X-axis direction). A corner portion formed by the long side in the first direction (e.g., the X-axis direction) and the short side in the second direction (e.g., the Y-axis direction) may be right-angled or rounded with a certain curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0091] In the accompanying drawings, the first direction (e.g., X-axis direction) and the second direction (e.g., Y-axis direction) may intersect each other and may be horizontal directions. For example, the first direction (e.g., X-axis direction) and the second direction (e.g., Y-axis direction) may be orthogonal to each other. For example, the third direction (e.g., Z-axis direction) may intersect with the first direction (e.g., X-axis direction) and the second direction (e.g., Y-axis direction) and may be a vertical direction. In this specification, the direction indicated by the arrow from the first direction to the third direction (e.g., X-axis direction, Y-axis direction, and Z-axis direction) may be referred to as one side, and the direction opposite thereto may be referred to as the other side.

[0092] The display panel 100 may be formed to be flat, but the embodiment is not limited thereto. For example, the display panel 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. For example, the display panel 100 may be flexibly formed so that it may be curved, bent, folded, or rolled.

[0093] The display panel 100 may include a display area DA displaying an image and a non-display area NDA disposed around the display area DA. The display area DA and the non-display area NDA may form a main area MA.

[0094] The display area DA may occupy most of the area of ​​the display panel 100. The display area DA may be disposed at the center of the display panel 100. Pixels each including an emission area may be disposed in the display area DA to display an image.

[0095] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be disposed to surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100.

[0096] The display pads PD may be arranged in the non-display area NDA to be connected to the circuit board 300. The display pads PD may be provided on a side edge portion of the display panel 100. For example, the display pads PD may be provided at a lower edge portion of the display panel 100.

[0097] The driving IC 200 may generate a data voltage, a source voltage, a scan timing signal, etc. The driving IC 200 may output a data voltage, a source voltage, a scan timing signal, etc.

[0098] The driver IC 200 may be disposed between the display pad PD and the display area DA in the non-display area NDA. Each of the driver ICs 200 may be attached to the non-display area NDA of the display panel 100 in a chip on glass (COG) method. In another example, each of the driver ICs 200 may be attached to the circuit board 300 in a chip on plastic (COP) method.

[0099] The circuit board 300 may be disposed on the display pad PD disposed on the side edge portion of the display panel 100. The circuit board 300 may be attached to the display pad PD by using a conductive adhesive member such as an anisotropic conductive film and an anisotropic conductive adhesive. Thus, the circuit board 300 may be electrically connected to the signal line of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

[0100] Figure 3 It is along Figure 1 A schematic cross-sectional view taken along line X1-X1'. Figure 4 is shown in a bent state Figure 3 Schematic cross-sectional view of a display device 10.

[0101] Apart from Figure 1 and Figure 2 In addition, reference Figure 3 and Figure 4 The display device 10 according to the embodiment may include a display panel 100, a polarizing film PF, a cover window CW, a panel cover PB, a driving IC 200, and a circuit board 300. The display panel 100 may include a substrate SUB, a display layer DISL, an encapsulation layer ENC, and a sensor electrode layer SENL.

[0102] The substrate SUB may have a hard material. For example, the substrate SUB may be made of glass. The substrate SUB may be formed of ultra-thin glass (UTG) having a thickness of about 500 μm or less. For example, the thickness of the substrate SUB may be about 200 μm. In another embodiment, the substrate SUB may include a first substrate made of a hard material and a second substrate made of a polymer resin made of a flexible material.

[0103] The display layer DISL may be disposed on the first surface of the substrate SUB. The display layer DISL may be a layer that displays an image. The display layer DISL may include a thin film transistor layer TFTL (see FIG. 1 ) in which a thin film transistor is formed. Figure 5 ) and a light emitting element layer EML in which a light emitting element emitting light is provided in the emission region (see Figure 5 ).

[0104] In the display area DA of the display layer DISL, a scan line, a data line, a power line, etc. of an emission area for emitting light may be provided. In the non-display area NDA of the display layer DISL, a scan driving circuit unit for outputting a scan signal to the scan line, a fan-out line connecting the data line and the driver IC 200, etc. may be provided.

[0105] The encapsulation layer ENC may be a layer for encapsulating the light emitting element layer EML of the display layer DISL to prevent oxygen or moisture from penetrating into the light emitting element layer EML of the display layer DISL. The encapsulation layer ENC may be disposed on the display layer DISL. The encapsulation layer ENC may be disposed on the top surface (or upper surface) and the side surface of the display layer DISL. The encapsulation layer ENC may be disposed to cover the display layer DISL.

[0106] The sensor electrode layer SENL may be disposed on the display layer DISL. The sensor electrode layer SENL may include sensor electrodes. The sensor electrode layer SENL may sense a user's touch using the sensor electrodes.

[0107] The polarizing film PF may be disposed on the sensor electrode layer SENL. The polarizing film PF may be disposed on the display panel 100 to reduce reflection of external light. The polarizing film PF may include a first base member, a linear polarizing plate, a phase delay film (such as a quarter wave plate (λ / 4 plate)), and a second base member. The first base member, the phase delay film, the linear polarizing plate, and the second base member of the polarizing film PF may be sequentially stacked on the display panel 100.

[0108] The cover window CW may be disposed on the polarizing film PF. The cover window CW may be attached to the polarizing film PF by a transparent adhesive member such as an optically clear adhesive (OCA) film.

[0109] The panel cover PB may be disposed on a second surface of the substrate SUB of the display panel 100. The second surface of the substrate SUB may be a surface opposite to the first surface. The panel cover PB may be attached to the second surface of the substrate SUB of the display panel 100 by an adhesive member. The adhesive member may be a pressure sensitive adhesive (PSA).

[0110] The panel cover under PB may include at least one of a light blocking member for absorbing light incident from the outside, a buffer member for absorbing impact from the outside, and a heat dissipation member for effectively dissipating heat from the display panel 100 .

[0111] like Figure 4 As shown in FIG. 1 , the circuit board 300 may be bent downward from the display panel 100. The circuit board 300 may be attached to the bottom surface (or lower surface) of the panel lower cover PB by an adhesive member 310. The adhesive member 310 may be a pressure sensitive adhesive.

[0112] The display device 10 may further include a through hole TH and an optical device OPD disposed in the through hole TH.

[0113] The through hole TH may be a hole capable of transmitting light, and may be a physical hole that penetrates not only the display panel 100 but also the panel cover PB and the polarizing film PF. For example, the through hole TH may penetrate the substrate SUB, the display layer DISL, the encapsulation layer ENC, and the sensor electrode layer SENL of the display panel 100. However, the embodiment is not limited thereto, and the through hole TH may penetrate the panel cover PB, but may not penetrate the display panel 100 and the polarizing film PF. The cover window CW may be provided to cover the through hole TH.

[0114] The optical device OPD may be spaced apart from the display panel 100, the panel cover PB, and the polarization film PF. The optical device OPD may be an optical sensor that senses light incident through the through hole TH, such as a proximity sensor, an illumination sensor, and a camera sensor.

[0115] The display device 10 according to the embodiment may include a residual trace line RSD disposed on the display panel 100. For example, the residual trace line RSD may be disposed between the display panel 100 and the polarizing film PF. The residual trace line RSD may be a residual trace line RSD in a manufacturing method S1 (see FIG. 1 ) for a display device to be described later. Fig.13 ) to remove the coating (non-conductive layer) CTL (see Fig.16 ) is formed in the case of removal traces.

[0116] In some embodiments, as shown in the drawings, the residual trace line RSD may be disposed on the sensor electrode layer SENL. However, embodiments are not limited thereto, and in the case where the sensor electrode layer SENL is omitted, the residual trace line RSD may be disposed on the encapsulation layer ENC.

[0117] Figure 5 is a schematic cross-sectional view showing an example of a display area of ​​the display device 10 according to the embodiment.

[0118] refer to Figure 5 , the display device 10 according to the embodiment may include a display panel 100 , a polarizing film PF, and a cover window CW.

[0119] In an embodiment, the display panel 100 may be an organic light emitting display panel having a light emitting element LEL including a light emitting layer 172. The display panel 100 may include a substrate SUB, a display layer DISL, an encapsulation layer ENC, and a sensor electrode layer SENL. The display layer DISL may include a thin film transistor layer TFTL including a thin film transistor and a light emitting element layer EML including a light emitting element LEL.

[0120] The substrate SUB may have a hard material. For example, the substrate SUB may be made of glass. The substrate SUB may be formed of ultra-thin glass (UTG) having a thickness of about 500 μm or less. For example, the thickness of the substrate SUB may be about 200 μm. In another embodiment, the substrate SUB may include a first substrate made of a hard material and a second substrate made of a polymer resin made of a flexible material.

[0121] The display layer DISL may include a thin film transistor layer TFTL including a thin film transistor and a light emitting element layer EML including a light emitting element LEL.

[0122] The thin film transistor layer TFTL may include a first buffer layer BF1 , a thin film transistor TFT, a gate insulating layer 130 , a first interlayer insulating layer 141 , a capacitor Cst, a second interlayer insulating layer 142 , a first data metal layer, a first organic layer 160 , a second data metal layer, and a second organic layer 180 .

[0123] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may be formed of an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. In another example, the first buffer layer BF1 may be formed as a multilayer in which a plurality of layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0124] An active layer including a channel region TCH, a source region TS, and a drain region TD of the thin film transistor TFT may be disposed on the first buffer layer BF1. The active layer may be formed of polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material. In the case where the active layer includes polycrystalline silicon or an oxide semiconductor material, the source region TS and the drain region TD of the active layer may be conductive regions doped with ions or impurities and having conductivity.

[0125] The gate insulating layer 130 may be disposed on the active layer of the thin film transistor TFT. The gate insulating layer 130 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0126] A first gate metal layer including a scan line, a gate electrode TG of the thin film transistor TFT, and a first capacitor electrode CAE1 of the capacitor Cst may be disposed on the gate insulating layer 130. The gate electrode TG of the thin film transistor TFT may overlap the channel region TCH in a third direction (e.g., Z-axis direction). The first gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0127] The first interlayer insulating layer 141 may be disposed on the first gate metal layer. The first interlayer insulating layer 141 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating layer 141 may include an inorganic layer.

[0128] The second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst may be disposed on the first interlayer insulating layer 141. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 in a third direction (e.g., the Z-axis direction). Therefore, the capacitor Cst may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and an inorganic insulating dielectric layer disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2 to serve as a dielectric layer. The second gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0129] The second interlayer insulating layer 142 may be disposed on the second gate metal layer. The second interlayer insulating layer 142 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating layer 142 may include an inorganic layer.

[0130] A first data metal layer including a first connection electrode CE1 and a data line may be disposed on the second interlayer insulating layer 142. The first connection electrode CE1 may be connected to the drain region TD through a first contact hole CT1 penetrating the gate insulating layer 130, the first interlayer insulating layer 141, and the second interlayer insulating layer 142. The first data metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0131] A first organic layer 160 for flattening a stepped portion due to the thin film transistor TFT may be disposed on the first data metal layer. The first organic layer 160 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0132] The second data metal layer including the second connection electrode CE2 may be disposed on the first organic layer 160. The second data metal layer may be connected to the first connection electrode CE1 through a second contact hole CT2 penetrating the first organic layer 160. The second data metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0133] The second organic layer 180 may be disposed on the second data metal layer. The second organic layer 180 may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0134] For example, the second data metal layer including the second link electrode CE2 and the second organic layer 180 may be omitted.

[0135] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element LEL and a pixel defining layer 190 .

[0136] Each of the light emitting elements LEL may include a pixel electrode 171, a light emitting layer 172, and a common electrode 173. Each of the emission areas EA may be a region where the pixel electrode 171, the light emitting layer 172, and the common electrode 173 are sequentially stacked so that holes from the pixel electrode 171 and electrons from the common electrode 173 may be combined with each other to emit light. For example, the pixel electrode 171 may be an anode electrode, and the common electrode 173 may be a cathode electrode.

[0137] A pixel electrode layer including a pixel electrode 171 may be formed on the second organic layer 180. The pixel electrode 171 may be connected to the second connection electrode CE2 through a third contact hole CT3 penetrating the second organic layer 180. The pixel electrode layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0138] In a top emission structure (or upper emission member) that emits light toward the common electrode 173 relative to the light emitting layer 172, the pixel electrode 171 may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0139] The pixel defining layer 190 may be used to define the emission area EA of the pixel. For example, the pixel defining layer 190 may be formed to expose a partial area of ​​the pixel electrode 171 on the second organic layer 180. The pixel defining layer 190 may cover an edge portion of the pixel electrode 171. The pixel defining layer 190 may be disposed in the third contact hole CT3. For example, the third contact hole CT3 may be filled with the pixel defining layer 190. The pixel defining layer 190 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0140] The spacer 191 may be disposed on the pixel defining layer 190. The spacer 191 may be used to support a mask during a process of manufacturing the light emitting layer 172. The spacer 191 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0141] The light emitting layer 172 may be formed on the pixel electrode 171. The light emitting layer 172 may include an organic material to emit light of a selected color. For example, the light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits selected light and may be formed using a phosphorescent material or a fluorescent material.

[0142] The common electrode 173 may be formed on the light emitting layer 172. The common electrode 173 may be formed to cover the light emitting layer 172. The common electrode 173 may be a common layer commonly formed in the emission area EA. A capping layer may be formed on the common electrode 173.

[0143] In the top emission structure (or upper emission member), the common electrode 173 may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In the case where the common electrode 173 is formed of a semi-transmissive conductive material, light emission efficiency may be improved due to a microcavity effect.

[0144] The encapsulation layer (non-conductive layer) ENC may be disposed on the light emitting element layer EML. The encapsulation layer ENC may include at least one inorganic layer TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EML. For example, the encapsulation layer ENC may include at least one encapsulation organic layer TFE2 to protect the light emitting element layer EML from impurities such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0145] The first encapsulation inorganic layer TFE1 may be disposed on the common electrode 173, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The encapsulation organic layer TFE2 may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0146] The sensor electrode layer (non-conductive layer) SENL may be disposed on the encapsulation layer ENC. The sensor electrode layer SENL may include a second buffer layer BF2, a first connection portion BE1, a first sensor insulating layer TINS1, sensor electrodes TE and RE, and a second sensor insulating layer TINS2. For example, the sensor electrode TE may be connected to the first connection portion BE1 through a contact hole TCNT1 passing through the first sensor insulating layer TINS1.

[0147] The second buffer layer BF2 may be disposed on the encapsulation layer ENC. The second buffer layer BF2 may include at least one inorganic layer. For example, the second buffer layer BF2 may be formed by a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The second buffer layer BF2 may be omitted.

[0148] The first connection portion BE1 may be disposed on the second buffer layer BF2. The first connection portion BE1 may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stack structure of aluminum and titanium (Ti / Al / Ti), a stack structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stack structure of an APC alloy and ITO (ITO / APC / ITO).

[0149] The first sensor insulating layer TINS1 may be disposed on the first connection portion BE1. The first sensor insulating layer TINS1 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0150] The sensor electrodes such as the driving electrode TE and the sensing electrode RE may be disposed on the first sensor insulating layer TINS1. For example, the dummy pattern may be disposed on the first sensor insulating layer TINS1. The driving electrode TE, the sensing electrode RE, and the dummy pattern may not overlap with the emission area EA. The driving electrode TE, the sensing electrode RE, and the dummy pattern may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0151] The second sensor insulating layer TINS2 may be disposed on the driving electrode TE, the sensing electrode RE, and the dummy pattern. The second sensor insulating layer TINS2 may include at least one of an inorganic layer and an organic layer. The inorganic layer may be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. The organic layer may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0152] The polarizing film PF may be disposed on the sensor electrode layer SENL. The polarizing film PF may be disposed on the display panel 100 to reduce (or minimize) reflection of external light. The polarizing film PF may include a first base member, a linear polarizing plate, a phase delay film (such as a quarter wave plate (λ / 4 plate)), and a second base member. The first base member, the phase delay film, the linear polarizing plate, and the second base member of the polarizing film PF may be sequentially stacked on the display panel 100.

[0153] The cover window CW may be disposed on the polarizing film PF. The cover window CW may be attached to the polarizing film PF by a transparent adhesive member such as an optically clear adhesive (OCA) film.

[0154] The display device 10 according to an embodiment may include a residual trace line RSD. The residual trace line RSD may be disposed on the display panel 100. For example, as shown in the figure, the residual trace line RSD may be disposed on the sensor electrode layer SENL. In an embodiment, the residual trace line RSD may be disposed on the second sensor insulating layer TINS2.

[0155] However, the embodiment is not limited thereto, and in the case where the display device 10 does not include the sensor electrode layer SENL, the residual trace line RSD may be disposed on the encapsulation layer ENC. In another embodiment, the residual trace line RSD may be disposed on the second encapsulation inorganic layer TFE3 (see Figure 8 ).

[0156] Figure 6 yes Figure 2 An enlarged schematic diagram of area A. Figure 7 It is along Figure 6 A schematic cross-sectional view taken along line X2-X2'.

[0157] Apart from Figure 5 In addition, reference Figure 6 and Figure 7 , the display area DA may include emission areas EA1, EA2, EA3, and EA4. The emission areas EA1, EA2, EA3, and EA4 may include a first emission area EA1 that emits light of a first color, a second emission area EA2 and a fourth emission area EA4 that emit light of a second color, and a third emission area EA3 that emits light of a third color. For example, the light of the first color may be light in a red wavelength band of about 600nm to about 750nm, the light of the second color may be light in a green wavelength band of about 480nm to about 560nm, and the light of the third color may be light in a blue wavelength band of about 370nm to about 460nm, but the embodiment is not limited thereto.

[0158] Figure 6 The second emission area EA2 and the fourth emission area EA4 are shown to emit light of the same color, such as light of the second color. However, the embodiment is not limited thereto. The second emission area EA2 and the fourth emission area EA4 may emit light of different colors. For example, the second emission area EA2 may emit light of the second color, and the fourth emission area EA4 may emit light of the fourth color.

[0159] For example, in Figure 6 , although each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 is shown to have a rectangular plan shape, the embodiment is not limited thereto. In the plan view, each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may have a polygonal shape other than a quadrilateral shape, a circular shape, or an elliptical shape.

[0160] In some embodiments, the third emission area EA3 may have the largest area (or size), and the second emission area EA2 and the fourth emission area EA4 may have the smallest area (or size). The area (or size) of the second emission area EA2 and the area (or size) of the fourth emission area EA4 may be the same as each other, but the embodiment is not limited thereto.

[0161] The second emission area EA2 and the fourth emission area EA4 may be alternately disposed in the first direction (eg, X-axis direction). The second emission area EA2 may be disposed in the second direction (eg, Y-axis direction). The fourth emission area EA4 may be disposed in the second direction (eg, Y-axis direction).

[0162] The first emission area EA1 and the third emission area EA3 may be alternately arranged in a first direction (e.g., an X-axis direction). The first emission area EA1 may be arranged in a second direction (e.g., a Y-axis direction). The third emission area EA3 may be arranged in the second direction (e.g., a Y-axis direction). Each of the first emission area EA1 and the third emission area EA3 may have a square planar shape, but the embodiment is not limited thereto.

[0163] The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may be an area in which a structure for driving pixels of the display area DA is disposed. The second non-display area NDA2 may be disposed outside the first non-display area NDA1. The second non-display area NDA2 may be an area outside the non-display area NDA. For example, the second non-display area NDA2 may be an area outside the display panel 100.

[0164] The first non-display area NDA1 may include a scan driving circuit unit SDC, a first power line VSL, a first dam DAM1, and a second dam DAM2.

[0165] The scan driving circuit unit SDC may include a stage STA. The stage STA may be respectively connected to the scan lines extending in the first direction (e.g., the X-axis direction) of the display area DA. For example, the stage STA may be connected one-to-one to the scan lines extending in the first direction (e.g., the X-axis direction) of the display area DA. The stage STA may sequentially apply scan signals to the scan lines.

[0166] The first power line VSL may be disposed outside the scan driving circuit unit SDC. For example, the first power line VSL may be disposed closer to the edge portion EG of the display panel 100 than the scan driving circuit unit SDC. The first power line VSL may extend in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the right side of the display panel 100.

[0167] The first power line VSL may be electrically connected to the common electrode 173 so that the common electrode 173 may be supplied with the first source voltage from the first power line VSL.

[0168] The first and second dams DAM1 and DAM2 may be structures for preventing the encapsulation organic layer TFE2 of the encapsulation layer ENC from overflowing into the edge portion EG of the display panel 100 .

[0169] The first dam DAM1 may be disposed to surround the display area DA, and the second dam DAM2 may be disposed to surround the first dam DAM1. Figure 6 As shown in , the first dam DAM1 and the second dam DAM2 may extend in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the right side of the display panel 100. The second dam DAM2 may be disposed outside the first dam DAM1. For example, the first dam DAM1 and the second dam DAM2 may also be disposed in the non-display area NDA on the upper side, the lower side, and the left side of the display panel 100. The first dam DAM1 and the second dam DAM2 may extend in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the left side of the display panel 100, and may extend in the first direction (e.g., the X-axis direction) in the non-display area NDA on the upper side and the lower side of the display panel 100.

[0170] The first dam DAM1 may be disposed closer to the scan driving circuit unit SDC than the second dam DAM2 , and the second dam DAM2 may be disposed closer to the edge portion EG of the display panel 100 than the first dam DAM1 .

[0171] although Figure 6 It is shown that the first dam DAM1 and the second dam DAM2 are disposed on the first power line VSL, but the embodiment is not limited thereto. For example, either the first dam DAM1 or the second dam DAM2 may not be disposed on the first power line VSL. In another example, neither the first dam DAM1 or the second dam DAM2 may be disposed on the first power line VSL. For example, the first dam DAM1 or the second dam DAM2 may be disposed outside the first power line VSL.

[0172] For example, despite Figure 6 It is shown that the display panel 100 according to the embodiment includes two dams DAM1 and DAM2, but the embodiment is not limited thereto. For example, the display panel 100 according to the embodiment may include three or more dams.

[0173] The second non-display area NDA2 may include a crack dam CRD and an edge area EGA.

[0174] The crack dam CRD may be a structure for preventing cracks from extending in a process of cutting the substrate SUB during a manufacturing process of the display device 10. For example, the crack dam CRD may be a structure for preventing cracks from extending in an inorganic layer of the encapsulation layer ENC.

[0175] The crack dam CRD may be disposed in the second non-display area NDA2 and may be disposed outside the first and second dams DAM1 and DAM2. For example, the crack dam CRD may be disposed closer to the edge portion EG of the display panel 100 than the first and second dams DAM1 and DAM2.

[0176] The crack dam CRD may be disposed along the left edge portion, the upper edge portion, and the right edge portion of the display panel 100. Figure 6 As shown in , the crack dam CRD may extend in a second direction (e.g., Y-axis direction) in the non-display area NDA on the right side of the display panel 100. For example, the crack dam CRD may also be provided in the non-display area NDA on the upper and left sides of the display panel 100. The crack dam CRD may extend in a second direction (e.g., Y-axis direction) in the non-display area NDA on the left side of the display panel 100, and may extend in a first direction (e.g., X-axis direction) in the non-display area NDA on the upper side of the display panel 100. The crack dam CRD may not be provided on the lower edge portion of the display panel 100. However, the embodiment is not limited thereto, and in another embodiment, the crack dam CRD may also be provided in the non-display area NDA below the display panel 100. For example, the crack dam CRD may extend in a first direction (e.g., X-axis direction).

[0177] The edge area EGA may be provided along the edge portion EG of the display panel 100. The edge area EGA may be an area in which a process trace generated in a process of cutting the substrate SUB is generated. For example, in the case where the substrate SUB is cut by spraying an etchant after laser irradiation by a laser processing device, the edge area EGA may be an area in which a process trace is formed on the top surface (or upper surface) US of the substrate SUB by the etchant. The width of the edge area EGA may be within about 30 μm, but the embodiment is not limited thereto.

[0178] like Figure 7 As shown in , the edge area EGA may include a first inclined surface IP1_1 formed by spraying an etchant after laser irradiation. The angle θ1 between the side surface SS1 and the top surface (or upper surface) US may be within about 90 degrees. For example, the angle θ1 between the side surface SS1 and the top surface (or upper surface) US may be substantially a right angle. The angle θ2 between the side surface SS1 and the first inclined surface IP1_1 and the angle θ3 between the first inclined surface IP1_1 and the bottom surface (or lower surface) BS may be an obtuse angle. The process traces formed on the top surface (or upper surface) US of the substrate SUB may overlap with the first inclined surface IP1_1 in a third direction (e.g., the Z-axis direction).

[0179] However, the embodiment is not limited thereto, and in some embodiments, the first inclined surface IP1_1 may be omitted. According to the manufacturing process of the display device 10, the first inclined surface IP1_1 may not be formed, and only the side surface SS1 may be provided between the top surface (or upper surface) US and the bottom surface (or lower surface) BS. For example, the side surface SS1 may have a curved shape as well as a flat surface. Hereinafter, in order to simplify the description, a case where the first inclined surface IP1_1 is included will be described as an example.

[0180] In the case of cutting the substrate SUB of the display panel 100 by spraying an etchant after irradiation of laser, the minimum distance D1 from the crack dam CRD to the edge area EGA of the display panel 100 can be reduced compared to the case of performing a polishing process after cutting the substrate SUB with a cutting member. Therefore, in the case of cutting the substrate SUB of the display panel 100 by spraying an etchant after irradiation of laser, the width of the second non-display area NDA2 can be significantly reduced. For example, the width of the non-display area NDA can be minimized.

[0181] In the display device 10 according to the embodiment, the residual trace line RSD may be disposed throughout the display area DA and the non-display area NDA For example, the residual trace line RSD may be disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2.

[0182] In some embodiments, Figure 6 As shown in , the residual trace line RSD may be disposed on the emission areas EA1, EA2, EA3, and EA4, the scan driving circuit unit SDC, the first power line VSL, the first dam DAM1, and the second dam DAM2. The residual trace line RSD may overlap the emission areas EA1, EA2, EA3, and EA4, the scan driving circuit unit SDC, the first power line VSL, the first dam DAM1, and the second dam DAM2 in a third direction (e.g., the Z-axis direction).

[0183] In some embodiments, Figure 7 As shown in , the residual trace RSD may not be disposed on the crack dam CRD, the edge area EGA, and the first inclined surface IP1_1. For example, the residual trace RSD may not overlap the crack dam CRD, the edge area EGA, and the first inclined surface IP1_1 in a third direction (eg, Z-axis direction).

[0184] In some embodiments, Figure 6As shown in , the outer boundary RSDa of the residual trace line RSD may be disposed along the left edge portion, the upper edge portion, the right edge portion, and the lower edge portion of the display panel 100. For example, the outer boundary RSDa of the residual trace line RSD may be closer to the center portion of the display panel 100 than the left edge portion, the upper edge portion, the right edge portion, and the lower edge portion of the display panel 100. For example, as Figure 6 As shown in , the outer boundary RSDa of the residual trace line RSD may extend in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the right side of the display panel 100. For example, the outer boundary RSDa of the residual trace line RSD may extend in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the left side of the display panel 100, and may extend in the first direction (e.g., the X-axis direction) in the non-display area NDA on the upper and lower sides of the display panel 100.

[0185] In some embodiments, the outer boundary RSDa of the residual trace RSD may be disposed inside the crack dam CRD. For example, the outer boundary RSDa of the residual trace RSD may be disposed inside the crack dam CRD at the left edge portion, the upper edge portion, the right edge portion, and the lower edge portion of the display panel 100. For example, the outer boundary RSDa of the residual trace RSD may be closer to the center portion of the display panel 100 than the crack dam CRD at the left edge portion, the upper edge portion, the right edge portion, and the lower edge portion of the display panel 100.

[0186] In some embodiments, the display device 10 may include a residual area RA in which the residual trace RSD is disposed, and a non-residual area NRA in which the residual trace RSD is not disposed.

[0187] The residual area RA may be an area inside (or defined by) the outer boundary RSDa of the residual trace RSD. The non-residual area NRA may be an area outside the outer boundary RSDa of the residual trace RSD.

[0188] In some embodiments, the residual area RA may be disposed inside the edge area EGA in a plan view. Figure 6As shown in , the residual area RA may be disposed on the other side of the edge area EGA in the first direction (e.g., the X-axis direction) in the non-display area NDA on the right side of the display panel 100. For example, the residual area RA may be disposed on one side of the edge area EGA in the first direction (e.g., the X-axis direction) in the non-display area NDA on the left side of the display panel 100, may be disposed on the other side of the edge area EGA in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the upper side of the display panel 100, and may be disposed on one side of the edge area EGA in the second direction (e.g., the Y-axis direction) in the non-display area NDA on the lower side of the display panel 100.

[0189] Figure 8 yes Figure 7 An enlarged schematic diagram of area C.

[0190] refer to Figure 8 , the crack dam CRD and the first organic layer 160 may include the same material. The crack dam CRD may be disposed on the first buffer layer BF1. The crack dam CRD may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0191] although Figure 8 The crack dam CRD is shown to include an organic film layer, but the embodiment is not limited thereto. For example, the crack dam CRD may further include another organic film layer. The other organic film layer of the crack dam CRD and the second organic layer 180 may include the same material. In another example, the crack dam CRD may further include another organic film layer. The other organic film layer of the crack dam CRD and the pixel defining layer 190 may include the same material. In another example, the crack dam CRD may further include another organic film layer. The other organic film layer of the crack dam CRD and the spacer 191 (see Figure 5 ) may comprise the same materials.

[0192] The first power line VSL and the first data metal layer including the first connection electrode CE1 and the data line may include the same material. The first power line VSL and the first data metal layer including the first connection electrode CE1 and the data line may be disposed on the same layer (at the same level). The first power line VSL may be disposed on the second interlayer insulating layer 142. The first power line VSL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0193] The first dam DAM1 and the second dam DAM2 may be disposed on the first power line VSL. The first dam DAM1 may include a first sub-dam SDAM1 and a second sub-dam SDAM2, and the second dam DAM2 may include a first sub-dam SDAM1, a second sub-dam SDAM2, and a third sub-dam SDAM3. The first sub-dam SDAM1 and the first organic layer 160 may include the same material and may be disposed on the same layer (at the same level). The second sub-dam SDAM2 and the second organic layer 180 may include the same material and may be disposed on the same layer (at the same level). The third sub-dam SDAM3 and the pixel defining layer 190 may include the same material and may be disposed on the same layer (at the same level).

[0194] The height of the first dam DAM1 may be lower than that of the second dam DAM2 , but the embodiment is not limited thereto. The height of the first dam DAM1 may be substantially the same as that of the second dam DAM2 , or may be higher than that of the second dam DAM2 .

[0195] The common electrode 173 may be connected to the first power line VSL exposed without being covered by the first organic layer 160 , the second organic layer 180 , and the first dam DAM1 . Therefore, the common electrode 173 may be supplied with the first source voltage of the first power line VSL.

[0196] The first encapsulation inorganic layer TFE1 may cover the first dam DAM1, the second dam DAM2, and the crack dam CRD in the non-display area NDA. In an embodiment, the first encapsulation inorganic layer TFE1 may extend in the non-display area NDA to be adjacent to the edge portion EG of the display panel 100. A side of the first encapsulation inorganic layer TFE1 may be disposed to align and overlap with a side of the substrate SUB.

[0197] However, the embodiment is not limited thereto, and in another embodiment, the first encapsulation inorganic layer TFE1 may not cover at least one of the second dam DAM2 and the crack dam CRD. For example, the first encapsulation inorganic layer TFE1 may not cover the crack dam CRD. In another example, an end of the first encapsulation inorganic layer TFE1 may be disposed inside the crack dam CRD. For example, an end of the first encapsulation inorganic layer TFE1 may be closer to the display panel 100 than the crack dam CRD.

[0198] The encapsulation organic layer TFE2 may be provided to cover the top surface (or upper surface) of the first dam DAM1, but not to cover the top surface (or upper surface) of the second dam DAM2. However, the embodiment is not limited thereto. The encapsulation organic layer TFE2 may not cover both the top surface (or upper surface) of the first dam DAM1 and the top surface (or upper surface) of the second dam DAM2. Due to the first dam DAM1 and the second dam DAM2, the encapsulation organic layer TFE2 may not overflow to the edge portion EG of the display panel 100.

[0199] The second encapsulation inorganic layer TFE3 may cover the first dam DAM1, the second dam DAM2, and the crack dam CRD in the non-display area NDA. In an embodiment, the second encapsulation inorganic layer TFE3 may extend in the non-display area NDA to be adjacent to the edge portion EG of the display panel 100. The side of the second encapsulation inorganic layer TFE3 may be disposed to align and overlap with the side of the substrate SUB.

[0200] However, the embodiment is not limited thereto, and in another embodiment, the second encapsulation inorganic layer TFE3 may not cover at least one of the second dam DAM2 and the crack dam CRD. For example, the second encapsulation inorganic layer TFE3 may not cover the crack dam CRD. In another example, an end of the second encapsulation inorganic layer TFE3 may be disposed inside the crack dam CRD. For example, an end of the second encapsulation inorganic layer TFE3 may be closer to the central portion of the display panel 100 than the crack dam CRD.

[0201] An inorganic encapsulation region in which the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 contact each other may be formed from the second dam DAM2 to the edge portion EG of the display panel 100. The inorganic encapsulation region may be disposed to surround the second dam DAM2.

[0202] exist Figure 8 In the embodiment, the scanning thin film transistor STFT of the scanning driving circuit unit SDC may be an example. For example, the scanning thin film transistor STFT may include a gate electrode STG, a channel region STCH, a source region STS, and a drain region STD. For example, the channel region STCH, the source region STS, and the drain region STD may be disposed on the first buffer layer BF1, and the gate electrode STG may overlap with the channel region STCH in a third direction (e.g., the Z-axis direction). Since the scanning thin film transistor STFT is basically combined with Figure 5 The described thin film transistors TFT are the same, so the description of the scanning thin film transistor STFT will be omitted.

[0203] In the display device 10 according to the embodiment, the thickness of the residual trace RSD may be several nanometers to several tens of nanometers. In the embodiment, in the manufacturing method S1 (see FIG. 1 ) for the display device to be described later, Fig.13), the residual trace RSD and coating CTL (see Fig.16 ) may include the same material. In another embodiment, the residual trace RSD and the layer below the residual trace RSD may include the same material. For example, the residual trace RSD and the second encapsulation inorganic layer TFE3 may include the same material. The residual trace RSD and the second sensor insulation layer TINS2 may include the same material.

[0204] As an example, in the coating CTL (see Fig.16 ) is removed, a residual trace RSD may be formed as a portion of the coating CTL is left behind. As another example, in the case where the coating CTL (see Fig.16 ) is removed, a residual trace line RSD may be formed as a portion of a layer below the residual trace line RSD is removed together with the coating layer CTL.

[0205] Fig. 9 yes Figure 2 An enlarged schematic diagram of area B. Fig.10 It is along Fig. 9 A schematic cross-sectional view taken along line X3-X3'. Fig.11 yes Fig.10 An enlarged schematic diagram of area D.

[0206] refer to Figures 9 to 11 , the display panel 100 according to the embodiment may include an inorganic encapsulation area IEA surrounding the through hole TH and a wiring area WLA surrounding the inorganic encapsulation area IEA.

[0207] The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 of the encapsulation layer ENC may contact each other so that the inorganic encapsulation area IEA may be a layer for preventing oxygen or moisture from penetrating into the light emitting element layer EML of the display layer DISL due to the through hole TH.

[0208] The inorganic encapsulation area IEA may include at least one dam, at least one tip portion, and at least one groove. Fig.11 As shown in FIG. , the inorganic encapsulation area IEA may include a first hole dam HDAM1 , a second hole dam HDAM2 , first to eighth tip portions T1 to T8 , and first to third grooves GR1 to GR3 .

[0209] The first tip portion T1 and the second tip portion T2 may be disposed closer to the wiring area WLA than the first hole dam HDAM1. The first tip portion T1 may be disposed closer to the wiring area WLA than the second tip portion T2. ​​The second tip portion T2 may be disposed between the first tip portion T1 and the first hole dam HDAM1.

[0210] The third tip portion T3, the fourth tip portion T4, the fifth tip portion T5, and the sixth tip portion T6 may be disposed between the first hole dam HDAM1 and the second hole dam HDAM2. At least a portion of the third tip portion T3 may overlap the first hole dam HDAM1 in a third direction (eg, Z-axis direction).

[0211] The seventh tip portion T7 and the eighth tip portion T8 may be disposed closer to the through hole TH than the second hole dam HDAM2. At least a portion of the seventh tip portion T7 may overlap the second hole dam HDAM2 in a third direction (eg, Z-axis direction). The eighth tip portion T8 may be disposed between the second hole dam HDAM2 and the through hole TH.

[0212] The first groove GR1 may be disposed between the first tip portion T1 and the second tip portion T2. ​​The second groove GR2 may be disposed between the third tip portion T3 and the fourth tip portion T4. The third groove GR3 may be disposed between the fifth tip portion T5 and the sixth tip portion T6.

[0213] The wiring area WLA may be an area in which bypass lines due to the through holes TH are provided. Some of the bypass lines may be connected to the data lines, and other of the bypass lines may be connected to the second power lines to which a second source voltage higher than the first source voltage is applied. However, other of the bypass lines may be connected to the scan lines. The wiring area WLA may be surrounded by the display area DA.

[0214] Fig.10 A cross section of an edge portion TEG of the through hole TH formed in a case where the substrate SUB is cut by spraying an etchant after laser irradiation by a laser processing device in a manufacturing process of the display device 10 is shown.

[0215] like Fig.10 As shown in , in the case where the substrate SUB is cut by spraying an etchant after laser irradiation by a laser processing device in the manufacturing process of the display device 10, the through hole edge area TEGA may be an area where a process trace is formed on the top surface (or upper surface) US of the substrate SUB. The width of the through hole edge area TEGA may be within about 30 μm, but the embodiment is not limited thereto.

[0216] The through hole edge area TEGA may include a second inclined surface IP1_2 formed by spraying an etchant after laser irradiation. The angle θ4 between the side surface SS2 of the edge portion TEG of the through hole TH and the top surface (or upper surface) US may be within about 90 degrees. For example, the angle θ4 between the side surface SS2 of the edge portion TEG of the through hole TH and the top surface (or upper surface) US may be substantially close to a right angle. The angle θ5 between the side surface SS2 of the edge portion TEG of the through hole TH and the second inclined surface IP1_2 and the angle θ6 between the second inclined surface IP1_2 and the bottom surface (or lower surface) BS may be an obtuse angle. The process trace formed on the top surface (or upper surface) US of the substrate SUB may overlap with the second inclined surface IP1_2 in a third direction (e.g., the Z-axis direction).

[0217] In the case of cutting the substrate SUB of the display panel 100 by spraying an etchant after laser irradiation, an angle θ5 between the side surface SS2 of the edge portion TEG of the through hole TH and the second inclined surface IP1_2 and an angle θ6 between the second inclined surface IP1_2 and the bottom surface (or lower surface) BS may vary with the depth of the laser irradiation area formed by the laser. Figure 7 The depth of the laser irradiated area formed by cutting performed by the laser along the edge portion TEG of the through hole TH may be different from the depth of the laser irradiated area formed by cutting performed by the laser along the edge portion TEG of the through hole TH.

[0218] For example, Fig.10 The angle θ5 between the side surface SS2 of the edge portion TEG of the through hole TH and the second inclined surface IP1_2 shown in FIG. Figure 7 An angle θ2 between the side surface SS1 and the first inclined surface IP1_1 is shown in FIG. Fig.10 The angle θ6 between the second inclined surface IP1_2 and the bottom surface (or lower surface BS shown in FIG. 5 ) may be greater than Figure 7 An angle θ3 between the first inclined surface IP1_1 and the bottom surface (or lower surface) BS shown in FIG.

[0219] like Fig.11 As shown in , the first dummy pattern DP1 and the second gate metal layer including the second capacitor electrode CAE2 of the capacitor Cst may include the same material and may be disposed on the same layer (at the same level). For example, the first dummy pattern DP1 may be disposed on the first interlayer insulating layer 141. The first dummy pattern DP1 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0220] The second dummy pattern DP2 and the first data metal layer including the first connection electrode CE1 and the data line may include the same material and may be disposed on the same layer (at the same level). For example, the second dummy pattern DP2 may be disposed on the second interlayer insulating layer 142. The second dummy pattern DP2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0221] The second dummy pattern DP2 may overlap the first dummy pattern DP1 in a third direction (eg, Z-axis direction).

[0222] The first to eighth tip portions T1 to T8 and the second data metal layer including the second connection electrode CE2 may include the same material and may be disposed on the same layer (at the same level). For example, the first to eighth tip portions T1 to T8 may be disposed on the first organic layer 160. The first to eighth tip portions T1 to T8 may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and alloys thereof.

[0223] Each of the first to eighth tip portions T1 to T8 may be connected to the second dummy pattern DP2 through a contact hole penetrating the first organic layer 160. Each of the first to eighth tip portions T1 to T8 may include an eaves structure in which a top surface (or upper surface) and a bottom surface (or lower surface) are exposed without being covered by the first organic layer 160, the second organic layer 180, the first hole dam HDAM1, and the second hole dam HDAM2. The fourth tip portion T4 and the fifth tip portion T5 may be formed integrally with each other. Each of the first to eighth tip portions T1 to T8 may be a protrusion pattern or a groove pattern for forming a groove (or a groove).

[0224] The through hole edge area TEGA may be disposed between the eighth tip portion T8 and the edge portion TEG of the through hole TH.

[0225] The first groove GR1 may be formed between the first tip portion T1 and the second tip portion T2, the second groove GR2 may be formed between the third tip portion T3 and the fourth tip portion T4, and the third groove GR3 may be formed between the fifth tip portion T5 and the sixth tip portion T6. The first groove GR1 may have an eaves structure formed by the first tip portion T1 and the second tip portion T2, the second groove GR2 may have an eaves structure formed by the third tip portion T3 and the fourth tip portion T4, and the third groove GR3 may have an eaves structure formed by the fifth tip portion T5 and the sixth tip portion T6.

[0226] Since the light emitting layer 172 is deposited by evaporation and the common electrode 173 is deposited by sputtering, the light emitting layer 172 and the common electrode 173 can be arranged to be disconnected at each of the first groove GR1, the second groove GR2 and the third groove GR3 because the step coverage is low. For example, the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 can be deposited by chemical vapor deposition, atomic layer deposition, etc., and thus can be formed to be continuous without being disconnected in each of the first groove GR1, the second groove GR2 and the third groove GR3 because the step coverage is high. The step coverage refers to the ratio of the degree of the film coated on the inclined portion to the degree of the film coated on the flat portion. The light emitting layer 172, the disconnected light emitting layer residue (or the disconnected light emitting layer residue) 172_D, the common electrode 173 and the disconnected common electrode residue (or the disconnected common electrode residue) 173_D can be respectively arranged in the first groove GR1, the second groove GR2 and the third groove GR3. For example, a portion TEF1_D of the first encapsulation inorganic layer TFE1 may be disposed in the first, second, and third grooves GR1, GR2, and GR3.

[0227] The first hole dam HDAM1 may include a first hole dam HDA1, a second hole dam HDA2, a third hole dam HDA3, and a fourth hole dam HDA4. The first hole dam HDA1 may be disposed on the first organic layer 160. The first hole dam HDA1 and the second organic layer 180 may include the same material. The first hole dam HDA1 may be disposed on the second tip portion T2 and the third tip portion T3. The second hole dam HDA2 may be disposed on the first hole dam HDA1. The second hole dam HDA2 and the pixel defining layer 190 may include the same material. The third hole dam HDA3 and the fourth hole dam HDA4 may be disposed on the second hole dam HDA2. The third hole dam HDA3, the fourth hole dam HDA4, and the spacer 191 may include the same material, but the embodiment is not limited thereto. The fourth hole dam HDA4 may be disposed closer to the through hole TH than the third hole dam HDA3. The thickness of the fourth hole dam HDA4 may be greater than the thickness of the third hole dam HDA3.

[0228] The second hole dam HDAM2 may include a fifth hole dam HDA5, a sixth hole dam HDA6, and a seventh hole dam HDA7. The fifth hole dam HDA5 may be disposed on the first organic layer 160. The fifth hole dam HDA5 and the second organic layer 180 may include the same material. The fifth hole dam HDA5 may be disposed on the seventh tip portion T7. The sixth hole dam HDA6 may be disposed on the fifth hole dam HDA5. The sixth hole dam HDA6 and the pixel defining layer 190 may include the same material. The seventh hole dam HDA7 may be disposed on the sixth hole dam HDA6. The seventh hole dam HDA7 and the spacer 191 may include the same material, but the embodiment is not limited thereto.

[0229] By the first hole dam HDAM1 and the second hole dam HDAM2 , the encapsulation organic layer TFE2 may be prevented from overflowing into the through hole TH.

[0230] The disconnected light emitting layer residue 172_D, the disconnected common electrode residue 173_D, the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may extend to the edge portion TEG of the through hole TH. An end of the disconnected light emitting layer residue 172_D, an end of the disconnected common electrode residue 173_D, an end of the first encapsulation inorganic layer TFE1, or an end of the second encapsulation inorganic layer TFE3 may coincide with the edge portion TEG of the through hole TH. However, the embodiment is not limited thereto, and an end of the disconnected light emitting layer residue 172_D, an end of the disconnected common electrode residue 173_D, an end of the first encapsulation inorganic layer TFE1, or an end of the second encapsulation inorganic layer TFE3 may not coincide with the edge portion TEG of the through hole TH.

[0231] like Fig.11 As shown in the figure, since the light emitting layer 172 and the common electrode 173 are disconnected in the first groove GR1, the second groove GR2 and the third groove GR3 respectively formed by the first tip portion T1 to the eighth tip portion T8, the light emitting layer 172 and the common electrode 173 exposed through the through hole TH can be protected from the penetration of oxygen, moisture, etc. through the through hole TH.

[0232] In some embodiments, Fig. 9 As shown in , the display device 10 according to the embodiment may include a residual area RA and a hole non-residual area HNRA.

[0233] The residual area RA may be an area in which the residual trace RSD is disposed. The residual area RA may overlap the inorganic encapsulation area IEA and the wiring area WLA in a third direction (e.g., the Z-axis direction). In a plan view, the residual area RA may surround the through hole TH. The residual area RA may not overlap the through hole TH in a third direction (e.g., the Z-axis direction).

[0234] The hole non-residue area HNRA may be an area in which the residual trace RSD is not provided. For example, the hole non-residue area HNRA may be surrounded by the residual area RA. The hole non-residue area HNRA may be an area in which the coating CTL is provided (see Fig.16 ) opening OP (see Fig.16 ) area.

[0235] The hole non-residual area HNRA may overlap with the through hole TH in a third direction (e.g., Z-axis direction). At least a portion of the hole non-residual area HNRA may overlap with the through hole edge area TEGA in a third direction (e.g., Z-axis direction). In an embodiment, the hole non-residual area HNRA may be disposed inside the first hole dam HDAM1 and the second hole dam HDAM2.

[0236] In some embodiments, the shape of the hole non-residual area HNRA may be consistent with (or aligned with) the shape of the through hole TH. For example, in the case where the through hole TH is a circular shape, the hole non-residual area HNRA may also have a circular shape. However, embodiments are not limited thereto.

[0237] In some embodiments, in a plan view, the hole non-residual area HNRA may be larger than the through hole TH. For example, in a plan view, the area (or size) of the hole non-residual area HNRA may be larger than the area (or size) of the through hole TH. However, embodiments are not limited thereto, and the size of the hole non-residual area HNRA may be equal to the size of the through hole TH.

[0238] In some embodiments, the residual trace RSD may not overlap with the through hole TH. For example, due to the coating layer CTL surrounding the through hole TH (see Fig.16 ) opening OP (see Fig.16 ), the residual trace RSD may not overlap with the through hole TH. The residual trace RSD may be disposed on the first to eighth tip portions T1 to T8, the first hole dam HDAM1, and the second hole dam HDAM2.

[0239] In some embodiments, the inner boundary RSDb of the residual trace RSD may surround the through hole TH. The inner boundary RSDb of the residual trace RSD may be the boundary between the residual area RA and the hole non-residual area HNRA. For example, in a plan view, the inner boundary RSDb of the residual trace RSD may be set outside the circumference of the through hole TH. The inner boundary RSDb of the residual trace RSD may be set outside the edge portion TEG of the through hole TH. However, the embodiment is not limited thereto, and the inner boundary RSDb of the residual trace RSD may coincide with the circumference of the through hole TH in a third direction (e.g., the Z-axis direction).

[0240] Fig.12is a photograph showing a process by which the residual trace RSD of the display device 10 according to the embodiment is formed.

[0241] refer to Fig.12 , in a manufacturing method S1 (see Fig.13 ), when the coating CTL is removed, a residual trace RSD may be formed. The coating CTL may be formed by a printing process such as inkjet.

[0242] The photographs arranged in the first row R1 show the state immediately after ink as the material of the coating CTL is deposited on any inorganic layer such as the second sensor insulating layer TINS2 or the second encapsulation inorganic layer TFE3. The photographs arranged in the second row R2 show the state of any inorganic layer after the coating CTL is removed.

[0243] Fig.12 The shape of the residual trace RSD is an example, and the shape of the residual trace RSD is not limited to the shape shown in the figure.

[0244] In the first row R1, the photographs arranged in the first column C1, the second column C2, and the third column C3 show a state in which the ink is applied with different densities and different amounts according to the width and thickness of the coating layer CTL. For example, the coating layer CTL of the first column C1 may have a smaller width and thickness than the coating layer CTL of the second column C2, and the coating layer CTL of the second column C2 may have a smaller width and thickness than the coating layer CTL of the third column C3.

[0245] In the second row R2, the photographs arranged in the first column C1, the second column C2, and the third column C3 respectively show the residual trace RSD formed as the coating CTL of the first column C1, the second column C2, and the third column C3 are removed. For example, the residual trace RSD in the first column C1 of the second row R2 may be formed as the coating CTL in the first column C1 of the first row R1 is removed, the residual trace RSD in the second column C2 of the second row R2 may be formed as the coating CTL in the second column C2 of the first row R1 is removed, and the residual trace RSD in the third column C3 of the second row R2 may be formed as the coating CTL in the third column C3 of the first row R1 is removed.

[0246] The photographs in the first row R1 may be taken by an optical microscope, and the photographs in the second row R2 may be taken by a scanning electron microscope (SEM).

[0247] As shown in the figure, the transmittance of the residual area (first area) RA in which the residual trace RSD is disposed may be different from the transmittance of the non-residual area (second area) NRA in which the residual trace RSD is not disposed. As an example, the transmittance of the residual area RA in which the residual trace RSD is disposed may be lower than the transmittance of the non-residual area NRA in which the residual trace RSD is not disposed, but the embodiment is not limited thereto.

[0248] Since the description of the non-residue area NRA can be applied to the hole non-residue area HNRA (see Fig. 9 ), so the detailed description thereof will be omitted.

[0249] Hereinafter, a method of manufacturing the display device 10 according to an embodiment will be described.

[0250] Fig.13 is a flowchart illustrating a method of manufacturing the display device 10 according to an embodiment. Fig.14 : is a schematic diagram showing the depth of the laser irradiation area formed by the laser processing apparatus according to the embodiment. Fig.15 It is shown Fig.13 Schematic perspective view of step S110. Fig.16 It is shown Fig.13 Schematic perspective view of step S120. Fig.17 It is shown Fig.13 Schematic perspective view of step S130. Fig.18 It is shown Fig.13 Schematic stereogram of step S140. Fig.19 It is shown Fig.13 Schematic stereogram of step S160. Fig. 20 It is shown Fig.13 Schematic plan view of step S140. Fig.21 It is shown Fig.13 Schematic stereogram of step S160. Fig. 22 It is shown Fig.13 Schematic perspective view of step S170. Fig.23 It is shown Fig.13 A schematic cross-sectional view of step S120 is shown in FIG. Fig.24 is a schematic cross-sectional view showing a coating layer according to an embodiment. Fig.25 It is shown Fig.13 A schematic cross-sectional view of step S130 is shown in FIG. Fig.26 It is shown Fig.13 A schematic cross-sectional view of step S160 is shown in FIG. Fig. 27 It is shown Fig.13 A schematic cross-sectional view of step S160 is shown in FIG. Fig.28 It is shown Fig.13 A schematic cross-sectional view of step S170 is shown in FIG. Fig.29 It is shown Fig.13 A cross-sectional view of step S120. Fig.30 It is shown Fig.13 A schematic cross-sectional view of step S140 is shown in FIG. Fig.31 It is shown Fig.13 A schematic cross-sectional view of step S160 is shown in FIG. Fig.32 It is shown Fig.13 A schematic cross-sectional view of step S160 is shown in FIG. Fig.33 It is shown Fig.13 A schematic cross-sectional view of step S170 is shown in FIG. Fig.34 is a photograph showing a through hole and its vicinity according to a comparative example. Fig.35 is a photograph showing a through hole and its vicinity according to an embodiment. Fig.23 It is along Fig.16 A schematic cross-sectional view taken along line X4-X4', and Fig.29 It is along Fig.16 A schematic cross-sectional view taken along line X5-X5'.

[0251] refer to Figures 13 to 33 In the manufacturing method S1 for the display device 10 according to the embodiment, the display unit DPC ( Fig.13 , or step S110 in the above process.

[0252] like Fig.16 , Fig.23 , Fig.24 and Fig.29 As shown in FIG. 1 , a coating layer CTL may be formed on the display unit DPC, and the display unit DPC may be inspected. Fig.13 , or step S120 in the above procedure.

[0253] For example, the coating layer CTL may be formed to cover the display cell DPC.

[0254] like Fig.16 As shown in , the coating layer CTL may be disposed on the display unit DPC. The coating layer CTL may cover the upper surface (or upper surface) of the display unit DPC. The coating layer CTL may include an opening OP exposing at least a portion of the display unit DPC. In an embodiment, in a plan view, the coating layer CTL may be smaller than the display unit DPC, but the embodiment is not limited thereto.

[0255] The outer boundary CTLa of the coating layer CTL may be disposed adjacent to the periphery of the display unit DPC. The shape of the outer boundary CTLa of the coating layer CTL may be consistent with (or aligned with) the shape of the periphery of the display unit DPC. In an embodiment, the outer boundary CTLa of the coating layer CTL may be located inside the periphery of the display unit DPC. For example, the outer boundary CTLa of the coating layer CTL may be closer to the central portion of the display unit DPC than the periphery of the display unit DPC, but the embodiment is not limited thereto.

[0256] The inner boundary CTLb of the coating layer CTL may be the circumference of the opening OP of the coating layer CTL. The shape of the inner boundary CTLb of the coating layer CTL may be consistent with (or aligned with) the shape of the opening OP. The shape of the inner boundary CTLb of the coating layer CTL may be consistent with (or aligned with) the shape of the through hole TH to be described later. In an embodiment, the inner boundary CTLb of the coating layer CTL may be located outside the through hole TH, but the embodiment is not limited thereto.

[0257] In some embodiments, the coating CTL may be formed by an inkjet printing process. For example, the coating CTL may be formed by curing the ink I coated on the display unit DPC by the inkjet head HD. However, the embodiment is not limited thereto, and the coating CTL may be formed by a coating process such as screen printing or a dispenser. The coating CTL may be cured by at least one of ultraviolet curing, thermal curing, and natural curing.

[0258] In an embodiment, the coating layer CTL may include an acrylic resin, but the embodiment is not limited thereto. For example, the coating layer CTL may be formed by curing the ink I including an acrylic resin, but the embodiment is not limited thereto.

[0259] In some embodiments, the coating layer CTL may include a material having acid resistance so as to protect the display unit DPC in an etching process to be described later. For example, the coating layer CTL may include at least one of an epoxy resin and a polyurethane resin. The coating layer CTL may selectively include at least one of an acrylic resin, an epoxy resin, and a polyurethane resin.

[0260] like Fig.23 , Fig.24 and Fig.29 As shown in FIG, the coating layer CTL may include a flat portion FA and an inclined portion SA.

[0261] The flat portion FA may occupy most of the area of ​​the coating CTL. The top surface (or upper surface) of the coating CTL may be flat in the flat portion FA. The thickness of the coating CTL in the flat portion FA may be substantially constant. For example, the thickness of the coating CTL is constant, meaning that the thickness difference of the coating CTL is about ±6% of the average thickness. For example, the difference between the thickness TH_F of the flat portion FA and the average thickness of the coating CTL may be within about 6% of the average thickness of the coating CTL. In an embodiment, the average thickness of the coating CTL may be in the range of about 40 μm to about 150 μm, but embodiments are not limited thereto.

[0262] The inclined portion SA may be disposed adjacent to the periphery of the display unit DPC and the opening OP of the coating layer CTL. In the inclined portion SA, the top surface (or upper surface) of the coating layer CTL may be an inclined surface. The inclined surface may be a curved shape in a cross-sectional view, but the embodiment is not limited thereto and may be linear.

[0263] In the inclined portion SA, the thickness of the coating CTL may decrease as it approaches the periphery of the display unit DPC, and may decrease as it approaches the opening OP of the coating CTL. In the inclined portion SA, the thickness of the coating CTL may increase as it approaches the flat portion FA.

[0264] An angle θs of a tangent line of the inclined portion SA at the outer and inner borders CTLa and CTLb of the coating CTL may be within about 30 degrees. For example, an angle θs of a tangent line of the inclined portion SA at the outer and inner borders CTLa and CTLb of the coating CTL may be within about 15 degrees.

[0265] Since the manufacturing method S1 for the display device 10 according to the embodiment includes the step of forming the coating layer CTL, process efficiency and process yield may be improved.

[0266] The comparative example may include a cutting process of attaching a protective film to the entire surface of the mother substrate MSUB instead of the coating layer CTL and removing a portion of the protective film according to the size of the display unit DPC. For example, the comparative example may include a cutting process of removing a portion of the protective film to form an opening (such as the opening OP of the coating layer CTL). Fig.34 As shown in , a portion of the protective film can be removed using a laser process. However, when the adhesive of the protective film is carbonized by the laser, carbonized foreign material may be generated at the cut portion, which may cause poor adhesion of the underlying layers. In the etching process to be described later, the etchant may penetrate between the poorly attached layers, which may cause corrosion and damage to the display unit DPC.

[0267] In the manufacturing method S1 for the display device 10 according to the embodiment, since the coating layer CTL having a desired shape can be formed by a printing process, the cutting process as in the comparative example can be omitted. Fig.35 As shown in , problems such as carbonized foreign matter, poor adhesion of layers, and etchant penetration may not occur, and thus process efficiency and process yield may be improved.

[0268] After forming the coating layer CTL, the display cells DPC may be inspected using an inspection device. After connecting a probe to a test pad provided on each of the display cells DPC, an illumination test of each of the display cells DPC may be performed.

[0269] In the case where the illumination test is performed after the display unit DPC is separated from the mother substrate MSUB by a cutting process, an additional process for removing the test pad may be required after the illumination test is completed. In the case where the illumination test is performed on the mother substrate MSUB, the test pad can be removed when the display unit DPC is separated from the mother substrate MSUB by laser irradiation and subsequent etching. Therefore, in the case where the illumination test is performed on the mother substrate MSUB, it is advantageous in that an additional process for removing the test pad is not required.

[0270] like Fig.17 and Fig.25 As shown in FIG. 1 , a first laser irradiation region CH1 ( 100 ) arranged along an edge portion of the display cell DPC can be formed by irradiating a first laser LR1 on a second surface facing a first surface of the mother substrate MSUB. Fig.13 , or step S130 in the above procedure.

[0271] Although various types of lasers may be used as the first laser LR1 according to an embodiment, the first laser LR1 may be an infrared Bessel beam having a wavelength of about 1030 nm.

[0272] like Fig.17 and Fig.25 As shown in FIG. 1 , the first laser LR1 may be irradiated on the second surface of the mother substrate MSUB. However, the embodiment is not limited thereto. The first laser LR1 may be irradiated on the first surface of the mother substrate MSUB.

[0273] The first scribe line LS1 may be defined as an imaginary line connecting the first laser irradiation region CH1. The first scribe line LS1 may be formed by irradiating the first laser LR1 to form the first laser irradiation region CH1 along an edge portion of the display cell DPC.

[0274] The one-side tolerance SE1 of the first laser LR1 may be within about 50 μm, and the two-side tolerance of the first laser LR1 may be within about 100 μm. When the first laser irradiation area CH1 is formed by the first laser LR1, the one-side tolerance SE1 of the first laser LR1 may be a cutting error in one direction (eg, X-axis direction).

[0275] like Fig.18 and Fig.30 As shown in FIG. 1 , a second laser irradiation region CH2 ( 100 ) for forming a through hole TH in each of the display cells DPC can be formed by irradiating a second laser LR2 on the second surface of the mother substrate MSUB. Fig.13 , or step S140 in the above procedure.

[0276] although Fig.13 It is shown that step S140 is performed after step S130 is performed, but the embodiment is not limited thereto. In order to reduce the process time, step S130 and step S140 may be performed simultaneously by providing laser processing devices LD1 and LD2. In another example, step S130 may be performed after step S140.

[0277] Although various types of lasers may be used as the second laser LR2 according to an embodiment, the second laser LR2 may be an infrared Bessel beam having a wavelength of about 1030 nm.

[0278] like Fig.18 and Fig.30 As shown in FIG. 1 , the second laser LR2 may be irradiated on the second surface of the mother substrate MSUB. However, the embodiment is not limited thereto. The second laser LR2 may be irradiated on the first surface of the mother substrate MSUB.

[0279] The second scribe line LS2 may be defined as an imaginary line connecting the second laser irradiation area CH2. The second scribe line LS2 may be formed by irradiating the second laser LR2 to form the second laser irradiation area CH2 along the edge portion of the through hole TH. The second scribe line LS2 may depend on the shape of the through hole TH (or be aligned therewith). For example, in the case where the through hole TH has a circular planar shape, the second scribe line LS2 may be formed in a circular shape.

[0280] The single-side tolerance SE2 of the second laser LR2 may be within about 50 μm, and the double-side tolerance of the second laser LR2 may be within about 100 μm. When the second laser irradiation area CH2 is formed by the second laser LR2, the single-side tolerance SE2 of the second laser LR2 may be a cutting error in one direction (eg, X-axis direction).

[0281] In the case where the first laser LR1 and the second laser LR2 are irradiated on the second surface of the mother substrate MSUB, as shown in FIG. Fig.14 As shown in , the depth TCH1 (or scribe length) of each of the first laser irradiation regions CH1 and the depth TCH2 (or scribe length) of each of the second laser irradiation regions CH2 can be adjusted according to the repetition rate, process speed, and pulse energy.

[0282] For example, Fig.14 As shown in (a) of FIG. 1 , the depth TCH1 of each of the first laser irradiation regions CH1 may be about 50 μm from the first surface of the mother substrate MSUB. For example, since the thickness of the mother substrate MSUB is about 500 μm, the depth TCH2 of each of the second laser irradiation regions CH2 may be about 500 μm. For example, the depth TCH2 of each of the second laser irradiation regions CH2 may be about 50 μm to about 500 μm from the first surface of the mother substrate MSUB.

[0283] The first laser LR1 for forming the first laser irradiation region CH1 may be irradiated at a repetition rate of about 10 kHz to about 250 kHz, a process speed of about 10 mm / s to about 250 mm / s, and a pulse energy of about 10 μJ to about 300 μJ. However, in order for the first laser LR1 to have a depth of about 225 μm from the first surface of the mother substrate MSUB, the irradiation conditions may include a repetition rate of about 17.5 kHz to about 125 kHz, a process speed of about 17.5 mm / s to about 125 mm / s, and a pulse energy of about 25 μJ to about 178 μJ.

[0284] The second laser LR2 for forming the second laser irradiation region CH2 may be irradiated at a repetition rate of about 1 kHz to about 50 kHz, a process speed of about 1 mm / s to about 50 mm / s, and a pulse energy of about 10 μJ to about 300 μJ. However, in order for the second laser LR2 to have a depth of about 400 μm to about 500 μm from the first surface of the mother substrate MSUB, the irradiation may be performed at a repetition rate of about 10 kHz, a process speed of about 10 mm / s, and a pulse energy of about 60 μJ to about 178 μJ. For example, when the second laser LR2 forms a circular second scribed line LS2, the first laser LR1 may form a first scribed line LS1 along an edge portion of each of the display cells DPC. Therefore, the process speed of the second laser LR2 may be less than the process speed of the first laser LR1.

[0285] like Fig.26 and Fig.31 As shown in FIG. , the protective film PRF can be attached to the coating CTL ( Fig.13 , or step S150 in the above procedure.

[0286] The protective film PRF may be attached to the entire first surface of the mother substrate MSUB. For example, the protective film PRF may be attached to the coating layer CTL and the exposed mother substrate MSUB not covered by the coating layer CTL. The protective film PRF may cover the first laser irradiation region CH1 and the second laser irradiation region CH2.

[0287] The protective film PRF may be an acid-resistant film so as to protect the display unit DPC from being affected by an etchant in an etching process for the mother substrate MSUB performed in the next step. For example, the protective film PRF may include at least one of polyethylene terephthalate (PET), polypropylene (PP), polycarbonate, polyethylene (PE), and polyvinyl chloride (PVC).

[0288] For example, the protection film PRF may include an adhesive layer thereunder. The adhesive layer may include at least one of a silicone-based, a polyurethane-based, and an acrylic-based material, but the embodiment is not limited thereto.

[0289] In the manufacturing method S1 for the display device 10 according to the embodiment, since the coating layer CTL includes the inclined portion SA, the protective film PRF can be allowed to be in close contact with the mother substrate MSUB. For example, due to the presence of the inclined portion SA of the coating layer CTL, the protective film PRF can be attached concavely toward the mother substrate MSUB. The protective film PRF can be firmly in contact with the outer boundary CTLa and the inner boundary CTLb of the coating layer CTL. Therefore, the etchant ECH can be prevented from penetrating along the top surface (or upper surface) of the sensor electrode layer SENL or the top surface (or upper surface) of the encapsulation layer ENC.

[0290] In the drawings, the concave portion of the protection film PRF is shown to be spaced apart from the first surface of the mother substrate MSUB. However, in some examples, the concave portion of the protection film PRF may be attached to the first surface of the mother substrate MSUB.

[0291] like Figures 19 to 21 , Fig.26 , Fig. 27 , Fig.31 and Fig.32 As shown in FIG. , the etchant ECH can be sprayed onto the second surface of the mother substrate MSUB without a separate mask to reduce the thickness of the mother substrate MSUB, the mother substrate MSUB can be cut along the first laser irradiation area CH1 and the second laser irradiation area CH2, and the protective film PRF ( Fig.13 , or step S160 in the above procedure.

[0292] When the etchant ECH is sprayed onto the second surface of the mother substrate MSUB, the mother substrate MSUB can be reduced from the first thickness TH1 to the second thickness TH2. Since the mother substrate MSUB is etched without a separate mask, isotropic etching can be performed in which the mother substrate MSUB is uniformly etched throughout the entire area of ​​the second surface.

[0293] Each of the first laser irradiation regions CH1 may include a physical hole formed by the first laser LR1 and a region around the physical hole whose physical properties are changed by the first laser LR1. In another example, each of the first laser irradiation regions CH1 may be a region whose physical properties are changed by the first laser LR1 without a physical hole. Therefore, the etching rate of the etchant ECH in each of the first laser irradiation regions CH1 may be higher than the etching rate in other regions of the mother substrate MSUB not irradiated with the laser.

[0294] In the case where the thickness of the mother substrate MSUB is reduced by the etchant ECH and the etchant ECH penetrates into the first laser irradiation region CH1 formed by the first laser LR1, a difference in etching rate may occur between a region in which the first laser irradiation region CH1 is formed and a region in which the first laser irradiation region CH1 is not formed due to the first laser irradiation region CH1. For example, the mother substrate MSUB may be performed using anisotropic etching in which an etching rate in a region in which the first laser irradiation region CH1 is formed is faster than an etching rate in a region in which the first laser irradiation region CH1 is not formed. Therefore, as Fig.28 As shown in FIG, a substrate SUB separated from the mother substrate MSUB may include a first inclined surface IP1_1 disposed between a side surface SS1 and a bottom surface (or lower surface) BS.

[0295] For example, when the etchant ECH penetrates into the first laser irradiation region CH1 formed by the first laser LR1, the mother substrate MSUB may be separated along the first cutting line CL1. For example, each of the display units DPC may be separated from the mother substrate MSUB. The first cutting line CL1 may be formed along the first scribe line LS1. In an embodiment, as shown in FIG. Fig. 20 As shown in FIG. 1 , the outer boundary CTLa of the coating layer CTL may be located at the inner side of the first cutting line CL1 . For example, the outer boundary CTLa of the coating layer CTL may be closer to the central portion of each display cell DPC than the first cutting line CL1 .

[0296] Since the first surface of the substrate SUB separated from the mother substrate MSUB is not penetrated by the etchant ECH due to the protective film PRF, and the second surface of the substrate SUB is etched by the etchant ECH, the first surface and the second surface of the substrate SUB may have differences in roughness, hardness, light transmittance, light reflectivity, local density, surface chemical structure, etc. For example, a dent due to the etchant ECH may appear on the second surface of the substrate SUB. The dent means that a fine defect (such as a scratch) existing on the second surface of the substrate SUB is enlarged by reacting with the etchant ECH.

[0297] For example, the single-sided tolerance of the laser may be about 50 μm, and the width of the first laser irradiation area CH1 formed by the first laser LR1 may be expanded by about 40 μm by the etchant ECH. Therefore, considering the double-sided tolerance of the laser of each of the display cells DPC and the width of the first laser irradiation area CH1 expanded by the etchant ECH, the spacing distance SD between the display cells DPC adjacent to each other may be about 280 μm, but the embodiment is not limited thereto.

[0298] Each of the second laser irradiation regions CH2 may include a physical hole formed by the second laser LR2 and a region around the physical hole whose physical properties are changed by the second laser LR2. In another example, each of the second laser irradiation regions CH2 may be a region whose physical properties are changed by the second laser LR2 without a physical hole. Therefore, the etching rate of the etchant ECH in each of the second laser irradiation regions CH2 may be higher than the etching rate in other regions of the mother substrate MSUB not irradiated with the laser.

[0299] Due to anisotropic etching, e.g. Fig.33 As shown in FIG. 1 , the substrate SUB separated from the mother substrate MSUB may include a second inclined surface IP1_2 disposed between a bottom surface (or lower surface) BS and a side surface SS2 of an edge portion TEG of the through hole TH.

[0300] For example, when the etchant ECH penetrates into the second laser irradiation region CH2 formed by the second laser LR2, the mother substrate MSUB may be separated along the second cutting line CL2 to form the through hole TH. The second cutting line CL2 may be formed along the second scribing line LS2. Fig. 20 As shown in FIG. 4 , the inner boundary CTLb of the coating layer CTL may be located outside the second cutting line CL2 .

[0301] like Fig.26 and Fig.31As shown in , since the depth of each of the second laser irradiation regions CH2 is deeper than the depth of each of the first laser irradiation regions CH1, the etchant ECH may penetrate into the second laser irradiation region CH2 earlier than the first laser irradiation region CH1. For example, since the second laser irradiation region CH2 is etched together with the thinning process in which the thickness of the mother substrate MSUB is reduced by the etchant ECH, the substrate SUB may be formed into a tapered cross-section by isotropically etching in the through hole TH formed by the second laser irradiation region CH2. In contrast, in the case where the thinning is performed, the first laser irradiation region CH1 is not etched. Therefore, a difference may occur between the length and angle of the inclination direction of the first inclined surface IP1_1 in the edge portion of the substrate SUB formed by the first laser irradiation region CH1, and the length and angle of the inclination direction of the second inclined surface IP1_2 in the through hole TH formed by the second laser irradiation region CH2.

[0302] After the etching process is completed, the protection film PRF may be separated (or removed).

[0303] Through the etching process, each of the display cells DPC may be separated from the mother substrate MSUB, and a through hole TH may be formed in each of the display cells DPC.

[0304] like Fig. 22 , Fig.28 and Fig.33 As shown in FIG. 1 , the driving IC 200 and the circuit board 300 may be attached to each of the display units DPC, and the coating layer CTL may be separated from each of the display units DPC ( Fig.13 , or step S170 in the above procedure.

[0305] In some embodiments, in the case of separating the coating CTL, the adhesion of the coating CTL may be different in the inclined portion SA and the flat portion FA. The adhesion of the coating CTL in the inclined portion SA may be in the range of about 10 gf / inch (inch) to about 150 gf / inch, and the adhesion of the coating CTL in the flat portion FA may be in the range of about 5 gf / inch to about 10 gf / inch.

[0306] As described above, by using laser and etching processes, the thickness of the substrate SUB may be reduced, the substrate SUB of each of the display cells DPC may be separated from the mother substrate MSUB, and the through holes TH may be formed at the same time, so that the efficiency of the manufacturing process may be improved.

[0307] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the embodiments of the present invention disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: A display panel comprising a display area and a non-display area adjacent to one side of the display area; as well as a residual trace, disposed on the display panel and disposed on the display area and the non-display area, The outer boundary of the residual trace is arranged to be adjacent to an edge portion of the display panel and is arranged to be closer to a central portion of the display panel than the edge portion of the display panel.

2. The display device according to claim 1, wherein: The outer boundary of the residual trace is surrounded by an outer boundary of the display panel in a plan view.

3. The display device according to claim 1, wherein: The display panel includes a crack dam adjacent to the edge portion of the display panel, and The outer boundary of the residual trace is closer to the central portion of the display panel than the crack dam.

4. The display device according to claim 1, wherein: The display panel includes a through hole penetrating the display panel and disposed in the display area, and The residual trace includes an opening surrounding the through hole.

5. The display device according to claim 4, wherein: The opening of the residual trace is larger than the through hole of the display panel in a plan view.

6. The display device according to claim 5, wherein: The opening of the residual trace and the through hole of the display panel have different sizes and the same shape in a plan view.

7. A display device, comprising: A display panel comprising at least one conductive layer and at least one non-conductive layer disposed on the conductive layer; as well as a residual trace disposed on at least a portion of the non-conductive layer, The light transmittance of the non-conductive layer in a first region in which the residual trace is disposed is different from the light transmittance of the non-conductive layer in a second region in which the residual trace is not disposed.

8. The display device according to claim 7, wherein: The residual trace is smaller than the display panel in plan view.

9. The display device according to claim 7, wherein: The residual trace includes at least one of an acrylic resin, an epoxy resin, and a polyurethane resin.

10. The display device according to claim 7, wherein: The residual trace is formed in a process in which a portion of the non-conductive layer is removed.

11. The display device according to claim 7, wherein: The display panel comprises: substrate; a light emitting element layer, disposed on the substrate; and an encapsulation layer, disposed on the light emitting element layer, and The residual trace is disposed on the encapsulation layer.

12. The display device according to claim 11, wherein: The encapsulation layer comprises: a first encapsulating inorganic layer; an encapsulation organic layer, disposed on the first encapsulation inorganic layer; and a second encapsulation inorganic layer disposed on the encapsulation organic layer, and The residual trace is disposed on the second encapsulating inorganic layer.

13. The display device according to claim 7, wherein: The display panel comprises: substrate; A light emitting element layer is disposed on the substrate; an encapsulation layer, disposed on the light-emitting element layer; and a sensor electrode layer, disposed on the packaging layer, and The residual trace is disposed on the sensor electrode layer.

14. The display device according to claim 13, wherein: The sensor electrode layer includes a sensor electrode and a sensor insulating layer, and The residual trace is disposed on the sensor insulating layer.

15. A method for manufacturing a display device, the method comprising: forming a plurality of display units on a mother substrate; forming a coating layer on each of the plurality of display cells; Forming a plurality of first laser irradiation areas by irradiating the mother substrate with a first laser; attaching a protective film on the mother substrate; and The mother substrate is cut along the plurality of first laser irradiation regions by spraying an etchant on the mother substrate without a mask.

16. The method according to claim 15, wherein: Forming the coating comprises: applying resin; and The resin is cured.

17. The method according to claim 16, wherein: The resin is applied by a printing process.

18. The method according to claim 15, wherein: The coating includes an inclined surface at an end of the coating.

19. The method according to claim 18, wherein: At the end of the coating layer, an angle of a tangent line relative to the inclined surface is equal to or less than 30 degrees.

20. The method according to claim 18, wherein: The coating comprises: an inclined portion adjacent to the end of the coating; and A flat portion is disposed on one side of the inclined portion.

21. The method according to claim 20, further comprising: removing the coating, When removing the coating, the adhesion force of the coating in the inclined portion is greater than the adhesion force of the coating in the flat portion.

22. The method according to claim 21, wherein: The adhesion of the coating in the inclined portion is 10 gf / inch to 150 gf / inch, and The adhesion of the coating in the flat portion is 5 gf / inch to 10 gf / inch.

23. The method according to claim 15, wherein: The coating layer includes at least one of acrylic resin, epoxy resin and polyurethane resin.

24. The method according to claim 15, wherein: The coating has an average thickness of 40 μm to 150 μm.

25. The method of claim 15, wherein: The protective film includes at least one of polyethylene terephthalate, polypropylene, polycarbonate, polyethylene, and polyvinyl chloride.

26. The method according to claim 25, wherein: The protective film includes an adhesive layer, and The adhesive layer includes at least one of a silicone-based, a polyurethane-based, and an acrylic-based material.

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