Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body and a plurality of sub-pixels. The sub-pixel includes a pixel electrode and an effective light emitting region. The pixel electrode includes a body portion and a connection portion that are interconnected. The main body part and the effective light-emitting area are the same in shape, and the main body part and at least part of the boundary of the pixel electrode coincide. The plurality of sub-pixels at least comprise one first sub-pixel and one second sub-pixel which have the same light emitting color. And the first sub-pixel and the second sub-pixel which are closest to each other are arranged along the second direction. The orthographic projection areas of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the substrate are different. Two orthographic projections of the connecting part and the main body part of at least one of the first sub-pixel and the second sub-pixel on a straight line extending along the first direction are at least partially not overlapped. The orthographic projection of the pixel electrode of the second sub-pixel on the straight line extending along the second direction is located in the orthographic projection of the pixel electrode of the first sub-pixel on the same straight line.

Description

[0001] This application is a divisional application. The application number of the original application is 202080002176.4, and the application date of the original application is September 29, 2020. The entire content of the original application can be incorporated into this application by reference.

[0002] This application claims priority to PCT application with international application number PCT / CN2020 / 086997 filed on April 26, 2020, and PCT application with international application number PCT / CN2020 / 114623 filed on September 10, 2020, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] Active-matrix organic light emitting diode (AMOLED) display substrates have been widely used in display devices due to their advantages such as self-luminescence, wide color gamut, high contrast, flexibility and high response.

[0005] At present, with the increasing density of pixel distribution in AMOLED display substrates, the size of pixels in AMOLED display substrates is gradually reduced, which limits the design space of pixels. On this basis, the reasonable optimization of the structure of pixel circuits and their manufacturing process is conducive to improving the display effect of the display device where the AMOLED display substrate is located. Summary of the invention

[0006] The purpose of the embodiments of the present disclosure is to provide a display substrate and a display device, which are used to effectively simplify the overall layout design of the pixel circuit in the display substrate on the basis of improving the sub-pixel distribution density, so as to improve the light transmittance of the display substrate.

[0007] In order to achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0008] On the one hand, some embodiments of the present disclosure provide a display substrate. The display substrate includes: a substrate and a plurality of sub-pixels. The sub-pixel includes a pixel electrode and an effective light-emitting area. The pixel electrode includes an interconnected main body and a connecting part. The main body has the same shape as the effective light-emitting area, and the main body overlaps with at least part of the boundary of the pixel electrode. The plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel with the same light-emitting color. The first sub-pixel and the second sub-pixel that are closest to each other are arranged along a second direction. The areas of the orthogonal projections of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the substrate are different. The two orthogonal projections of the connecting part and the main body of at least one sub-pixel of the first sub-pixel and the second sub-pixel on a straight line extending along the first direction at least partially do not overlap. The orthogonal projection of the pixel electrode of the second sub-pixel on a straight line extending along the second direction is located within the orthogonal projection of the pixel electrode of the first sub-pixel on the same straight line. The second direction intersects with the first direction, and the value range of the angle between the two is 80° to 100°.

[0009] In the disclosed embodiment, multiple sub-pixels with the same luminous color adopt two different structures of the first sub-pixel and the second sub-pixel. The shapes of the pixel electrodes in the first sub-pixel and the second sub-pixel are designed as described above, which can effectively simplify the overall layout design of the pixel circuit in the display substrate on the basis of improving the sub-pixel distribution density, thereby improving the light transmittance of the display substrate.

[0010] In some embodiments, the main body includes a first side, a second side, and a third side connected in sequence; the third side extends along the second direction. The connecting portion is connected to the second side and is spaced apart from the first side. A straight line connecting any point on the first side to any point on the edge of the connecting portion extending along the second direction and away from the third side in the first direction, and an area enclosed by the main body and the connecting portion is a notch area.

[0011] In some embodiments, the display substrate further comprises a plurality of layers between the base substrate and the pixel electrode; the plurality of layers comprises at least one metal pattern. In a direction perpendicular to the base substrate, in each layer from the base substrate to the pixel electrode, at least a portion of the notch area does not overlap with the metal pattern.

[0012] In some other embodiments, the display substrate further comprises a plurality of layers between the base substrate and the pixel electrode; the plurality of layers comprises a semiconductor pattern and at least one metal pattern. In the direction perpendicular to the base substrate, in each layer from the base substrate to the pixel electrode, at least a portion of the notch area does not overlap with the semiconductor pattern or the metal pattern.

[0013] In some embodiments, the connection portion of the pixel electrode in the first sub-pixel includes: a bent portion and a compensation portion connected to the bent portion. The compensation portion extends along the second direction. The bent portion is connected to the second side, and there is a gap between the bent portion and the first side.

[0014] In some embodiments, the ratio of the area of ​​the notch region to the area of ​​two orthographic projections of the bent portion on the substrate is in the range of 0.2-5.

[0015] In some embodiments, a maximum dimension of the compensation portion along the first direction is greater than a maximum dimension of the bent portion along the first direction.

[0016] In some embodiments, a maximum dimension of a connecting portion of the pixel electrode in the second sub-pixel along the second direction is less than or equal to a maximum dimension of a bent portion of the pixel electrode in the first sub-pixel along the second direction.

[0017] In some embodiments, the sub-pixel further comprises a pixel circuit. The pixel circuit comprises a driving transistor.

[0018] The orthographic projection of the metal pattern having the same potential as the control electrode of the driving transistor on the substrate is the first projection. The area where the orthographic projection of the pixel electrode on the substrate in the first sub-pixel overlaps with the first projection is the first area. The area where the orthographic projection of the pixel electrode on the substrate in the second sub-pixel overlaps with the first projection is the second area. The ratio of the first area to the second area ranges from 0.8 to 1.2.

[0019] In some embodiments, the display substrate further includes: a first gate metal layer between the base substrate and the pixel electrode, and a first metal layer between the first gate metal layer and the pixel electrode. The metal pattern having the same potential as the control electrode of the driving transistor includes: a first electrode of a capacitor located in the first gate metal layer, and a first switching electrode located in the first metal layer.

[0020] An overlapping area of ​​the orthographic projections of the pixel electrode of the first sub-pixel and the first electrode of the capacitor on the substrate is smaller than an overlapping area of ​​the orthographic projections of the pixel electrode of the second sub-pixel and the first electrode of the capacitor on the substrate; and an overlapping area of ​​the orthographic projections of the pixel electrode of the first sub-pixel and the first switching electrode on the substrate is larger than an overlapping area of ​​the orthographic projections of the pixel electrode of the second sub-pixel and the first switching electrode on the substrate.

[0021] In some embodiments, the display substrate further comprises: a plurality of signal lines extending along the first direction. The orthographic projection of the pixel electrode of the first sub-pixel on the base substrate overlaps with the orthographic projections of at least three signal lines located in the same layer on the base substrate.

[0022] In some embodiments, the at least three signal lines located in the same layer include: at least one gate scanning signal line, at least one light emitting control signal line, and at least one reset control signal line.

[0023] In some embodiments, the display substrate further includes: a first insulating layer and a plurality of connecting electrodes. The first insulating layer is located between the pixel electrode and the connecting electrode and has a plurality of first vias. The pixel electrode is coupled to the connecting electrode through the first vias. The sub-pixel further includes a pixel circuit. The plurality of pixel circuits are arranged in a row along the first direction and in a column along the second direction. The orthographic projections of the plurality of first vias corresponding to the plurality of pixel circuits in the same row on the substrate are arranged along a first straight line. In the plurality of sub-pixels corresponding to the plurality of pixel circuits in the same row, the effective light-emitting area of ​​the first sub-pixel and the effective light-emitting area of ​​the second sub-pixel are respectively located on both sides of the first straight line.

[0024] In some embodiments, the display substrate further includes: a second insulating layer and a plurality of driving electrodes. The second insulating layer is located between the connecting electrode and the driving electrode and has a plurality of second via holes. The connecting electrode is coupled to the driving electrode through the second via holes. There is a gap between the orthographic projections of the first via hole and the second via hole corresponding to the same connecting electrode on the base substrate.

[0025] In some embodiments, the orthographic projections of the plurality of second conductive holes corresponding to the plurality of pixel circuits in the same row on the substrate are arranged along a second straight line.

[0026] In some embodiments, the distance between the orthographic projection of any one of the first conductive via and the second conductive via on the base substrate to the effective light emitting area of ​​the corresponding sub-pixel is greater than 2 μm.

[0027] In some embodiments, the orthographic projections of the first conductive hole and the second conductive hole on the substrate have substantially the same shape and area. The orthographic projections of the first conductive hole and the second conductive hole corresponding to the same connecting electrode on the substrate are arranged along a third straight line.

[0028] In some embodiments, the shapes of the orthographic projections of the driving electrode and the connecting electrode on the base substrate are substantially the same, and the orthographic projection area of ​​the connecting electrode on the base substrate is larger than the orthographic projection area of ​​the driving electrode on the base substrate.

[0029] In some embodiments, the orthographic projection of the driving electrode on the base substrate is located within the orthographic projection of the connecting electrode on the base substrate, and a portion of the boundaries of the orthographic projections of the two electrodes overlap or substantially overlap.

[0030] In some embodiments, the orthographic projection of the connection electrode on the base substrate and the orthographic projection of the drive electrode on the base substrate have a non-overlapping portion, and the orthographic projection of the first conductive hole on the base substrate overlaps the non-overlapping portion.

[0031] In some embodiments, the display substrate further includes a semiconductor pattern layer and a third insulating layer. The semiconductor pattern layer is located between the base substrate and the drive electrode. The third insulating layer is located between the drive electrode and the semiconductor pattern layer and has a plurality of third via holes. The drive electrode is coupled to a corresponding portion of the semiconductor pattern layer through the third via hole. There is a gap between two of the three orthographic projections of the third via hole, the second via hole, and the first via hole corresponding to the same drive electrode on the base substrate.

[0032] In some embodiments, the minimum distance between the orthographic projection of any one of the first conductive hole and the second conductive hole on the substrate and the orthographic projection of the third conductive hole on the substrate is in the range of 0.8 μm to 10 μm. The minimum distance between the orthographic projection of the first conductive hole and the second conductive hole on the substrate is in the range of 1 μm to 10 μm.

[0033] In some embodiments, the display substrate further includes a plurality of data lines. The data lines are arranged in the same layer as the drive electrodes. The third insulating layer further includes a plurality of fourth via holes. The data lines are connected to corresponding pixel circuits through the fourth via holes. The data lines extend along the second direction, and the data lines include a plurality of protrusions protruding toward the corresponding pixel circuits in the first direction. The overlapping area between the orthographic projection of the fourth via hole on the base substrate and the orthographic projection of the protrusion on the base substrate is 70%-100% of the orthographic projection area of ​​the fourth via hole on the base substrate.

[0034] In some embodiments, the display substrate further comprises a plurality of power signal lines. The plurality of power signal lines comprise at least one first power signal line. The first power signal line is disposed in the same layer as the connection electrode. The first power signal line comprises a plurality of first sub-power signal lines extending along the first direction and a plurality of second sub-power signal lines extending along the second direction. The first sub-power signal line is interconnected with the second sub-power signal line.

[0035] There is a gap between the two effective light-emitting areas of the first sub-pixel and the second sub-pixel that are closest to each other. The orthographic projection of the first sub-power signal line on the substrate passes through the gap between the two effective light-emitting areas of the first sub-pixel and the second sub-pixel. At least one of the second sub-power signal lines has at least one break. The orthographic projection of a virtual line between two endpoints of the break in the second direction on the substrate passes through the two effective light-emitting areas of the first sub-pixel and the second sub-pixel and the orthographic projection of the gap on the substrate. The second sub-power signal line with the break does not overlap with the two effective light-emitting areas of the first sub-pixel and the second sub-pixel and the orthographic projection of the gap on the substrate.

[0036] In some embodiments, the plurality of power signal lines further include a plurality of second power signal lines. The second power signal lines extend along the second direction. When the display substrate further includes a second insulating layer and a plurality of driving electrodes, the second power signal lines are disposed in the same layer as the driving electrodes. The second insulating layer further includes a plurality of fifth conductive vias. The second sub-power signal lines are coupled to the second power signal lines through the fifth conductive vias.

[0037] The orthographic projections of the second power signal line and the second sub-power signal line coupled thereto on the substrate at least partially overlap. The orthographic projection of the second power signal line on the substrate partially overlaps with the orthographic projection of the effective light-emitting area of ​​any one of the first sub-pixel and the second sub-pixel on the substrate.

[0038] In some embodiments, the orthographic projections of the plurality of fifth vias in the same row along the first direction on the substrate are located on a fourth straight line extending along the first direction. The distance between the orthographic projection of the fifth via on the substrate and the orthographic projection of any effective light-emitting area on the substrate is greater than 2.5 um.

[0039] In some embodiments, the first sub-pixel and the second sub-pixel that are closest to each other constitute a sub-pixel pair. A sub-pixel group includes a first color sub-pixel, a sub-pixel pair, and a third color sub-pixel arranged in sequence along the first direction. The sub-pixel pair is configured to emit a second color light. The center of the orthographic projection of at least one of the first effective light-emitting area of ​​the first color sub-pixel and the third effective light-emitting area of ​​the third color sub-pixel on the substrate is located within the orthographic projection of the corresponding first sub-power signal line on the substrate.

[0040] In some embodiments, two second sub-power signal lines located on both sides of the first effective light-emitting area of ​​the first color sub-pixel and adjacent to the first effective light-emitting area are at unequal distances from a center line of the first effective light-emitting area extending along the second direction. The display substrate further includes a plurality of pads and a plurality of support portions arranged in the same layer as the first power signal line. The pads extend along the second direction. The pads are located between the first effective light-emitting area and the second sub-power signal line, and are coupled to the second sub-power signal line via the support portion. The distance between the second sub-power signal line coupled to the pads and the center line of the first effective light-emitting area extending along the second direction is greater than the distance between another second sub-power signal line adjacent to the first effective light-emitting area and the center line. The pads are also coupled to the first sub-power signal line.

[0041] In some embodiments, the shape of the pad is substantially a long strip, and the center of the orthographic projection of the pad on the base substrate is located within the orthographic projection of the first sub-power signal line coupled thereto on the base substrate.

[0042] In some embodiments, the ratio of the two distances between the orthographic projections of the two effective light-emitting areas of the first sub-pixel and the second sub-pixel on the substrate and the orthographic projections of the first sub-power signal line located between the two effective light-emitting areas on the substrate ranges from 0.9 to 1.1.

[0043] On the other hand, a display device is provided. The display device comprises a display substrate as described in any of the above embodiments. The beneficial effects that can be achieved by the display device in the embodiment of the present disclosure are the same as the beneficial effects that can be achieved by the display substrate in the above embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in some embodiments of the present disclosure, the drawings required for use in the description of some embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and a person skilled in the art can also obtain other drawings based on these drawings.

[0045] Figure 1 is a schematic structural diagram of a display device according to some embodiments of the present disclosure;

[0046] Figure 2A is an enlarged schematic diagram of a display substrate in the M0 region according to some embodiments of the present disclosure;

[0047] Figure 2B is a schematic structural diagram of a sub-pixel group according to some embodiments of the present disclosure;

[0048] Figure 2C is a schematic diagram of the distribution of sub-pixels on a substrate according to some embodiments of the present disclosure;

[0049] Figure 3 is a schematic structural diagram of a pixel circuit according to some embodiments of the present disclosure;

[0050] Figure 4 is a schematic diagram of the structure of each pixel electrode in a sub-pixel group according to some embodiments of the present disclosure;

[0051] Figure 5 is an enlarged schematic diagram of a display substrate in an M1 region according to some embodiments of the present disclosure;

[0052] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H and Fig.6I A schematic top view of different layers of a display substrate during its preparation process according to some embodiments of the present disclosure;

[0053] Figure 6E' is a schematic diagram of the positions of the via holes in the first metal layer and the second interlayer insulating layer 140 according to some embodiments of the present disclosure;

[0054] Figure 6G' A schematic diagram of the position of the second metal layer and the via hole in the first planar layer 122 according to some embodiments of the present disclosure;

[0055] Figure 6H'is a schematic diagram of the position of the second metal layer and the via hole in the second planar layer 121 according to some embodiments of the present disclosure;

[0056] Figure 6I' is a schematic diagram of the position between the second metal layer and the pixel electrode layer according to some embodiments of the present disclosure;

[0057] Fig. 7A is a partial schematic diagram of a display substrate according to some embodiments of the present disclosure;

[0058] Figure 7B is a schematic cross-sectional view of a display substrate along the AA' direction according to some embodiments of the present disclosure;

[0059] Figure 7C is a schematic cross-sectional view of a display substrate along the BB' direction according to some embodiments of the present disclosure;

[0060] Fig.7D is a schematic cross-sectional view of a display substrate along the CC' direction according to some embodiments of the present disclosure;

[0061] Fig. 7E is a schematic cross-sectional view of a display substrate along the DEFGH direction according to some embodiments of the present disclosure;

[0062] Figure 7F is a schematic cross-sectional view along the LMN direction of a display substrate according to some embodiments of the present disclosure;

[0063] Figure 7G is a schematic cross-sectional view of a display substrate along the RST direction according to some embodiments of the present disclosure;

[0064] Figure 8 A schematic diagram of the positions of a first conductive hole, a second conductive hole, a third conductive hole and a pixel electrode according to some embodiments of the present disclosure;

[0065] Fig. 9 Schematic diagram of the position between a pixel electrode of a first sub-pixel and an adjacent pixel electrode according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in some embodiments of the present disclosure to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on some embodiments in the present disclosure, all other embodiments that can be obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0067] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0068] In the following, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of components in the drawings. It should be understood that these directional terms may be relative concepts. They are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0069] The terms "first", "second", etc., ordinal numbers are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0070] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0071] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0072] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0073] The use of "suitable for" or "configured to" herein is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because a process, step, calculation or other action "based on" one or more stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0074] As used herein, “approximately” or “substantially” includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation can be determined by one of ordinary skill in the art taking into account measurement errors and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system).

[0075] In addition, in order to clearly indicate multiple layers and regions in the drawings, the thickness of each layer in the drawings is exaggerated to clearly illustrate the relative positions of the layers. When a portion of a layer, film, region, plate, etc. is described as being "above" or "on" another portion, the description includes not only the case where it is "directly" above the other portion, but also the case where there are other layers therebetween.

[0076] The embodiment of the present disclosure provides a display device. The display device is, for example, a mobile phone, a tablet computer (pad), a computer, a smart wearable product (for example, a smart watch, a smart bracelet), a portable electronic device, a virtual reality (VR) terminal, an augmented reality (AR) terminal, etc. The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above display device.

[0077] The display device provided by the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings.

[0078] For the convenience of explanation, the following takes the display device 01 as an example. Figure 1 Take the mobile phone shown in the figure as an example. In this case, the display device 01 at least includes a housing 11 and a display substrate 10 installed in the housing 11. The housing 11 is usually provided with a receiving cavity (PCB), a battery, a camera and other components. Figure 1not shown).

[0079] Figure 2A for Figure 1 FIG. 1 is an enlarged schematic diagram of the display substrate 10 in the M0 region. Figure 2B FIG. 1 is a schematic diagram of the structure of a sub-pixel group in the display substrate 10. Figure 2A and Figure 2B , the display substrate 10 is taken as an AMOLED display substrate as an example for description, but the present invention is not limited thereto.

[0080] In some embodiments, Figure 2A and Figure 2B As shown, the display substrate 10 includes a base substrate 100 and a plurality of sub-pixel groups 200 located on the base substrate 100. Each sub-pixel group can be composed of a plurality of sub-pixels, and each sub-pixel includes a pixel electrode and an effective light-emitting area. For example, each sub-pixel group 200 includes a first color sub-pixel 210, a second color sub-pixel pair 220, and a third color sub-pixel 230 arranged along a first direction (the X direction shown in the figure). The second color sub-pixel pair 220 includes a first sub-pixel 22-1 and a second sub-pixel 22-2 arranged along a second direction (the Z direction shown in the figure) and having the same light-emitting color. The effective light-emitting area of ​​the first color sub-pixel 210 is the first effective light-emitting area 2100. The effective light-emitting area of ​​the first sub-pixel 22-1 in the second color sub-pixel 220 is the first sub-effective light-emitting area 2201, and the effective light-emitting area of ​​the second sub-pixel 22-2 is the second sub-effective light-emitting area 2202. The effective light-emitting area of ​​the third color sub-pixel 230 is the third effective light-emitting area 2300.

[0081] The pixel electrode of the above sub-pixel includes a main body portion and a connecting portion that are interconnected. Figure 2B As shown in the figure, the pixel electrode 211 of the first color sub-pixel 210 includes an interconnected main body portion 2111 and a connecting portion 2112; the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 includes an interconnected main body portion 221-11 and a connecting portion 221-12; the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 includes an interconnected main body portion 221-21 and a connecting portion 221-22; the pixel electrode 231 of the third color sub-pixel 230 includes an interconnected main body portion 2311 and a connecting portion 2312. Figure 2B It is understood that the main body of each pixel electrode has substantially the same shape as the effective light-emitting area of ​​the sub-pixel to which it belongs, and the main body overlaps with at least a portion of the boundary of the pixel electrode.

[0082] Please combine Figure 2B It is understood that in some embodiments, Figure 2CAs shown, the multiple sub-pixels on the base substrate 100 include at least a first sub-pixel 22-1 and a second sub-pixel 22-2 with the same luminous color. The areas of the orthographic projections of the two pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the base substrate 100 are different. The two orthographic projections of the connecting portion and the main body of at least one sub-pixel in the first sub-pixel 22-1 and the second sub-pixel 22-2 on the straight line extending along the first direction (for example, the X direction) at least partially do not overlap. The orthographic projection of the pixel electrode of the second sub-pixel 22-2 on the straight line extending along the second direction (for example, the Z direction) is located within the orthographic projection of the pixel electrode of the first sub-pixel 22-1 on the same straight line. Here, the second direction intersects with the first direction, and the angle between the two is in the range of 80° to 100°. In the disclosed embodiment, multiple sub-pixels with the same luminous color adopt two different structures as shown in the first sub-pixel 22-1 and the second sub-pixel 22-2. By designing the shapes of the pixel electrodes in the first sub-pixel 22-1 and the second sub-pixel 22-2, the overall layout design of the pixel circuit in the display substrate 10 can be effectively simplified on the basis of improving the sub-pixel distribution density, so as to improve the light transmittance of the display substrate 10.

[0083] For the convenience of explanation, the following shows that the substrate 10 adopts Figure 2A The structure shown in is taken as an example for detailed description.

[0084] Please continue reading Figure 2A , multiple sub-pixel groups 200 are arranged along a first direction (e.g., X direction) to form sub-pixel rows. Multiple sub-pixel rows are arranged along a second direction (e.g., Z direction), and the sub-pixel groups of any two adjacent rows in the multiple sub-pixel rows are misaligned along the first direction, that is, any two adjacent sub-pixel rows have a certain offset along the first direction. Therefore, in any two adjacent sub-pixel rows, the sub-pixels configured to emit the same color light are not aligned in the second direction. Taking the arrangement of the second color sub-pixel pair 220 as an example, as Figure 2A As shown, in any two rows of second color sub-pixel pairs 220 adjacent along the second direction, the second color sub-pixel pairs 220 in the second row R2 are offset from the second color sub-pixel pairs 220 in the first row R1 along the first direction, and the first row R1 and the second row R2 are arranged along the second direction.

[0085] Furthermore, in some examples, with the first direction being the row direction, the subpixel groups in the subpixel rows of odd-numbered rows are arranged in the same manner, and the subpixel groups in the subpixel rows of even-numbered rows are arranged in the same manner.

[0086] Optionally, the offset of two adjacent sub-pixel rows in the first direction is approximately half of the size of the sub-pixel group 200 in the first direction. For example, the size of the sub-pixel group 200 in the first direction is the pitch of the sub-pixel group 200 in the first direction. The pitch here refers to the distance between the centers of the effective light-emitting areas of the two first color sub-pixels 210 in the two adjacent sub-pixel groups 200 in the first direction. The center of the effective light-emitting area here refers to the geometric center of its orthographic projection shape on the substrate. The orthographic projection shape of the effective light-emitting area on the substrate 100 is approximately a regular pattern, such as a symmetrical pattern.

[0087] In addition, it can be understood that the center involved in some embodiments of the present disclosure refers to the geometric center of a regular shape, and refers to the approximate geometric center of an irregular shape. For example, a regular shape with a high degree of similarity to the irregular shape is simulated, and then the geometric center of the simulated shape is used as the center of the irregular shape.

[0088] The first direction and the second direction intersect, and the angle between them may be in the range of 80° to 100°. For example, the first direction and the second direction are two directions perpendicular to each other in the same plane. For example, the plane is the plane where the sub-pixels are arranged, that is, the plane parallel to the substrate 100.

[0089] The above sub-pixel group is a repeating unit, and its repetition only refers to the repetition of the sub-pixel arrangement, and other structures can be different or the same. In addition, the repetition refers to the approximate position, shape, and size. In some cases, for the needs of wiring or opening, the shape may be slightly different, such as openings at different positions.

[0090] In some examples, the first color subpixel 210 is a red subpixel R. The first subpixel 22-1 and the second subpixel 22-2 in the second color subpixel pair 220 correspond to green subpixels G1 and G2. The third color subpixel 230 is a blue subpixel B. However, the colors of the subpixels can be interchanged.

[0091] Understandably, see Figure 3 In an AMOLED display substrate or an active light-emitting display substrate similar thereto, each sub-pixel includes a light-emitting device 0220 and a pixel circuit 0221 coupled to the light-emitting device 0220. The pixel circuit 0221 can drive the light-emitting device 0220 to emit light. The light-emitting device 0220 generally includes an anode, a light-emitting layer, and a cathode stacked in sequence. The electrode coupled to the pixel circuit 0221 in the light-emitting device 0220 is represented as a pixel electrode of the corresponding sub-pixel, and the electrode is, for example, an anode. The following description takes the pixel electrode being an anode as an example.

[0092] For example, Figure 3As shown in FIG. 1 , the pixel circuit 0221 includes a driving circuit 0222, a first light emitting control circuit 0223, a second light emitting control circuit 0224, a data writing circuit 0225, a storage circuit 0226, a threshold compensation circuit 0227, and a reset circuit 0228. The driving circuit 0222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current to the light emitting device 0220 to drive it to emit light.

[0093] The first light-emitting control circuit 0223 is coupled to the first voltage terminal VDD and the first terminal of the driving circuit 0222, respectively, and is configured to realize the connection between the driving circuit 0222 and the first voltage terminal VDD is turned on or off. The second light-emitting control circuit 0224 is coupled to the second terminal of the driving circuit 0222 and the anode of the light-emitting device 0220, respectively, and is configured to realize the connection between the driving circuit 0222 and the light-emitting device 0220 is turned on or off. The data writing circuit 0225 is coupled to the first terminal of the driving circuit 0222, and is configured to write the data signal into the storage circuit 0226 under the control of the gate scanning signal. The storage circuit 0226 is coupled to the control terminal of the driving circuit 0222 and the first voltage terminal VDD, respectively, and is configured to store the data signal. The threshold compensation circuit 0227 is coupled to the control terminal of the driving circuit 0222 and the second terminal of the driving circuit 0222, respectively, and is configured to perform threshold compensation on the driving circuit 0222. The reset circuit 0228 is coupled to the control terminal of the driving circuit 0222 and the anode of the light emitting device 0220 , and is configured to reset the control terminal of the driving circuit 0222 and the anode of the light emitting device 0220 under the control of a reset control signal.

[0094] Optional, such as Figure 3 As shown, the driving circuit 0222 includes a driving transistor T1. The control end of the driving circuit 0222 is the control electrode of the driving transistor T1, the first end of the driving circuit 0222 is the first electrode of the driving transistor T1, and the second end of the driving circuit 0222 is the second electrode of the driving transistor T1. The data writing circuit 0225 includes a data writing transistor T2. The storage circuit 0226 includes a capacitor C. The threshold compensation circuit 0227 includes a compensation transistor T3. The first light emission control circuit 0223 includes a first light emission control transistor T4. The second light emission control circuit 0224 includes a second light emission control transistor T5. The reset circuit 0228 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0095] The first electrode of the data writing transistor T2 is coupled to the first electrode of the driving transistor T1, the second electrode of the data writing transistor T2 is configured to be coupled to the data line Vd to receive the data signal, and the control electrode of the data writing transistor T2 is configured to be coupled to the first gate scanning signal line Ga1 to receive the scanning signal. The first electrode of the capacitor C is coupled to the first voltage terminal VDD, and the second electrode of the capacitor C is coupled to the control electrode of the driving transistor T1. The first electrode of the compensation transistor T3 is coupled to the second electrode of the driving transistor T1, the second electrode of the compensation transistor T3 is coupled to the control electrode of the driving transistor T1, and the control electrode of the compensation transistor T3 is configured to be coupled to the second gate scanning signal line Ga2 to receive the compensation control signal. The first electrode of the first reset transistor T6 is configured to be coupled to the first reset power supply terminal Vinit1 to receive the first reset signal, the second electrode of the first reset transistor T6 is coupled to the control electrode of the driving transistor T1, and the control electrode of the first reset transistor T6 is configured to be coupled to the first reset control signal line Rst1 to receive the first sub-reset control signal. The first electrode of the second reset transistor T7 is configured to be coupled to the second reset power supply terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is coupled to the first electrode of the light emitting device 0220, and the control electrode of the second reset transistor T7 is configured to be coupled to the second reset control signal line Rst2 to receive the second sub-reset control signal. The first electrode of the first light emitting control transistor T4 is coupled to the first voltage terminal VDD, the second electrode of the first light emitting control transistor T4 is coupled to the first electrode of the driving transistor T1, and the control electrode of the first light emitting control transistor T4 is configured to be coupled to the first light emitting control signal line EM1 to receive the first light emitting control signal. The first electrode of the second light emitting control transistor T5 is coupled to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T5 is coupled to the anode of the light emitting device 0220, and the control electrode of the second light emitting control transistor T5 is configured to be coupled to the second light emitting control signal line EM2 to receive the second light emitting control signal. The cathode of the light emitting device 0220 is coupled to the second voltage terminal VSS.

[0096] Here, one of the first voltage terminal VDD and the second voltage terminal VSS is a high voltage terminal, and the other is a low voltage terminal. For example, the first voltage terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage. The second voltage terminal VSS is a voltage source to output a constant second voltage, and the second voltage is a negative voltage, etc. Or, for example, the first voltage terminal VDD is a power signal line, and the power signal line is, for example, a first power signal line and a second power signal line located in different layers and interconnected. The second voltage terminal VSS is grounded.

[0097] In some examples, the scan signal and the compensation control signal can be the same.

[0098] Optionally, the control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 are coupled to the same signal line, such as the first gate scanning signal line Ga1, to receive the same signal (e.g., scanning signal). In this way, the second gate scanning signal line Ga2 may not be provided in the display substrate to reduce the total number of signal lines.

[0099] Optionally, the control electrode of the data write transistor T2 and the control electrode of the compensation transistor T3 are respectively coupled to different signal lines, that is, the control electrode of the data write transistor T2 is coupled to the first gate scan signal line Ga1, and the control electrode of the compensation transistor T3 is coupled to the second gate scan signal line Ga2, and the first gate scan signal line Ga1 and the second gate scan signal line Ga2 both transmit the same signal.

[0100] In other examples, the scan signal and the compensation control signal are different, so that the control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 can be controlled separately, thereby increasing the control flexibility of the pixel circuit.

[0101] Likewise, in some examples, the first light emitting control signal and the second light emitting control signal are the same.

[0102] Optionally, the control electrode of the first light emission control transistor T4 and the control electrode of the second light emission control transistor T5 are coupled to the same signal line, such as the first light emission control signal line EM1, to receive the same signal (e.g., the first light emission control signal). In this way, the second light emission control signal line EM2 may not be provided in the display substrate to reduce the total number of signal lines.

[0103] Optionally, the control electrode of the first light-emitting control transistor T4 and the control electrode of the second light-emitting control transistor T5 are respectively coupled to different signal lines. The control electrode of the first light-emitting control transistor T4 is coupled to the first light-emitting control signal line EM1, and the control electrode of the second light-emitting control transistor T5 is coupled to the second light-emitting control signal line EM2, and the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 transmit the same signal.

[0104] In some other examples, the first light emission control transistor T4 and the second light emission control transistor T5 are different types of transistors, for example, the first light emission control transistor T4 is a P-type transistor, and the second light emission control transistor T5 is an N-type transistor. The first light emission control signal and the second light emission control signal are different, and the embodiments of the present disclosure are not limited to this.

[0105] Likewise, in some examples, the first sub-reset control signal and the second sub-reset control signal are the same.

[0106] Optionally, the control electrode of the first reset transistor T6 and the control electrode of the second reset transistor T7 are coupled to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (e.g., the first sub-reset control signal). In this way, the second reset control signal line Rst2 may not be provided in the display substrate to reduce the total number of signal lines.

[0107] Optionally, the control electrode of the first reset transistor T6 and the control electrode of the second reset transistor T7 are respectively coupled to different signal lines. The control electrode of the first reset transistor T6 is coupled to the first reset control signal line Rst1, and the control electrode of the second reset transistor T7 is coupled to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal.

[0108] In some other examples, the first sub-reset control signal and the second sub-reset control signal may also be different.

[0109] In addition, in some examples, the second sub-reset control signal may be the same as the scan signal. For example, the control electrode of the second reset transistor T7 may be coupled to the first gate scan signal line Ga1 to receive the scan signal Ga1 as the second sub-reset control signal.

[0110] In addition, the first reset power supply terminal Vinit1 coupled to the first electrode of the first reset transistor T6 and the second reset power supply terminal Vinit2 coupled to the first electrode of the second reset transistor T7 can be a DC reference voltage terminal to output a constant DC reference voltage. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same, for example, the first electrode of the first reset transistor T6 and the first electrode of the second reset transistor T7 are connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be a high voltage terminal or a low voltage terminal, as long as they can provide the first reset signal and the second reset signal to reset the control electrode of the driving transistor T1 and the anode of the light-emitting device 0220, and the embodiment of the present disclosure is not limited to this. For example, the first electrode of the first reset transistor T6 and the first electrode of the second reset transistor T7 can be connected to the reset power supply signal line Init respectively.

[0111] It should be noted that Figure 3 The driving circuit 0222, data writing circuit 0225, storage circuit 0226, threshold compensation circuit 0227 and reset circuit 0228 in the pixel circuit 0221 shown are only for illustration. The specific structures of the driving circuit 0222, data writing circuit 0225, storage circuit 0226, threshold compensation circuit 0227 and reset circuit 0228 can be set according to actual application requirements, and the embodiments of the present disclosure do not specifically limit this.

[0112] For example, according to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. For the sake of clarity, the embodiment of the present disclosure takes the transistor as a P-type transistor (for example, a P-type MOS transistor) as an example to elaborate on the technical solution of the present disclosure. That is to say, in the description of the embodiment of the present disclosure, the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the first reset transistor T6 and the second reset transistor T7, etc. can all be P-type transistors. However, the transistors of the embodiment of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) according to actual needs to realize the functions of one or more transistors in the embodiment of the present disclosure.

[0113] It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics, and the thin film transistor may include an oxide semiconductor thin film transistor, an amorphous silicon thin film transistor or a polycrystalline silicon thin film transistor, etc. The first pole and the second pole of the transistor may be symmetrical in structure, so the first pole and the second pole may be indistinguishable in physical structure. In the embodiment of the present disclosure, the gate of the transistor is its control pole, the first pole is one of the source or the drain, and the second pole is the other of the source or the drain. The first pole and the second pole of all or part of the transistors in the embodiment of the present disclosure can be interchangeable as needed.

[0114] It should be noted that, in the embodiment of the present disclosure, the pixel circuit 0221 can be Figure 3 In addition to the 7T1C structure (ie, seven transistors and one capacitor) shown, a structure including other numbers of transistors may also be used, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0115] The pixel electrode of the light emitting device 0220 is coupled to the pixel circuit 0221 , and its shape can be designed according to actual needs to optimize the wiring design of the pixel circuit 0221 and ensure that each sub-pixel has a high distribution density, thereby improving the display effect of the display device.

[0116] In some embodiments, see Figure 2B and Figure 4In at least two sub-pixels of the sub-pixel group 200, for example, the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220, the pixel electrode includes a main body portion and a connecting portion that are interconnected. The first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are: the first sub-pixel 22-1 and the second sub-pixel 22-2 that are closest to each other among the plurality of first sub-pixels 22-1 and the plurality of second sub-pixels 22-2, and the first sub-pixel 22-1 and the second sub-pixel 22-2 are arranged along the second direction.

[0117] The shape of the aforementioned main body is roughly the same as the shape of the effective light-emitting area of ​​the light-emitting device 0220 in which it is located, and part of the edge of the main body is the corresponding edge of the pixel electrode, that is, the main body and its pixel electrode partially overlap. The part where the connecting part is connected to the main body is provided with a notch. For example, the main body includes a first side, a second side and a third side connected in sequence, wherein the third side extends along the second direction; the second side is connected to the connecting part, and there is a gap between the first side and the connecting part, that is, the first side is not connected to the connecting part. In this way, the connecting straight line from any point on the first side to any point on the edge of the connecting part extending in the second direction and away from the third side in the first direction, the area enclosed by the main body and the connecting part is the area where the notch is located, that is, the notch area. Here, the first side, the second side and the third side can be straight sides or folded sides; they are distinguished by whether they are connected to the connecting part.

[0118] Figure 2B The pixel electrode of each sub-pixel is Figure 4 The pixel electrodes of the same color sub-pixels have the same structure, but their shapes are slightly different. For example, Figure 2B The shape of the connection part of each pixel electrode is relatively regular; Figure 4 The shape of the connection portion of each pixel electrode has a large curvature. This embodiment of the present disclosure is not limited to this.

[0119] For example, Figure 2B and Figure 4As shown, in the second color sub-pixel pair 220, the pixel electrode 221-1 of the first sub-pixel 22-1 includes a main body 221-11 and a connecting portion 221-12. The connecting portion 221-12 includes: a curved portion 2-1 connected to its main body 221-11, and a compensation portion 2-2 connected to the curved portion 2-1. The main body 221-11, the curved portion 2-1 and the compensation portion 2-2 are an integral structure. The compensation portion 2-2 extends along the second direction. The maximum dimension D2max of the compensation portion 2-2 along the first direction is greater than the maximum dimension D1max of the curved portion 2-1 along the first direction. Here, the curved portion 2-1 is located between the main body 221-11 and the compensation portion 2-2, and the transition between the curved portion 2-1 and the main body 221-11 and the compensation portion 2-2 can be smoothly processed. The maximum dimension of the curved portion 2-1 along the first direction is its cross-sectional dimension along the first direction. As such, the bent portion 2 - 1 may have a smaller line width than the compensating portion 2 - 2 .

[0120] In the first sub-pixel 22-1, the main body 221-11 includes a first side a2-1, a second side b2-1, and a third side c2-1 connected in sequence. The third side c2-1 extends along the Z direction, the second side b2-1 is connected to the curved portion 2-1 in the connecting portion 221-12, and there is a gap between the first side a2-1 and the connecting portion 221-12. A connecting straight line from any point on the first side a2-1 to any point on the edge of the connecting portion 221-12 extending along the Z direction and away from the third side c2-1 in the X direction, and an area surrounded by the main body 221-11 and the connecting portion 221-12 is a notch area 221-13.

[0121] Here, any point on the edge of the connecting portion 221-12 extending along the Z direction and away from the third side c2-1 in the X direction, for example, is the endpoint of the bending portion 2-1 connected to the compensation portion 2-2 and away from the third side c2-1 in the X direction; or is the endpoint of the free end of the compensation portion 2-2 away from the third side c2-1 in the X direction; but is not limited to this.

[0122] The line width of the above-mentioned curved portion 2-1 is relatively small, which is conducive to ensuring that the orthographic projection area of ​​the notch area 221-13 on the base substrate 100 is relatively large. In some examples, the ratio of the orthographic projection area of ​​the notch area 221-13 on the base substrate 100 to the orthographic projection area of ​​the curved portion 2-1 on the base substrate 100 may be in the range of 0.2 to 5. For example, the ratio of the orthographic projection area of ​​the notch area 221-13 on the base substrate 100 to the orthographic projection area of ​​the curved portion 2-1 on the base substrate 100 is one of 0.2, 1.5, 3 and 5. In this way, by setting a notch area 221-13 with a relatively large area in the first sub-pixel 22-1, it is possible to avoid setting a metal pattern in the notch area 221-13, thereby better improving the light transmittance of the display substrate 10.

[0123] The pixel electrode 221-2 of the second sub-pixel 22-2 and the pixel electrode 221-1 of the first sub-pixel 22-1 have different orthographic projection areas on the base substrate 100, and their structures are correspondingly different. For example, two orthographic projections of the connection portion and the main body portion of at least one of the first sub-pixel 22-1 and the second sub-pixel 22-2 on a straight line extending along the first direction at least partially do not overlap.

[0124] For example, Figure 2B and Figure 4 As shown in , the pixel electrode 221-2 of the second sub-pixel 22-2 includes a main body 221-21 and a connecting portion 221-22. The main body 221-21 and the connecting portion 221-22 are an integrated structure. The main body 221-21 includes a first side a2-2, a second side b2-2 and a third side c2-2 connected in sequence, wherein the third side c2-2 extends along the Z direction, the second side b2-2 is connected to the connecting portion 221-22, and there is a gap between the first side a2-2 and the connecting portion 221-22. At least one side edge of the connecting portion 221-22 can be bent, for example, the edge of the connecting portion 221-22 away from the third side c2-2 in the X direction is bent. A connecting straight line from any point on the first side a2-2 of the main body 221-21 to any point on the edge of the connecting portion 221-22 extending in the Z direction and away from the third side c2-1 in the X direction, the main body 221-21 and the connecting portion 221-22 form a notch area 221-23. Similarly, by providing the notch area 221-23 in the second sub-pixel 22-2, it is possible to avoid providing a metal pattern in the notch area 221-23, thereby further improving the light transmittance of the display substrate 10.

[0125] Optional, please continue to Figure 2B and Figure 4 , the maximum dimension of the connection portion 221-22 of the pixel electrode 221-2 in the second sub-pixel 22-2 in the second direction is less than or equal to the maximum dimension of the bent portion 2-1 of the pixel electrode 221-1 in the first sub-pixel 22-1 in the second direction. In this way, when the main body 221-21 of the pixel electrode 221-2 in the second sub-pixel 22-2 is substantially the same as the main body 221-11 of the pixel electrode 221-1 in the first sub-pixel 22-1, the dimension of the pixel electrode 221-2 in the second sub-pixel 22-2 in the second direction is less than the dimension of the pixel electrode 221-1 in the first sub-pixel 22-1 in the same direction.

[0126] Please combine Figure 2AIt is understood that, in any two rows of second color sub-pixel pairs 220 adjacent along the second direction (e.g., Z direction), the second color sub-pixel pairs 220 of the second row R2 are misaligned with the second color sub-pixel pairs 220 of the first row R1 along the first direction (e.g., X direction). The connecting portion 221-12 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 extends between the pixel electrodes 221-2 of the corresponding two adjacent second sub-pixels 22-2 in the second color sub-pixel pair 220 of the first row R1. For example, the bent portion 2-1 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 and the connecting portion 221-22 of the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 of the first row R1 are approximately located on a straight line extending along the first direction. The compensation portion 2-2 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 is located between the main body portions 221-21 of the pixel electrode 221-2 of two corresponding adjacent second sub-pixels 22-2 in the second color sub-pixel pair 220 of the first row R1. In this way, the orthographic projection of the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 of the first row R1 on the straight line extending along the second direction is within the orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 of the second row R2 on the same straight line.

[0127] Please combine Figure 5 It is understood that the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are designed as above, which is conducive to arranging four pixel circuits 0221 in parallel along the first direction in the space corresponding to each sub-pixel group 200. Therefore, on the basis of improving the sub-pixel distribution density, the overall layout design of the pixel circuit 0221 in the display substrate 10 can be simplified.

[0128] In some embodiments, the pixel electrode 211 of the first color sub-pixel 210 and the pixel electrode 231 of the third color sub-pixel 230 may also refer to the structural design of the pixel electrode 221 - 2 in the second sub-pixel 22 - 2 described above.

[0129] For example, Figure 2B and Figure 4As shown, the pixel electrode 211 of the first color sub-pixel 210 includes a main body 2111 and a connecting part 2112 that are interconnected. The main body 2111 and the connecting part 2112 are an integral structure. The main body 2111 includes a first side a1-1, a second side b1-1, and a third side c1-1 that are connected in sequence, wherein the third side c1-1 extends along the Z direction, the second side b1-1 is connected to the connecting part 2112, and there is a gap between the first side a1-1 and the connecting part 2112. The edge of at least one side of the connecting part 2112 can be bent, for example, the edge of the connecting part 2112 that is away from the third side c1-1 in the X direction is bent. A connecting straight line from any point on the first side a1-1 of the main body 2111 to any point on the edge of the connecting part 2112 that extends along the Z direction and is away from the third side c1-1 in the X direction, and the main body 2111 and the connecting part 2112 form a notch area 2113.

[0130] For example, Figure 2B and Figure 4 As shown, the pixel electrode 231 of the third color sub-pixel 230 includes an interconnected main body 2311 and a connecting portion 2312. The main body 2311 and the connecting portion 2312 are an integral structure. The main body 2311 includes a first side a3-1, a second side b3-1 and a third side c3-1 connected in sequence, wherein the third side c3-1 extends along the Z direction, the second side b3-1 is connected to the connecting portion 2312, and there is a gap between the first side a3-1 and the connecting portion 2312. The edge of at least one side of the connecting portion 2312 can be bent, for example, the edge of the connecting portion 2312 away from the third side c3-1 in the X direction is bent. A connecting straight line from any point on the first side b3-1 of the main body 2311 to any point on the edge of the connecting portion 2312 extending along the Z direction and away from the third side c1-1 in the X direction, and the main body 2311 and the connecting portion 2312 surround a notch area 2313.

[0131] Therefore, by setting the notch area 2113 in the first color sub-pixel 210 and setting the notch area 2313 in the third color sub-pixel 230 , the light transmittance of the display substrate 10 can be further improved.

[0132] In addition, if Figure 2BAs shown, in each sub-pixel group 200, the connection portion 2112 in the first color sub-pixel 210 is located on the side of its main body 2111 close to the second color sub-pixel pair 220. The areas of the anodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are different. The connection portions 221-12 and 221-22 in the second color sub-pixel pair 220 are respectively located on the side of its main body away from the first color sub-pixel 210. For example, the projections of the connection portion and the main body of at least one of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the straight line extending along the first direction at least partially do not overlap. The orthographic projection of the connection portion 2312 in the third color sub-pixel 230 on the straight line extending along the first direction is located within the orthographic projection of its main body 2311 on the same straight line. For example, the center line of the third effective light-emitting area 2300 of the third color sub-pixel 230 along the second direction passes through its main body 2311 and the connection portion 2312.

[0133] In each sub-pixel group 200, the shape of the main body of the pixel electrode of each sub-pixel is substantially the same as the shape of the corresponding effective light-emitting area, and the orthographic projection area of ​​the main body of the pixel electrode of each sub-pixel on the substrate 100 is larger than the orthographic projection area of ​​the corresponding effective light-emitting area on the substrate 100. For example, the geometric center of the main body of the pixel electrode of each sub-pixel is substantially coincident with the geometric center of the corresponding effective light-emitting area. For example, the main body 2111 of the pixel electrode 211 of the first color sub-pixel 210 and the main body 2311 of the pixel electrode 231 of the third color sub-pixel 230 are substantially hexagonal or elliptical in shape, and the main body of the pixel electrode of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 is substantially pentagonal, circular or teardrop-shaped.

[0134] In some embodiments, a plurality of pixel circuits 0221 are arranged in a row along a first direction and in a column along a second direction. Each transistor in the pixel circuit 0221 adopts a top gate structure, and some of the transistors therein may also be a double gate structure, such as the compensation transistor T3 and the first reset transistor T6. However, this is not limited thereto. Taking this as an example, the structure of each layer in the display substrate 10 is schematically described. When the transistor adopts other structures, the structure of each layer in the display substrate 10 may be adaptively adjusted accordingly.

[0135] Figure 5 Schematic diagram of a top-down structure of multiple sub-pixels in some embodiments of the present disclosure. FIG. 6A to FIG. 6IIt is a schematic diagram of a partial layer top-down structure during the sub-pixel manufacturing process, wherein four adjacent pixel circuits corresponding to a first color sub-pixel 210, a second sub-pixel 22-2 in a second color sub-pixel pair 220, a third color sub-pixel 230, and a first sub-pixel 22-1 in another second color sub-pixel pair 220 in an adjacent staggered row are taken as examples, and the positions of the transistors of a pixel circuit 0221 included in one sub-pixel are illustrated, and the positions of the components included in the pixel circuit 0221 in other sub-pixels are roughly the same as the positions of the transistors included in the sub-pixel.

[0136] In addition, the display substrate 10 generally includes a plurality of layers between the base substrate 100 and the pixel electrode, and the plurality of layers include at least one metal layer and at least one insulating layer. Figure 7A to Figure 7G The layers shown in the figure are understood. The embodiment of the present disclosure provides a cross-sectional diagram of the layer structure of a display substrate 10, but is not limited thereto. According to different pixel circuit structures, the layer structure of the display substrate 10 can also be adaptively modified.

[0137] As shown in Figure 5, the pixel circuit 0221 includes Figure 4 The driving transistor T1, data writing transistor T2, compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, second reset transistor T7 and capacitor C are shown; wherein the position of capacitor C overlaps with the driving transistor T1, which is not marked for reference.

[0138] Fig. 6A The top view structure of a semiconductor pattern layer 310 in the display substrate 10 is shown. The semiconductor pattern layer 310 can be formed by patterning semiconductor materials. The semiconductor pattern layer 310 can be used to make the active layers in the above-mentioned driving transistor T1, data writing transistor T2, compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6 and second reset transistor T7. The semiconductor pattern layer 310 includes an active layer pattern (channel region) and a doping region pattern (source-drain doping region) of each transistor of each sub-pixel, and the active layer pattern and doping region pattern of each transistor in the same pixel circuit are integrally arranged.

[0139] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region thereof may be obtained by conducting through doping or the like. Thus, the active layer of each transistor of each sub-pixel is an integral pattern formed of p-silicon. Each transistor in the same pixel circuit includes a doping region pattern (i.e., a source region and a drain region) and an active layer pattern, and the active layers of different transistors are separated by a doping structure.

[0140] For example, the semiconductor pattern layer 310 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.

[0141] For example, the active semiconductor layers in the pixel circuits of sub-pixels of different colors arranged along the first direction have no connection and are disconnected from each other. The active semiconductor layers in the pixel circuits of sub-pixels arranged along the second direction can be integrated or disconnected from each other.

[0142] Figure 6B The top view of a first gate metal layer 320 in the display substrate 10 is shown. The first gate metal layer 320 is a patterned metal film. A gate insulating layer 160 is formed on the semiconductor pattern layer 310. The first gate metal layer 320 is located on the gate insulating layer 160 and is insulated from the semiconductor pattern layer 310.

[0143] For example, the first gate metal layer 320 is used to make the gates of the above-mentioned driving transistor T1, data writing transistor T2, compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6 and second reset transistor T7, as well as the first electrode CC1 of capacitor C.

[0144] Here, signal lines such as the scanning signal line Ga (including the first gate scanning signal line Ga1 and the second gate scanning signal line Ga2), the reset control signal line Rst (including the first reset control signal line Rst1 and the second reset control signal line Rst2), and the light-emitting control signal line EM (including the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2) coupled to the gate of each transistor in the pixel circuit 0221 can also be formed by the first gate metal layer 320.

[0145] In some examples, the first gate scan signal line Ga1 and the second gate scan signal line Ga2 are the same signal line Ga, the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line Rst, and the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are the same signal line EM, but not limited to this.

[0146] For example, the display substrate 10 further includes: a plurality of signal lines extending along the first direction. The orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 on the base substrate overlaps with the orthographic projections of at least three signal lines located on the same layer on the base substrate 100. For example, the reset control signal line, the gate scanning signal line and the light emitting control signal line are arranged in the same layer, all of which extend along the first direction and are arranged along the second direction. The orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 on the base substrate overlaps with the orthographic projections of one reset control signal line, one gate scanning signal line and one light emitting control signal line on the base substrate 100.

[0147] For example, Figure 6B As shown in the dotted boxes in the figure, the gate of the data write transistor T2 can be the portion where the scan signal line Ga overlaps with the semiconductor pattern layer 310. The gate of the first light-emitting control transistor T4 can be the first portion where the light-emitting control signal line EM overlaps with the semiconductor pattern layer 310, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line EM overlaps with the semiconductor pattern layer 310. The gate of the first reset transistor T6 is the first portion where the reset control signal line Rst overlaps with the semiconductor pattern layer 310. The gate of the second reset transistor T7 is the second portion where the reset control signal line Rst overlaps with the semiconductor pattern layer 310. The threshold compensation transistor T3 can be a thin film transistor with a dual-gate structure, the first gate of the threshold compensation transistor T3 can be the portion where the scan signal line Ga overlaps with the semiconductor pattern layer 310, and the second gate of the threshold compensation transistor T3 can be the portion where the protruding structure P protruding from the scan signal line Ga overlaps with the semiconductor pattern layer 310. Figure 3 It can be understood that the gate of the driving transistor T1 can be the first electrode CC1 of the capacitor C.

[0148] It should be noted that the portion of the semiconductor pattern layer 310 facing the gate of the transistor is the channel of the transistor. After being conductively conductive by processes such as ion doping, the semiconductor pattern portions on both sides of each channel can serve as the first and second electrodes of the corresponding transistor.

[0149] In addition, for example Figure 6BAs shown in , the scanning signal line Ga, the reset control signal line Rst and the light emitting control signal line EM are arranged along the first direction (X direction). The scanning signal line Ga is located between the reset control signal line Rst and the light emitting control signal line EM. In this way, for each pixel circuit 0221, in the second direction, the first electrode CC1 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scanning signal line Ga and the light emitting control signal line EM. The protruding structure P protruding from the scanning signal line Ga is located on the side of the scanning signal line Ga away from the light emitting control signal line EM. The gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 are all located on the first side of the gate of the driving transistor T1. The gate of the first light emitting control transistor T4 and the gate of the second light emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.

[0150] Here, the first side and the second side of the gate of the driving transistor T1 are two sides of the gate of the driving transistor T1 that are opposite to each other in the second direction. For example, in the XZ plane, the first side of the gate of the driving transistor T1 may be the upper side of the gate of the driving transistor T1, and the second side of the gate of the driving transistor T1 may be the lower side of the gate of the driving transistor T1. Optionally, the side of the display substrate used for binding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor T1 is the side closer to the IC. The upper side of the gate of the driving transistor T1 is the opposite side of its lower side, for example, the side of the gate of the driving transistor T1 that is farther away from the IC.

[0151] For each pixel circuit 0221, in the first direction, the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5, and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. Here, the third side and the fourth side of the gate of the driving transistor T1 are two sides of the gate of the driving transistor T1 that are opposite to each other in the first direction X. For example, in Figure 6B In the XZ plane shown, the third side of the gate of the driving transistor T1 may be the left side of the gate of the driving transistor T1 , and the fourth side of the gate of the driving transistor T1 may be the right side of the gate of the driving transistor T1 .

[0152] It should be added that the structure of the pixel circuit 0221 can be Figure 6B The mirror structure of the structure shown, that is, each layer structure of the pixel circuit 0221 is based on the channel region of the driving transistor T1, and the left and right structures are flipped. Therefore, the relationship between the left and right sides of the above-mentioned gate can be opposite.

[0153] Figure 6C The top view of a second gate metal layer 330 in the display substrate 10 is shown. The second gate metal layer 330 is a patterned metal film. A first interlayer insulating layer 150 is formed on the first gate metal layer 320. The second gate metal layer 330 is located on the first interlayer insulating layer 150 and is insulated from the first gate metal layer 320.

[0154] For example, the second gate metal layer 330 is used to form the second electrode CC2 of the capacitor C, the reset power signal line Init, and the light shielding portion S. The second electrode CC2 of the capacitor C at least partially overlaps with the orthographic projection of the first electrode CC1 of the capacitor C on the base substrate 100 to form the capacitor C. Optionally, an opening is provided on the second electrode CC2 of the capacitor C, and the orthographic projection of the opening on the base substrate 100 is located within the orthographic projection of the first electrode CC1 of the capacitor C on the base substrate 100; the orthographic projection of the portion of the second electrode CC2 of the capacitor C other than the opening on the base substrate 100 partially overlaps with the orthographic projection of the first electrode CC1 of the capacitor C on the base substrate 100.

[0155] In addition, for example, Figure 6C As shown in FIG. 2 , the second electrode CC2 of the capacitor C is formed by the second gate metal layer 330. Thus, in the pixel circuits 0221 in the same row, the second electrodes CC2 of the capacitors C are interconnected, which can reduce the resistance of the corresponding metal wiring in the second gate metal layer 330, thereby reducing the voltage drop (IR DROP) of the power supply voltage.

[0156] In addition, in some examples, the compensation transistor T3 adopts a dual-gate transistor, and the semiconductor pattern portion between the two channels thereof is in a floating state when the compensation transistor T3 is turned off, and is susceptible to the influence of the surrounding line voltage and jumps, thereby affecting the leakage current of the compensation transistor T3, and further affecting the luminous brightness. In order to keep the voltage of the semiconductor pattern portion between the two channels of the compensation transistor T3 stable, the light shielding portion S is designed to form a capacitor with the semiconductor pattern portion located between the two channels of the compensation transistor T3, and the light shielding portion S is connected to the second power signal line to obtain a constant voltage, thereby ensuring that the voltage of the semiconductor pattern portion in the floating state can be kept stable. The orthographic projection of the light shielding portion S on the base substrate 100 overlaps with the orthographic projection of the semiconductor pattern portion located between the two channels of the compensation transistor T3 on the base substrate 100, and can also prevent the problem of electrical characteristics of the semiconductor pattern portion being changed due to light.

[0157] For example, a second interlayer insulating layer 140 and a first metal layer are sequentially stacked on the second gate metal layer 330 in a direction away from the base substrate 100 . Fig.6D The top view structure of a first metal layer 340 in the display substrate 10 is shown. Fig. 6E The distribution of multiple vias required for achieving electrical connection between the first metal layer 340 and the semiconductor pattern layer 310 , the first gate metal layer 320 , and the second gate metal layer 330 is shown. Figure 6E' The first metal layer 340 and Fig. 6E The first metal layer 340 is a patterned metal film. The first metal layer 340 can be used to make the data line Vd, the second power signal line 500, the first transfer electrode 341, the second transfer electrode 342 and the driving electrode 343. The data line Vd and the second power signal line 500 both extend along the second direction, and there is a gap between the data line Vd and the second power signal line 500 corresponding to the same pixel circuit 0221.

[0158] like Fig.6D , Fig. 6E and Figure 6E' As shown in , the data line Vd is electrically connected to the second electrode T2-2 of the data write transistor T2 through the conduction hole 381 penetrating the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140. The second power signal line 500 is electrically connected to the first electrode T4-1 of the first light emission control transistor T4 through the conduction hole 382 penetrating the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140. The second power signal line 500 and the data line Vd are alternately arranged along the first direction. The second power signal line 500 is electrically connected to the second electrode CC2 of the capacitor C through the conduction hole 3831 penetrating the second interlayer insulating layer 140. The second power signal line 500 is electrically connected to the light shielding portion S through the conduction hole 3832 penetrating the second interlayer insulating layer 140 to provide a constant voltage to the light shielding portion S. One end of the first switching electrode 341 is electrically connected to the second electrode of the compensation transistor T3 through a via hole 384 penetrating through the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140. The other end of the first switching electrode 341 is electrically connected to the gate of the driving transistor T1 (i.e., the first electrode CC1 of the capacitor C) through a via hole 385 penetrating through the first interlayer insulating layer 150 and the second interlayer insulating layer 140. One end of the second switching electrode 342 is electrically connected to the reset power signal line Init through a via hole 386 penetrating through the second interlayer insulating layer 140. The other end of the second switching electrode 342 is electrically connected to the first electrode of the second reset transistor T7 through a via hole 387 penetrating through the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140. The driving electrode 343 is electrically connected to the second electrode of the second light emitting control transistor T5 through a via hole 388 penetrating through the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140.

[0159] In some examples, such as Figure 6E'As shown in , the data line Vd includes a body 610 extending along the second direction, and a convex portion 620 protruding toward the corresponding pixel circuit 0221 in the first direction. Optionally, the overlapping area of ​​the orthographic projection of the via 381 on the substrate 100 and the orthographic projection of the convex portion 620 on the substrate 100 can be 70% to 100% of the orthographic projection area of ​​the via 381 on the substrate 100, for example, 70%, 80% or 100%. That is to say, the electrical connection between the data line Vd and the pixel circuit 0221 is mainly achieved through the electrical connection between its convex portion 620 and the pixel circuit 0221. In this way, when the line width of the data line Vd body 610 is narrow, the convex portion 620 can be used to ensure good electrical connection between the data line Vd and the pixel circuit 0221.

[0160] For example, a passivation layer 123 and a first flat layer 122 may be sequentially stacked on the first metal layer 340 in a direction away from the base substrate 100 to insulate and protect the first metal layer 340. However, the present invention is not limited thereto. For example, the positions of the passivation layer 123 and the first flat layer 122 may be interchanged; or, only the first flat layer 122 is disposed on the side of the first metal layer 340 away from the base substrate 100, without the passivation layer 123.

[0161] The following description will be made by taking an example that the passivation layer 123 and the first planar layer 122 are stacked on the first metal layer 340 , and the first planar layer 122 is located on a side of the passivation layer 123 away from the base substrate 100 .

[0162] For example, a second metal layer is formed on the first planar layer 122 . Fig. 6F The top view structure of a second metal layer 350 in the display substrate 10 is shown. Figure 6G The distribution of multiple vias required for achieving electrical connection between the second metal layer 350 and the first metal layer 340 is shown. Figure 6G' The second metal layer 350 and Figure 6G The second metal layer 350 is a patterned metal film. The second metal layer 350 can be used to make the first power signal line 400 and the connecting electrode 450. The connecting electrode 450 is arranged in a one-to-one correspondence with the driving electrode 343 in the first metal layer 340, and the connecting electrode 450 is electrically connected to the driving electrode 343 through the conductive hole 352 penetrating the first flat layer 122 and the passivation layer 123.

[0163] For example, a second planarization layer 121 and a pixel electrode layer 360 are sequentially stacked on the second metal layer 350 in a direction away from the base substrate 100 . Figure 6H The distribution of the plurality of via holes in the second planar layer 121 is shown. Figure 6H'The relative positions between the second metal layer 350 and the vias in the second planar layer 121 are shown. Fig.6I The distribution of pixel electrodes in the pixel electrode layer 360 is shown. Figure 6I' The positional relationship between the pixel electrode layer 360, the second metal layer 350, the first via hole H1, and the second via hole H2 is shown. Here, the first via hole H1 is a via hole 1210 that penetrates the second flat layer 121. The second via hole H2 is a via hole 352 that penetrates the first flat layer 122 and the passivation layer 123. The pixel electrode layer 360 is a patterned metal film. The pixel electrode layer 360 can be used to make the pixel electrode in each sub-pixel. According to the arrangement of each sub-pixel in the aforementioned sub-pixel group 200, the structure of the pixel electrode in each sub-pixel is as described above. The pixel electrode is electrically connected to the connecting electrode 450 through the via hole 1210 that penetrates the second flat layer 121.

[0164] In some embodiments, please combine Figure 2A and Figure 6I' It is understood that the orthographic projections of the first conductive holes H1 corresponding to the plurality of pixel circuits located in the same row along the first direction on the substrate 100 extend along the first straight line L1. The orthographic projections of the plurality of second conductive holes H2 corresponding to the plurality of pixel circuits located in the same row along the first direction on the substrate 100 extend along the second straight line L2. The effective light-emitting area 2201 of the first sub-pixel 22-1 and the effective light-emitting area 2202 of the second sub-pixel 22-2 corresponding to the plurality of pixel circuits located in the same row along the first direction are respectively located on both sides of the first straight line L1. There is a gap D2 between the orthographic projections of the first conductive holes H1 and the second conductive holes H2 corresponding to the same connecting electrode 450 on the substrate. In this way, in the process of making the second conductive hole H2, the connecting electrode 450 and the first conductive hole H1, the following problems caused by the overlapping of the orthographic projections of the first conductive hole H1 and the second conductive hole H2 on the base substrate 100 can be avoided, for example: the second metal layer 350 is recessed at the second conductive hole H2, the second flat layer 121 cannot be completely etched, and the pixel electrode layer 360 is recessed at the first conductive hole H1, etc.; thereby, it is beneficial to ensure the flatness of the pixel electrode in the pixel electrode layer 360, and the electrical connection performance between the pixel electrode and the connecting electrode 450, so as to enhance the display effect of the display substrate.

[0165] It should be added that the passivation layer 123 and the first flat layer 122 are sequentially stacked on the surface of each transistor away from the base substrate, and the second via H2 penetrates the first flat layer 122 and the passivation layer 123, and has a certain hole depth. After the second metal layer 350 is formed, the second metal layer 350 is easily recessed at the second via H2. The second flat layer 121 is formed on the surface of the second metal layer 350 away from the base substrate 100, and the second flat layer 121 is usually difficult to completely fill the recess of the second metal layer 350 at the second via H2. Therefore, if the first via H1 formed in the second flat layer 121 overlaps with the orthographic projection of the second via H2 on the base substrate 100, it is easy to cause the pixel electrode in the subsequent pixel electrode layer 360 to have a more serious sinking problem at the first via H1. The embodiment of the present disclosure can effectively improve the above problems by setting a gap D2 between the orthographic projections of the first via H1 and the second via H2 on the base substrate.

[0166] In addition, if Figure 2A and Figure 6I' As shown in , optionally, the orthographic projections of the first via holes H1 corresponding to the plurality of pixel circuits located in the same column along the second direction on the base substrate 100 are arranged along the third straight line L3. Optionally, the orthographic projections of the first via holes H1 and the second via holes H2 corresponding to the same connection electrode 450 on the base substrate 100 are arranged along the third straight line L3. In this way, the first via holes H1 and the second via holes H2 are distributed in an array in the display substrate 10, which is convenient for manufacturing and is also conducive to simplifying the layout design of the corresponding mask.

[0167] It can be understood that, in some examples, the orthographic projection of the first conductive hole H1 on the base substrate 100 and the orthographic projection of the second conductive hole H2 on the base substrate 100 have substantially the same shape and area. Here, the shapes of the first conductive hole H1 and the second conductive hole H2 can be regular rectangles or circles, so as to facilitate the determination of the overlap area between the connecting electrode 450 and the pixel electrode, and between the connecting electrode 450 and the driving electrode 343, so as to ensure that the connecting line between the pixel electrode and the pixel circuit (for example, the connecting electrode 450 and the driving electrode 343) has a small resistance value.

[0168] In some embodiments, the orthographic projection of the connection electrode 450 on the substrate 100 and the orthographic projection of the drive electrode 343 on the substrate 100 have substantially the same shape. Optionally, the orthographic projection area of ​​the connection electrode 450 on the substrate 100 is greater than the orthographic projection area of ​​the drive electrode 343 on the substrate 100. For example, the orthographic projection of the drive electrode 343 on the substrate 100 is located within the orthographic projection of the corresponding connection electrode 450 on the substrate 100, and a portion of the boundaries of the orthographic projections of the two overlap or substantially overlap. For example, the orthographic projection of the connection electrode 450 on the substrate 100 and the orthographic projection of the drive electrode 343 on the substrate 100 have a non-overlapping portion, and the orthographic projection of the first conductive hole H1 on the substrate 100 overlaps with the non-overlapping portion. This facilitates the arrangement of the first conductive hole H1 and the second conductive hole H2 on a straight line along the first direction and the second direction, and reasonably improves the space utilization of the display substrate, so that the display substrate has a higher light transmittance.

[0169] In some embodiments, please combine Figure 6I' and Figure 8 It is understood that the driving electrode 343 is electrically connected to the second electrode of the second light emitting control transistor T5 through the conduction hole 388 penetrating the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140. The conduction hole 388 penetrating the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140 is taken as the third conduction hole H3, and the third conduction hole H3, the second conduction hole H2 and the first conduction hole H1 corresponding to the same driving electrode 343 have a gap between two of the three orthographic projections on the base substrate 100.

[0170] Optionally, the distance B1 between the orthographic projection of any one of the first conductive hole H1 and the second conductive hole H2 on the base substrate 100 and the effective light-emitting area of ​​the corresponding sub-pixel is greater than 2 μm, and its value range is, for example, 2 μm to 20 μm. Figure 8 As shown in FIG. 1 , a distance B1 between an orthographic projection of any one of the first conductive hole H1 and the second conductive hole H2 on the base substrate 100 and an effective light emitting area K of the corresponding sub-pixel is greater than or equal to 2.5 μm.

[0171] Optionally, the minimum interval between the orthographic projection of at least one of the first conductive hole H1 and the second conductive hole H2 on the base substrate 100 and the orthographic projection of the corresponding third conductive hole H3 on the base substrate 100 is greater than 0.8 μm, and its value range is, for example, 0.8 μm to 10 μm. The minimum interval between the orthographic projections of the first conductive hole H1 and the second conductive hole H2 on the base substrate 100 is greater than 1 μm, and its value range is, for example, 1 μm to 10 μm. For example, Figure 8As shown in , the minimum interval B2 between the orthographic projection of the first conductive hole H1 on the substrate 100 and the orthographic projection of the corresponding second conductive hole H2 on the substrate 100 is 1.2 μm; the minimum interval B3 between the orthographic projection of the second conductive hole H2 on the substrate 100 and the orthographic projection of the corresponding third conductive hole H3 on the substrate 100 is 0.9 μm. The first conductive hole H1 and the second conductive hole H2 are arranged along a straight line extending in the second direction, and the minimum interval between the orthographic projection of the first conductive hole H1 on the substrate 100 and the orthographic projection of the corresponding third conductive hole H3 on the substrate 100 is 2.1 μm (0.9 μm+1.2 μm).

[0172] In the process of manufacturing the third via H3, the driving electrode 343 and the second via H2, the following problems can be avoided due to the overlapping of the orthographic projections of the second via H2 and the third via H3 on the base substrate 100, for example: the first metal layer 340 is recessed at the third via H3, the passivation layer 123 and the first flat layer 122 cannot be completely etched, and the connecting electrode 450 is recessed at the second via H2, etc.; thereby, it is beneficial to ensure the flatness of the connecting electrode 450 and the electrical connection performance between the connecting electrode 450 and the driving electrode 343, so as to improve the display effect of the display substrate.

[0173] In addition, optionally, the orthographic projection shape of the third conductive hole H3 on the base substrate 100 may be substantially the same as the shapes of the first conductive hole H1 and the second conductive hole H2. For example, the shape of the third conductive hole H3 may be a regular rectangle or circle.

[0174] Optionally, the orthographic projections of the third conductive holes H3 corresponding to the plurality of pixel circuits located in the same column along the second direction on the base substrate 100 extend and are arranged along the same straight line.

[0175] Optionally, the orthographic projections of the third conductive holes H3 corresponding to the plurality of pixel circuits located in the same row along the first direction on the base substrate 100 extend along the same straight line.

[0176] Thus, in some embodiments, a plurality of third via holes H3 are distributed in an array in the display substrate 10, which is not only convenient for manufacturing, but also conducive to the design of the relative distribution position between the third via holes H3 and the second via holes H2 and the first via holes H1, so as to reasonably improve the space utilization of the display substrate and make the display substrate have a higher light transmittance.

[0177] In addition, in some embodiments, the via hole 381 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 is the fourth via hole H4. The orthographic projections of the fourth via holes H4 corresponding to the plurality of pixel circuits located in the same column along the second direction on the base substrate 100 can be arranged along the same straight line to facilitate manufacturing and reasonably improve the space utilization of the display substrate, so that the display substrate has a higher light transmittance.

[0178] In some embodiments, Figure 6G' As shown in FIG. 1 , the first power signal line 400 includes a plurality of first sub-power signal lines 410 extending along a first direction and a plurality of second sub-power signal lines 420 extending along a second direction. The first sub-power signal lines 410 are interconnected with the second sub-power signal lines 420. That is, the first power signal lines 400 are distributed in a grid shape.

[0179] Please combine Figure 5 and Figure 6G' It is understood that in the same second color sub-pixel pair 220, there is a gap between the effective light-emitting area of ​​the first sub-pixel 22-1 and the effective light-emitting area of ​​the second sub-pixel 22-2. The orthographic projection of the first sub-power signal line 410 on the base substrate 100 passes through the gap between the effective light-emitting area of ​​the first sub-pixel 22-1 and the effective light-emitting area of ​​the second sub-pixel 22-2. That is to say, in the same second color sub-pixel pair 220, the orthographic projection of the gap between the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the straight line extending along the second direction does not overlap with the orthographic projection of the effective light-emitting areas in the second color sub-pixel pair on the same straight line.

[0180] In some examples, the center of the orthographic projection of at least one of the first effective light-emitting area 2100 of the first color sub-pixel 210 and the third effective light-emitting area 2300 of the third color sub-pixel 230 on the substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the substrate 100. That is, the first sub-power signal line 410 can serve as the symmetric center of the first effective light-emitting area 2100 and the third effective light-emitting area 2300, so that the portions of the first effective light-emitting area 2100 and the third effective light-emitting area 2300 located on both sides of the first sub-power signal line 410 have consistent application environments, thereby ensuring that the intensity of light emitted from the first effective light-emitting area 2100 and the third effective light-emitting area 2300 is uniform, so as to improve color deviation.

[0181] In some examples, the ratio of the two distances between the orthographic projections of the two effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the same second color sub-pixel pair 220 on the substrate substrate to the orthographic projections of the corresponding first sub-power signal line 410 on the substrate substrate 100 is in the range of 0.9 to 1.1. That is, in the same second color sub-pixel pair 220, the first sub-effective light-emitting area 2201 of the first sub-pixel 22-1 and the second sub-effective light-emitting area 2202 of the second sub-pixel 22-2 are substantially the same distance from the same first sub-power signal line 410. For example, the first sub-effective light-emitting area 2201 of the first sub-pixel 22-1 and the second sub-effective light-emitting area 2202 of the second sub-pixel 22-2 are symmetrically arranged with the first sub-power signal line 410 as the center. In this way, the two effective light-emitting areas in the second color sub-pixel pair 220 not only have the same light-emitting area, but also can have a consistent application environment relative to the first sub-power signal line 410 to improve color deviation.

[0182] At least one second sub-power signal line 420 has a break 421, that is, the second sub-power signal line 420 is not a continuous signal line. The second sub-power signal line 420 includes a plurality of signal line segments disconnected from each other, and the interval between any two adjacent signal line segments along its extension direction is the above-mentioned break 421. The effective light-emitting area and the interval of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are located at the break 421. For example, the orthographic projection of the second sub-power signal line 420 on the substrate 100, the orthographic projection of the effective light-emitting area and the interval of the first sub-pixel 22-1 and the second sub-pixel 22-2 that do not pass through the substrate 100. The orthographic projection of the virtual line between the two endpoints of the break 421 in the second direction on the substrate 100, and the orthographic projection of the effective light-emitting area and the interval of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the substrate 100.

[0183] Optionally, the second sub-power signal line 420 with the break 421 does not overlap with the two effective light-emitting areas of the corresponding second color sub-pixel pair and the orthographic projections of the intervals therebetween on the base substrate.

[0184] Optionally, the orthographic projection of the first power signal line 400 on the substrate 100 does not overlap with the orthographic projection of the effective light-emitting area of ​​the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 on the substrate 100. That is, the orthographic projection of the effective light-emitting area of ​​the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 on the substrate 100 may overlap with the orthographic projection of the corresponding break 421 in the second sub-power signal line 420 on the substrate 100, but does not overlap with the orthographic projection of the physical part of the first sub-power signal line 410 and the second sub-power signal line 420 on the substrate 100. This is conducive to improving the flatness of the film layer in the second color sub-pixel pair 220 located in the effective light-emitting area and located on the side of the pixel electrode away from the substrate 100, thereby minimizing the color deviation of the second color sub-pixel pair 220 during display.

[0185] In addition, the second sub-power signal line 420 and the second power signal line 500 extend in the same direction. The second sub-power signal line 420 is electrically connected to the second power signal line 500 through the via 352 that penetrates the first planar layer 122 and the passivation layer 123. Thus, the second power signal line 500 and the first power signal line 400 can be connected in parallel to reduce the resistance of the metal wiring in the second metal layer 350, thereby reducing the voltage drop (IR DROP) of the power supply voltage.

[0186] Optionally, the orthographic projections of the second power signal line 500 and the second sub-power signal line 420 coupled thereto on the substrate 100 at least partially overlap. The orthographic projection of the second power signal line 500 on the substrate 100 partially overlaps with the orthographic projections of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 on the substrate 100. For example, the orthographic projection of the second sub-power signal line 420 on the substrate 100 is located within the orthographic projection of the second power signal line 500 on the substrate 100. For example, the second power signal line 500 may substantially overlap with the portion of the second sub-power signal line 420 except the break 421, but the line width of the second sub-power signal line 420 is partially adjusted and does not completely overlap with the second power signal line 500, for example, the area of ​​the overlapped portion of the second power signal line 500 and the second sub-power signal line 420 accounts for more than 70% of the orthographic projection area of ​​the second power signal line 500 on the substrate 100.

[0187] Optionally, the second sub-power signal line 420 has slightly different widths in the first direction at different positions in the extension direction thereof, for example, the second sub-power signal line 420 has a reduced width at positions corresponding to certain color sub-pixels. Similarly, the second power signal line 500 has slightly different widths in the first direction at different positions in the extension direction thereof.

[0188] In some examples, the second power signal line 500 is consistent with the portion with a wider line width in the second sub-power signal line 420. Figure 6G' It is understood that, in this way, the via hole 352 penetrating the first flat layer 122 and the passivation layer 123 is the fifth via hole H5, and the orthographic projections of the plurality of fifth via holes H5 located in the same row along the first direction on the base substrate 100 can be arranged along the fourth straight line L4. In addition, the distance from the orthographic projection of the fifth via hole H5 on the base substrate 100 to the orthographic projection of any effective light-emitting area on the base substrate 100 is greater than 2.5 um.

[0189] In some embodiments, two second sub-power signal lines 420 located on both sides of the first effective light-emitting area 2100 of the first color sub-pixel 210 and adjacent to the first effective light-emitting area 2100 are unequally distant from a center line extending along the second direction of the first effective light-emitting area 2100. For example, a second sub-power signal line 420 adjacent to the first effective light-emitting area 2100 in the first direction and distant from a center line extending along the second direction of the first effective light-emitting area 2100 is greater than another second sub-power signal line 420 adjacent to the first effective light-emitting area 2100 in the first direction.

[0190] Based on this, the display substrate 10 further includes a plurality of pads 430 disposed in the same layer as the first power signal line 400, and a plurality of support portions 440 disposed in the same layer as the pads 430. The aforementioned second metal layer 350 can also be used to make the pads 430 and the support portions 440. The pads 430 extend along the second direction and are coupled correspondingly to the first sub-power signal line 410. The pads 430 are located between the first effective light-emitting area 2100 and the second sub-power signal line 420. The pads 430 can adopt a long strip structure extending along the second direction. The two ends of the pads 430 along the second direction are respectively coupled correspondingly to the second sub-power signal line through the support portions 440 to form a closed ring structure. Optionally, the center of the orthographic projection of the pads 430 on the base substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the base substrate 100. That is, the first sub-power signal line 410 can be the symmetry center of the pads 430. The distances from the first effective light-emitting area 2100 to the pads 430 and the second sub-power signal line 420 located on both sides thereof in the first direction are roughly the same. For example, the ratio of the distances between the two ranges from 0.9 to 1.1, thereby ensuring that both sides of the first effective light-emitting area 2100 have a relatively consistent application environment. The intensity of light emitted from the first effective light-emitting area 2100 is uniform, which is beneficial to improving color deviation.

[0191] In addition, the spacer 430 is electrically connected to the first power signal line 400 , which can prevent the spacer 430 from being in a floating state, thereby affecting the normal operation of the light-emitting device 0220 .

[0192] Optionally, the orthographic projection of the spacer 430 on the base substrate 100 does not overlap with the orthographic projection of the first effective light-emitting area 2100 on the base substrate, which can prevent the spacer 430 from affecting the display of the first color sub-pixel 210 .

[0193] Optionally, the orthographic projections of the spacer 430 and the pixel electrode 211 of the first color sub-pixel 210 on the base substrate 100 do not overlap, or the overlapping area between the two is very small, which is beneficial to reducing color deviation.

[0194] Optionally, the size of the pad 430 along the second direction is greater than its size along the first direction. The size of the pad 430 along the second direction is smaller than the size of the first effective light-emitting area 2100 along the same direction. When the display substrate in the embodiment of the present disclosure is applied to under-screen fingerprint detection, the size of the pad 430 along the second direction can be designed to be smaller than the size of the first effective light-emitting area in the same direction to improve the light transmittance of the display substrate.

[0195] In some embodiments, along a direction perpendicular to the base substrate 100, in each film layer from the base substrate 100 to the pixel electrode layer 360, at least a portion of the notch area of ​​the pixel electrode does not overlap with the metal patterns in each metal layer, so that the light transmittance of this portion of the area is greater than 60%.

[0196] Optionally, along a direction perpendicular to the base substrate 100, in each film layer from the base substrate 100 to the pixel electrode layer 360, at least a portion of the recessed area does not overlap with the metal patterns in each metal layer and the semiconductor patterns in the semiconductor pattern layer, so that the light transmittance of this portion of the area is greater than 70%.

[0197] In this way, when the display substrate 10 is used for optical under-screen fingerprint detection, the light-transmitting part of the notch area can be used to reflect light, so as to facilitate the detection of fingerprint lines. It should be noted that there may be other light-transmitting areas in the display substrate 10, for example: any area that does not overlap with the metal layers of the display substrate 10 along a direction perpendicular to the base substrate 100. This embodiment of the present disclosure will not be described in detail.

[0198] Optical under-screen fingerprint detection technology usually uses the light emitted by the display substrate 10 as the light source. The fingerprint sensor is usually arranged on the non-display side of the display substrate, for example, it can be located on the side of the light-emitting device 0220 close to the base substrate 100, so as to realize the under-screen fingerprint detection function.

[0199] For example, the light emitted by each sub-pixel can be used for display and as light for fingerprint detection under the screen, and a top film layer for placing the finger can also be provided on the side of the sub-pixel away from the substrate 100. The fingerprint sensor for collecting the fingerprint image can be arranged on the same side of the display substrate 10 as each sub-pixel, and the fingerprint sensor is arranged on the side of the light-emitting device 0220 in each sub-pixel close to the substrate 100, for detecting the reflected light reflected from the fingerprint on the surface of the top film layer. The fingerprint sensor may include a plurality of detection units arranged in an array. In order to realize the fingerprint detection function under the screen, at least part of the film layers such as the top film and the substrate substrate is transparent, and a light-transmitting area is provided between adjacent sub-pixels so that the reflected light of the fingerprint on the surface of the top film can be incident on the fingerprint sensor to obtain the fingerprint image. Since the anode of the light-emitting device of each sub-pixel is easy to affect the light transmittance, it also affects the sensitivity of fingerprint detection. Therefore, providing a notch in the pixel electrode of the light-emitting device can effectively improve the light transmittance in the display substrate.

[0200] It should be supplemented that, in some embodiments, in the two pixel circuits of the first sub-pixel 22-1 and the second sub-pixel 22-2, the metal having the same potential as the control electrode of the driving transistor T1 includes: the first electrode CC1 of the capacitor C located in the first gate metal layer 320, and the first switching electrode 341 located in the first metal layer 340. The orthographic projection of the first electrode CC1 of the capacitor C and the first switching electrode 341 in each pixel circuit on the base substrate 100 is taken as the first projection, the projection area of ​​the orthographic projection of the pixel electrode of the first sub-pixel 22-1 on the base substrate 100 and the overlapped first projection is taken as the first area, and the projection area of ​​the orthographic projection of the pixel electrode of the second sub-pixel 22-2 on the base substrate 100 and the overlapped first projection is taken as the second area, then the value range of the area ratio of the first area to the second area can be: 0.8 to 1.2. That is, the first area and the second area are substantially the same. This helps to ensure that the loads of the two pixel circuits of the first sub-pixel 22-1 and the second sub-pixel 22-2 are consistent, thereby avoiding the problem of uneven light output brightness of the first sub-pixel 22-1 and the second sub-pixel 22-2.

[0201] Since the orthographic projection of the first electrode CC1 of the capacitor C in each pixel circuit on the substrate substrate 100 and the orthographic projection of the first switching electrode 341 on the substrate substrate 100 partially overlap, and the shapes of the two pixel electrodes in the first sub-pixel 22-1 and the second sub-pixel 22-2 are different, therefore, optionally, the area of ​​overlap between the orthographic projections of the pixel electrode 221-1 of the first sub-pixel 22-1 and the first electrode CC1 of the capacitor C on the substrate substrate 100 is smaller than the area of ​​overlap between the orthographic projections of the pixel electrode 221-2 of the second sub-pixel 22-2 and the first electrode CC1 of the capacitor C on the substrate substrate 100; and the area of ​​overlap between the orthographic projections of the pixel electrode 221-1 of the first sub-pixel 22-1 and the first switching electrode 341 on the substrate substrate 100 is larger than the area of ​​overlap between the orthographic projections of the pixel electrode 221-2 of the second sub-pixel 22-2 and the first switching electrode 341 on the substrate substrate 100.

[0202] Furthermore, in some embodiments, Fig. 9As shown, the compensation part 2-2 of the pixel electrode 221-1 of the first sub-pixel 22-1 includes: a first compensation part 2-21 electrically connected to the curved part 2-1, and a second compensation part 2-22 located on a side of the first compensation part 2-21 away from the curved part 2-1 and electrically connected to the first compensation part 2-21. The first compensation part 2-21 and the second compensation part 2-22 can adopt a long strip structure extending along the second direction. The orthographic projection of the second compensation part 2-22 on the base substrate 100 does not overlap with the orthographic projection of the first electrode CC1 of the capacitor C on the base substrate 100. The size of the second compensation part 2-22 in the first direction is smaller than the size of the first compensation part 2-21 in the same direction, which is conducive to obtaining more light-transmissive areas in the display substrate 10 to improve the light transmittance of the display substrate 10.

[0203] In addition, if Fig. 9 As shown, in some examples, the compensation portion 2-2 of the pixel electrode 221-1 in the first sub-pixel 22-1 is located between the pixel electrode 231 of the adjacent third color sub-pixel 230 and the pixel electrode 211 of the first color sub-pixel 210. The first distance W1 from the second compensation portion 2-22 to the pixel electrode 231 of the third color sub-pixel 230 in the first direction may be substantially the same as the second distance W2 from the second compensation portion 2-22 to the pixel electrode 211 of the first color sub-pixel 210 in the first direction. The third distance W3 from the first compensation portion 2-21 to the pixel electrode 231 of the third color sub-pixel 230 in the first direction may be substantially the same as the fourth distance W4 from the first compensation portion 2-21 to the pixel electrode 211 of the first color sub-pixel 210 in the first direction. The first distance W1 is greater than the third distance W3, and the second distance W2 is greater than the fourth distance W4. For example, the ratio of the second distance W2 to the first distance W1 ranges from 0.9 to 1.1. For example, the first distance W1 has a value range of 4.5 μm to 6.5 μm, and for example, it is 5.47 μm. The second distance W2 has a value range of 4.5 μm to 6.5 μm, and for example, it is 5.73 μm. The ratio of the fourth distance W4 to the third distance W3 has a value range of 0.9 to 1.1. For example, the third distance W3 has a value range of 2.5 μm to 4.0 μm, and for example, it is 3.0 μm. The second distance W2 has a value range of 2.5 μm to 4.0 μm, and for example, it is 3.0 μm.

[0204] The structure of each sub-pixel in the display substrate 10 is as described above. In some embodiments, by reducing the area of ​​the electrode in each sub-pixel outside the effective light-emitting area, the area of ​​light blocking can be reduced to improve the light transmittance of the display substrate. For example, while ensuring that the area of ​​the effective light-emitting area of ​​each sub-pixel remains unchanged, by changing the shape of the portion of the pixel electrode outside the effective light-emitting area, such as the connecting portion, that is, by increasing the area ratio of the effective light-emitting area to the pixel electrode, the effect of the pixel electrode on light blocking can be reduced, thereby improving the light transmittance of the display substrate.

[0205] For example, in the first color sub-pixel 210, the area ratio of the first effective light-emitting area 2100 to the pixel electrode 211 ranges from 53% to 55%. In the second color sub-pixel pair 220, the area ratio of the first sub-effective light-emitting area 2201 to the pixel electrode 221-1 ranges from 43.5% to 48%, and the area ratio of the second sub-effective light-emitting area 2202 to the pixel electrode 221-2 ranges from 43.5% to 48%. In the third color sub-pixel 230, the area ratio of the third effective light-emitting area 2300 to the pixel electrode 231 ranges from 67.5% to 69%. For example, in the first color sub-pixel 210, the area ratio of the first effective light-emitting area 2100 to the pixel electrode 211 is 54.9%. In the second color sub-pixel pair 220, the area ratio of the first sub-effective light-emitting area 2201 to the pixel electrode 221-1 is 47%, and the area ratio of the second sub-effective light-emitting area 2202 to the pixel electrode 221-2 is 47%. In the third color sub-pixel 230, the area ratio of the third effective light-emitting area 2300 to the pixel electrode 231 is 68.3%. This ensures that the display substrate 10 has a good light transmittance as a whole, thereby improving the sensitivity of fingerprint detection.

[0206] In addition, optionally, the area ratio of the first effective light-emitting area 2100, the effective light-emitting area of ​​the second color sub-pixel pair 220, and the third effective light-emitting area 2300 is approximately 1:1.27:1.47. The area ratio of the pixel electrode 211 in the first color sub-pixel 210, the pixel electrode in the second color sub-pixel pair 220, and the pixel electrode 231 in the third color sub-pixel 230 is approximately 1:1.48:1.18. Here, the "area ratio" refers to the ratio of the areas of the orthographic projection on the substrate.

[0207] In order to clearly illustrate the layer structure of the display substrate 10 in some embodiments of the present disclosure, please refer to Fig. 7A Some embodiments of the present disclosure also provide cross-sectional examples of multiple local areas in a display substrate 10 . Figure 7B for Fig. 7A The cross-sectional view of the display substrate 10 along the AA′ direction is shown. Figure 7C for Fig. 7AA schematic cross-sectional view of the display substrate 10 along the BB′ direction is shown. Fig.7D for Fig. 7A A schematic cross-sectional view of a display substrate 10 along the CC′ direction is shown.

[0208] Fig. 7E for Fig. 7A The display substrate 10 is shown as a schematic cross-sectional view along the DEFGH direction. Figure 7F for Fig. 7A A schematic cross-sectional view of a display substrate 10 along the LMN direction is shown. Figure 7G for Fig. 7A The cross-sectional view of the display substrate 10 along the RST direction is shown in FIG. FIG. 6A to FIG. 6I ,as well as Figure 7A to Figure 7G understand.

[0209] Here, Figure 7B to Figure 7G The cross-sectional views in FIG. 1 are all based on the example that the passivation layer 123 and the first flat layer 122 are formed between the first metal layer 340 and the second metal layer 350, and the first flat layer 122 is located on the side of the passivation layer 123 away from the base substrate 100. However, the present invention is not limited thereto.

[0210] Please combine Figure 7B to Figure 7G It is understood that the display substrate 10 also includes a pixel defining layer 130 located on the pixel electrode layer 360. The pixel defining layer 130 has a plurality of openings for defining an effective light-emitting area of ​​a sub-pixel. The light-emitting device 0220 includes an anode, a light-emitting layer, and a cathode that are stacked in sequence. The anode of the light-emitting device 0220 is coupled to the pixel circuit 0221. The opening in the pixel defining layer 130 exposes the anode of the light-emitting device 0220. At least part of the light-emitting layer of the light-emitting device 0220 is located in the opening, and the cathode is located on the side of the pixel defining layer 130 facing the base substrate. When the light-emitting layer of the subsequent light-emitting device 0220 is formed in the opening of the pixel defining layer 130, the portion of the light-emitting layer in contact with the anode can emit light under the voltage drive of the anode and the cathode to form an effective light-emitting area.

[0211] Here, "effective light-emitting area" may refer to a two-dimensional plane area, which is parallel to the substrate 100. It should be noted that, due to process reasons, the size of the opening of the pixel defining layer 130 away from the substrate 100 is slightly larger than the size of the part close to the substrate 100, or the size gradually increases from the side close to the substrate 100 to the side away from the substrate 100. Therefore, the size of the effective light-emitting area may be slightly different from the size of the opening at different positions in the pixel defining layer 130, but the overall area shape and size are basically the same. For example, the orthographic projection of the effective light-emitting area on the substrate 100 is roughly coincident with the orthographic projection of the corresponding opening in the pixel defining layer 130 on the substrate 100. For example, the orthographic projection of the effective light-emitting area on the substrate 100 completely falls within the orthographic projection of the corresponding opening in the pixel defining layer 130 on the substrate 100, and the two are similar in shape, and the orthographic projection area of ​​the effective light-emitting area on the substrate 100 is slightly smaller than the orthographic projection area of ​​the corresponding opening in the pixel defining layer 130 on the substrate 100.

[0212] like Fig. 7A As shown in FIG. 1 , the second color sub-pixel pair 220 includes a first sub-effective light emitting area 2201 and a second sub-effective light emitting area 2202 with a gap therebetween. The “gap” refers to a substantial portion of the pixel defining layer 130 between two openings defined by the pixel defining layer 130 .

[0213] In addition, in the same second color sub-pixel pair 220, the dimension of the interval between the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 along the second direction is smaller than the dimension of the first effective light-emitting area 2100 along the second direction, and the dimension of the interval along the second direction is smaller than the dimension of the third effective light-emitting area 2300 along the second direction.

[0214] Optionally, along the second direction, the size of the first effective light-emitting area 2100 is larger than the size of the third effective light-emitting area 2300. For example, the size of the first effective light-emitting area 2100 may be 45-49 microns, for example, 47 microns; the size of the third effective light-emitting area 2300 may be 38-42 microns, for example, 40 microns.

[0215] In some examples, such as Fig. 7AAs shown, the shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are substantially the same. The ratio of the distance between the orthographic projection of the first sub-power signal line 410 on the substrate 100 and the two centers of the two orthographic projections of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 on the substrate 100 is 0.9 to 1.1. For example, the distance between the orthographic projection of the first sub-power signal line 410 on the substrate 100 and the two centers of the two orthographic projections of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 on the substrate 100 is substantially equal. Thus, the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 are symmetrically distributed relative to the first sub-power signal line 410, which is conducive to ensuring the environmental consistency of the first sub-pixel 22-1 and the second sub-pixel 22-2 included in the second color sub-pixel pair 220. However, the present invention is not limited thereto. For example, the orthographic projection of the first sub-power signal line 410 on the base substrate 100 may also be closer to one of the second color sub-pixel pairs 220. In addition, optionally, the orthographic projection of the first sub-power signal line 410 on the base substrate 100 does not overlap with the orthographic projections of the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 on the base substrate 100.

[0216] The center of the above-mentioned orthographic projection refers to the geometric center of the orthographic projection shape. The shape of the orthographic projection of the effective light-emitting area on the substrate is determined by the shape of the effective light-emitting area. The shape of the effective light-emitting area is roughly the same as the shape of the opening of the corresponding pixel defining layer 130.

[0217] For example, Fig. 7A As shown, the shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 include a pentagon, a circle or a water drop shape. Fig. 7A It is schematically shown that the shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are pentagons, and the pentagon includes a set of parallel opposite sides (parallel to the second direction) and a vertical side (parallel to the first direction), and the vertical side is perpendicular to the set of parallel opposite sides, and the two vertical sides of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 in each second color sub-pixel pair 220 are adjacently arranged. For example, the first sub-power signal line 410 is located between the two vertical sides and passes through the midpoint of the shortest line between the two vertical sides.

[0218] In addition, although Fig. 7AThe shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 in the embodiment include a strict angle formed by two line segments, but in some embodiments, the intersection shape of the two line segments of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 may be a rounded shape, such as a circle or a teardrop shape. That is, on the basis of the above-mentioned pentagonal shape, the corners of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are rounded. For example, when forming the opening of the pixel defining layer 130, the corners of the opening may form a rounded shape, so that the shape of the formed effective light-emitting area may be a rounded shape.

[0219] A partial cross-section of the second color sub-pixel pair 220 is shown in FIG. Figure 7B As shown in . In the second color sub-pixel pair 220, the light-emitting layer 223 and the cathode layer 222 are sequentially stacked on the surface of the pixel defining layer 130 away from the base substrate 100, and are in contact with the pixel electrode 221 exposed by the corresponding opening in the pixel defining layer 130. Some embodiments of the present disclosure are described by taking the light-emitting layer 223 in the first sub-pixel 22-1 and the second sub-pixel 22-2 included in the second color sub-pixel pair 220 as an example, for example, the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the same second color sub-pixel pair 220 is a connected whole film layer, that is, the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 is a continuous and complete pattern, or the positive projection of the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the same second color sub-pixel pair 220 on the base substrate 100 is continuous and complete, and the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 can be obtained by manufacturing an opening. But it is not limited thereto. For example, the light emitting layers of the first sub-pixel 22 - 1 and the second sub-pixel 22 - 2 included in the same second color sub-pixel pair 200 may also be separated.

[0220] A partial cross-section of the first color sub-pixel 210 is shown in FIG. Figure 7C and Fig.7D In the first color sub-pixel 210 , the light emitting layer 213 and the cathode layer 212 are sequentially stacked on the surface of the pixel defining layer 130 away from the base substrate 100 , and are in contact with the pixel electrode 211 exposed by the corresponding opening in the pixel defining layer 130 .

[0221] Another partial cross-section of the first color sub-pixel 210 is as follows: Fig. 7EAs shown in . In the first color sub-pixel 210, the pixel electrode 211 is electrically connected to the connection electrode 450 through the conduction hole 1210 penetrating the second flat layer 121. The connection electrode 450 is electrically connected to the driving electrode 343 through the conduction hole 351 penetrating the first flat layer 122 and the passivation layer 123. The driving electrode 343 is electrically connected to the second electrode T5-2 of the second light-emitting control transistor through the conduction hole 388 penetrating the second interlayer insulating layer 140, the first interlayer insulating layer 150 and the gate insulating layer 160. The orthographic projections of the conduction hole 1210, the conduction hole 351 and the conduction hole 388 on the base substrate 100 do not overlap, and there is a gap between them.

[0222] The partial cross section of the third color sub-pixel 230 is as follows: Figure 7F As shown in . In the third color sub-pixel 230, the orthographic projection of the pixel electrode 231 on the base substrate 100 partially overlaps with the orthographic projection of the first sub-power signal line 410 on the base substrate 100. The light-emitting layer 233 and the cathode layer 232 are sequentially stacked on the surface of the pixel defining layer 130 away from the base substrate 100, and are in contact with and connected to the pixel electrode 231 exposed by the corresponding opening in the pixel defining layer 130.

[0223] The partial cross section of the first sub-pixel 22-1 is as follows: Figure 7G As shown in . In the first sub-pixel 22-1, the pixel electrode 221-1 includes a main body 221-11, a bent portion 2-21 and a compensation portion 2-22. The light-emitting layer 223-1 and the cathode layer 222-1 are sequentially stacked on the surface of the pixel defining layer 130 away from the base substrate 100, and are in contact with and connected to the main body 221-11 of the pixel electrode 221-1 exposed by the corresponding opening in the pixel defining layer 130. Fig. 7A In the cross section along the RS direction, there is a gap between the main portion 221-11 of the pixel electrode 221-1 and the bent portion 2-21, and between the bent portion 2-21 and the compensation portion 2-22. The second sub-power signal line 420 in the first power signal line 400 can be electrically connected to the second power signal line 500 through the conductive hole 352 penetrating the first flat layer 122 and the passivation layer 123. The second power signal line 500 can be electrically connected to the first electrode T4-1 of the first light emission control transistor through the conductive hole 382 penetrating the second interlayer insulating layer 140, the first interlayer insulating layer 150 and the gate insulating layer 160.

[0224] In some of the above embodiments, the gate insulating layer 160, the first interlayer insulating layer 150, the second interlayer insulating layer 140, the passivation layer 123, the first planar layer 122 and the second planar layer 121 are used to insulate and protect the corresponding conductive layer, such as a metal layer or a semiconductor layer. Optionally, the gate insulating layer 160, the first interlayer insulating layer 150, the second interlayer insulating layer 140 and the passivation layer 123 are made of inorganic insulating materials, such as silicon nitride or silicon oxide. The first planar layer 122 and the second planar layer 121 are made of organic insulating materials, such as organic insulating resin.

[0225] Another embodiment of the present disclosure provides a display device, comprising any of the above display substrates. The display device can avoid the occurrence of color cast as much as possible, can also apply fingerprint detection technology, and has a high fingerprint detection sensitivity.

[0226] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0227] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: substrate substrate; A plurality of sub-pixels, wherein the sub-pixels include a pixel electrode and an effective light-emitting area; the pixel electrode includes a main body portion and a connecting portion that are interconnected; the main body portion has the same shape as the effective light-emitting area, and the main body portion overlaps with at least a portion of the boundary of the pixel electrode; the plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel that emit the same light color; The areas of the orthographic projections of the connection parts of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the substrate are different; the two orthographic projections of the connection part and the main part of at least one of the first sub-pixel and the second sub-pixel on a straight line extending along the first direction at least partially do not overlap; The orthographic projection of the pixel electrode of the second sub-pixel on the straight line extending along the second direction is located within the orthographic projection of the pixel electrode of the first sub-pixel on the same straight line; The second direction intersects with the first direction, and an angle between the second direction and the first direction is in the range of 80° to 100°.

2. The display substrate according to claim 1, characterized in that: The main body comprises a first side, a second side and a third side connected in sequence; the third side extends along the second direction; The connecting portion is connected to the second side and has a gap with the first side; An area enclosed by a connecting straight line from any point on the first side to any point on the edge of the connecting portion extending along the second direction and away from the third side in the first direction, the main body portion, and the connecting portion is a notch area.

3. The display substrate according to claim 2, characterized in that: It also includes a plurality of layers between the base substrate and the pixel electrode; the plurality of layers include at least one metal pattern; Wherein, along a direction perpendicular to the base substrate, in each layer from the base substrate to the pixel electrode, at least a part of the notch area does not overlap with the metal pattern.

4. The display substrate according to claim 2, characterized in that: Also includes a plurality of layers located between the base substrate and the pixel electrode; the plurality of layers include a semiconductor pattern and at least one metal pattern; Wherein, along a direction perpendicular to the base substrate, in each layer from the base substrate to the pixel electrode, at least a part of the recessed area does not overlap with the semiconductor pattern or the metal pattern.

5. The display substrate according to claim 2, characterized in that: The connecting portion of the pixel electrode in the first sub-pixel includes: a bent portion and a compensation portion connected to the bent portion; The bent portion is connected to the second side; and there is a gap between the bent portion and the first side.

6. The display substrate according to claim 5, characterized in that: A maximum dimension of the compensation portion along the first direction is greater than a maximum dimension of the bent portion along the first direction.

7. The display substrate according to claim 1, characterized in that: Also includes: a first gate metal layer between the base substrate and the pixel electrode, and a first metal layer between the first gate metal layer and the pixel electrode; The sub-pixel also includes a pixel circuit; The pixel circuit includes a driving transistor; A metal pattern having the same potential as the control electrode of the driving transistor, comprising: a first electrode of a capacitor located in the first gate metal layer, and a first switching electrode located in the first metal layer; Among them, the area of ​​overlap between the pixel electrode of the first sub-pixel and the corresponding orthographic projection of the first electrode of the capacitor on the substrate is smaller than the area of ​​overlap between the pixel electrode of the second sub-pixel and the corresponding orthographic projection of the first electrode of the capacitor on the substrate; and the area of ​​overlap between the pixel electrode of the first sub-pixel and the corresponding orthographic projection of the first switching electrode on the substrate is larger than the area of ​​overlap between the pixel electrode of the second sub-pixel and the corresponding orthographic projection of the first switching electrode on the substrate.

8. The display substrate according to claim 1, characterized in that: Also includes: A plurality of signal lines extending along the first direction; an orthographic projection of a pixel electrode of the first sub-pixel on the base substrate overlaps with an orthographic projection of at least three signal lines located in the same layer on the base substrate.

9. The display substrate according to any one of claims 1 to 8, characterized in that: Also includes: a plurality of pixel circuits, wherein the sub-pixels include the pixel circuits; A plurality of the pixel circuits are arranged in a row along the first direction and in a column along the second direction; The display substrate further comprises: a second flat layer and a plurality of first conductive holes located in the second flat layer; the second flat layer is located between the pixel electrode and the pixel circuit, and the pixel electrode is electrically connected to the pixel circuit through the first conductive holes; The orthographic projections of the plurality of first conductive holes corresponding to the plurality of pixel circuits in the same row on the substrate are arranged along a first straight line.

10. The display substrate according to claim 9, characterized in that: Also includes: a passivation layer and a plurality of driving electrodes; The passivation layer is located between the pixel electrode and the driving electrode and has a plurality of conducting holes; The pixel electrode is electrically connected to the driving electrode through the conducting hole.

11. The display substrate according to claim 10, characterized in that: The orthographic projection of the driving electrode on the base substrate at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

12. The display substrate according to claim 10, characterized in that: Also includes: A semiconductor pattern layer, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer; The semiconductor pattern layer is located between the base substrate and the driving electrode; The gate insulating layer, the first interlayer insulating layer and the second interlayer insulating layer are located between the driving electrode and the semiconductor pattern layer; the display substrate further includes a plurality of third conductive holes; the driving electrode is coupled to a corresponding portion of the semiconductor pattern layer through the third conductive holes; There is a gap between any two of the three orthographic projections of the third conductive hole and the first conductive hole corresponding to the same driving electrode on the substrate.

13. The display substrate according to claim 1, characterized in that: Also includes: a plurality of sub-pixel groups; At least one of the sub-pixel groups includes: a first color sub-pixel, a second color sub-pixel pair, and a third color sub-pixel; The second color sub-pixel pair includes two effective light-emitting areas.

14. The display substrate according to claim 1, characterized in that: The orthographic projection areas of the main parts of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the base substrate are the same.

15. The display substrate according to claim 13, characterized in that: In at least one of the sub-pixel groups, the connection portion in the first color sub-pixel is located on a side of the main portion thereof close to the second color sub-pixel pair.

16. The display substrate according to claim 13, characterized in that: The connecting portion of the second color sub-pixel pair is located on a side of the main body portion of the second color sub-pixel pair that is away from the first color sub-pixel along the symmetry axis of the main body portion along the second direction.

17. The display substrate according to claim 13, characterized in that: The connection portion of the third color sub-pixel is offset from the first color sub-pixel along the second direction.

18. The display substrate according to claim 13, characterized in that: The main body of the pixel electrode of the first color sub-pixel includes a first side, a second side and a third side connected in sequence; the third side extends along the second direction; The connecting portion is connected to the second side and has a gap with the first side; An area enclosed by a connecting straight line from any point on the first side to any point on the edge of the connecting portion extending along the second direction and away from the third side in the first direction, the main body portion, and the connecting portion is a notch area.

19. The display substrate according to claim 1, characterized in that: The sub-pixel further includes a pixel circuit, which is electrically connected to the pixel electrode and includes at least 7 transistors.

20. A display device, characterized in that: A display substrate comprising any one of claims 1-19.

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