Display device

Abstract

The display device includes a pixel electrode disposed on a substrate; a bank layer covering an edge of the pixel electrode and defining a plurality of light emitting regions and non-light emitting regions; a light emitting layer disposed on the pixel electrode and the bank layer; a common electrode disposed on the light emitting layer; a cap layer disposed on the common electrode; a counter substrate facing the substrate; and an optical member disposed on the pair of substrates. The cap layer includes a first cap layer disposed on the common electrode, and a second cap layer disposed on the first cap layer and overlapping the plurality of light emitting regions.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Our information society increasingly requires various forms of display devices for displaying images. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light-emitting display device. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic (e.g., semiconductor) light-emitting element, and a micro light-emitting display device including a micro light-emitting element.

[0004] The organic light emitting element may include two electrodes facing each other and a light emitting layer interposed between the two electrodes. The light emitting layer may receive electrons and holes from the two electrodes, where the electrons and holes are recombined to generate excitons and emit light, for example, when the generated excitons change from an excited state to a ground state.

[0005] An organic light emitting display device including an organic light emitting element does not require a light source such as a backlight unit. As a result, the organic light emitting display device has low power consumption, can be made light and thin, and has a wide viewing angle, high brightness and contrast, and a fast response speed. Due to these high-quality characteristics, the organic light emitting display device is receiving attention as a next-generation display device. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of reducing reflectivity of external light.

[0007] However, the various aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the following detailed description.

[0008] According to aspects of the present disclosure, a display device may include: a pixel electrode disposed on a substrate; a dam layer covering an edge of the pixel electrode and defining a plurality of light-emitting areas and a non-light-emitting area; a light-emitting layer disposed on the pixel electrode and the dam layer; a common electrode disposed on the light-emitting layer; a cover layer disposed on the common electrode; a counter substrate facing the substrate; and an optical member disposed on the counter substrate, wherein the cover layer includes a first cover layer disposed on the common electrode, and a second cover layer disposed on the first cover layer and overlapping the plurality of light-emitting areas.

[0009] In an embodiment, the first capping layer overlaps the plurality of light emitting regions and the non-light emitting region, and the first capping layer overlaps the second capping layer.

[0010] In an embodiment, the thickness of the first cover layer is to

[0011] In an embodiment, the refractive index of each of the first cap layer and the second cap layer is 1.8 to 2.2.

[0012] In an embodiment, the thickness of the second cover layer is to

[0013] In an embodiment, the first cap layer and the second cap layer include different materials.

[0014] In an embodiment, the sum of the thickness of the first cover layer and the thickness of the second cover layer in each of the plurality of light emitting regions is to

[0015] In an embodiment, the first cover layer is disposed below the second cover layer or on the second cover layer.

[0016] In an embodiment, the optical member includes a base layer, a colorant layer disposed on the base layer, and an adhesive layer disposed on the colorant layer.

[0017] In an embodiment, the colorant layer transmits light within a wavelength band of 440 nm to 490 nm, light within a wavelength band of 510 nm to 580 nm, and light within a wavelength band of 610 nm to 660 nm, and absorbs light within other wavelength bands.

[0018] According to aspects of the present disclosure, a display device includes: a pixel electrode disposed on a substrate; a dam layer covering an edge of the pixel electrode and defining a light-emitting area and a non-light-emitting area; a light-emitting layer disposed on the pixel electrode and the dam layer; a common electrode disposed on the light-emitting layer; a cover layer disposed on the common electrode; a counter substrate facing the substrate; and an optical member disposed on the counter substrate, wherein the cover layer includes a first area overlapping with the light-emitting area, and a second area overlapping with the non-light-emitting area, and a thickness of the first area is greater than a thickness of the second area.

[0019] In an embodiment, the thickness of the first region is to

[0020] In an embodiment, the thickness of the second region is to

[0021] In an embodiment, the first area does not overlap with the non-luminescent area, and the second area does not overlap with the luminescent area.

[0022] In an embodiment, the capping layer includes an inorganic insulating material or an organic insulating material.

[0023] In an embodiment, the upper surface of the cover layer is flat and arranged parallel to the substrate.

[0024] According to aspects of the present disclosure, a display device includes: a pixel electrode disposed on a substrate; a dam layer covering an edge of the pixel electrode and defining a light-emitting area and a non-light-emitting area; a light-emitting layer disposed on the pixel electrode and the dam layer; a common electrode disposed on the light-emitting layer; a cover layer disposed on the common electrode; a thin-film encapsulation layer disposed on the cover layer; and an optical member disposed on the thin-film encapsulation layer, wherein the cover layer includes a first area overlapping with the light-emitting area, and a second area overlapping with the non-light-emitting area, and a thickness of the first area is greater than a thickness of the second area.

[0025] In an embodiment, the thin film encapsulation layer includes a first encapsulation inorganic layer disposed on the capping layer, an encapsulation organic layer disposed on the first encapsulation inorganic layer, and a second encapsulation inorganic layer disposed on the encapsulation organic layer.

[0026] In an embodiment, the first area does not overlap with the non-luminescent area, and the second area does not overlap with the luminescent area.

[0027] In an embodiment, the optical component includes a base layer, a colorant layer disposed on the base layer, and an adhesive layer disposed on the colorant layer, wherein the colorant layer transmits light within a wavelength band of 440nm to 490nm, light within a wavelength band of 510nm to 580nm, and light within a wavelength band of 610nm to 660nm, and absorbs light within other wavelength bands.

[0028] In the display device according to the embodiment, the capping layer having different thicknesses in the light emitting region and the non-light emitting region is formed, so that it is possible to reduce reflection of external light in the non-light emitting region and improve light emitting efficiency in the light emitting region.

[0029] In addition, since the display device further includes an optical member, reflection of external light can be reduced and a polarizing plate can be omitted.

[0030] However, the effects of the present disclosure are not limited to those set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings.

[0032] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0033] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment.

[0034] Figure 3 is a schematic layout diagram showing a plurality of lines included in a display device according to an embodiment.

[0035] Figure 4 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0036] Figure 5 is a schematic cross-sectional view of a sub-pixel of a display device according to an embodiment.

[0037] Figure 6 is a plan view of a display device according to an embodiment.

[0038] Figure 7 It is along Figure 6 A cross-sectional view taken along line Q1-Q1'.

[0039] Figure 8 : is a schematic cross-sectional view showing a stacked structure of a non-light emitting region and a light emitting region of a display device according to an embodiment.

[0040] Fig. 9 is a cross-sectional view of an optical member according to an embodiment.

[0041] Fig.10 is a graph showing transmittance of an optical member with respect to wavelength according to an embodiment.

[0042] Fig.11 is a cross-sectional view of a display device according to an embodiment.

[0043] Fig.12 is a cross-sectional view of a display device according to an embodiment.

[0044] Fig.13 is a schematic diagram of a capping layer according to an embodiment.

[0045] Fig.14 is a cross-sectional view of a display device according to an embodiment.

[0046] Fig.15 is a schematic diagram of a capping layer according to an embodiment.

[0047] Fig.16 is a cross-sectional view of a display device according to an embodiment.

[0048] Fig.17 and Fig.18 is a cross-sectional view illustrating a method of manufacturing the display device according to the embodiment through processes.

[0049] Fig.19 A graph illustrating the wavelength dependence of reflectance from a display device according to an embodiment is shown.

[0050] Fig. 20 A graph illustrating the dependence of the relative luminous efficiency-reflected reflectivity on the wavelength is shown.

[0051] Fig.21 A graph illustrating the dependence of the amount of reflected light on the thickness of the cap layer is shown.

[0052] The use of the same reference numbers in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0053] Exemplary embodiments are described more fully below with reference to the accompanying drawings, in which exemplary embodiments are shown. Other embodiments may take different forms, and the present disclosure should not be construed as limited to the exemplary embodiments set forth herein. Rather, the illustrated embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the claims to those skilled in the art.

[0054] Hereinafter, a layer referred to as being “on” another layer or substrate may be directly on the other layer or substrate, or one or more intervening layers may also be present.

[0055] It will be understood that although the terms "first", "second", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed later can be referred to as the second element. Similarly, the second element can also be named as the first element.

[0056] The features of various embodiments of the present disclosure can be partially or entirely separated or combined with each other, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together.

[0057] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 is a schematic plan view of a display device 10 according to the embodiment.

[0059] In the present specification, "above", "top" and "upper surface" refer to the direction upward from the display device 10, that is, the third direction DR3, and "below", "bottom" and "lower surface" refer to the direction opposite to the third direction DR3. In addition, "left", "right", "upper" and "lower surface" refer to directions when the display device 10 is viewed in a plan view. For example, "right" refers to the first direction DR1, "left" refers to the direction opposite to the first direction DR1, "upper" refers to the second direction DR2, and "lower" refers to the direction opposite to the second direction DR2.

[0060] Reference Figure 1 , the display device 10 may display a dynamic image or a still image. The display device 10 may be any electronic device that provides a display screen. Examples of the display device 10 may include a television, a notebook computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a camcorder, all of which provide a display screen.

[0061] The display device 10 may include a display panel that provides a display screen. Examples of the display panel may include an inorganic light emitting diode display panel, an organic light emitting diode display panel, a quantum dot light emitting display panel, a plasma display panel, and a field emission display panel. The following describes an example including an organic light emitting diode display panel, but the present disclosure is not limited to this case, and other display panels may also be applied as long as the same technical spirit is applicable.

[0062] The shape of the display device 10 can be Figure 1 The example shown in can be variously modified. For example, the display device 10 can have various shapes, such as a horizontally long-side rectangle, a vertically long-side rectangle, a square, a quadrilateral with rounded corners (vertices), other polygons, and a circle. The shape of the display area DPA of the display device 10 can also be similar to the overall shape of the display device 10. Figure 1 In FIG. 1 , the display device 10 and each of the display area DPA are generally shaped like a similar horizontally long-side rectangular shape.

[0063] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is an area where an image can be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DPA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DPA may generally occupy the center of the display device 10.

[0064] The display area DA may include a plurality of pixels PX. The pixels PX may be arranged in a matrix. Each of the pixels PX may be rectangular or square in a plan view. However, the present disclosure is not limited thereto, and each of the pixels PX may also have other shapes, such as a rhombus shape, each side of which is at a non-perpendicular angle relative to an adjacent side. The pixels PX may also be strip-shaped or island-shaped. In addition, each of the pixels PX may include one or more light-emitting elements EL (see Figure 4 ), each of the light emitting elements EL emits light of a specific wavelength band to display a specific color.

[0065] The non-display area NDA may be disposed around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may be rectangular, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 10. Wiring or circuit drivers in the display device 10 may be positioned in the non-display area NDA, or an external device may be installed in the non-display area NDA.

[0066] Figure 2 is a schematic cross-sectional view of a display device 10 according to the embodiment.

[0067] Reference Figure 2 ,according to Figure 1 The display device 10 of the embodiment may include a substrate 100, a counter substrate 200 facing the substrate 100, a sealing member 250 bonding the substrate 100 and the counter substrate 200 together, and an optical member 300 disposed on the counter substrate 200. In addition, the display device 10 may include a display element layer EVL disposed on the substrate 100, and a cover layer CPL disposed on the display element layer EVL.

[0068] The substrate 100 may be used as a base for the display device 10. The substrate 100 may be made of a rigid material having rigidity. In some embodiments, the substrate 100 may include, but is not limited to, glass. For example, the substrate 100 may include quartz.

[0069] The display element layer EVL may be disposed on the substrate 100 in the third direction DR3. The display element layer EVL may form a display screen and define a display area DPA (see FIG. 1 ) of the display device 10. Figure 1 That is, the area on the substrate 100 where the display element layer EVL is disposed may be the display area DPA, and the area where the display element layer EVL is not disposed may be the non-display area NDA (see Figure 1 ). The display element layer EVL may overlap the display area DPA in the third direction DR3, and may not overlap the non-display area NDA in the third direction DR3.

[0070] The display element layer EVL may include elements and circuits for displaying images. For example, the display element layer EVL in the display area DPA may include a switching element, a pixel circuit, a conductive pattern, and a light-emitting element, which will be further described later. Each of the multiple light-emitting elements may include at least one of an organic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode based on an inorganic material (e.g., a micro light-emitting diode (LED)), and a nano light-emitting diode based on an inorganic material (e.g., a nano LED). For ease of description, the following description is taken as an example of a case where the light-emitting element is an organic light-emitting diode.

[0071] The cover layer CPL may be disposed on the display element layer EVL. The cover layer CPL may cover the display element layer EVL to protect the display element layer EVL, and may reduce the reflectivity of the non-light emitting area in the display area DPA. The cover layer CPL will be described in more detail later.

[0072] The counter substrate 200 may be disposed on the substrate 100, and may face the substrate 100. In an embodiment, the counter substrate 200 may be made of a transparent material such as glass, plastic, etc., and may be rigid or flexible.

[0073] The sealing member 250 may be disposed between the substrate 100 and the counter substrate 200 in the non-display area NDA. The sealing member 250 may be disposed along the edges of the substrate 100 and the counter substrate 200 in the non-display area NDA, and may surround the display area DPA in a plan view. The sealing member 250 may bond the substrate 100 and the counter substrate 200 to each other. In an embodiment, the sealing member 250 may be made of an inorganic or organic material. For example, the sealing member 250 may be made of an inorganic material such as glass frit, or an organic material such as epoxy resin, but the present disclosure is not limited thereto.

[0074] The optical member 300 may be disposed on the counter substrate 200. The optical member 300 may reduce reflection of external light incident on the display device 10 from the outside of the display device 10. The optical member 300 will be described in more detail later.

[0075] Figure 3 FIG. 1 is a diagram showing a display device 10 according to an embodiment (see FIG. Figure 1 ) is a schematic layout diagram of multiple lines included in.

[0076] Reference Figure 3 , the display device 10 may include a plurality of lines. These lines may include a scan line SCL, a sensing line SSL, a data line DTL, an initialization voltage line VIL, a first voltage line VDL, and a second voltage line VSL. In addition, the display device 10 may include Figure 3 Other lines not shown.

[0077] The scan lines SCL and the sensing lines SSL may extend in the first direction DR1. The scan lines SCL and the sensing lines SSL may be connected to a scan driver SDR. The scan driver SDR may include a driving circuit. The scan driver SDR may be disposed in the display area DPA (see Figure 1 ) on one side in the direction opposite to the first direction DR1, but the present disclosure is not limited thereto. The scan driver SDR may be connected to the signal wiring pattern CWL, and at least one end of the signal wiring pattern CWL may be in the non-display area NDA (see Figure 1 ) is formed in the pad WPD_CW, and thus the signal wiring pattern CWL can be connected to an external device.

[0078] As used herein, the term "connected" may mean that any one component and another component are connected to each other not only by physical contact but also by another component. In addition, it is understood that any one component and another component connected to each other may be an integral component. In addition, the connection between any one component and another component may be interpreted as including, in addition to the connection by direct contact, also including an electrical connection through another component.

[0079] The data line DTL and the initialization voltage line VIL may extend in a second direction DR2, and the second direction DR2 is at an angle to the first direction DR1. The first voltage line VDL and the second voltage line VSL extend in the first direction DR1 and the second direction DR2. In each of the first voltage line VDL and the second voltage line VSL, a portion extending in the first direction DR1 and a portion extending in the second direction DR2 ( Figure 3 The first voltage line VDL and the second voltage line VSL may have a mesh structure covering the entire display area DPA, but the present disclosure is not limited thereto. Each pixel PX of the display device 10 may be connected to at least one data line DTL, an initialization voltage line VIL, a first voltage line VDL, and a second voltage line VSL.

[0080] The data line DTL, the initialization voltage line VIL, the first voltage line VDL, and the second voltage line VSL may be electrically connected to one or more wiring pads WPD. Each wiring pad WPD may be arranged in a pad area PDA. In an embodiment, a wiring pad WPD_DT (referred to as a "data pad") of the data line DTL, a wiring pad WPD_Vint (referred to as an "initialization voltage pad") of the initialization voltage line VIL, a wiring pad WPD_VDD (referred to as a "first power pad") of the first voltage line VDL, and a wiring pad WPD_VSS (referred to as a "second power pad") of the second voltage line VSL may be arranged in a pad area PDA, and the pad area PDA is positioned on one side of the display area DPA in the second direction DR2. An external device may be mounted on the wiring pad WPD or otherwise connected to the wiring pad WPD. The external device may be mounted on the wiring pad WPD, for example, by an anisotropic conductive film or ultrasonic bonding.

[0081] Each pixel PX (see Figure 1 ) or sub-pixel SPXn (see Figure 4 ) (wherein n is an integer from 1 to 3) includes a pixel driving circuit. Figure 3 The above-mentioned lines shown in can transmit the driving signal to each pixel driving circuit while passing through or surrounding each pixel PX. Each pixel driving circuit (pixel circuit) may include a transistor and a capacitor. For different embodiments, the number of transistors and capacitors in each pixel driving circuit may be different. According to an exemplary embodiment, the pixel driving circuit of each sub-pixel SPXn of the display device 10 may have a 3T1C structure including three transistors and one capacitor. Although the pixel driving circuit described in detail below is an example of a 3T1C structure, the present disclosure is not limited thereto, and other various modified pixel structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure are also applicable.

[0082] Figure 4 is an equivalent circuit diagram of a sub-pixel SPXn according to an embodiment.

[0083] Reference Figure 4 According to the display device 10 of the embodiment (see Figure 1 ) each sub-pixel SPXn includes three transistors TR1 to TR3 and a storage capacitor Cst in addition to the light emitting element EL.

[0084] The light emitting element EL emits light having an intensity according to the current supplied to the light emitting element EL through the first transistor TR1. The light emitting element EL includes a first electrode, a second electrode, and at least one light emitting layer disposed therebetween. The light emitting layer may emit light of a specific wavelength band in response to an electrical signal received via the first electrode and the second electrode.

[0085] A first end of the light emitting element EL may be connected to the source electrode of the first transistor TR1, and a second end of the light emitting element EL may be connected to a second voltage line VSL, to which a low potential voltage (referred to as a second power supply voltage) lower than a high potential voltage of the first voltage line VDL (hereinafter, referred to as a first power supply voltage) is supplied. In addition, a first end of the light emitting element EL may be connected to a source electrode of the third transistor TR3 and an electrode of the storage capacitor Cst.

[0086] The first transistor TR1 adjusts the current flowing from the first voltage line VDL to which the first power supply voltage is supplied to the light emitting element EL according to the voltage difference between the gate electrode and the source electrode of the first transistor TR1. For example, the first transistor TR1 may be a driving transistor for driving the light emitting element EL. The first transistor TR1 may have a gate electrode connected to the source electrode of the second transistor TR2, a source electrode connected to the first electrode of the light emitting element EL, and a drain electrode connected to the first voltage line VDL to which the first power supply voltage is applied.

[0087] The second transistor TR2 is turned on by a scan signal from the scan line SCL to connect the data line DTL to the gate electrode of the first transistor TR1. The second transistor TR2 may have a gate electrode connected to the scan line SCL, a source electrode connected to the gate electrode of the first transistor TR1, and a drain electrode connected to the data line DTL.

[0088] The third transistor TR3 is turned on by the sensing signal from the sensing line SSL to connect the initialization voltage line VIL to the first end of the light emitting element EL. The third transistor TR3 may have a gate electrode connected to the sensing line SSL, a drain electrode connected to the initialization voltage line VIL, and a source electrode connected to the first end of the light emitting element EL or the source electrode of the first transistor TR1.

[0089] In the embodiment, each of the transistors TR1 to TR3 is not limited to having a source electrode and a drain electrode connected as described above, and the electrode described as a source (or drain) electrode may be replaced with a drain (or source) electrode. In addition, each of the transistors TR1 to TR3 may be formed as a thin film transistor. In addition, although Figure 4, each of the transistors TR1 to TR3 is an N-type metal oxide semiconductor field effect transistor (MOSFET), but the present disclosure is not limited thereto. That is, each of the transistors TR1 to TR3 may alternatively be a P-type MOSFET, or some of them may be N-type MOSFETs and the others may be P-type MOSFETs.

[0090] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor TR1. The storage capacitor Cst stores a difference between the gate voltage and the source voltage of the first transistor TR1.

[0091] The structure of the sub-pixel SPXn of the display device 10 according to the embodiment will now be described in detail with further reference to other drawings.

[0092] Figure 5 The display device 10 according to the embodiment (see Figure 1 ) is a schematic cross-sectional view of a sub-pixel SPXn. Figure 5 Specifically and in more detail, the above reference Figure 2 The configuration of the display element layer EVL of the display device 10 is described.

[0093] according to Figure 5 The display device 10 of the embodiment may include a display element layer EVL disposed on a substrate 100 .

[0094] The display element layer EVL may specifically include a buffer layer 115 disposed on the substrate 100. The buffer layer 115 may include an inorganic layer that can prevent air or moisture from penetrating. The buffer layer 115 may include a silicon compound, a metal oxide, or the like. For example, the buffer layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These materials may be used alone or in combination with each other. The buffer layer 115 may be a single layer or a multilayer composed of a stack of different materials.

[0095] The switching element STn may be disposed on the buffer layer 115. The switching element STn may include a semiconductor layer 120, a gate electrode 130, a source electrode 140, and a drain electrode 145. The switching element STn may form a part of a pixel circuit, and each of a plurality of pixel circuits may include one or more such switching elements STn. Figure 5 1 shows one switching element STn provided in the sub-pixel SPXn of the display device 10, but the sub-pixel SPXn may include a plurality of switching elements STn as described above. In one example, the switching element STn may be a driving transistor or a switching transistor of the pixel circuit. Specifically, the switching element STn may correspond to the above Figure 4 The first transistor TR1.

[0096] The semiconductor layer 120 may be disposed on the buffer layer 115. The semiconductor layer 120 may be partially overlapped by the gate electrode 130, which will be further described later.

[0097] The semiconductor layer 120 may include polycrystalline silicon, monocrystalline silicon, or an oxide semiconductor. In an embodiment, the semiconductor layer 120 may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0098] A gate insulating layer 125 may be disposed on the semiconductor layer 120. The gate insulating layer 125 may serve as a gate insulating film of the switching element STn.

[0099] The gate insulating layer 125 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 125 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials may be used alone or in combination with each other. The gate insulating layer 125 may be a single layer or a multilayer composed of a stack of different materials.

[0100] The gate electrode 130 may be disposed on the gate insulating layer 125. The gate electrode 130 may overlap with the channel region of the semiconductor layer 120 in the third direction DR3 as the thickness direction. The gate electrode 130 may include a metal. For example, the gate electrode 130 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0101] The interlayer insulating layer 135 may be disposed on the gate electrode 130. The interlayer insulating layer 135 may be disposed on the gate electrode 130 and the gate insulating layer 125. The interlayer insulating layer 135 may serve as an insulating film between the gate electrode 130 and other layers disposed on the gate electrode 130. In addition, the interlayer insulating layer 135 may cover the gate electrode 130 to protect the gate electrode 130.

[0102] The interlayer insulating layer 135 may include a silicon compound, a metal oxide, etc. For example, the interlayer insulating layer 135 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials may be used alone or in combination with each other. The interlayer insulating layer 135 may be a single layer or a multilayer composed of a stack of different materials.

[0103] The source electrode 140 and the drain electrode 145 may be disposed on the interlayer insulating layer 135. The source electrode 140 may be connected to the semiconductor layer 120 through a first contact hole CH1 penetrating the interlayer insulating layer 135 and the gate insulating layer 125. The drain electrode 145 may be connected to the semiconductor layer 120 through a second contact hole CH2 penetrating the interlayer insulating layer 135 and the gate insulating layer 125.

[0104] The source electrode 140 and the drain electrode 145 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Each of the source electrode 140 and the drain electrode 145 may be a single layer or a multilayer.

[0105] The via layer 150 may be disposed on the switching element STn. The via layer 150 may provide a flat surface on a contour or step under the via layer 150 so that the pixel electrode PE n is formed on the via layer 150 .

[0106] The via layer 150 may include an inorganic insulating material or an organic insulating material. For example, the organic insulating material may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin or benzocyclobutene (BCB). The via layer 150 may be a single layer or a multilayer composed of a stack of different materials.

[0107] The light emitting element ELn may be disposed on the via layer 150. The light emitting element ELn may include a pixel electrode PEn, a light emitting layer OL, and a common electrode CE.

[0108] The pixel electrode PEn may be disposed on the via layer 150. The pixel electrode PEn may be disposed in a pattern shape in each sub-pixel SPXn (see Figure 4 ). The pixel electrode PEn may be an anode of the light emitting element ELn. The pixel electrode PEn may be connected to the drain electrode 145 of the switching element STn through a third contact hole CH3 penetrating the via layer 150.

[0109] The pixel electrode PEn may be a reflective electrode. The pixel electrode PEn may have a stacked structure of a material layer with a high work function and a reflective material layer, and the material layer with a high work function includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or indium oxide (In 2 O 3 ), the reflective material layer includes materials such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. The material layer with a high work function may be disposed on the reflective material layer so that the material layer with a high work function is positioned near the light-emitting layer OL. The pixel electrode PEn may have a multilayer structure of, but not limited to, ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO.

[0110] The bank layer 155 may be disposed on the pixel electrode PEn. The bank layer 155 may include an opening OP partially exposing the pixel electrode PEn. The bank layer 155 may be made of an organic insulating material or an inorganic insulating material. For example, the bank layer 155 may include at least one of a photoresist, a polyimide resin, an acrylic resin, a silicon compound, and a polyacrylic resin. The bank layer 155 may display black. The bank layer 155 may include a colorant that displays black, such as a dye or a pigment. The bank layer 155 that displays black may prevent the color mixing of light between adjacent sub-pixels SPXn.

[0111] The light emitting layer OL may be disposed on the pixel electrode PEn. The light emitting layer OL may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The light emitting layer OL may emit red light, blue light, or green light for each sub-pixel SPXn.

[0112] The common electrode CE may be disposed on the light emitting layer OL and the bank layer 155. The common electrode CE may be disposed on the entire display area DPA (see FIG. 1 ) of the substrate 100. Figure 6 ). The common electrode CE may be a common electrode disposed across a plurality of sub-pixels SPXn. The common electrode CE may be a cathode of the light emitting element ELn.

[0113] The common electrode CE may be translucent or transparent. When the common electrode CE is translucent, the common electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. In addition, when the thickness of the common electrode CE is tens to hundreds of angstroms, the common electrode CE may be translucent.

[0114] When the common electrode CE is transparent, the common electrode CE may include a transparent conductive oxide (TCO). For example, the common electrode CE may include tungsten oxide (W x O y ), titanium oxide (TiO 2 ), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO) or magnesium oxide (MgO).

[0115] Figure 6 The display device 10 according to the embodiment (see Figure 1 )’s floor plan. Figure 7 It is along Figure 6 A cross-sectional view taken along line Q1-Q1'. Figure 8 1 is a schematic cross-sectional view illustrating a stack structure of a non-light emitting area NLA and a light emitting area LA of a display device 10 according to an embodiment. Fig. 9 is a cross-sectional view of an optical member 300 according to an embodiment. Fig.10 is a graph showing transmittance of the optical member 300 with respect to wavelength according to the embodiment.

[0116] Reference Figures 6 to 10 , a plurality of light emitting areas LA1 to LA3 and a non-light emitting area NLA may be defined in the substrate 100. The light emitting areas LA1 to LA3 may be areas where light generated by the light emitting elements EL1 to EL3 is emitted to the outside, and the non-light emitting area NLA may be an area where light is not emitted to the outside. In an embodiment, the first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3 may be sequentially and repeatedly arranged along the first direction DR1 in the display area DPA.

[0117] The first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3 may have the same width measured in the first direction DR1. For example, the first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3 may have the same size or plane area. However, the present disclosure is not limited thereto, and the first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3 may also have different widths measured in the first direction DR1. For example, the width of the first light emitting area LA1 may be smaller than the width of the third light emitting area LA3, and the width of the third light emitting area LA3 may be smaller than the width of the second light emitting area LA2.

[0118] The light emitting areas LA1 to LA3 may emit light of different colors. In an embodiment, the first light emitting area LA1 may emit light of a first color, the second light emitting area LA2 may emit light of a second color, and the third light emitting area LA3 may emit light of a third color. In an embodiment, the light of the first color may be blue light having a peak wavelength in a range of about 440 nm to about 480 nm, and the light of the second color may be red light having a peak wavelength in a range of about 610 nm to about 650 nm. In addition, the light of the third color may be green light having a peak wavelength in a range of about 510 nm to about 550 nm. However, the present disclosure is not limited thereto, and the light of the second color may also be green light, and the light of the third color may also be red light.

[0119] The switching elements ST1 to ST3 may be disposed on the substrate 100. In an embodiment, the first switching element ST1 may overlap the first light emitting area LA1 of the substrate 100, the second switching element ST2 may overlap the second light emitting area LA2, and the third switching element ST3 may overlap the third light emitting area LA3. However, the present disclosure is not limited thereto. In an embodiment, at least one of the first switching element ST1, the second switching element ST2, and the third switching element ST3 may overlap the non-light emitting area NLA.

[0120] The via layer 150 may be disposed on the substrate 100 on which the switching elements ST1 to ST3 are disposed, and the bank layer 155 and the light emitting elements EL1 to EL3 may be disposed on the via layer 150 .

[0121] Specifically, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be positioned on the via layer 150. The first pixel electrode PE1 may be positioned in the first light emitting area LA1, but at least a portion of the first pixel electrode PE1 may extend to the non-light emitting area NLA. The second pixel electrode PE2 may be positioned in the second light emitting area LA2, but at least a portion of the second pixel electrode PE2 may extend to the non-light emitting area NLA. The third pixel electrode PE3 may be positioned in the third light emitting area LA3, but at least a portion of the third pixel electrode PE3 may extend to the non-light emitting area NLA. The first pixel electrode PE1 may penetrate the via layer 150 and may be connected to the first switching element ST1. The second pixel electrode PE2 may penetrate the via layer 150 and may be connected to the second switching element ST2. The third pixel electrode PE3 may penetrate the via layer 150 and may be connected to the third switching element ST3.

[0122] The bank layer 155 may be disposed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The bank layer 155 may define a first light emitting area LA1, a second light emitting area LA2, a third light emitting area LA3, and a non-light emitting area NLA. That is, an area of ​​the first pixel electrode PE1 that is not covered by the bank layer 155 may be the first light emitting area LA1. An area of ​​the second pixel electrode PE2 that is not covered by the bank layer 155 may be the second light emitting area LA2. In addition, an area of ​​the third pixel electrode PE3 that is not covered by the bank layer 155 may be the third light emitting area LA3. In addition, an area where the bank layer 155 is positioned may be the non-light emitting area NLA.

[0123] The light emitting layer OL may be disposed on the first to third pixel electrodes PE1 to PE3 and the bank layer 155. In an embodiment where the display device 10 is an organic light emitting display device, the light emitting layer OL may include an organic layer including an organic material. The organic layer may include an organic light emitting layer EML, and may include a hole transport layer HTL and an electron transport layer ETL as auxiliary layers for auxiliary light emission.

[0124] like Figure 8 As shown in , the organic light emitting layer EML may be patterned to include a separate region in each of the light emitting regions LA1 to LA3, and each region of the organic light emitting layer EML may emit light of a color corresponding to each of the light emitting regions LA1 to LA3. For example, the organic light emitting layer EML disposed in the first light emitting region LA1 may emit blue light, the organic light emitting layer EML disposed in the second light emitting region LA2 may emit red light, and the organic light emitting layer EML disposed in the third light emitting region LA3 may emit green light.

[0125] The hole transport layer HTL may be disposed between the organic light emitting layer EML and each of the pixel electrodes PE1 to PE3. However, the present disclosure is not limited thereto, and at least one of the hole injection layer and the electron blocking layer may be further disposed between the organic light emitting layer EML and each of the pixel electrodes PE1 to PE3. The electron transport layer ETL may be disposed between the organic light emitting layer EML and the common electrode CE. However, the present disclosure is not limited thereto, and at least one of the hole blocking layer and the electron injection layer may be further disposed between the organic light emitting layer EML and the common electrode CE. The hole transport layer HTL and the electron transport layer ETL may be common layers continuously disposed in the light emitting regions LA1 to LA3 and the non-light emitting region NLA. For example, the hole transport layer HTL and the electron transport layer ETL may cover the entire display area DPA (see Figure 6 ).

[0126] The common electrode CE may be disposed on the light emitting layer OL. The common electrode CE may be a common layer continuously disposed in the light emitting areas LA1 to LA3 and the non-light emitting area NLA.

[0127] The first pixel electrode PE1, the light emitting layer OL and the common electrode CE may form a first light emitting element EL1. The second pixel electrode PE2, the light emitting layer OL and the common electrode CE may form a second light emitting element EL2. The third pixel electrode PE3, the light emitting layer OL and the common electrode CE may form a third light emitting element EL3. The first light emitting element EL1, the second light emitting element EL2 and the third light emitting element EL3 may be organic light emitting diodes.

[0128] The switching elements ST1 to ST3, the via layer 150, the bank layer 155, and the light emitting elements EL1 to EL3 may constitute a display element layer EVL (see Figure 2 ).

[0129] Cover layer CPL (see Figure 2 ) may be disposed on the display element layer EVL. The cover layer CPL may protect the display element layer EVL and reduce reflection of external light incident from the outside by making the external light disappear through destructive interference. The cover layer CPL may include a first cover layer CPL1 and a second cover layer CPL2 disposed on the first cover layer CPL1.

[0130] The first cover layer CPL1 may be directly disposed on the display element layer EVL to directly cover the display element layer EVL. The first cover layer CPL1 may overlap each of the light emitting areas LA1 to LA3 and the non-light emitting area NLA of the display element layer EVL. For example, the first cover layer CPL1 may be continuously disposed across the light emitting areas LA1 to LA3 and the non-light emitting area NLA.

[0131] The first cover layer CPL1 may include at least one of an inorganic material and an organic material that can protect the top of the display element layer EVL. In some embodiments, the inorganic material may be an inorganic insulating material or an inorganic deposition material, and the organic material may be an organic insulating material or an organic deposition material. In some embodiments, the inorganic material may include, for example, any one or more of silicon nitride, aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, and niobium oxide. In some embodiments, the organic material may include any one or more of a hole transport layer, a hole injection layer, and an electron transport layer.

[0132] The first cover layer CPL1 may have a predetermined thickness to make the incident external light disappear by destructive interference. Depending on the refractive index of the first cover layer CPL1, the thickness T1 of the first cover layer CPL1 may be to External light incident into the display device 10 may be reflected from the upper surface of the first cover layer CPL1 (e.g., from the interface between the first cover layer CPL1 and the air layer), and may be reflected from the lower surface of the first cover layer CPL1 (e.g., from the interface between the first cover layer CPL1 and the common electrode CE). Depending on the thickness and refractive index of the first cover layer CPL1, light (especially visible light) reflected from the upper and lower surfaces of the first cover layer CPL1 may destructively interfere with each other to disappear. In the current embodiment, the first cover layer CPL1 having a thickness T1 of to The first cover layer CPL1 may reduce reflection of external light by extinguishing incident external light.

[0133] The first cover layer CPL1 may have a refractive index of 1.8 to 2.2 so as to reflect external light and effectively transmit internally emitted light. The refractive index of the first cover layer CPL1 may preferably be 1.9 to 2.1. In an embodiment, the refractive index of the first cover layer CPL1 may be 2.

[0134] The second cover layer CPL2 may be disposed on the first cover layer CPL1. The second cover layer CPL2 may overlap with the light emitting areas LA1 to LA3 of the display element layer EVL. Specifically, the second cover layer CPL2 may overlap with the first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3. The second cover layer CPL2 may not overlap with the non-light emitting area NLA of the display element layer EVL. The second cover layer CPL2 may be disposed in the shape of a plurality of islands to correspond to the light emitting areas LA1 to LA3, respectively, and the areas between the plurality of islands may correspond to the non-light emitting area NLA. In addition, the second cover layer CPL2 may not overlap with the embankment layer 155.

[0135] The second cap layer CPL2 may improve the light emitting efficiency of the light emitting elements EL1 to EL3 by increasing the thickness of the cap layer CPL in each of the light emitting regions LA1 to LA3. The thickness T2 of the second cap layer CPL2 may be to A portion of the light emitted from the light emitting layer OL in each of the light emitting elements EL1 to EL3 may be output through the cover layer CPL. The other portion of the light may be reflected from the lower surface of the common electrode CE, the interface between the common electrode CE and the cover layer CPL, and the upper surface of the cover layer CPL, and then may be reflected again from each of the pixel electrodes PE1 to PE3 to propagate upward. Here, a resonance phenomenon in which various lights of desired wavelengths constructively interfere with each other may occur, and the light emitting efficiency may be improved by the resonance phenomenon.

[0136] In the current embodiment, a to The second cap layer CPL2 may have a thickness T2, and the thickness T3 of the cap layer CPL in each of the light emitting areas LA1 to LA3 may be to The thickness T3 of the cap layer CPL in each of the light emitting areas LA1 to LA3 may be the sum T1+T2 of the thickness T1 of the first cap layer CPL1 and the thickness T2 of the second cap layer CPL2. to Then, a resonance thickness that can cause a resonance phenomenon of light emitted from the light emitting elements EL1 to EL3 can be formed. Accordingly, the light emission efficiency of each of the light emitting elements EL1 to EL3 can be improved.

[0137] The second cover layer CPL2 may include an inorganic material or an organic material. In some embodiments, the inorganic material may be an inorganic insulating material or an inorganic deposition material, and the organic material may be an organic insulating material or an organic deposition material. In some embodiments, the inorganic material may include, for example, any one or more of silicon nitride, aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, and niobium oxide. In some embodiments, the organic material may include any one or more of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin. In an embodiment, the second cover layer CPL2 may include a different material from the first cover layer CPL1. For example, the first cover layer CPL1 and the second cover layer CPL2 may be made of different inorganic materials.

[0138] The second cover layer CPL2 may have a refractive index of 1.8 to 2.2 so as to effectively reflect and transmit the internally emitted light. The refractive index of the second cover layer CPL2 may specifically be 1.9 to 2.1. In an embodiment, the refractive index of the second cover layer CPL2 may be 2. The refractive index of the second cover layer CPL2 may be the same as the refractive index of the first cover layer CPL1. In an embodiment, the refractive index of the second cover layer CPL2 may be different from the refractive index of the first cover layer CPL1. However, the present disclosure is not limited thereto, and the refractive index of each of the first cover layer CPL1 and the second cover layer CPL2 may be variously adjusted within the above range.

[0139] Optical member 300 (see Figure 2 ) may be disposed on the counter substrate 200. The optical member 300 may be an anti-reflection member that prevents reflection of external light.

[0140] Reference Fig. 9 and Fig.10 , the optical member 300 may include a base layer 310 , a colorant layer 320 , and an adhesive layer 330 .

[0141] The base layer 310 may include a polymer film. The polymer film may include, for example, any one of polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), and cycloolefin polymer (COP). In an embodiment, the base layer 310 may be triacetyl cellulose.

[0142] The colorant layer 320 may be disposed on the surface of the base layer 310. The colorant layer 320 may include a colorant that absorbs light in a specific wavelength band. The colorant layer 320 may include a first colorant, a second colorant, a third colorant, and a fourth colorant. The first colorant may absorb light in a wavelength band of about 390nm to 440nm. The second colorant may absorb light in a wavelength band of about 490nm to 510nm. The third colorant may absorb light in a wavelength band of about 580nm to 610nm. The fourth colorant may absorb light in a wavelength band of about 660nm to 690nm. The first to fourth colorants may transmit light in wavelength bands other than the light in the wavelength bands they absorb.

[0143] The colorant layer 320 may transmit blue light having a wavelength band of about 440 nm to about 490 nm, green light having a wavelength band of about 510 nm to about 580 nm, and red light having a wavelength band of about 610 nm to about 660 nm. The colorant layer 320 may transmit light emitted from the display element layer EVL and absorb light within the above wavelength band among external light incident from the outside, thereby reducing reflection of external light. The colorant layer 320 may be formed by mixing the above colorant in a transparent resin.

[0144] The adhesive layer 330 may be disposed on a surface of the colorant layer 320. The adhesive layer 330 may bond the optical member 300 to the counter substrate 200. The adhesive layer 330 may be, for example, a pressure sensitive adhesive (PSA) layer.

[0145] Fig.10 The optical component 300 (see Fig. 9 ) is a graph showing the wavelength dependence of the transmittance of an embodiment of the present invention. Fig.10 As shown in FIG. 1 , the optical member 300 can absorb light in a specific wavelength band and transmit light in other wavelength bands. Accordingly, the optical member 300 can transmit light from the display element layer EVL (see FIG. 1 ). Figure 2 ) and absorbs light in the above-mentioned wavelength band among external light incident from the outside, thereby reducing reflection of external light. In addition, when compared with a polarizing plate, the optical member 300 can have excellent transmittance, and when the optical member 300 is used, an alignment process that may be required when a polarizing plate is used to control reflected light can be omitted.

[0146] As described above, the display device 10 according to the embodiment may include the capping layer CPL including the first capping layer CPL1 and the second capping layer CPL2. Therefore, it is possible to reduce reflection of external light in the non-emission area NLA and improve luminous efficiency of the emission areas LA1 to LA3.

[0147] Fig.11 The display device 10 according to the embodiment (see Figure 1 ) cross-sectional view.

[0148] Reference Fig.11 , the current embodiment is different from the above Figures 6 to 10 The embodiment of the present invention is different in that the present embodiment includes a first cover layer CPL1 disposed in each light emitting area LA1, LA2 or LA3, and a second cover layer CPL2 disposed on the first cover layer CPL1 and in the light emitting areas LA1 to LA3 and the non-light emitting area NLA. Fig.11 The same elements and features of the embodiment as those of the above-described embodiment are described below, and the differences are described below.

[0149] Fig.11 Example of a cap layer CPL (see Figure 2 ) can be set in the display element layer EVL (see Figure 2 ) and may include a first cover layer CPL1 and a second cover layer CPL2 disposed on the first cover layer CPL1.

[0150] The first cover layer CPL1 may be directly disposed on the display element layer EVL. The first cover layer CPL1 may overlap with the light emitting areas LA1 to LA3 of the display element layer EVL. Specifically, the first cover layer CPL1 may overlap with the first light emitting area LA1, the second light emitting area LA2, and the third light emitting area LA3. The first cover layer CPL1 may not overlap with the non-light emitting area NLA of the display element layer EVL. The first cover layer CPL1 may be disposed in the shape of a plurality of islands to correspond to the light emitting areas LA1 to LA3, respectively, and the areas between the plurality of islands may correspond to the non-light emitting area NLA. In addition, the first cover layer CPL1 may not overlap with the embankment layer 155.

[0151] The first cap layer CPL1 may improve the light emitting efficiency of the light emitting elements EL1 to EL3 by increasing the thickness of the cap layer CPL in each of the light emitting regions LA1 to LA3. The thickness of the first cap layer CPL1 may be arrive The first cap layer CPL1 may include an inorganic material or an organic material. In some embodiments, the inorganic material may be an inorganic insulating material or an inorganic deposition material, and the organic material may be an organic insulating material or an organic deposition material. In some embodiments, the inorganic material may include, for example, any one or more of silicon nitride, aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, and niobium oxide. In some embodiments, the organic material may include any one or more of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0152] The first cover layer CPL1 may have a refractive index of 1.8 to 2.2 in order to effectively reflect and transmit the internally emitted light. The refractive index of the first cover layer CPL1 may be specifically 1.9 to 2.1. In an embodiment, the refractive index of the first cover layer CPL1 may be 2.

[0153] The second cover layer CPL2 may be disposed on the display element layer EVL and the first cover layer CPL1. The second cover layer CPL2 may cover the display element layer EVL and the first cover layer CPL1. The second cover layer CPL2 may overlap the light emitting areas LA1 to LA3 and the non-light emitting area NLA of the display element layer EVL. For example, the second cover layer CPL2 may be continuously disposed across the light emitting areas LA1 to LA3 and the non-light emitting area NLA.

[0154] The second cover layer CPL2 may include an inorganic insulating material that can protect the top of the display element layer EVL. The inorganic insulating material may include, for example, any one or more of silicon nitride, aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, and niobium oxide. The second cover layer CPL2 may be made of an inorganic insulating material different from that of the first cover layer CPL1.

[0155] The second cover layer CPL2 may have a predetermined thickness to make the incident external light disappear by destructive interference. The thickness of the second cover layer CPL2 may be arrive With a thickness of to The second cover layer CPL2 may reduce reflection of external light incident into the non-light emitting area NLA by making the external light disappear.

[0156] The second cover layer CPL2 may have a refractive index of 1.8 to 2.2 so as to reflect external light and effectively transmit internally emitted light. The refractive index of the second cover layer CPL2 may be the same as that of the first cover layer CPL1. However, the present disclosure is not limited thereto, and the refractive index of the second cover layer CPL2 may be variously adjusted within the above range.

[0157] According to an embodiment, the thickness of the cap layer CPL in each of the light emitting areas LA1 to LA3 may be to The thickness of the cap layer CPL in each of the light emitting areas LA1 to LA3 may be the sum of the thickness of the first cap layer CPL1 and the thickness of the second cap layer CPL2. to Then, a resonance thickness that can cause a resonance phenomenon of the light emitting elements EL1 to EL3 can be formed. Accordingly, the light emission efficiency of each of the light emitting elements EL1 to EL3 can be improved.

[0158] Fig.12 The display device 10 according to the embodiment (see Figure 1 ) cross-sectional view. Fig.13 is based on Fig.12 Schematic diagram of a cover layer CPL of an embodiment.

[0159] Reference Fig.12 and Fig.13 , the current embodiment is different from the above Figures 6 to 11 The embodiment of FIG. 4 is different in that the cap layer CPL is a single layer and includes an inorganic insulating material.

[0160] The cover layer CPL can be arranged on the display element layer EVL (see Figure 2). The cover layer CPL may be a single layer including an inorganic insulating material. The cover layer CPL may be manufactured by depositing an inorganic insulating material on the display element layer EVL, and then depositing the same inorganic insulating material on the inorganic insulating material. The process of manufacturing the cover layer CPL is described in more detail below.

[0161] like Fig.13 As shown in FIG, the capping layer CPL may include a first region CP1 and a second region CP2.

[0162] The first region CP1 may overlap with the light emitting regions LA1 to LA3 of the display element layer EVL. Specifically, the first region CP1 may overlap with the first light emitting region LA1, the second light emitting region LA2, and the third light emitting region LA3. The first region CP1 may not overlap with the non-light emitting region NLA of the display element layer EVL. The first region CP1 may be set in the shape of a plurality of islands to correspond to the light emitting regions LA1 to LA3, respectively, and the regions between the plurality of islands may correspond to the non-light emitting region NLA. In addition, the first region CP1 may not overlap with the embankment layer 155.

[0163] The second region CP2 may overlap with the non-emission region NLA of the display element layer EVL. The second region CP2 may not overlap with the first emission region LA1, the second emission region LA2, and the third emission region LA3. The second region CP2 may be arranged in a grid form to correspond to the non-emission region NLA, and the regions defined by the grid form may correspond to the emission regions LA1 to LA3, respectively. In addition, the second region CP2 may overlap with the bank layer 155.

[0164] The first region CP1 may have to The second region CP2 may have a thickness T4 of 1 to 2 in order to improve the light emitting efficiency of the light emitting elements EL1 to EL3 corresponding to the light emitting regions LA1 to LA3, respectively. arrive The thickness T5 of the first region CP1 may be greater than the thickness T5 of the second region CP2 so as to reduce the reflection of external light in the non-light emitting area NLA. The thickness T4 of the first region CP1 may be greater than the thickness T5 of the second region CP2. The difference between the thickness T4 of the first region CP1 and the thickness T5 of the second region CP2 may be arrive

[0165] In an embodiment, the uppermost surface of the first region CP1 of the cover layer CPL may be disposed adjacent to the counter substrate 200. Here, the uppermost surface may be a surface disposed at the highest point from the substrate 100 in the third direction DR3. The uppermost surface of the first region CP1 may be disposed closer to the counter substrate 200 than the uppermost surface of the second region CP2. In addition, at least a portion of the upper surface of the first region CP1 may be recessed toward the substrate 100.

[0166] In the current embodiment, since a cover layer CPL including a first area CP1 overlapping each of the light-emitting areas LA1 to LA3 and a second area CP2 overlapping the non-light-emitting area NLA is formed, it is possible to reduce reflection of external light in the non-light-emitting area NLA and improve light-emitting efficiency in the light-emitting areas LA1 to LA3.

[0167] Fig.14 The display device 10 according to the embodiment (see Figure 1 ) cross-sectional view. Fig.15 is based on Fig.14 Schematic diagram of a cover layer CPL of an embodiment.

[0168] Reference Fig.14 and Fig.15 , the current embodiment and Figures 6 to 11 The embodiment of is different in that the cap layer CPL is a single layer and includes an organic material. Fig.14 and Fig.15 Examples and Fig.12 and Fig.13 The difference of the embodiment is that Fig.14 and Fig.15 The cover layer CPL in the embodiment has a relatively flat uppermost surface.

[0169] The cover layer CPL can be arranged on the display element layer EVL (see Figure 2 ). The cover layer CPL may be a single layer including an organic insulating material. The cover layer CPL may be manufactured by applying an organic insulating material on the display element layer EVL using a solution process.

[0170] like Fig.15 As shown in FIG. 1 , the cap layer CPL may include a first region CP1 and a second region CP2. Fig.12 and Fig.13 The arrangements of the first region CP1 and the second region CP2 are the same, so a description thereof will be omitted.

[0171] The first region CP1 may have to The second region CP2 may have a thickness T4 of 1 to 2 in order to improve the light emitting efficiency of the light emitting elements EL1 to EL3 corresponding to the light emitting regions LA1 to LA3, respectively. arrive The thickness T5 of the first region CP1 may be greater than the thickness T5 of the second region CP2 so as to reduce the reflection of external light in the non-light emitting area NLA. The thickness T4 of the first region CP1 may be greater than the thickness T5 of the second region CP2. The difference between the thickness T4 of the first region CP1 and the thickness T5 of the second region CP2 may be arrive

[0172] In an embodiment, the upper surface of the cover layer CPL may be flat. For example, the upper surface of the cover layer CPL may be arranged parallel to the upper surface of the substrate 100. Accordingly, the upper surface of the first region CP1 and the upper surface of the second region CP2 may be aligned with each other. The lowermost surface of the first region CP1 may be arranged adjacent to the substrate 100. Here, the lowest surface may be a surface that is arranged at the lowest point from the substrate 200 in a direction opposite to the third direction DR3. The lowermost surface of the first region CP1 may be arranged closer to the substrate 100 than the lowermost surface of the second region CP2. In addition, at least a portion of the lower surface of the first region CP1 may extend downward toward the substrate 100.

[0173] In the current embodiment, since the cover layer CPL includes a first area CP1 overlapping each of the light-emitting areas LA1 to LA3 and a second area CP2 overlapping the non-light-emitting area NLA, it is possible to reduce reflection of external light in the non-light-emitting area NLA and improve light-emitting efficiency in the light-emitting areas LA1 to LA3.

[0174] Fig.16 The display device 10 according to the embodiment (see Figure 1 ) cross-sectional view.

[0175] Reference Fig.16 , the current embodiment and Figures 6 to 15 The embodiment of FIG. 1 is different in that the counter substrate 200 and the sealing member 250 are omitted, and the thin film encapsulation layer TFEL is disposed on the cap layer CPL.

[0176] Display Component Layer EVL (see Figure 2 ) may be disposed on the substrate 100, and the cover layer CPL may be disposed on the display element layer EVL. The cover layer CPL may be Figures 6 to 15 Any of the described cover layers CPL. The thin film encapsulation layer TFEL may be disposed on the cover layer CPL, and the optical member 300 may be disposed on the thin film encapsulation layer TFEL.

[0177] The thin film encapsulation layer TFEL may be commonly positioned in the first light emitting area LA1, the second light emitting area LA2, the third light emitting area LA3, and the non-light emitting area NLA. In an embodiment, the thin film encapsulation layer TFEL may directly cover the cover layer CPL, and may cover the display element layer EVL.

[0178] In an embodiment, the thin film encapsulation layer TFEL may include a first encapsulation inorganic layer TFE1 , an encapsulation organic layer TFE2 , and a second encapsulation inorganic layer TFE3 sequentially stacked on the cap layer CPL.

[0179] The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may each include any one or more of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride, and lithium fluoride. The encapsulation organic layer TFE2 may include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, or perylene resin.

[0180] The structure of the thin film encapsulation layer TFEL is not limited to the above-mentioned example, and the stacking structure of the thin film encapsulation layer TFEL may be variously changed.

[0181] exist Fig.16 In the display device 10 shown in FIG. 1 , the substrate 100 may be a rigid substrate or a flexible substrate. Accordingly, the display device 10 may be a rigid display device or a foldable display device that can be folded and unfolded.

[0182] Fig.17 and Fig.18 FIG. 1 is a diagram showing a process for manufacturing the display device 10 according to the embodiment (see FIG. 1 ). Figure 1 ) method. Fig.17 and Fig.18 The manufacturing method of the above Fig.11 The present invention relates to a process for manufacturing a cover layer CPL of a display device.

[0183] Reference Fig.17 The display element layer EVL is formed by forming a plurality of switching elements ST1 to ST3, a plurality of light emitting elements EL1 to EL3, a via layer 150 and a bank layer 155 on the substrate 100 (see Figure 2 ).

[0184] Subsequently, the substrate 100 is inverted, and the first mask MS1 is aligned to correspond to the surface of the substrate 100. The first mask MS1 may be placed to face the display element layer EVL. The first mask MS1 may include an opening area MO and a blocking area MB. The opening area MO may be an area through which the deposition material passes, and the blocking area MB may be an area through which the deposition material cannot pass but is blocked. The opening area MO may be placed to correspond to the light emitting areas LA1 to LA3 of the display element layer EVL, respectively, and the blocking area MB may be placed to correspond to the non-light emitting area NLA.

[0185] Subsequently, a first cover layer CPL1 is formed by depositing an inorganic insulating material on the substrate 100 on which the first mask MS1 is aligned. The deposition process may use chemical vapor deposition (CVD) or physical vapor deposition (PVD). A portion of the inorganic insulating material may be deposited on each of the light-emitting regions LA1 to LA3 of the display element layer EVL through the opening region MO of the first mask MS1. Other portions of the inorganic insulating material may not be deposited on the non-light-emitting region NLA of the display element layer EVL because the blocking region MB of the first mask MS1 blocks deposition on the non-light-emitting region NLA. Therefore, the first cover layer CPL1 may be formed on each of the light-emitting regions LA1 to LA3 of the display element layer EVL.

[0186] Then, refer to Fig.18 , the second mask MS2 is aligned to correspond to the surface of the substrate 100. The second mask MS2 may be placed to face the display element layer EVL (see Figure 2 ). The second mask MS2 may include an opening area MO2 and a blocking area MB2. The opening area MO2 may be positioned to correspond to the light emitting areas LA1 to LA3 and the non-light emitting area NLA of the display element layer EVL, and the blocking area MB may be positioned to correspond to an area other than the display element layer EVL.

[0187] Subsequently, a second cover layer CPL2 is formed by depositing an inorganic insulating material on the substrate 100 on which the second mask MS2 is aligned. A portion of the inorganic insulating material may be deposited on the light emitting areas LA1 to LA3 and the non-light emitting area NLA of the display element layer EVL through the opening area MO2 of the second mask MS2. The deposition of another portion of the inorganic insulating material may be blocked by the blocking area MB2 of the second mask MS2. Therefore, the second cover layer CPL2 may be formed on the light emitting areas LA1 to LA3 and the non-light emitting area NLA of the display element layer EVL.

[0188] Then, the substrate 100 and the counter substrate 200 (see Fig.11 ) can be joined together, and the optical member 300 (see Fig.11 ) can be attached to the surface of the counter substrate 200 to produce Fig.11 The display device 10 shown in FIG. Figure 1 ).

[0189] Hereinafter, a simulation example of the above-described display device 10 will be described.

[0190] Simulation 1

[0191] In a structure in which a bank layer, a hole transport layer, an electron transport layer, and a common electrode are stacked on a substrate, by increasing the thickness of the cap layer from Change to and To simulate the reflectivity of the display device according to the thickness of the cover layer on the common electrode. Here, the reflectivity shows the result reflecting the relative visibility and does not reflect the result of the relative luminous efficiency. In addition, the common electrode affecting the reflectivity is set to The simulation results are as follows: Fig.19 and Fig. 20 as shown in .

[0192] Fig.19 A graph illustrating the wavelength dependence of reflectance from a display device according to an embodiment is shown. Fig. 20 A graph illustrating the dependence of the relative luminous efficiency-reflected reflectivity on the wavelength is shown. Fig.19 and Fig. 20 , the horizontal axis represents wavelength, the vertical axis represents reflectivity, and each curve represents the thickness of the cap layer.

[0193] Reference Fig.19 , the reflectivity is relatively lower when the cap layer is provided than when no cap layer is provided. In particular, as the thickness of the cap layer increases from Reduce to The overall reflectivity is reduced.

[0194] Reference Fig. 20 , when reflecting the relative luminous efficiency, the reflectivity is relatively lower when the cap layer is provided than when no cap layer is provided. In particular, when the thickness of the cap layer is and The reflectivity is significantly lower.

[0195] Simulation 2

[0196] In a structure in which a bank layer, a hole transport layer, an electron transport layer, a common electrode and a cap layer are stacked on a substrate, by to The thickness of the cover layer was varied within a range to simulate the amount of reflected light. These simulation results are shown in Tables 1 and Fig.21 Shown in.

[0197] Fig.21 A graph illustrating the dependence of the amount of reflected light on the thickness of the cover layer is shown. Fig.21 , the horizontal axis represents the thickness of the cover layer, and the vertical axis represents the amount of reflected light.

[0198] [Table 1]

[0199]

[0200]

[0201] Refer to Table 1 and Fig.21 , when the thickness of the cap layer is When the thickness of the cover layer is , the amount of reflected light is 2.56.

[0202] It is obvious from the above results that when the thickness of the cap layer is When the thickness of the cap layer is The amount of reflected light is reduced by approximately 95% compared to the

[0203] Therefore, in the current embodiment, by forming a non-light emitting region with a thickness of about to In addition, by forming a cover layer with a thickness of about to The cover layer can maximize the luminous efficiency of the light-emitting element.

[0204] In the display device according to the embodiment, the capping layer having different thicknesses is formed in the light emitting area and the non-light emitting area, so that it is possible to reduce the reflection of external light in the non-light emitting area and improve the light emitting efficiency in the light emitting area.

[0205] In addition, since the display device further includes an optical member, reflection of external light can be reduced and a polarizing plate can be omitted.

[0206] However, the effects of the present disclosure are not limited to those set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the claims.

[0207] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the exemplary embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed exemplary embodiments are used in a general and descriptive sense only and not for purposes of limitation.

Claims

1. A display device, wherein: The display device comprises: A pixel electrode is disposed on the substrate; a bank layer covering the edge of the pixel electrode and defining a plurality of light-emitting areas and non-light-emitting areas; A light-emitting layer, disposed on the pixel electrode and the bank layer; A common electrode, disposed on the light-emitting layer; A cover layer, disposed on the common electrode; to the substrate, facing the substrate; and an optical member disposed on the pair of substrates, Wherein, the cover layer comprises: A first covering layer, disposed on the common electrode; and A second cover layer is disposed on the first cover layer and overlaps the plurality of light emitting regions.

2. The display device according to claim 1, wherein: The first capping layer overlaps the plurality of light emitting regions and the non-light emitting region, and the first capping layer overlaps the second capping layer.

3. The display device according to claim 1, wherein: The thickness of the first cap layer is to 4. The display device according to claim 1, wherein: The refractive index of each of the first cap layer and the second cap layer is 1.8 to 2.

2.

5. The display device according to claim 1, wherein: The thickness of the second cap layer is to 6. The display device according to claim 1, wherein: The first capping layer and the second capping layer include different materials.

7. The display device according to claim 1, wherein: The sum of the thickness of the first cover layer and the thickness of the second cover layer in each of the plurality of light emitting regions is to 8. The display device according to claim 1, wherein: The first cover layer is disposed under the second cover layer or on the second cover layer.

9. The display device according to claim 1, wherein: The optical component comprises: Base layer; a colorant layer disposed on the base layer; and The adhesive layer is disposed on the colorant layer.

10. The display device according to claim 9, wherein: The colorant layer transmits light in a wavelength band of 440 nm to 490 nm, light in a wavelength band of 510 nm to 580 nm, and light in a wavelength band of 610 nm to 660 nm, and absorbs light in other wavelength bands.

11. A display device, wherein: The display device comprises: A pixel electrode is disposed on the substrate; a bank layer covering the edge of the pixel electrode and defining a light-emitting area and a non-light-emitting area; A light-emitting layer, disposed on the pixel electrode and the bank layer; A common electrode, disposed on the light-emitting layer; A cover layer, disposed on the common electrode; to the substrate, facing the substrate; and an optical member disposed on the pair of substrates, The cover layer includes a first region overlapping with the light-emitting region and a second region overlapping with the non-light-emitting region, and a thickness of the first region is greater than a thickness of the second region.

12. The display device according to claim 11, wherein: The thickness of the first region is to 13. The display device according to claim 11, wherein: The thickness of the second region is to 14. The display device according to claim 11, wherein: The first area does not overlap with the non-luminescent area, and the second area does not overlap with the luminescent area.

15. The display device according to claim 11, wherein: The capping layer includes an inorganic insulating material or an organic insulating material.

16. The display device according to claim 11, wherein: The upper surface of the cover layer is flat and disposed parallel to the substrate.

17. A display device, wherein: The display device comprises: A pixel electrode is disposed on the substrate; a bank layer covering the edge of the pixel electrode and defining a light-emitting area and a non-light-emitting area; A light-emitting layer, disposed on the pixel electrode and the bank layer; A common electrode, disposed on the light-emitting layer; A cover layer, disposed on the common electrode; a thin film encapsulation layer, disposed on the cover layer; and an optical component, disposed on the thin film encapsulation layer, The cover layer includes a first region overlapping with the light-emitting region and a second region overlapping with the non-light-emitting region, and a thickness of the first region is greater than a thickness of the second region.

18. The display device according to claim 17, wherein: The thin film encapsulation layer includes a first encapsulation inorganic layer disposed on the capping layer, an encapsulation organic layer disposed on the first encapsulation inorganic layer, and a second encapsulation inorganic layer disposed on the encapsulation organic layer.

19. The display device according to claim 17, wherein: The first area does not overlap with the non-luminescent area, and the second area does not overlap with the luminescent area.

20. The display device according to claim 17, wherein: The optical component comprises: Base layer; a colorant layer disposed on the base layer; and an adhesive layer disposed on the colorant layer, The colorant layer transmits light within a wavelength band of 440 nm to 490 nm, light within a wavelength band of 510 nm to 580 nm, and light within a wavelength band of 610 nm to 660 nm, and absorbs light within other wavelength bands.

Images