Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes: a substrate including: an emission area including a first emission portion and a second emission portion; and a non-emission region disposed between the first emission portion and the second emission portion; a first light emitting member including a first display element disposed on the first emission portion of the substrate; a first thin film encapsulation layer disposed on the first light emitting member; and a second light emitting member disposed on the first thin film encapsulation layer and including a second display element overlapping the second emission portion, in which the first light emitting member further includes: a first pixel defining layer defining a first opening; and a bank member disposed on the first pixel defining layer and including a first bank layer and a second bank layer, the second display element overlapping the first pixel defining layer and the bank member in a direction perpendicular to an upper surface of the substrate, and the second display element contacting the second bank layer in a direction toward the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0143448 filed in the Korean Intellectual Property Office on October 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] With the development of an information-oriented society, various demands for display devices are increasing. For example, display devices are being used by various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among such flat panel display devices, a light emitting display device includes a light emitting element that emits light by itself so that each of the pixels of the display panel can emit light by itself. Accordingly, the light emitting display device can display an image without supplying light to a backlight unit of the display panel.

[0005] Recently, as various electronic devices have been developed, the demand for high aperture ratio and high resolution display devices is increasing. Since a display device with high aperture ratio and high resolution requires high pixel density, a display device for implementing it and a method for manufacturing such a display device may be required. Summary of the invention

[0006] The embodiment provides a display device having a high aperture ratio and a high resolution and a method of manufacturing the display device.

[0007] It should be noted that the objects of the present disclosure are not limited to the above objects; and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0008] An embodiment of a display device may include: a substrate, including: an emission area, including a first emission part and a second emission part; and a non-emission area, arranged between the first emission part and the second emission part; a first light-emitting member, including a first display element arranged on the first emission part of the substrate; a first thin film encapsulation layer, arranged on the first light-emitting member; and a second light-emitting member, arranged on the first thin film encapsulation layer and including a second display element overlapping with the second emission part, wherein the first light-emitting member further includes: a first pixel defining layer, defining a first opening; and a dam member, arranged on the first pixel defining layer and including a first dam layer and a second dam layer, wherein the second display element overlaps with the first pixel defining layer and the dam member in a direction perpendicular to the upper surface of the substrate, and wherein the second display element may contact the second dam layer in a direction toward the substrate.

[0009] The first display element may include: a first electrode; a first display emission layer disposed on the first electrode; and a second electrode disposed on the first display emission layer, wherein the first display emission layer and the second electrode are in contact with a side surface of the first dam layer facing the first emission portion, and wherein the second electrode may be electrically connected to the first dam layer.

[0010] The second bank layer may include a tip portion protruding from a side surface of the first bank layer toward the first emission portion, and wherein the side surface of the first bank layer and the tip portion of the second bank layer form an undercut portion.

[0011] The first pattern layer may be disposed between the first electrode and the first pixel defining layer in a direction perpendicular to an upper surface of the substrate in the non-emission region, and wherein the first pattern layer may contact the first display emission layer.

[0012] The first opening may define a first emitting portion.

[0013] The first thin film encapsulation layer may include: a first encapsulation layer, which is in contact with the first display element and the dam member; a second encapsulation layer, which includes an organic material and is disposed on the first encapsulation layer; and a third encapsulation layer, which includes an inorganic material and is disposed on the second encapsulation layer, and wherein the second encapsulation layer may be completely surrounded by the first encapsulation layer and the third encapsulation layer in the first emission portion.

[0014] The second encapsulation layer may not overlap the second emission portion.

[0015] The second light emitting member may further include a second pixel defining layer overlapping the first emission portion and defining the second opening, and wherein the second pixel defining layer may overlap the first display element in a direction perpendicular to an upper surface of the substrate.

[0016] The second display element may include: a third electrode; a second display emission layer disposed on the third electrode; and a common electrode disposed on the second display emission layer and the second pixel defining layer.

[0017] The third electrode may contact the second bank layer in a direction toward the substrate, and wherein the third electrode may be electrically connected to the second bank layer, the first bank layer, and the first electrode.

[0018] The second pattern layer may be disposed between the third electrode and the second pixel defining layer in a direction perpendicular to the upper surface of the substrate in the non-emission region, and wherein the second pattern layer may contact the second display emission layer.

[0019] The second opening may define a second emitting portion.

[0020] The first pixel defining layer may have a mesh pattern completely surrounding the first emission portion in a plan view, and wherein the second pixel defining layer may have a mesh pattern completely surrounding the second emission portion in a plan view.

[0021] In plan view, the emitting area may be larger than the non-emitting area.

[0022] An embodiment of a display device may include: a substrate, including: a first emission region including a first emission part and a second emission part and a second emission region spaced apart from the second emission part, the first emission part being arranged between the second emission region and the second emission part; a first light-emitting member, arranged on the substrate and including: a first light-emitting element overlapping the first emission part; a second light-emitting element overlapping the second emission region; and a dam member overlapping the second emission part; a first encapsulation layer, arranged on the first light-emitting member; and a second light-emitting member, arranged on the first encapsulation layer and including a third light-emitting element overlapping the second emission part, wherein the dam member includes: a first portion in contact with the first light-emitting element; a second portion in contact with the third light-emitting element; and a third portion in contact with the second light-emitting element, and wherein the first portion, the second portion and the third portion are spaced apart from each other, and the first encapsulation layer is arranged between the first portion, the second portion and the third portion.

[0023] The first encapsulation layer may include: a first inorganic layer surrounding the first portion; and a second inorganic layer surrounding the third portion, and wherein the first inorganic layer and the second inorganic layer may be spaced apart from each other in a direction parallel to the upper surface of the substrate, and the second portion is disposed between the first inorganic layer and the second inorganic layer.

[0024] The first light emitting member may further include a first pixel defining layer disposed between the substrate and the dam member, wherein the first pixel defining layer includes: a first sub-portion contacting the first portion; and a second sub-portion contacting the third portion, and wherein the first sub-portion and the second sub-portion may be spaced apart from each other, and the second portion is disposed between the first sub-portion and the second sub-portion.

[0025] The second light emitting element may include an anode electrode, and wherein the second portion may be in contact with the anode electrode in a direction toward the substrate.

[0026] An embodiment of a method for manufacturing a display device may include: preparing a substrate, the substrate including: an emission region including a first emission portion and a second emission portion; and a non-emission region disposed between the first emission portion and the second emission portion; forming a first electrode disposed on the first emission portion of the substrate and a first sacrificial layer disposed on the first electrode, and forming a first pixel defining material layer covering the first sacrificial layer and exposing a portion of the first electrode; forming a first dam material layer covering the first electrode and the first pixel defining material layer and a second dam material layer disposed on the first dam material layer, and then removing a portion of the first dam material layer, a portion of the second dam material layer, and a portion of the first pixel defining material layer by an etching process to form a first hole and a second hole overlapping the first electrode and spaced apart from each other; partially etching the interior of the first hole by an etching process to form a first dam layer and a second dam layer having a tip portion protruding from the first dam layer toward the first emission portion, and forming a first pixel defining layer defining a first opening; forming a first dam material layer disposed on the first electrode a first display emission layer and a second electrode, so that the first display emission layer and the second electrode can contact the side surface of the first dam layer in the first emission part, and form a first thin film encapsulation layer covering the second electrode, the first dam layer and the second dam layer; remove a portion of the first thin film encapsulation layer in the second emission part by an etching process to expose a portion of the second dam layer in the second emission part; in the second emission part, form a third electrode arranged on the second dam layer and the first thin film encapsulation layer and a second sacrificial layer arranged on the third electrode, and form a second pixel defining layer covering a portion of the second sacrificial layer, overlapping with the first emission part and defining a second opening; use the second pixel defining layer as a mask, remove the second sacrificial layer arranged on the third electrode by an etching process, form a second display emission layer arranged on the third electrode, and then form a common electrode completely covering the second display emission layer and the second pixel defining layer; and form a second thin film encapsulation layer arranged on the common electrode, wherein the formation of the third electrode may include setting the third electrode to contact the second dam layer.

[0027] The first pixel defining layer may overlap the second display emission layer in a direction perpendicular to an upper surface of the substrate, and the second pixel defining layer overlaps the first display emission layer in a direction perpendicular to the upper surface of the substrate.

[0028] The display device according to the embodiment may include a first light emitting member and a second light emitting member stacked vertically. A first pixel defining layer included in the first light emitting member may define a first opening, and a second pixel defining layer included in the second light emitting member may define a second opening. Light emitted from the first opening and light emitted from the second opening may have the same color.

[0029] The display device according to the embodiment can be designed so that the first opening and the second opening do not overlap each other in a direction perpendicular to the upper surface of the substrate, so that the emission area can be expanded while the non-emission area is reduced. In this way, the display device according to the embodiment can have a high aperture ratio and high resolution.

[0030] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic perspective view showing an electronic device according to an embodiment;

[0033] Figure 2 is a schematic perspective view showing a display device included in an electronic device according to an embodiment;

[0034] Figure 3 yes Figure 2 A schematic cross-sectional view of a display device;

[0035] Figure 4 yes Figure 3 A schematic plan view of a display layer;

[0036] Figure 5 It is shown Figure 4 A schematic plan view of a layout of emission regions in a display region of FIG.

[0037] Figure 6 It is along Figure 5 A schematic cross-sectional view of the display area taken along line X1-X1';

[0038] Figure 7 yes Figure 6 an enlarged schematic cross-sectional view of a first emission portion of a first emission region;

[0039] Figure 8 yes Figure 6 an enlarged schematic cross-sectional view of a second emission portion of a first emission region;

[0040] Fig. 9 It is shown Figure 6 A schematic plan view of the layout of the first pixel defining layer and the second pixel defining layer in FIG.

[0041] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 and Fig.23 It is used for graphic manufacturing Figure 6 Schematic cross-sectional view of a method of displaying element layers in FIG. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor do they limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0043] Unless otherwise specified, the illustrated embodiments should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter, individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0044] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading will not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements. Further, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same figure numbers and / or reference characters represent the same elements.

[0045] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or directly coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. Further, the X-axis, Y-axis and Z-axis are not limited to three axes of a rectangular coordinate system such as an x-axis, a y-axis and a z-axis, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be interpreted as only A, only B or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms "first", "second", etc. can be used in this article to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element.

[0047] Spatially relative terms such as "below," "below," "lower," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and thereby describe the relationship of one element to another element(s) as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" may encompass both the above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0048] The terms used in this article are for the purpose of describing specific embodiments, and are not intended to be limiting. As used in this article, unless the context clearly indicates otherwise, the singular forms "one" and "the (described)" are intended to also include plural forms. In addition, when used in this specification, the terms "include" and / or "comprise" and their variants specify the existence of stated features, integral bodies, steps, operations, elements, parts and / or its groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or its groups. It should also be noted that, as used in this article, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, and therefore, are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0049] Various embodiments are described herein with reference to schematic cross-sectional illustrations and / or exploded illustrations of embodiments and / or intermediate members. Therefore, variations in the shapes of the illustrations, such as due to manufacturing techniques and / or tolerances, are contemplated. Therefore, the embodiments disclosed herein should not be interpreted as being limited to specific illustrated shapes of regions, but rather should include deviations in shapes due to, for example, manufacturing. In this way, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not intended to be limiting.

[0050] According to the convention in the art, some embodiments are described and illustrated in the accompanying drawings with functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control them to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also considered that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules. Further, without departing from the scope of the inventive concept, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules.

[0051] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 is a schematic perspective view showing an electronic device 1 according to the embodiment.

[0053] refer to Figure 1 , the electronic device 1 can display a moving image or a still image. The electronic device 1 may include an electronic device that provides a display screen. For example, the electronic device 1 may include a television, a laptop computer, a monitor, an electronic billboard, an Internet of Things (IoT) device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display device, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a video camera, etc.

[0054] exist Figure 1In , a first direction (e.g., X-axis direction), a second direction (e.g., Y-axis direction), and a third direction (e.g., Z-axis direction) are defined. The first direction (e.g., X-axis direction) and the second direction (e.g., Y-axis direction) may be perpendicular to each other, the first direction (e.g., X-axis direction) and the third direction (e.g., Z-axis direction) may be perpendicular to each other, and the second direction (e.g., Y-axis direction) and the third direction (e.g., Z-axis direction) may be perpendicular to each other. The first direction (e.g., X-axis direction) may refer to the horizontal direction in the drawings, the second direction (e.g., Y-axis direction) may refer to the vertical direction in the drawings, and the third direction (e.g., Z-axis direction) may refer to the up and down direction (i.e., thickness direction) in the drawings. As used herein, unless otherwise specifically stated, a direction may refer to a direction indicated by an arrow as well as an opposite direction. If it is necessary to distinguish between the two opposite directions, one of the two directions may be referred to as "one side in the direction" and the other direction may be referred to as "the opposite side in the direction". In Figure 1 , a side indicated by an arrow indicating a direction is referred to as a side in the direction, and the opposite side is referred to as an opposite side in the direction.

[0055] In the following description of the surface of the electronic device 1 or the elements of the electronic device 1, for ease of explanation, the surface on the side facing the displayed image (i.e., the side indicated by the arrow in the third direction (e.g., the Z-axis direction)) will be referred to as the upper surface, and the opposite surface will be referred to as the lower surface. However, it should be understood that the embodiments are not limited to this. The surface and the opposite surface of each of the elements may be referred to as the front surface and the rear surface, respectively, or may be referred to as the first surface and the second surface, respectively. In the description of the relative positions of the elements of the electronic device 1, the side in the third direction (e.g., the Z-axis direction) may be referred to as the upper side, and the opposite side in the third direction (e.g., the Z-axis direction) may be referred to as the lower side.

[0056] The shape of the electronic device 1 can be modified in various ways. For example, the electronic device 1 can have a shape such as a rectangle with longer lateral sides, a rectangle with longer vertical sides, a square, a quadrilateral with rounded corners (eg, vertices), other polygons, a circle, etc.

[0057] The electronic device 1 may include a display area DA and a non-display area NDA. In the display area DA, an image may be displayed. In the non-display area NDA, no image may be displayed. The display area DA may be referred to as an active area, and the non-display area NDA may be referred to as an inactive area. The display area DA may generally occupy the center of the electronic device 1.

[0058] Figure 2 is a schematic perspective view showing a display device 10 included in the electronic device 1 according to an embodiment.

[0059] refer to Figure 2 , the electronic device 1 according to the embodiment may include a display device 10. The display device 10 may provide a display screen that displays an image in the electronic device 1. Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting display device, a plasma display device, a field emission display device, and the like. In the following description, an organic light emitting diode display device may be used as an example of a display device, but the embodiment is not limited thereto. Any other display device may be used as long as the technical idea of ​​the present disclosure can be applied in the same manner.

[0060] In a plan view (or when viewed from the top), the display device 10 may have a shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle having a shorter side in a first direction (e.g., X-axis direction) and a longer side in a second direction (e.g., Y-axis direction). The corner where the shorter side in the first direction (e.g., X-axis direction) intersects with the longer side in the second direction (e.g., Y-axis direction) may be rounded with a certain curvature. However, it should be understood that the embodiments are not limited thereto. The corner may be formed at a right angle. The shape of the display device 10 in a plan view (or when viewed from the top) is not limited to a quadrilateral shape, but may be formed in a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0061] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0062] The display panel 100 may include a main area MA and an auxiliary area SBA. The main area MA may include a display area DA including pixels for displaying an image and a non-display area NDA disposed around the display area DA.

[0063] The display area DA may emit light from an emission area or an opening area to be described later. For example, the display area DA may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0064] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be defined as an edge portion of the main area MA of the display panel 100. The non-display area NDA may include a line driver supplying a signal to the display area DA and a line connecting the display driver 200 with the display area DA.

[0065] The auxiliary area SBA may extend from one side of the main area MA. The auxiliary area SBA may include a flexible material that is bendable, foldable, or rollable. For example, in the case where the auxiliary area SBA is bent, the auxiliary area SBA may overlap the main area MA in the thickness direction (e.g., the third direction or the Z-axis direction). The auxiliary area SBA may include a display pad PD (see FIG. 1 ) connected to the display driver 200 and the circuit board 300. Figure 4 According to another embodiment, the auxiliary area SBA may be eliminated, and the display driver 200 and the display pad may be disposed in the non-display area NDA.

[0066] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines DL (see Figure 4 ), which will be described later. For example, the display driver 200 may supply a power supply voltage to the voltage lines VL1 and VL2 (see Figure 4 ), and supplies the gate control signal to the gate driver 210 (see Figure 4 ). The display driver 200 may be implemented as an integrated circuit (IC) and may be attached to the display panel 100 by a chip on glass (COG) technology, a chip on plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 may be disposed in the auxiliary area SBA, and when the auxiliary area SBA is bent, the display driver 200 may overlap with the main area MA in the thickness direction. For another example, the display driver 200 may be mounted on the circuit board 300.

[0067] The circuit board 300 may be attached to the display pad of the display panel 100 using an anisotropic conductive film (ACF). The circuit board 300 may be electrically connected to the display pad. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0068] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensor layer 180 (see FIG. 1 ) of the display panel 100. Figure 3 ).

[0069] Figure 3 yes Figure 2 Schematic cross-sectional view of a display device 10 .

[0070] refer to Figure 3 , the display panel 100 may include a display layer DPL, a touch sensor layer 180 and a color filter layer 190 . The display layer DPL may include a substrate 110 , a thin film transistor layer 130 , a display element layer 150 and a thin film encapsulation layer 170 .

[0071] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that is bendable, foldable, or rollable. For example, the substrate 110 may include a polymer resin such as polyimide (PI). However, the embodiment is not limited thereto. According to another embodiment, the substrate 110 may include a glass material or a metal material.

[0072] The thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may be disposed in the display area DA, the non-display area NDA, and the auxiliary area SBA. The thin film transistor layer 130 may include a thin film transistor layer 130 that forms a pixel PX (see Figure 4 ) thin film transistor TFT (see Figure 6 ).

[0073] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 may be disposed in the display area DA. The display element layer 150 may include display elements ED1 and ED2 (see Figure 6 ). For example, the self-luminous element according to the embodiment may include at least one of the following light-emitting diodes: an organic light-emitting diode including an organic emission layer, a quantum dot light-emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light-emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light-emitting diode (micro LED). However, the embodiment is not limited thereto.

[0074] The thin film encapsulation layer 170 may be disposed on the display element layer 150. The thin film encapsulation layer 170 may overlap the display area DA and the non-display area NDA. The thin film encapsulation layer 170 may cover the upper surface and the side surface of the display element layer 150, and may protect the display element layer 150 from external oxygen and moisture. The thin film encapsulation layer 170 may include at least one inorganic film and at least one organic film for encapsulating the display element layer 150.

[0075] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may overlap the display area DA and the non-display area NDA. The touch sensor layer 180 may sense a user's touch through mutual capacitance sensing or self capacitance sensing.

[0076] The color filter layer 190 may be disposed on the touch sensor layer 180. The color filter layer 190 may overlap the display area DA and the non-display area NDA. The color filter layer 190 may absorb some of the light introduced from the outside of the display device 10 to reduce the reflection of the external light. Accordingly, the color filter layer 190 may prevent the distortion of the color due to the reflection of the external light.

[0077] Since the color filter layer 190 is disposed (e.g., directly disposed) on the touch sensor layer 180, the display device 10 may not require a separate substrate for the color filter layer 190. Therefore, the thickness of the display device 10 may be relatively small. For example, in some implementations, the color filter layer 190 may be eliminated.

[0078] like Figure 3 As shown in , the portion of the display layer DPL overlapping the auxiliary area SBA may be bent. When a portion of the display layer DPL is bent, the display driver 200, the circuit board 300, and the touch driver 400 may overlap the main area MA in a third direction (eg, Z-axis direction).

[0079] Figure 4 yes Figure 3 Schematic plan view of the display layer DPL.

[0080] refer to Figure 4 , the display layer DPL according to the embodiment may include pixels PX overlapping the display area DA of the main area MA, gate lines GL, data lines DL, and second voltage lines VL2.

[0081] Each of the pixels PX may be defined as a minimum unit of output light. Each of the pixels PX may form a corresponding first to third emission areas EA1, EA2, and EA3 (see Figure 5 ), which will be described later.

[0082] The gate lines GL may supply gate signals received from the gate driver 210 to the pixels PX. The gate lines GL may extend in a first direction (eg, X-axis direction) and may be spaced apart from each other in a second direction (eg, Y-axis direction) crossing the first direction (eg, X-axis direction).

[0083] The data lines DL may supply the pixels PX with data voltages received from the display driver 200. The data lines DL may extend in the second direction (eg, the Y-axis direction) and may be spaced apart from each other in the first direction (eg, the X-axis direction).

[0084] The second voltage line VL2 may apply a power supply voltage received from the display driver 200 to the pixel PX. The power supply voltage may be at least one of a driving voltage, an initialization voltage, and a reference voltage. The second voltage lines VL2 may extend in a second direction (e.g., a Y-axis direction) and may be spaced apart from each other in a first direction (e.g., an X-axis direction).

[0085] The display layer DPL according to an embodiment may overlap the non-display area NDA of the main area MA, and may include a first voltage line VL1 , a gate driver 210 , a fan-out line FOL, and a gate control line GCL.

[0086] The gate driver 210 may generate a gate signal based on the gate control signal, and may sequentially supply the gate signal to the gate lines GL in a specific order.

[0087] The first voltage line VL1 may surround the display area DA and may be disposed in the non-display area NDA. The first voltage line VL1 may apply a power voltage received from the display driver 200 to the pixel PX. For example, the first voltage line VL1 may be electrically connected to various lines disposed in the display area DA.

[0088] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the data line DL.

[0089] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210. Although the gate driver 210 is disposed only in the non-display area NDA, on the left side of the display area DA in the drawings, the embodiment is not limited thereto. According to another embodiment, the display device 10 may include gate drivers 210 disposed on the left and right sides of the display area DA, respectively.

[0090] The display layer DPL according to the embodiment may overlap the auxiliary area SBA, and may include a display driver 200 and a display pad PD.

[0091] The display driver 200 may output a signal and a voltage for driving the pixel PX to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. Therefore, the data voltage may be applied to the pixel PX so that the brightness of the pixel PX may be controlled. For example, the display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0092] The display pad DP may be connected to a graphic system through the circuit board 300. The display pad DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0093] Figure 5 It is shown Figure 4 A schematic plan view of a layout of emission regions in a display area DA.

[0094] refer to Figure 5 , the display area DA according to the embodiment may include first to third emission areas EA1 , EA2 , and EA3 and a non-emission area NLA.

[0095] The non-emission area NLA may be disposed to surround the first to third emission areas EA1, EA2, and EA3. The non-emission area NLA may help prevent light emitted from the first to third emission areas EA1, EA2, and EA3 from being mixed.

[0096] The colors of the light emitted from the first to third emission areas EA1, EA2, and EA3 may be determined according to the first display element ED1 (see FIG. 1 ). Figure 6 ) and the second display element ED2 (see Figure 6 ) type, which will be described later.

[0097] According to an embodiment, the first emission area EA1 may include a first emission portion EA1a and a second emission portion EA1b. In a plan view, the first emission portion EA1a and the second emission portion EA1b may be spaced apart from each other, and a non-emission area NLA is between the first emission portion EA1a and the second emission portion EA1b. In a plan view, the first emission portion EA1a and the second emission portion EA1b may be surrounded (e.g., completely surrounded) by the non-emission area NLA. The first emission portion EA1a and the second emission portion EA1b may emit light of the same color. As an example, the first emission portion EA1a and the second emission portion EA1b may emit red light. Although the first emission portion EA1a and the second emission portion EA1b have the same size in the drawings, the embodiment is not limited thereto. For example, the size (or area) and shape of the first emission portion EA1a and the second emission portion EA1b may be adjusted as needed.

[0098] According to an embodiment, the second emission area EA2 may include a first emission portion EA2a and a second emission portion EA2b. In a plan view, the first emission portion EA2a and the second emission portion EA2b may be spaced apart from each other, and a non-emission area NLA is between the first emission portion EA2a and the second emission portion EA2b. In a plan view, the first emission portion EA2a and the second emission portion EA2b may be surrounded (e.g., completely surrounded) by the non-emission area NLA. The first emission portion EA2a and the second emission portion EA2b may emit light of the same color. As an example, the first emission portion EA2a and the second emission portion EA2b may emit green light. Although the first emission portion EA2a is smaller than the second emission portion EA2b in the drawings, the embodiment is not limited thereto. For example, the size (or area) and shape of the first emission portion EA2a and the second emission portion EA2b may be adjusted as needed.

[0099] According to an embodiment, the third emission area EA3 may include a first emission portion EA3a and a second emission portion EA3b. In a plan view, the first emission portion EA3a and the second emission portion EA3b may be spaced apart from each other, and a non-emission area NLA is between the first emission portion EA3a and the second emission portion EA3b. In a plan view, the first emission portion EA3a and the second emission portion EA3b may be surrounded (e.g., completely surrounded) by the non-emission area NLA. The first emission portion EA3a and the second emission portion EA3b may emit light of the same color. As an example, the first emission portion EA3a and the second emission portion EA3b may emit blue light. Although the first emission portion EA3a and the second emission portion EA3b have the same size in the drawings, the embodiment is not limited thereto. For example, the size (or area) and shape of the first emission portion EA3a and the second emission portion EA3b may be adjusted as needed.

[0100] At least one first emission region EA1, at least two second emission regions EA2, and at least one third emission region EA3 arranged adjacent to each other may form a single pixel group PXG. The pixel group PXG may be the smallest unit emitting white light. However, the type and / or quantity of each of the first to third emission regions EA1, EA2, and EA3 forming the pixel group PXG may vary according to the embodiment.

[0101] Figure 6 It is along Figure 5 Schematic cross-sectional view of the display area DA taken along line X1 - X1 ′.

[0102] Figure 6 1 is a schematic cross-sectional view of a portion in the display area DA of the display device 10, showing cross sections of the substrate 110, the thin film transistor layer 130, the display element layer 150, and the thin film encapsulation layer 170. Figure 3 The substrate 110 is described; and therefore, for convenience of description, redundant description will be omitted.

[0103] refer to Figure 6 , the thin film transistor layer 130 may be disposed on the substrate 110. The thin film transistor layer 130 may include a first buffer layer 111, a thin film transistor TFT, a gate insulating layer 113, a first interlayer dielectric layer 121, a capacitor electrode CPE, a second interlayer dielectric layer 123, a first connection electrode CNE1, a first through hole layer 125, a second connection electrode CNE2, and a second through hole layer 127.

[0104] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer 111 may include inorganic films alternately stacked on each other.

[0105] The thin film transistor TFT may be disposed on the first buffer layer 111 and may form a pixel circuit connected to each of the pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include an active layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0106] The active layer ACT may be disposed on the first buffer layer 111. The active layer ACT may overlap the gate electrode GE in a third direction (eg, Z-axis direction) and may be insulated from the gate electrode GE by the gate insulating layer 113. A material of a portion of the active layer ACT may be made conductive to form a source electrode SE and a drain electrode DE.

[0107] The gate electrode GE may be disposed on the gate insulating layer 113. The gate electrode GE may overlap the active layer ACT with the gate insulating layer 113 interposed therebetween.

[0108] The gate insulating layer 113 may be disposed on the active layer ACT. For example, the gate insulating layer 113 may cover the active layer ACT and the first buffer layer 111 and may insulate the active layer ACT from the gate electrode GE. The gate insulating layer 113 may include a contact hole through which the first connection electrode CNE1 passes.

[0109] The first interlayer dielectric layer 121 may cover the gate electrode GE and the gate insulating layer 113. The first interlayer dielectric layer 121 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer dielectric layer 121 may be connected to the contact hole of the gate insulating layer 113 and the contact hole of the second interlayer dielectric layer 123.

[0110] The capacitor electrode CPE may be disposed on the first interlayer dielectric layer 121. The capacitor electrode CPE may overlap the gate electrode GE in a third direction (eg, Z-axis direction). The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0111] The second interlayer dielectric layer 123 may cover the capacitor electrode CPE and the first interlayer dielectric layer 121. The second interlayer dielectric layer 123 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer dielectric layer 123 may be connected to the contact hole of the first interlayer dielectric layer 121 and the contact hole of the gate insulating layer 113.

[0112] The first connection electrode CNE1 may be disposed on the second interlayer dielectric layer 123. The first connection electrode CNE1 may connect (e.g., electrically connect) the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the first interlayer dielectric layer 121, the second interlayer dielectric layer 123, and the gate insulating layer 113 to contact the drain electrode DE of the thin film transistor TFT.

[0113] The first via layer 125 may cover the first connection electrode CNE1 and the second interlayer dielectric layer 123. The first via layer 125 may provide a flat surface throughout the underlying elements / components / structures. The first via layer 125 may include a contact hole through which the second connection electrode CNE2 passes.

[0114] The second connection electrode CNE2 may be disposed on the first via layer 125. The second connection electrode CNE2 may be inserted into a contact hole formed in the first via layer 125 to contact the first connection electrode CNE1. The second connection electrode CNE2 may connect (eg, electrically connect) the first connection electrode CNE1 with the first electrode AE1.

[0115] The second via layer 127 may cover the second connection electrode CNE2 and the first via layer 125. The second via layer 127 may include a contact hole through which the first electrode AE1 passes.

[0116] The display element layer 150 may be disposed on the thin film transistor layer 130. The display element layer 150 according to the embodiment may include a first light emitting member 150-1 and a second light emitting member 150-2. The first light emitting member 150-1 and the second light emitting member 150-2 may be sequentially stacked in a third direction (e.g., the Z-axis direction). Since the display device 10 according to the embodiment includes the first light emitting member 150-1 and the second light emitting member 150-2 including different emission parts, the emission area can be expanded while reducing the non-emission area. In this way, the display device 10 according to the embodiment can be implemented to have a high aperture ratio and a high resolution.

[0117] The first light emitting member 150 - 1 may be disposed on the second via layer 127 . The first light emitting member 150 - 1 may include a first display element ED1 , a first pixel defining layer 151 , a residual pattern layer 153 (or a first pattern layer), and a dam member 160 .

[0118] The first pixel defining layer 151 may be disposed on the second through hole layer 127 and the first electrode AE1. The first pixel defining layer 151 may overlap the first to third emission areas EA1, EA2, and EA3, respectively, so that the first to third emission areas EA1, EA2, and EA3 may be spaced apart from each other. The first pixel defining layer 151 according to the embodiment may include a first opening OP1 defining a first emission portion EA1a of the first emission area EA1, a first emission portion EA2a of the second emission area EA2, and a first emission portion EA3a of the third emission area EA3. The first opening OP1 may overlap (e.g., be aligned with) the first to third emission areas EA1, EA2, and EA3, respectively, to expose the first electrode AE1. For example, the first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3 may be defined by the first pixel defining layer 151.

[0119] In some embodiments, the first pixel defining layer 151 may include a first portion 151a and a second portion 151b. This will be described in detail later.

[0120] The first pixel defining layer 151 may include an inorganic insulating material. For example, the first pixel defining layer 151 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0121] The dam member 160 may be disposed on the first pixel defining layer 151. The dam member 160 may include a first dam layer 161 and a second dam layer 163 including different metal materials to perform different functions. The second dam layer 163 may have a tip portion TIP protruding from the first dam layer 161 toward the first emission portion EA1a of the first emission region EA1, the first emission portion EA2a of the second emission region EA2, and the first emission portion EA3a of the third emission region EA3 in a first direction (e.g., an X-axis direction).

[0122] The first display element ED1 may be disposed on the second through-hole layer 127. According to an embodiment, the first display element ED1 may include a first light emitting element ED11 overlapping the first emission portion EA1a of the first emission area EA1, a second light emitting element ED12 overlapping the first emission portion EA2a of the second emission area EA2, and a third light emitting element ED13 overlapping the first emission portion EA3a of the third emission area EA3. The first display element ED1 may include a first electrode AE1, a first display emission layer EL1, and a second electrode CE1. For example, the first light emitting element ED11 may include a first anode electrode AE11, a first emission layer EL11, and a first cathode electrode CE11, the second light emitting element ED12 may include a second anode electrode AE12, a second emission layer EL12, and a second cathode electrode CE12, and the third light emitting element ED13 may include a third anode electrode AE13, a third emission layer EL13, and a third cathode electrode CE13.

[0123] According to some embodiments, the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13 may emit light of different colors. For example, the first light emitting element ED11 may emit light of a first color (i.e., red light), the second light emitting element ED12 may emit light of a second color (i.e., green light), and the third light emitting element ED13 may emit light of a third color (i.e., blue light).

[0124] The first electrode AE1 may be disposed on the second through hole layer 127. According to an embodiment, the first electrode AE1 may be connected (e.g., electrically connected) to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2 on opposite sides in a third direction (e.g., the Z-axis direction). According to an embodiment, the first electrode AE1 may be connected (e.g., electrically connected) to the third electrode AE2 through the first bank barrier layer 161 and the second bank barrier layer 163 on one side in the third direction (e.g., the Z-axis direction).

[0125] For example, the first electrode AE1 may have a stacked structure of a material layer having a high work function and a reflective material layer, wherein the material layer having a high work function includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In 2 O 3 ), the reflective material layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. For example, the first electrode AE1 may have ITO / Mg, ITO / MgF 2, ITO / Ag, and ITO / Ag / ITO. However, the embodiment is not limited thereto.

[0126] According to an embodiment, the first electrode AE1 may include a first anode electrode AE11 overlapping the first emission portion EA1a of the first emission area EA1 and the second emission portion EA2b of the second emission area EA2, a second anode electrode AE12 overlapping the first emission portion EA2a of the second emission area EA2 and the second emission portion EA1b of the first emission area EA1, and a third anode electrode AE13 overlapping the first emission portion EA3a of the third emission area EA3 and the second emission portion EA2b of the second emission area EA2.

[0127] The first to third anode electrodes AE11 , AE12 , and AE13 may be spaced apart from each other in a first direction (eg, X-axis direction) by the first portion 151 a of the first pixel defining layer 151 .

[0128] The first display emission layer EL1 may be disposed on the first electrode AE1. The first display emission layer EL1 may be an organic emission layer made of an organic material and may be formed on the first electrode AE1 by a deposition process or a photo patterning process during a manufacturing process. When the thin film transistor TFT applies a specific voltage to the first electrode AE1 and the second electrode CE1 receives a cathode voltage, holes and electrons may move to the first display emission layer EL1 through the hole transport layer and the electron transport layer, respectively, and they may be recombined in the first display emission layer EL1 to emit light.

[0129] According to an embodiment, the first display emission layer EL1 may include a first emission layer EL11 overlapping a first emission portion EA1a of the first emission area EA1, a second emission layer EL12 overlapping a first emission portion EA2a of the second emission area EA2, and a third emission layer EL13 overlapping a first emission portion EA3a of the third emission area EA3. According to an embodiment, the first display emission layer EL1 may emit light of different colors according to the materials included in the first emission layer EL11, the second emission layer EL12, and the third emission layer EL13. For example, the first emission layer EL11 may emit red light of a first color, the second emission layer EL12 may emit green light of a second color, and the third emission layer EL13 may emit blue light of a third color. However, it should be understood that the embodiment is not limited thereto. For example, the first display emission layer EL1 may be separately disposed in each of the first emission area to the third emission area EA1, EA2, and EA3, and may be in contact with the first dam layer 161 in the non-emission area NLA.

[0130] In some embodiments, the residual pattern layer 153 (or first pattern layer) may be disposed between the first electrode AE1 and the first pixel defining layer 151 in the third direction (eg, Z-axis direction) in the non-emission area NLA. The residual pattern layer 153 will be described later.

[0131] The second electrode CE1 may be disposed on the first display emission layer EL1. The second electrode CE1 may include a transparent conductive material so that light generated in the first display emission layer EL1 may be output. The second electrode CE1 may receive a common voltage or a low-level voltage. For example, when the first electrode AE1 receives a voltage equal to the data voltage and the second electrode CE1 receives a low-level voltage, a potential difference may be formed between the first electrode AE1 and the second electrode CE1 so that the first display emission layer EL1 may emit light.

[0132] According to an embodiment, the second electrode CE1 may include a metal such as Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, Ba, or a compound thereof (eg, BaF 2 ) or a mixture thereof (eg, a mixture of Ag and Mg) or a material having a multilayer structure such as LiF / Ca or LiF / Al, a material having a low work function. The second electrode CE1 may further include a transparent metal oxide layer disposed on the material layer having a low work function.

[0133] According to an embodiment, the second electrode CE1 may include a first cathode electrode CE11 overlapping the first emission portion EA1a of the first emission region EA1, a second cathode electrode CE12 overlapping the first emission portion EA2a of the second emission region EA2, and a third cathode electrode CE13 overlapping the first emission portion EA3a of the third emission region EA3. The first cathode electrode CE11 may be disposed on the first emission layer EL11, may cover (e.g., completely cover) the first emission layer EL11, and may be in contact with the first bank layer 161. The second cathode electrode CE12 may be disposed on the second emission layer EL12, may cover (e.g., completely cover) the second emission layer EL12, and may be in contact with the first bank layer 161. The third cathode electrode CE13 may be disposed on the third emission layer EL13, may cover (e.g., completely cover) the third emission layer EL13, and may be in contact with the first bank layer 161. For example, according to an embodiment, the second electrode CE1 may be separately disposed in each of the first to third emission areas EA1 , EA2 , and EA3 , and may be connected (eg, electrically connected) to another second electrode CE1 through the first bank layer 161 .

[0134] The thin film encapsulation layer 170 according to the embodiment may include a first thin film encapsulation layer 170-1 and a second thin film encapsulation layer 170-2. The first thin film encapsulation layer 170-1 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175. The second thin film encapsulation layer 170-2 will be described later.

[0135] The first encapsulation layer 171 may be disposed on the dam member 160 and the first display element ED1. The first encapsulation layer 171 may cover along the contour formed by the dam member 160 and the first display element ED1. For example, the first encapsulation layer 171 may have different levels depending on the underlying elements / structures it covers.

[0136] The first encapsulation layer 171 may include a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3, respectively disposed in the first to third emission areas EA1, EA2, and EA3. The first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3 may be spaced apart from each other in a first direction (e.g., an X-axis direction), and the dam member 160 and the third electrode AE2 included in the second light emitting member 150-2 are interposed between the first inorganic layer 171-1, the second inorganic layer 171-2, and the third inorganic layer 171-3.

[0137] The first encapsulation layer 171 may include an inorganic material for preventing oxygen or moisture from penetrating into the first light emitting member 150-1. For example, the first encapsulation layer 171 may include aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N 2 O).

[0138] The second encapsulation layer 173 may be disposed on the first encapsulation layer 171. The second encapsulation layer 173 may overlap the first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3. The second encapsulation layer 173 may not overlap the second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3.

[0139] The second encapsulation layer 173 may include a first organic layer 173-1 overlapping the first emission portion EA1a of the first emission area EA1, a second organic layer 173-2 overlapping the first emission portion EA2a of the second emission area EA2, and a third organic layer 173-3 overlapping the first emission portion EA3a of the third emission area EA3. The first organic layer 173-1, the second organic layer 173-2, and the third organic layer 173-3 may be spaced apart from each other in a first direction (e.g., an X-axis direction), and the first encapsulation layer 171 and the dam member 160 are interposed between the first organic layer 173-1, the second organic layer 173-2, and the third organic layer 173-3.

[0140] The second encapsulation layer 173 may include an organic material and may protect the first light emitting member 150-1 from particles such as dust. For example, the second encapsulation layer 173 may provide a flat surface on the first encapsulation layer 171 having different levels. For example, the second encapsulation layer 173 may include silicone resin, acrylic resin, epoxy resin, and a mixture thereof.

[0141] The third encapsulation layer 175 may be disposed on the first encapsulation layer 171 and the second encapsulation layer 173. The third encapsulation layer 175 may cover (eg, completely cover) the first encapsulation layer 171 and the second encapsulation layer 173.

[0142] The third encapsulation layer 175 may include a first inorganic layer 175-1, a second inorganic layer 175-2, and a third inorganic layer 175-3, respectively disposed in the first to third emission areas EA1, EA2, and EA3. The first inorganic layer 175-1, the second inorganic layer 175-2, and the third inorganic layer 175-3 may be spaced apart from each other in a first direction (e.g., an X-axis direction), and the dam member 160 and the third electrode AE2 included in the second light emitting member 150-2 are interposed between the first inorganic layer 175-1, the second inorganic layer 175-2, and the third inorganic layer 175-3.

[0143] The third encapsulation layer 175 may include an inorganic material for preventing oxygen or moisture from penetrating into the first light emitting member 150-1. For example, the third encapsulation layer 175 may include aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and silicon oxynitride (Si 2 N2 O).

[0144] The second light emitting member 150-2 may be disposed on the first thin film encapsulation layer 170-1 and the second bank layer 163. The second light emitting member 150-2 may include a second display element ED2, a second pixel defining layer 155, and a residual pattern layer 157 (or a second pattern layer).

[0145] The second pixel defining layer 155 may be disposed on the third encapsulation layer 175 included in the first thin film encapsulation layer 170-1. The second pixel defining layer 155 may be disposed to overlap the first to third emission areas EA1, EA2, and EA3, respectively, so that the first to third emission areas EA1, EA2, and EA3 may be spaced apart from each other. For example, the second pixel defining layer 155 may be disposed to overlap the first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3.

[0146] The second pixel defining layer 155 according to the embodiment may include a second opening OP2 defining the second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3. The second opening OP2 may overlap (e.g., be aligned with) the first to third emission areas EA1, EA2, and EA3, respectively, to expose the third electrode AE2. For example, the second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3 may be defined by the second pixel defining layer 155.

[0147] According to an embodiment, the second pixel defining layer 155 may include a transparent inorganic insulating material. For example, the second pixel defining layer 155 may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Accordingly, even if the second pixel defining layer 155 is disposed to overlap the first display element ED1 in a third direction (e.g., Z-axis direction), the second pixel defining layer 155 according to an embodiment may transmit light output from the first display element ED1.

[0148] The second display element ED2 may be disposed on the second bank layer 163 and the third encapsulation layer 175. According to an embodiment, the second display element ED2 may include a first light emitting element ED21 overlapping the second emission portion EA1b of the first emission area EA1, a second light emitting element ED22 overlapping the second emission portion EA2b of the second emission area EA2, and a third light emitting element ED23 overlapping the second emission portion EA3b of the third emission area EA3. The second display element ED2 may include a third electrode AE2, a second display emission layer EL2, and a common electrode CE2. For example, according to an embodiment, the first light emitting element ED21 may include a first anode electrode AE21, a first emission layer EL21, and a common electrode CE2, the second light emitting element ED22 may include a second anode electrode AE22, a second emission layer EL22, and a common electrode CE2, and the third light emitting element ED23 may include a third anode electrode AE23, a third emission layer EL23, and a common electrode CE2.

[0149] According to some embodiments, the first light emitting element ED21, the second light emitting element ED22, and the third light emitting element ED23 may emit light of different colors. For example, the first light emitting element ED21 may emit light of a first color (e.g., red light), the second light emitting element ED22 may emit light of a second color (e.g., green light), and the third light emitting element ED23 may emit light of a third color (e.g., blue light).

[0150] The third electrode AE2 may be disposed on the second bank layer 163 and the third encapsulation layer 175. The third electrode AE2 may contact the second bank layer 163 and the third encapsulation layer 175. According to an embodiment, the third electrode AE2 may be connected (e.g., electrically connected) to the second bank layer 163, the first bank layer 161, and the first electrode AE1 in a third direction (e.g., Z-axis direction).

[0151] For example, the third electrode AE2 may have a stacked structure of a material layer containing a high work function and a reflective material layer, wherein the material layer containing a high work function includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In 2 O 3 ), the reflective material layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. For example, the third electrode AE2 may have ITO / Mg, ITO / MgF 2 , ITO / Ag, and ITO / Ag / ITO. However, the embodiment is not limited thereto.

[0152] According to an embodiment, the third electrode AE2 may include a first anode electrode AE21 overlapping the second emission portion EA1b of the first emission area EA1, a second anode electrode AE22 overlapping the second emission portion EA2b of the second emission area EA2, and a third anode electrode AE23 overlapping the second emission portion EA3b of the third emission area EA3.

[0153] The first anode electrode AE21 , the second anode electrode AE22 , and the third anode electrode AE23 may be spaced apart from each other in the first direction (eg, the X-axis direction) by the second pixel defining layer 155 .

[0154] The second display emission layer EL2 may be disposed on the third electrode AE2. The second display emission layer EL2 may be an organic emission layer made of an organic material and may be formed on the third electrode AE2 by a deposition process or a photo patterning process during a manufacturing process. When the thin film transistor TFT applies a specific voltage to the third electrode AE2 and the common electrode CE2 receives a common voltage, holes and electrons may move to the second display emission layer EL2 through the hole transport layer and the electron transport layer, respectively, and they may be recombined in the second display emission layer EL2 to emit light.

[0155] According to an embodiment, the second display emission layer EL2 may include a first emission layer EL21 overlapping the second emission portion EA1b of the first emission area EA1, a second emission layer EL22 overlapping the second emission portion EA2b of the second emission area EA2, and a third emission layer EL23 overlapping the second emission portion EA3b of the third emission area EA3. According to an embodiment, the second display emission layer EL2 may emit light of different colors according to the materials included in the first emission layer EL21, the second emission layer EL22, and the third emission layer EL23. For example, the first emission layer EL21 may emit red light of a first color, the second emission layer EL22 may emit green light of a second color, and the third emission layer EL23 may emit blue light of a third color. However, it should be understood that the embodiment is not limited thereto.

[0156] In some embodiments, a residual pattern layer 157 (or a second pattern layer) may be disposed between the third electrode AE2 and the second pixel defining layer 155 in the third direction (eg, Z-axis direction) in the non-emission area NLA. The residual pattern layer 157 will be described later.

[0157] The common electrode CE2 may be disposed on the entire surface of the second display emission layer EL2 and the second pixel defining layer 155. For example, the common electrode CE2 may be a common layer disposed across the first emission area to the third emission area EA1, EA2, and EA3 and the non-emission area NLA. The common electrode CE2 may include a transparent conductive material so that light generated in the second display emission layer EL2 may be output.

[0158] According to an embodiment, the common electrode CE2 may include a metal such as Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, and Ba, or a compound thereof (eg, BaF 2 ) or a mixture thereof (eg, a mixture of Ag and Mg) or a material having a multilayer structure such as LiF / Ca or LiF / Al, a material layer having a low work function. The common electrode CE2 may further include a transparent metal oxide layer disposed on the material layer having a low work function.

[0159] The second thin film encapsulation layer 170 - 2 may be disposed on the second light emitting member 150 - 2 . The second thin film encapsulation layer 170 - 2 may include a first encapsulation layer 177 , a second encapsulation layer 178 , and a third encapsulation layer 179 .

[0160] The first encapsulation layer 177 may be disposed (e.g., completely disposed) on the common electrode CE2. The first encapsulation layer 177 may include an inorganic material and may cover (e.g., completely cover) the common electrode CE2. The first encapsulation layer 177 may prevent oxygen or moisture from penetrating into the second light-emitting member 150-2. For example, the second encapsulation layer 178 may be disposed (e.g., completely disposed) on the first encapsulation layer 177. The second encapsulation layer 178 may protect the second light-emitting member 150-2 from particles such as dust, and may provide a flat surface throughout the first encapsulation layer 177 having different levels. For example, the third encapsulation layer 179 may be formed (e.g., completely formed) on the second encapsulation layer 178. The third encapsulation layer 179 may include an inorganic material and may cover (e.g., completely cover) the second encapsulation layer 178.

[0161] For example, the first encapsulation layer 177 and the third encapsulation layer 179 may include at least one of the following materials: aluminum oxide (Al 2 O 3 ), titanium oxide (Ti 2 O 3 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4) and silicon oxynitride (Si 2 N 2 O). For example, the second encapsulation layer 178 may include silicone resin, acrylic resin, epoxy resin, and a mixture thereof.

[0162] Figure 7 yes Figure 6 FIG. 1 is an enlarged schematic cross-sectional view of a first emission portion EA1a of a first emission area EA1.

[0163] refer to Figure 7 , the first emission portion EA1a of the first emission area EA1 may be adjacent to the non-emission area NLA in the first direction (e.g., the X-axis direction), and the first emission portion EA1a of the first emission area EA1 may be spaced apart from the second emission portion EA2b of the second emission area EA2 on the opposite side in the first direction (e.g., the X-axis direction), and the non-emission area NLA is interposed between the first emission portion EA1a of the first emission area EA1 and the second emission portion EA2b of the second emission area EA2. For example, the first emission portion EA1a of the first emission area EA1 may be spaced apart from the second emission portion EA1b of the first emission area EA1 on one side in the first direction (e.g., the X-axis direction), and the non-emission area NLA is interposed between the first emission portion EA1a of the first emission area EA1 and the second emission portion EA1b of the first emission area EA1.

[0164] As described above, the first pixel defining layer 151 according to the embodiment may include the first opening OP1 defining the first emission portion EA1a of the first emission area EA1, and the first opening OP1 may expose a portion of the first display element ED1.

[0165] According to an embodiment, the first pixel defining layer 151 may include a first portion 151a and a second portion 151b. The first portion 151a and the second portion 151b may expose a portion of the first display element ED1 and may be spaced apart from each other in a first direction (e.g., an X-axis direction). For example, the first portion 151a may be disposed on the second through-hole layer 127, and the second portion 151b may be spaced apart from the second through-hole layer 127 and disposed on the first anode electrode AE11.

[0166] The first portion 151a and the second portion 151b of the first pixel defining layer 151 may be formed as a single body during the manufacturing process of the display device 10 and then may be separated by a light patterning process. Accordingly, the first portion 151a and the second portion 151b may include the same material. The manufacturing process will be described later.

[0167] According to an embodiment, during a process of manufacturing the first display element ED1, the display device 10 may include a sacrificial layer SFL (see Fig.10 ). The sacrificial layer SFL may be disposed between the first pixel defining layer 151 and the first electrode AE1, and may then be partially removed by a subsequent wet etching process. The portion of the sacrificial layer SFL that is not removed may remain as a residual pattern layer 153 (or a first pattern layer) between the first pixel defining layer 151 and the first electrode AE1. The residual pattern layer 153 may overlap the non-emission area NLA in a third direction (e.g., the Z-axis direction), and may be disposed in contact with the first display emission layer EL1 in a first direction (e.g., the X-axis direction).

[0168] In some embodiments, the residual pattern layer 153 may be surrounded by (e.g., completely surrounded by) the first pixel defining layer 151, the first display emission layer EL1, and the first electrode AE1. The residual pattern layer 153 may contact the first pixel defining layer 151, the first display emission layer EL1, and the first electrode AE1. For example, the residual pattern layer 153 may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin oxide (IZO), and the like.

[0169] According to an embodiment, the first bank layer 161 may be disposed on the first pixel defining layer 151. The first bank layer 161 may include a metal having high conductivity. For example, the first bank layer 161 may include aluminum (Al).

[0170] According to some embodiments, the first bank layer 161 may include a side surface 1c of the first emission portion EA1a facing the first emission area EA1. The side surface 1c of the first bank layer 161 may include a structure that is recessed toward the non-emission area NLA than the first pixel defining layer 151. The side surface 1c of the first bank layer 161 may be in contact with the first emission layer EL11, the first cathode electrode CE11, and the first inorganic layer 171-1. As described above, the second electrode CE1 according to the embodiment may be separately disposed in each of the first to third emission areas EA1, EA2, and EA3. The separated second electrode CE1 may be connected (e.g., electrically connected) to another second electrode CE1 through the first bank layer 161.

[0171] For example, the first emission layer EL11 and the first cathode electrode CE11 may contact the side surface 1c of the first bank layer 161 in the non-emission area NLA. For example, the first emission layer EL11 and the first cathode electrode CE11 may contact the side surface 1c of the first bank layer 161 below the tip portion TIP of the second bank layer 163. According to an embodiment, the first emission layer EL11 may be covered (e.g., completely covered) by the first cathode electrode CE11.

[0172] The second bank layer 163 may be disposed on the first bank layer 161. The second bank layer 163 may include a material having a lower etching rate than the first bank layer 161, and, for example, may include titanium (Ti).

[0173] According to some embodiments, the second bank layer 163 may include a side surface 3c facing the first emission portion EA1a of the first emission area EA1. The side surface 3c of the second bank layer 163 may have a shape protruding toward the first emission portion EA1a than the side surface 1c of the first bank layer 161. For example, the side surface 1c of the first bank layer 161 may have a shape concave from the side surface 3c of the second bank layer 163. Accordingly, the second bank layer 163 may include a tip portion TIP protruding toward the first emission portion EA1a, and accordingly, an undercut portion may be formed between the tip portion TIP of the second bank layer 163 and the side surface 1c of the first bank layer 161.

[0174] According to some embodiments, the thickness of the second bank barrier layer 163 in the third direction (eg, the Z-axis direction) may be smaller than the thickness of the first bank barrier layer 161 in the third direction (eg, the Z-axis direction).

[0175] According to an embodiment, the first inorganic layer 171-1 included in the first encapsulation layer 171 may cover (e.g., completely cover) the first cathode electrode CE11 in the first emission portion EA1a of the first emission area EA1. The first inorganic layer 171-1 may cover (e.g., completely cover) the side surface 1c of the first bank layer 161 and the tip portion TIP of the second bank layer 163 in the non-emission area NLA. The first inorganic layer 171-1 may be in contact with the side surface 1c of the first bank layer 161 and the tip portion TIP of the second bank layer 163.

[0176] For example, according to an embodiment, the first inorganic layer 171-1 may cover (e.g., completely cover) the second dam layer 163 in the second emission portion EA1b of the first emission area EA1 and the second emission portion EA2b of the second emission area EA2, and the first inorganic layer 171-1 may be in contact with the second dam layer 163.

[0177] According to an embodiment, the first organic layer 173-1 included in the second encapsulation layer 173 may be disposed on the first inorganic layer 171-1 in the first emission portion EA1a of the first emission area EA1. For example, the first organic layer 173-1 may not overlap with the second emission portion EA1b of the first emission area EA1 or the second emission portion EA2b of the second emission area EA2. The first inorganic layer 175-1 included in the third encapsulation layer 175 may be disposed on the first organic layer 173-1, and the first organic layer 173-1 may be surrounded by the first encapsulation layer 171 and the third encapsulation layer 175 (e.g., completely surrounded).

[0178] According to an embodiment, the second display element ED2 may be disposed on the third encapsulation layer 175. As described above, the second display element ED2 may overlap the second emission portion EA1b of the first emission area EA1 and the second emission portion EA2b of the second emission area EA2, but the second display element ED2 may not overlap the first emission portion EA1a of the first emission area EA1.

[0179] According to an embodiment, during a process of manufacturing the second display element ED2, the display device 10 may include a sacrificial layer SFL (see Fig.21 ). The sacrificial layer SFL may be disposed between the second pixel defining layer 155 and the third electrode AE2, and may then be partially removed by a subsequent wet etching process. The portion of the sacrificial layer SFL that is not removed may remain as a residual pattern layer 157 (or a second pattern layer) between the second pixel defining layer 155 and the third electrode AE2. The residual pattern layer 157 may overlap the non-emission area NLA in a third direction (e.g., the Z-axis direction), and may be disposed in contact with the second display emission layer EL2 in a first direction (e.g., the X-axis direction).

[0180] According to some embodiments, the residual pattern layer 157 may be surrounded by (e.g., completely surrounded by) the second pixel defining layer 155, the second display emission layer EL2, and the third electrode AE2. The residual pattern layer 157 may contact the second pixel defining layer 155, the second display emission layer EL2, and the third electrode AE2. For example, the residual pattern layer 157 may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin oxide (IZO), and the like.

[0181] The second pixel defining layer 155 may be disposed on the first inorganic layer 175-1 in the first emission portion EA1a of the first emission area EA1. The second pixel defining layer 155 may define the second emission portion EA1b of the first emission area EA1 and the second emission portion EA2b of the second emission area EA2. The second pixel defining layer 155 may separate the first anode electrode AE21 from the second anode electrode AE22 in a first direction (e.g., an X-axis direction).

[0182] According to an embodiment, the second pixel defining layer 155 may overlap the first display element ED1 and the first thin film encapsulation layer 170 - 1 in a third direction (eg, Z-axis direction). For convenience of description, other redundant descriptions will be omitted.

[0183] Although the first emission portion EA1a and the periphery of the first emission area EA1 have been described in the accompanying drawings for ease of explanation, it should be understood that the first emission portion EA2a and the periphery of the second emission area EA2 and the first emission portion EA3a and the periphery of the third emission area EA3 may include similar structures and features as the first emission portion EA1a and the periphery of the first emission area EA1.

[0184] Figure 8 yes Figure 6 FIG. 1 is an enlarged schematic cross-sectional view of a second emission portion EA1b of a first emission area EA1.

[0185] refer to Figure 8 , the second emission portion EA1b of the first emission area EA1 may be adjacent to the non-emission area NLA in the first direction (e.g., the X-axis direction), and the second emission portion EA1b of the first emission area EA1 may be spaced apart from the first emission portion EA1a of the first emission area EA1 on the opposite side in the first direction (e.g., the X-axis direction), and the non-emission area NLA is interposed between the second emission portion EA1b of the first emission area EA1 and the first emission portion EA1a of the first emission area EA1. For example, the second emission portion EA1b of the first emission area EA1 may be spaced apart from the first emission portion EA2a of the second emission area EA2 on one side in the first direction (e.g., the X-axis direction), and the non-emission area NLA is interposed between the second emission portion EA1b of the first emission area EA1 and the first emission portion EA2a of the second emission area EA2.

[0186] According to an embodiment, the first anode electrode AE11 and the second anode electrode AE12 may be spaced apart from each other in a first direction (e.g., X-axis direction) by the first portion 151a of the first pixel defining layer 151. For example, the first anode electrode AE11 may be disposed in the first emission portion EA1a of the first emission area EA1, and the second anode electrode AE12 may be disposed in the second emission portion EA1b of the first emission area EA1 and the first emission portion EA2a of the second emission area EA2.

[0187] According to some embodiments, the first anode electrode AE11 disposed in the first emission portion EA1a of the first emission area EA1 and the second anode electrode AE12 disposed in the first emission portion EA2a of the second emission area EA2 may not contact the first dam layer 161, while the second anode electrode AE12 in the second emission portion EA1b of the first emission area EA1 may contact the first dam layer 161.

[0188] According to an embodiment, the dam member 160 may include a first portion 160a, a second portion 160b, and a third portion 160c. The first portion 160a, the second portion 160b, and the third portion 160c of the dam member 160 may be spaced apart from each other in a first direction (e.g., an X-axis direction), and the first encapsulation layer 171 is interposed between the first portion 160a, the second portion 160b, and the third portion 160c of the dam member 160. During the process of manufacturing the display device 10, the first portion 160a, the second portion 160b, and the third portion 160c of the dam member 160 may be formed as a single body, and then may be separated into shapes as shown in the drawings by a light patterning process. Accordingly, the first portion 160a, the second portion 160b, and the third portion 160c of the dam member 160 may include the same material. The manufacturing process will be described later.

[0189] In some embodiments, the first portion 160 a of the dam member 160 may include a first portion 161 a of the first dam layer 161 and a first portion 163 a of the second dam layer 163 .

[0190] The first portion 161a of the first bank layer 161 may be disposed on the first portion 151a of the first pixel defining layer 151. The first portion 161a may be disposed in contact with the first portion 151a of the first pixel defining layer 151. The first portion 161a may be in contact with the first emission layer EL11 and the first cathode electrode CE11 in the non-emission area NLA. The first portion 161a may be in contact with the first inorganic layer 171-1 in the second emission portion EA1b of the first emission area EA1. Accordingly, the first portion 161a of the first bank layer 161 may be in contact with the first emission layer EL11, the first cathode electrode CE11, the first inorganic layer 171-1, and the first portion 151a of the first pixel defining layer 151, and may be surrounded by the first emission layer EL11, the first cathode electrode CE11, the first inorganic layer 171-1, the second bank layer 163, and the first portion 151a of the first pixel defining layer 151.

[0191] The first portion 163a of the second bank layer 163 may be disposed on the first portion 161a of the first bank layer 161. The first portion 163a of the second bank layer 163 may have a tip portion TIP protruding toward the first emission portion EA1a of the first emission region EA1 more than the first portion 161a of the first bank layer 161. The first portion 163a of the second bank layer 163 may be surrounded by the first inorganic layer 171-1.

[0192] In some embodiments, the second portion 160 b of the dam member 160 may include a second portion 161 b of the first dam layer 161 and a second portion 163 b of the second dam layer 163 .

[0193] The second portion 161b of the first bank layer 161 may be disposed on the second anode electrode AE12. The second portion 161b may contact the second anode electrode AE12, and thus, the second portion 161b may be connected (eg, electrically connected) to the second anode electrode AE12.

[0194] The second portion 161b of the first bank layer 161 may be spaced apart from the first portion 161a in the first direction (e.g., the X-axis direction), and the first inorganic layer 171-1 is interposed between the second portion 161b of the first bank layer 161 and the first portion 161a. The second portion 161b may contact the first inorganic layer 171-1 on the opposite side in the first direction (e.g., the X-axis direction). The second portion 161b may contact the second inorganic layer 171-2 on one side in the first direction (e.g., the X-axis direction). For example, the first inorganic layer 171-1 and the second inorganic layer 171-2 may be separated from each other by the second portion 161b of the first bank layer 161.

[0195] The second portion 163b of the second bank layer 163 may be disposed on the second portion 161b of the first bank layer 161. The second portion 163b may contact the first anode electrode AE21 on one side in the third direction (e.g., the Z-axis direction), and may contact the second portion 161b of the first bank layer 161 on the opposite side in the third direction (e.g., the Z-axis direction). Accordingly, the second anode electrode AE12 and the first anode electrode AE21 may be connected (e.g., electrically connected) to each other through the second portion 160b of the bank member 160.

[0196] For example, the second portion 163b of the second bank layer 163 may contact the second inorganic layer 171-2 on one side in the first direction (eg, X-axis direction) and may contact the first inorganic layer 171-1 on the opposite side in the first direction (eg, X-axis direction).

[0197] In some embodiments, the third portion 160 c of the dam member 160 may include a third portion 161 c of the first dam layer 161 and a third portion 163 c of the second dam layer 163 .

[0198] The third portion 161c of the first bank layer 161 may be disposed on the second portion 151b of the first pixel defining layer 151. For example, the third portion 161c may be disposed to overlap the second anode electrode AE12 in a third direction (eg, Z-axis direction) but may not contact the second anode electrode AE12.

[0199] The third portion 161c of the first bank layer 161 may contact the second emission layer EL12 and the second cathode electrode CE12 in the non-emission area NLA, and may contact the second inorganic layer 171-2 in the second emission portion EA1b of the first emission area EA1. Accordingly, the third portion 161c may contact the second emission layer EL12, the second cathode electrode CE12, the second inorganic layer 171-2, and the second portion 151b of the first pixel defining layer 151, and may be surrounded by the second emission layer EL12, the second cathode electrode CE12, the second inorganic layer 171-2, the second bank layer 163, and the second portion 151b of the first pixel defining layer 151.

[0200] The third portion 163c of the second bank layer 163 may be disposed on the third portion 161c of the first bank layer 161. The third portion 163c of the second bank layer 163 may have a tip portion TIP protruding toward the first emission portion EA2a of the second emission region EA2 than the third portion 161c of the first bank layer 161. The third portion 163c of the second bank layer 163 may be surrounded by the second inorganic layer 171-2.

[0201] According to an embodiment, the first anode electrode AE21 and the first emission layer EL21 included in the second display element ED2 may overlap the first pixel defining layer 151 in a third direction (e.g., Z-axis direction), and the first anode electrode AE21 and the first emission layer EL21 included in the second display element ED2 may overlap the first portion 160a, the second portion 160b, and the third portion 160c of the embankment member 160 in the third direction (e.g., Z-axis direction). For convenience of description, other redundant descriptions will be omitted.

[0202] Although the second emission portion EA1b and the periphery of the first emission area EA1 have been described in the accompanying drawings for ease of explanation, it should be understood that the second emission portion EA2b and the periphery of the second emission area EA2 and the second emission portion EA3b and the periphery of the third emission area EA3 may include similar structures and features as the second emission portion EA1b and the periphery of the first emission area EA1.

[0203] Fig. 9 It is shown Figure 6 Schematic plan view of the layout of the first pixel defining layer 151 and the second pixel defining layer 155 in FIG.

[0204] refer to Fig. 9 , in a plan view, the first opening OP1 may be defined by the first pixel defining layer 151. In a plan view, the first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3 may be defined by the first opening OP1. For example, in a plan view, the first pixel defining layer 151 may surround (e.g., completely surround) the first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3. For example, in a plan view, the first pixel defining layer 151 may be in a grid pattern to expose the first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3.

[0205] For example, in a plan view, the second opening OP2 may be defined by the second pixel defining layer 155. In a plan view, the second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3 may be defined by the second opening OP2. For example, in a plan view, the second pixel defining layer 155 may surround (e.g., completely surround) the second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3. For example, in a plan view, the second pixel defining layer 155 may be in a grid pattern to expose the second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3.

[0206] like Fig. 9 As shown in , a portion of the first pixel defining layer 151 and a portion of the second pixel defining layer 155 may overlap each other in a third direction (e.g., Z-axis direction). A portion where the first pixel defining layer 151 and the second pixel defining layer 155 overlap each other in a third direction (e.g., Z-axis direction) in a plan view (or when viewed from the top) may be defined as a non-emission area NLA.

[0207] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 and Fig.23 It is used for graphic manufacturing Figure 6 Schematic cross-sectional view of a method for displaying an element layer 150 in FIG. Figures 10 to 23 1 is a schematic cross-sectional view showing a process of manufacturing the first light emitting member 150 - 1 and the second light emitting member 150 - 2 of the display element layer 150 .

[0208] refer to Fig.10, a first electrode AE1 may be formed on the thin film transistor layer 130, and a sacrificial layer SFL may be formed on the first electrode AE1. The first electrode AE1 may include a first anode electrode AE11, a second anode electrode AE12, and a third anode electrode AE13. The first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13 may be spaced apart from each other on the thin film transistor layer 130. The first anode electrode AE11 may be disposed across the first emission portion EA1a of the first emission area EA1 and the second emission portion EA2b of the second emission area EA2. The second anode electrode AE12 may be disposed across the second emission portion EA1b of the first emission area EA1 and the first emission portion EA2a of the second emission area EA2. The third anode electrode AE13 may be disposed across the first emission portion EA3a of the third emission area EA3 and the second emission portion EA2b of the second emission area EA2. For example, the thin film transistor layer 130 may be disposed on the substrate 110, and reference has been made above to Figure 6 The structure of the thin film transistor layer 130 is described. For convenience of description, the detailed description will be omitted.

[0209] For example, the first pixel defining material layer 151L may be formed to cover the first anode electrode AE11, the second anode electrode AE12, the third anode electrode AE13, and the sacrificial layer SFL. The first pixel defining material layer 151L may cover (e.g., completely cover) the sacrificial layer SFL disposed on each of the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13, and may overlap with each of the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13, so that the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13 may be spaced apart from each other.

[0210] The sacrificial layer SFL may prevent the upper surface of the first electrode AE1 from contacting the first pixel defining layer 151. The sacrificial layer SFL may include an oxide semiconductor. For example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin oxide (IZO), etc.

[0211] For example, refer to Fig.11 , a first dam material layer 161L may be formed to cover (eg, completely cover) the first electrode AE1 and the first pixel defining material layer 151L, and a second dam material layer 163L may be formed (eg, completely formed) on the first dam material layer 161L.

[0212] For example, refer to Fig.12, a photoresist PR may be formed on the second bank material layer 163L, and the first and second bank material layers 161L and 163L may be partially etched using the photoresist PR as a mask (first etching). The photoresist PR may be separated on the bank material layers 161L and 163L.

[0213] For example, the first (1st) etching process may be performed by dry etching. Since the first etching (1st etching) process is performed by dry etching, the first pixel defining material layer 151L including an inorganic material and the first and second bank material layers 161L and 163L including different metal materials may be etched.

[0214] Through this process, the first hole HOL1 may be formed to overlap the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13, respectively, and the second hole HOL2 may be formed to overlap portions of the second bank material layer 161L and the second bank material layer 163L. For example, through this process, the first pixel defining material layer 151L may be divided into the first portion 151a and the second portion 151b.

[0215] For example, refer to Fig.13 A second etching process (second etching) may be performed to form Figure 6 The tip portion TIP of the bank member 160 shown in FIG. 1 and the sacrificial layer SFL is partially removed. For example, the second etching process may be performed according to a wet etching process.

[0216] Through this process, the sacrificial layer SFL disposed on the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13 may be partially removed. It should be noted that the sacrificial layer SFL may not be completely removed, but may remain in the space between the first pixel defining layer 151 and the first electrode AE1 in the third direction (e.g., the Z-axis direction) as a residual pattern layer 153 (or a first pattern layer).

[0217] According to an embodiment, the first bank material layer 161L may include a material having an etching rate faster than that of the second bank material layer 163L. Accordingly, by performing the etching process, a side surface 3c of the second bank material layer 163L may protrude from a side surface 1c of the first bank material layer 161L, and the first bank layer 161 and the second bank layer 163 may have Figure 6 For example, the second bank barrier layer 163 may have a tip portion TIP protruding from the side surface 1c of the first bank barrier layer 161 toward the first opening OP1, and an undercut portion may be formed between the tip portion TIP of the second bank barrier layer 163 and the side surface 1c of the first bank barrier layer 161.

[0218] For example, refer to Fig.14 , a first display emission layer EL1 may be deposited on each of the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13. The first display emission layer EL1 may include a first emission layer EL11 in contact with the first anode electrode AE11, a second emission layer EL12 in contact with the second anode electrode AE12, and a third emission layer EL13 in contact with the third anode electrode AE13. The first display emission layer EL1 may be formed by a thermal evaporation process or a photolithography process to overlap each of the first anode electrode AE11, the second anode electrode AE12, and the third anode electrode AE13.

[0219] For example, the second electrode CE1 may be deposited on each of the first emission layer EL11, the second emission layer EL12, and the third emission layer EL13. The second electrode CE1 may include a first cathode electrode CE11 in contact with the first emission layer EL11, a second cathode electrode CE12 in contact with the second emission layer EL12, and a third cathode electrode CE13 in contact with the third emission layer EL13. The second electrode CE1 may be formed on each of the first emission layer EL11, the second emission layer EL12, and the third emission layer EL13 by a thermal evaporation process or a light pattern (photolithography) process. Through this process, the first display element ED1 included in the first light emitting member 150-1 may be formed.

[0220] As described above, the first display emission layer EL1 and the second electrode CE1 may contact the side surface 1 c of the first bank layer 161 , and the second electrode CE1 may be connected (eg, electrically connected) to another second electrode CE1 through the first bank layer 161 .

[0221] For example, refer to Fig.15 , a first encapsulation material layer 171L may be formed to cover (e.g., completely cover) the second electrode CE1 and the dam member 160. The first encapsulation material layer 171L may include an inorganic material, and may cover along a contour formed by the second electrode CE1 and the dam member 160. Accordingly, the first encapsulation material layer 171L may include different levels.

[0222] According to an embodiment, through this process, the first light emitting element ED11 , the second light emitting element ED12 , and the third light emitting element ED13 may be covered (eg, completely covered) by the first encapsulation layer 171 .

[0223] For example, refer to Fig.16, a second encapsulation layer 173 may be coated to provide a flat surface over the first encapsulation material layer 171L overlapping each of the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13. The second encapsulation layer 173 may overlap each of the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13 and be spaced apart from each other. The second encapsulation layer 173 may include a first organic layer 173-1 overlapping the first light emitting element ED11, a second organic layer 173-2 overlapping the second light emitting element ED12, and a third organic layer 173-3 overlapping the third light emitting element ED13.

[0224] refer to Fig.17 and Fig.18 , a sacrificial layer SFL may be formed (e.g., completely formed) on the first encapsulation material layer 171L and the second encapsulation layer 173, and a photoresist PR may be formed on the sacrificial layer SFL so that the photoresist PR may overlap with the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13. According to an embodiment, the sacrificial layer SFL may be formed with the above reference Figures 10 to 12 The sacrificial layer SFL is described to include the same material. For example, a third etching (3rd etching) process may be performed to etch the sacrificial layer SFL and a portion of the first encapsulation material layer 171L using the photoresist PR as a mask. For example, the third etching process may be a dry etching process.

[0225] Through this process, Fig.18 As shown in , the first encapsulation material layer 171L may be formed into a first inorganic layer 171-1, a second inorganic layer 171-2, and a third inorganic layer 171-3 that are spaced apart from each other. The first inorganic layer 171-1 may cover (e.g., completely cover) the first light emitting element ED11, the second inorganic layer 171-2 may cover (e.g., completely cover) the second light emitting element ED12, and the third inorganic layer 171-3 may cover (e.g., completely cover) the third light emitting element ED13.

[0226] For example, through this process, the second bank layer 163 of the bank member 160 that does not contact the first, second, and third light emitting elements ED11, ED12, and ED13 may be exposed.

[0227] refer to Fig.19 and Fig. 20, a third encapsulation material layer 175L and a sacrificial layer SFL may be formed (e.g., completely formed) on the first encapsulation material layer 171L and the second bank barrier layer 163, and a photoresist PR may be formed on the sacrificial layer SFL so that the photoresist PR may overlap each of the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13. According to an embodiment, the sacrificial layer SFL may overlap with the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13. Figures 10 to 12 The sacrificial layer SFL is described to include the same material. For example, a fourth etching (4th etching) process may be performed to etch the sacrificial layer SFL and a portion of the third encapsulation material layer 175L using the photoresist PR as a mask. For example, the fourth etching process may be a dry etching process.

[0228] Through this process, the third encapsulation material layer 175L may be formed as Fig. 20 For example, the third encapsulation layer 175 may be formed as a first inorganic layer 175-1, a second inorganic layer 175-2, and a third inorganic layer 175-3 spaced apart from each other to overlap the first light emitting element ED11, the second light emitting element ED12, and the third light emitting element ED13, respectively.

[0229] For example, through this process, the second bank layer 163 of the bank member 160 that does not contact the first, second, and third light emitting elements ED11, ED12, and ED13 may be exposed.

[0230] For example, refer to Fig.21 , a third electrode AE2 may be formed to contact the second bank barrier layer 163 exposed in the previous process. The third electrode AE2 may include a first anode electrode AE21, a second anode electrode AE22, and a third anode electrode AE23. The first anode electrode AE21, the second anode electrode AE22, and the third anode electrode AE23 may be spaced apart from each other on the third encapsulation layer 175.

[0231] The first anode electrode AE21 of the third electrode AE2 may be arranged to overlap with (e.g., be aligned with) the second emission portion EA1b of the first emission region EA1, the second anode electrode AE22 may be arranged to overlap with (e.g., be aligned with) the second emission portion EA2b of the second emission region EA2, and the third anode electrode AE23 may be arranged to overlap with (e.g., be aligned with) the second emission portion EA3b of the third emission region EA3.

[0232] In this process, each of the first, second, and third anode electrodes AE21, AE22, and AE23 contacts the second bank layer 163 so that the third electrode AE2 may be connected (eg, electrically connected) to the second bank layer 163, the first bank layer 161, and the first electrode AE1.

[0233] For example, a sacrificial layer SFL may be formed on each of the first anode electrode AE21, the second anode electrode AE22, and the third anode electrode AE23, and a second pixel defining layer 155 may be formed to partially cover each of the first anode electrode AE21, the second anode electrode AE22, and the third anode electrode AE23. The second pixel defining layer 155 may separate and insulate the first anode electrode AE21, the second anode electrode AE22, and the third anode electrode AE23 from each other. The sacrificial layer SFL used in this process may be the same as that described above with reference to Figures 10 to 12 The described sacrificial layer SFL includes the same material.

[0234] refer to Fig. 22 , a fifth etching process (5th etching) may be performed to remove the sacrificial layer SFL disposed on each of the first anode electrode AE21, the second anode electrode AE22, and the third anode electrode AE23 using the second pixel defining layer 155 as a mask. As an example, the fifth etching process may be performed according to a wet etching process.

[0235] Through this process, a portion of the sacrificial layer SFL disposed on each of the first anode electrode AE21, the second anode electrode AE22, and the third anode electrode AE23 may be removed. The portion of the sacrificial layer SFL that remains without being removed may be provided as a residual pattern layer 157 (or a second pattern layer) between the third electrode AE2 and the second pixel defining layer 155.

[0236] For example, refer to Fig.23 , the common electrode CE2 may be formed to cover (eg, completely cover) the second display emission layer EL2 and the second pixel defining layer 155 included in the second display element ED2, and the second thin film encapsulation layer 170-2 may be formed (eg, completely formed) on the common electrode CE2. In this way, the Figure 6 The display element layer 150 shown in FIG. The first emission portion EA1a of the first emission area EA1, the first emission portion EA2a of the second emission area EA2, and the first emission portion EA3a of the third emission area EA3 may be defined by the first pixel defining layer 151. The second emission portion EA1b of the first emission area EA1, the second emission portion EA2b of the second emission area EA2, and the second emission portion EA3b of the third emission area EA3 may be defined by the second pixel defining layer 155.

[0237] like Fig.23 As shown in , the display device 10 according to the embodiment includes a first light emitting member 150-1 and a second light emitting member 150-2 including different emission areas, so that the emission area can be expanded while the non-emission area can be reduced. In this way, the display device 10 according to the embodiment can be implemented to have a high aperture ratio and a high resolution.

[0238] Embodiments have been disclosed herein, and although terms are used, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art, features, characteristics, and / or elements described in conjunction with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless specifically indicated otherwise. Accordingly, one of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: A substrate, comprising: an emission region including a first emission portion and a second emission portion; and a non-emission region disposed between the first emission portion and the second emission portion; a first light emitting member including a first display element disposed on the first emitting portion of the substrate; A first thin film encapsulation layer is disposed on the first light emitting component; and a second light emitting member disposed on the first thin film encapsulation layer and including a second display element overlapping the second emission portion, The first light emitting member further comprises: a first pixel defining layer defining a first opening; and a dam member disposed on the first pixel defining layer and comprising a first dam layer and a second dam layer. The second display element overlaps the first pixel defining layer and the dam member in a direction perpendicular to an upper surface of the substrate, and The second display element contacts the second bank layer in a direction toward the substrate.

2. The display device according to claim 1, wherein: The first display element comprises: a first electrode; A first display emission layer, disposed on the first electrode; and The second electrode is disposed on the first display emission layer, wherein: The first display emission layer and the second electrode are in contact with a side surface of the first bank layer facing the first emission portion, and The second electrode is electrically connected to the first bank layer.

3. The display device according to claim 2, wherein: The second bank layer includes a tip portion protruding from the side surface of the first bank layer toward the first emission portion, and The side surface of the first bank layer and the tip portion of the second bank layer form an undercut portion.

4. The display device according to claim 3, wherein: A first pattern layer is disposed between the first electrode and the first pixel defining layer in the non-emission region in the direction perpendicular to the upper surface of the substrate, and The first pattern layer contacts the first display emission layer.

5. The display device according to claim 4, wherein: The first opening defines the first emitting portion.

6. The display device according to any one of claims 1 to 5, wherein: The first thin film encapsulation layer includes: a first encapsulation layer in contact with the first display element and the dam member; a second encapsulation layer including an organic material and disposed on the first encapsulation layer; and a third encapsulation layer including an inorganic material and disposed on the second encapsulation layer, and The second encapsulation layer is completely surrounded by the first encapsulation layer and the third encapsulation layer in the first emission portion.

7. The display device according to claim 6, wherein: The second encapsulation layer does not overlap the second emitting portion.

8. The display device according to claim 2, wherein: The second light emitting member further includes a second pixel defining layer overlapping the first emission portion and defining a second opening, and The second pixel defining layer overlaps the first display element in the direction perpendicular to the upper surface of the substrate.

9. The display device according to claim 8, wherein: The second display element comprises: a third electrode; A second display emission layer, disposed on the third electrode; and A common electrode is disposed on the second display emission layer and the second pixel defining layer.

10. The display device according to claim 9, wherein: The third electrode contacts the second bank layer in the direction toward the substrate, and The third electrode is electrically connected to the second bank layer, the first bank layer, and the first electrode.

11. The display device according to claim 9, wherein: A second pattern layer is disposed between the third electrode and the second pixel defining layer in the non-emission region in the direction perpendicular to the upper surface of the substrate, and The second pattern layer contacts the second display emission layer.

12. The display device according to claim 8, wherein: The second opening defines the second emitting portion.

13. The display device according to claim 8, wherein: In a plan view, the first pixel defining layer has a grid pattern that completely surrounds the first emission portion, and In the plan view, the second pixel defining layer has a grid pattern completely surrounding the second emission portion.

14. The display device according to claim 8, wherein: In a plan view, the emission area is larger than the non-emission area.

15. A display device, comprising: A substrate, comprising: a first emission region including a first emission portion and a second emission portion and a second emission region spaced apart from the second emission portion, the first emission portion being disposed between the second emission region and the second emission portion; A first light emitting member is disposed on the substrate and includes: a first light emitting element overlapping the first emission portion; a second light emitting element overlapping the second emission region; and a dam member overlapping the second emission portion; A first encapsulation layer is disposed on the first light emitting member; and A second light emitting member is disposed on the first encapsulation layer and includes a third light emitting element overlapping the second emission portion, wherein: The dam member includes: a first portion in contact with the first light emitting element; a second portion in contact with the third light emitting element; and a third portion in contact with the second light emitting element; and The first portion, the second portion, and the third portion are spaced apart from each other, and the first encapsulation layer is disposed between the first portion, the second portion, and the third portion.

16. The display device according to claim 15, wherein: The first encapsulation layer includes: a first inorganic layer surrounding the first portion; and a second inorganic layer surrounding the third portion, and The first inorganic layer and the second inorganic layer are spaced apart from each other in a direction parallel to an upper surface of the substrate, and the second portion is disposed between the first inorganic layer and the second inorganic layer.

17. The display device according to claim 16, wherein: The first light emitting member further includes a first pixel defining layer disposed between the substrate and the dam member, The first pixel defining layer includes: a first sub-portion contacting the first portion; and a second sub-portion contacting the third portion, and The first sub-portion and the second sub-portion are spaced apart from each other, and the second portion is disposed between the first sub-portion and the second sub-portion.

18. The display device according to claim 17, wherein: The second light emitting element includes an anode electrode, and The second portion contacts the anode electrode in a direction toward the substrate.

19. A method for manufacturing a display device, the method comprising: Prepare a substrate, the substrate comprising: an emission region including a first emission portion and a second emission portion; and a non-emission region disposed between the first emission portion and the second emission portion; forming a first electrode disposed on the first emission portion of the substrate and a first sacrificial layer disposed on the first electrode, and forming a first pixel defining material layer covering the first sacrificial layer and exposing a portion of the first electrode; forming a first bank material layer covering the first electrode and the first pixel defining material layer and a second bank material layer disposed on the first bank material layer, and then removing a portion of the first bank material layer, a portion of the second bank material layer, and a portion of the first pixel defining material layer by an etching process to form a first hole and a second hole overlapping the first electrode and spaced apart from each other; partially etching an inner portion of the first hole through an etching process to form a first bank layer and a second bank layer having a tip portion protruding from the first bank layer toward the first emission portion, and forming a first pixel defining layer defining a first opening; forming a first display emission layer and a second electrode disposed on the first electrode so that the first display emission layer and the second electrode are in contact with a side surface of the first bank layer in the first emission portion, and forming a first thin film encapsulation layer covering the second electrode, the first bank layer and the second bank layer; removing a portion of the first thin film encapsulation layer in the second emission portion by an etching process to expose a portion of the second bank layer in the second emission portion; In the second emission portion, a third electrode disposed on the second bank layer and the first thin film encapsulation layer and a second sacrificial layer disposed on the third electrode are formed, and a second pixel defining layer covering a portion of the second sacrificial layer, overlapping the first emission portion and defining a second opening is formed; Using the second pixel defining layer as a mask, removing the second sacrificial layer disposed on the third electrode through an etching process, forming a second display emission layer disposed on the third electrode, and then forming a common electrode completely covering the second display emission layer and the second pixel defining layer; and forming a second thin film encapsulation layer disposed on the common electrode, The forming of the third electrode includes disposing the third electrode to contact the second barrier layer.

20. The method according to claim 19, wherein: The first pixel defining layer overlaps the second display emission layer in a direction perpendicular to the upper surface of the substrate, and The second pixel defining layer overlaps the first display emission layer in the direction perpendicular to the upper surface of the substrate.

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