Improved trajectory planning with clock skew

Abstract

Trajectory planning to improve clock skew is disclosed. In one aspect, an array of nodes includes a plurality of nodes having clock distribution circuitry configured to distribute a clock signal to each of the nodes. The clock signal propagates in a first direction at least between adjacent nodes. The nodes (202) also include a trajectory plan that includes a plurality of conductive lines to carry communication signals that propagate between the adjacent nodes. The plurality of conductive lines includes a first conductive line (404) configured to carry a first communication signal in a direction opposite the first direction and a second conductive line (402) configured to carry a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 371,951, filed August 19, 2022, the entire contents and all purposes of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to distributed timing, and more specifically, to techniques for reducing clock skew. BACKGROUND

[0004] An artificial intelligence (AI) processor can be constructed using an array of processing nodes. The nodes forming the array can communicate with their neighboring nodes in order to perform processing tasks. A clock signal can be provided to each node so that the nodes can be synchronized to enable communication between them. One technique to provide a clock signal to an array of nodes is distributed timing. SUMMARY

[0005] In one aspect, a node array having trajectory planning for improved clock skew is provided, the node array comprising: a first node comprising a computing circuitry and a plurality of wires configured to communicate a communication signal generated by the first node to a neighboring node of the node array; a second node, the second node being one of the neighboring nodes; and a third node, the third node being one of the neighboring nodes, wherein a clock signal propagates from the second node to the first node to the third node in a first direction; and wherein the plurality of wires of the first node comprises: a first wire configured to communicate a first communication signal to the second node in a direction opposite the first direction, and a second wire configured to communicate a second communication signal to the third node in the first direction, wherein a width of the first wire is greater than a width of the second wire.

[0006] In certain embodiments, the width of the first wire and the width of the second wire facilitate meeting setup time and hold time of electronic components in the second node and the third node.

[0007] In certain embodiments, the plurality of wires further comprises: a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to communicate a plurality of first communication signals to the second node in a direction opposite the first direction, and a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to communicate a plurality of second communication signals to the third node in the first direction, wherein the plurality of first wires are interleaved with the plurality of second wires.

[0008] In certain embodiments, the array of nodes further comprises: a fourth node that is one of the adjacent nodes; and a fifth node that is one of the adjacent nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction that is perpendicular to the first direction, wherein the plurality of conductive lines of the first node further comprises: a third conductive line that extends in the second direction and is configured to communicate a third communication signal to the fourth node in a direction opposite the second direction; and a fourth conductive line that extends in the second direction and is configured to communicate a fourth communication signal to the fifth node in the second direction, wherein a width of the third conductive line is greater than a width of the fourth conductive line.

[0009] In certain embodiments, each of the first node, the second node, the third node, the fourth node, and the fifth node has a length in the first direction that is greater than a length in the second direction, a width of the first conductive line is greater than a width of the third conductive line, and a width of the second conductive line is greater than a width of the fourth conductive line.

[0010] In certain embodiments, the plurality of conductive lines further comprises: a plurality of third conductive lines that extend in the second direction and include the third conductive line, the plurality of third conductive lines being configured to communicate a plurality of third communication signals to the fourth node in a direction opposite the second direction, and a plurality of fourth conductive lines that extend in the second direction and include the fourth conductive line, the plurality of fourth conductive lines being configured to communicate a plurality of fourth communication signals to the fifth node in the second direction, wherein the plurality of third conductive lines are interleaved with the plurality of fourth conductive lines.

[0011] In certain embodiments, the clock signal has a substantially fixed delay when propagating between adjacent nodes.

[0012] In certain embodiments, the nodes of the array of nodes are configured to operate with a timing offset compared to other nodes based on a timing at which the nodes receive the clock signal.

[0013] In another aspect, there is provided a node of an array of nodes having trajectory planning for improving clock skew in the array of nodes, the node comprising: a computing circuitry configured to generate a communication signal; and a plurality of conductive lines configured to enable propagation of the communication signal to a neighboring node of the array of nodes, wherein the node of the array of nodes is configured to receive a distributed clock signal that propagates between the neighboring nodes in at least a first direction, wherein the plurality of conductive lines comprises: a first conductive line configured to communicate a first communication signal in a direction opposite the first direction, and a second conductive line configured to communicate a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

[0014] In certain embodiments, the width of the first wire and the width of the second wire facilitate meeting setup time and hold time of electronic components in respective destination nodes of the first communication signal and the second communication signal.

[0015] In certain embodiments, the plurality of wires further comprises: a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to transmit a plurality of first communication signals in a direction opposite the first direction, and a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to transmit a plurality of second communication signals in the first direction, wherein the plurality of first wires are interleaved with the plurality of second wires.

[0016] In certain embodiments, the clock signal further propagates between adjacent nodes in a second direction, the second direction being perpendicular to the first direction, and the plurality of wires further comprises: a third wire extending in the second direction and configured to transmit a third communication signal in a direction opposite the second direction; and a fourth wire extending in the third second and configured to transmit a fourth communication signal in the second direction, wherein a width of the third wire is greater than a width of the fourth wire.

[0017] In certain embodiments, a length of the node in the first direction is greater than a length of the node in the second direction, the width of the first wire is greater than the width of the third wire, and the width of the second wire is greater than the width of the fourth wire.

[0018] In certain embodiments, the plurality of wires further comprises: a plurality of third wires extending in the second direction and including the third wire, the plurality of third wires configured to transmit a plurality of third communication signals in a direction opposite the second direction, and a plurality of fourth wires extending in the second direction and including the fourth wire, the plurality of fourth wires configured to transmit a plurality of fourth communication signals in the second direction, wherein the plurality of third wires are interleaved with the plurality of fourth wires.

[0019] In certain embodiments, the clock signal is further configured to be distributed with a substantially fixed latency when propagating between adjacent nodes.

[0020] In certain embodiments, the node is configured to operate with a timing offset compared to other nodes of the array of nodes based on a timing at which the node receives the clock signal.

[0021] In yet another aspect, a method of fabricating an array of nodes is provided, the method comprising: forming a first node, the first node comprising a computing circuitry device and a plurality of conductive lines configured to communicate a communication signal generated by the first node to an adjacent node of the array of nodes; forming a second node, the second node being one of the adjacent nodes; and forming a third node, the third node being one of the adjacent nodes, wherein a clock signal propagates from the second node to the first node to the third node in a first direction, and wherein the plurality of conductive lines of the first node comprises: a first conductive line configured to communicate a first communication signal to the second node in a direction opposite the first direction, and a second conductive line configured to communicate a second communication signal in the first direction, wherein a width of the first conductive line is greater than a width of the second conductive line.

[0022] In certain embodiments, the width of the first conductive line and the width of the second conductive line are selected to satisfy setup time and hold time of electronic components in the second node and the third node.

[0023] In certain embodiments, the plurality of conductive lines further comprises: a plurality of first conductive lines extending in the first direction and including the first conductive line, the plurality of first conductive lines configured to communicate a plurality of first communication signals to the second node in a direction opposite the first direction, and a plurality of second conductive lines extending in the first direction and including the second conductive line, the plurality of second conductive lines configured to communicate a plurality of second communication signals to the third node in the first direction, wherein the plurality of first conductive lines are interleaved with the plurality of second conductive lines.

[0024] In certain embodiments, the array of nodes further comprises: a fourth node, the fourth node being one of the adjacent nodes; and a fifth node, the fifth node being one of the adjacent nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, the plurality of conductive lines of the first node further comprising: a third conductive line extending in the second direction and configured to communicate a third communication signal to the fourth node in a direction opposite the second direction; and a fourth conductive line extending in the second direction and configured to communicate a fourth communication signal to the fifth node in the second direction, wherein a width of the third conductive line is greater than a width of the fourth conductive line. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a schematic block diagram of an example chip according to aspects of the present disclosure.

[0026] Figure 2 is a node clock level diagram associated with an example array of nodes, such as Figure 1 the array of nodes of FIG. 1.

[0027] Figure 3FIG. illustrates a portion of a node array including example clock propagation directions, according to aspects of the present disclosure.

[0028] Figure 4A and Figure 4B FIG. illustrates example clock propagation directions and signal propagation directions for nodes of an array, according to aspects of the present disclosure.

[0029] Figure 5A and Figure 5B FIG. illustrates multiple example signal propagation directions for nodes of an array, according to aspects of the present disclosure. DETAILED DESCRIPTION

[0030] The following description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein can be embodied in many different forms, for example, as defined and covered by the claims. In the description, reference is made to the accompanying drawings, which form a part of the disclosure, in which like reference characters can refer to similar or functionally similar elements throughout the drawings. It will be appreciated that the elements illustrated in the figures are not necessarily drawn to scale. Furthermore, it will be appreciated that certain embodiments can include more elements or less elements than shown in a figure. In addition, some embodiments can encompass any suitable combination of features from two or more figures. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0031] Node Array Primer

[0032] The present disclosure relates to clock distribution networks in which clock signals arrive at nodes of a node array at different times. Timing with a fixed offset can be referred to as average synchronous timing. Embodiments disclosed herein relate to average synchronous clock networks that can be modularly built from common circuit devices. Clock signals for such networks can be locally low-skewed and average synchronous at a coarse level.

[0033] Traditionally, clock signals are built and routed at the top level of a chip, which increases the design effort, area, and power consumption. In this case, clock distribution is a custom design at the top level of the chip. One approach is to route clock signals in channels between sub-blocks. This can disrupt the design and consume area. Another approach is to push top-level clocks down into sub-blocks. This can slow the design process and cause the same part of the design to fork, creating unique copies. Traditional approaches can result in clock signals arriving at all receivers at nearly the same time. The circuit can then operate in a lock step.

[0034] In the clock distribution networks disclosed herein, the clock arrives at different receivers at different times. The clock signal can be distributed through a two-dimensional (2D) array of nodes such that the clock signal arrives at different nodes with different timing offsets. Due to the clock distribution structure, the arrival times can be grouped by contour or wave on the die. At the local level, the circuitry of a node can operate in a lock step. More generally, the circuitry in different nodes of the array of nodes can operate with timing offsets relative to each other. By having different nodes perform calculations with timing offsets relative to each other, peak current from the power grid can be reduced. The quality of the power supply signal can also be improved by such calculations. The calculation circuitry can be designed to handle the arrival time differences of the clock signal.

[0035] The clock distribution networks disclosed herein can simplify the top-level design and clock circuitry construction of a chip. Timing with fixed offsets can be referred to as average synchronous timing. The embodiments disclosed herein allow for the modular construction of average synchronous clock networks with instances of a generic subpart design. The clock signal of such networks can be locally low-skewed and average synchronous on a coarser level.

[0036] The clock distribution disclosed herein can be applied to any suitable chip. In certain applications, the clock distribution disclosed herein can be applied to chips each comprising an array of smaller computing nodes. The computing nodes can be referred to as processors or cores. In this way, the clock signal can form an arrival time wave on the array. Each computing node can receive a low-skewed clock signal. The computing nodes of the array can be designed to have only interfaces to neighbor computing nodes to resolve the arrival time differences (skews) of the average synchronous clock phases. For example, the chips disclosed herein with clock distribution networks can have a 35-phase average synchronous clock or a 41 -phase average synchronous clock. The clock distribution described herein can be used in a square (equal number of rows and columns) array of nodes or in a rectangular array of nodes with different numbers of rows and columns.

[0037] Figure 1 is a schematic block diagram of an example chip 100 according to aspects of the present disclosure. The chip 100 can be an integrated circuit die. The chip 100 can include an array of nodes 102 (also referred to as an array of computing nodes) with distributed timing, one or more serializer / deserializer (SerDes) clock blocks 104, a clock generator 106, and a clock controller 108. The SerDes clock blocks 104 can interface with other chips 100 forming an array of chips 100. In certain application instances, the array of nodes 102 can be included on a chip 100 in a system on a chip, on an array of chips 100 on a printed circuit board, etc. In certain applications, Figure 1The node array 102 can be implemented on a system on a chip packaged with a chip-scale packaging structure. For example... Figure 1 As shown in the embodiments, clock generator 106 can be implemented outside of node array 102. In some embodiments, clock generator 106 may include phase-locked loop (PLL). Clock generator 106 can be arranged to provide clock signals to computing nodes at the corner of node array 102. Clock controller 108 can also be implemented outside of node array 102. Nodes within node array 102 can include node-to-node interfaces that can be configured for synchronous communication. Core-to-serializer / deserializer (SerDes) interfaces can be asynchronous.

[0038] exist Figure 1 In the node array 102 with distributed timing, each node can be an instance of computing circuitry (also referred to as a processing core or computing node). In some applications, most nodes can be implemented as instances of computing circuitry, and one or more nodes can be implemented as instances of different circuitry. Even if the other circuitry of at least some nodes differs from that of other nodes, each node of the node array 102 can include an instance of substantially the same clock distribution circuitry. In the node array 102, nodes can be tiled and adjacent. For example, each node of the node array 102 can be independent and interconnected with one or more neighboring nodes. Meanwhile, the node array 102 can be implemented without using top-level wires or gates. Thus, nodes can be configured to communicate with adjacent nodes via short connectors using lower-level wires. In some embodiments, the nodes of the node array 102 can be stepped without mirroring or rotation. In some implementations, nodes can be connected to power lines (V... DD / V SS The power grid spacing can be aligned. For example, the height and width of each node can be a multiple of the power grid spacing. The power grid spacing can also be aligned with the bump spacing.

[0039] Each node in node array 102 may include an instance of substantially the same clock distribution circuitry. Nodes may be designed such that the output clock line of a node is aligned with the input clock line of its adjacent node. Nodes may be arranged in a stepped or tiled manner in the node array, such that the clock output line is aligned with and electrically connected to the clock input line of an adjacent node arranged downstream to receive the clock signal. Using such electrical connections, the node array can be implemented without a channel or top-level wiring for clock distribution. In some embodiments, the fan-out of the clock distribution circuitry may be balanced for the inverter.

[0040] As described herein, a clock signal received at a root node can be propagated from the root node to two adjacent nodes by one delay unit. The root node can be located in a corner of the node array 102. The delay unit can be a fixed offset for a given node array. The delay unit can correspond to a delay from buffering the clock signal (e.g., using an inverter) and a wire delay associated with the clock signal propagated to its adjacent node(s).

[0041] One of the two adjacent nodes can be located in the same row as the root node, and the other of the two adjacent nodes can be located in the same column as the root node. The adjacent nodes are contiguous to the root node. As one example, the adjacent nodes are to the south and east of the root node in Figure 2 . In this example, the clock signal continues to propagate by one more delay unit to adjacent nodes in the node array to the south and east of the two adjacent nodes of the root node. This type of clock signal propagation continues through the clock distribution network in the node array 102 until the clock signal reaches a node in the node array 102 diagonally opposite the root node. In this example, signals routed from the originating node that generate the signal to adjacent nodes north or west of the originating node can travel upstream and lose one delay unit in the node array 102, while signals routed from the originating node to adjacent nodes south or east can travel downstream and gain one delay unit in the node array 102. The signals that travel upstream can be routed faster than the signals that travel downstream to resolve the unit delay problem and to meet setup and hold time specifications.

[0042] Figure 2 is a node clock level diagram associated with an example node array, such as the node array 102 of Figure 1 . The example node array 102 has 18 rows and 18 columns. For 18 rows 18 columns, there can be 324 nodes. As another example, the node array 102 can include 360 nodes arranged in rows and columns. This clock diagram includes the number of unit delays for the clock signal output of the nodes of the array. For example, the root node in the northwest corner has 1 unit delay. The two adjacent nodes that receive the clock signal from the root node have 2 unit delays. Nodes on diagonals from the southwest to the northeast can have the same unit delay. Using the clock distribution circuitry described herein, the unit delay can be a fixed offset. The nodes along these diagonals can receive clock signals with substantially the same timing delay. These diagonals can be referred to as phases or waves. A phase corresponds to a different clock signal arrival time in the nodes. Corresponding to Figure 2 the clock signal distribution of the diagram of

[0043] In some embodiments, the clock signal may propagate as a wave passing through the node array 102 in the row or column direction, rather than as a wave forming along the diagonal of the node array. For example, each node may output a clock signal to the south or east, rather than outputting clock signals to both the south and east. In this way, the clock signal may propagate as a wave traveling to the south or east. However, aspects of this disclosure are not limited to a specific direction of travel for the clock signal, and the clock signal may propagate along other diagonals and / or to the north or west.

[0044] When routing signals between nodes, consider Figure 2 The offset. Signals routed from the starting node that generated the signal to nodes on the north or west side can travel upstream, and in the corresponding... Figure 2 A unit delay is lost in the node array. Signals routed from the starting node to nodes on the south or east side can travel downstream, and in the corresponding... Figure 2 A unit delay is achieved in the node array. Upstream signals can be routed faster than downstream signals to address the unit delay issue and satisfy setup and hold time specifications.

[0045] In some embodiments, each node of the node array 102 may be an instance of computing circuitry. In some applications, most nodes include instances of computing circuitry, and one or more remaining nodes include instances of different circuitry, such as global nodes. A global node may refer to a node that does not include circuitry for performing processing tasks. In some embodiments, both computing nodes and global nodes may include communication interfaces to enable communication with neighboring nodes. In some embodiments, the communication interface of a computing node may be the same as the communication interface of a global node.

[0046] Trajectory planning for reducing clock skew

[0047] This disclosure relates to trajectory planning (also known as wiring planning) for signal communication between nodes, which is "clock skew-aware". The trajectory planning described herein can improve upstream and downstream signal timing to reduce or eliminate skew caused by the direction of signal travel relative to the direction of clock signal propagation.

[0048] Other aspects of the present disclosure provide techniques for defining metal trace widths for a heavily replicated functional design having a meshed clock distribution. Certain electronic design automation tools allow traces to be defined by selecting the width, spacing, and / or location of the metal traces under the guidance of a design rule handbook. Aspects of the present disclosure also provide methods for defining trace planning for functional design units and assigning traces to signals based on the direction of communication traffic. For example, signals that travel with (e.g., in the same direction as) a clock signal can be routed with a smaller width trace, while signals that travel against (e.g., in the opposite direction as) a clock signal can be routed with a larger width trace. Some or all of these signals can also be directionally staggered with each other (signal directions alternate) to reduce or minimize signal integrity issues (e.g., crosstalk). In some applications, for example, all signals can be directionally staggered.

[0049] Typically, the traces in which communication signals travel can have substantially the same width and spacing, regardless of the direction in which the signals travel. This width and spacing can be sized for the longest and / or shortest expected delay time. Such width and spacing can be designed to meet setup time and hold time specifications. The use of traces for staggered signals as described herein can also allow for higher frequency designs and reduce the area used by traces by minimizing the size of the wires (also referred to as traces) used to meet design objectives. This can both reduce the design as well as allow more replicated modules to be installed in the same physical area, thereby increasing the performance of each die.

[0050] Figure 3 A portion of a node array 102 including example clock propagation directions is illustrated in accordance with aspects of the present disclosure. As shown, the portion of the node array 102 includes a plurality of nodes 202. The nodes 202 are arranged in rows and columns. In some embodiments, clock signals can propagate through the node array 102 in a vertical direction and a horizontal direction. As shown, the clock signals can propagate in a first direction 204 between the nodes 202 from top to bottom, and the clock signals can propagate in a second direction 206 between the nodes 202 from left to right. As shown, the clock signals can propagate in two orthogonal directions in the node array 102. As shown, the clock signals can propagate through the node array 102 with a delay. Figure 3 Figure 3 Figure 3 Figure 2

[0051] Figure 4A Figure 4B Example clock propagation directions and signal propagation directions for a node 202 of an array 102 in accordance with aspects of the present disclosure are illustrated. In particular, a portion of the node 202 is shown. As shown, the portion of the node 202 includes a plurality of nodes 202. The nodes 202 are arranged in rows and columns. In some embodiments, clock signals can propagate through the node 202 in a vertical direction and a horizontal direction. As shown, the clock signals can propagate in a first direction 204 between the nodes 202 from top to bottom, and the clock signals can propagate in a second direction 206 between the nodes 202 from left to right. As shown, the clock signals can propagate in two orthogonal directions in the node 202. As shown, the clock signals can propagate through the node 202 with a delay. Figure 4A As shown, horizontal wires are configured to allow communication signals to propagate in a horizontal direction, while​​​​​Figure 4B The illustration shows a vertical conductor configured to allow communication signals to propagate in the vertical direction.

[0052] refer to Figure 4A Node 202 includes a first horizontal conductor 402 configured to propagate communication signals between nodes from left to right in a second direction 206. Node 202 also includes a second horizontal conductor 404 configured to propagate communication signals between nodes from right to left in the opposite direction to the second direction 206. The arrows at the ends of the horizontal lines 402 and 404 in the figures are for illustrative purposes only, indicating the direction of signal propagation.

[0053] refer to Figure 4B Node 202 also includes a first vertical conductor 406 configured to propagate communication signals between nodes from top to bottom in a first direction 204. Node 202 also includes a second vertical conductor 408 configured to propagate communication signals between nodes from bottom to top in the opposite direction to the first direction 204. The arrows at the ends of the vertical conductors 406 and 408 in the figures are for illustrative purposes only, indicating the direction of signal propagation.

[0054] In some embodiments, the first horizontal conductor 402 and the second horizontal conductor 404 may be formed in a different layer than the first vertical conductor 406 and the second vertical conductor 408. The vertical conductors 406 and 408 may extend in a first direction 204, which is orthogonal to a second direction 206 in which the horizontal conductor 402 extends.

[0055] Communication signals between nodes 202 are designed to reach destination node 202 (e.g., by adjaculating adjacent nodes to nodes from which they are departing) to meet setup and hold time specifications. As used herein, setup time generally refers to the minimum amount of time required for an electronic component's input to remain stable before a clock edge to ensure that the component can correctly read its input. Hold time, as used herein, generally refers to the minimum amount of time required for an electronic component's input to remain stable after a clock edge to ensure that the component can correctly read its input. Setup and hold times can be defined for any electrical component that reads its input signal at a timing defined by a clock signal; such electrical components include, for example, flip-flops, registers, memories, processors, multiplexers, decoders, etc.

[0056] Because in Figure 4ACommunication signals propagating from left to right along the second direction 206 (e.g., via the first horizontal wire 402) can have longer propagation delays and still satisfy setup and hold times, as these signals propagate in the second direction 206. The timing at which a communication signal will stabilize at the input of a node 202 to satisfy the setup and hold times of the node 202 depends on the time at which the clock signal will arrive at the node 202. For example, because communication signals traveling along the first horizontal wire 402 propagate in the second direction 206, the communication signals propagating along the first horizontal wire 402 can arrive at a neighboring node at an earlier time relative to the clock signal propagating to the neighboring node along the second direction 206 than the communication signals propagating along the second horizontal wire 404 that travel in the opposite direction of the clock signal.

[0057] Communication signals propagating in the opposite direction of the clock signal (e.g., along the second horizontal wire 404 or the second vertical wire 408) can be designed to have shorter propagation delays than communication signals propagating in the same direction as the clock signal (e.g., along the first horizontal wire 402 or the first vertical wire 406). Thus, communication signals propagating in the same direction as the clock signal can be considered to have a benefit of clock propagation time, while communication signals propagating in the opposite direction of the clock signal can be considered to have a loss of clock propagation time.

[0058] To achieve longer propagation delays for communication signals propagating in the same direction as the clock signal and shorter propagation delays for communication signals propagating in the opposite direction of the clock signal, aspects of the present disclosure relate to techniques for tuning wire delays to satisfy setup and hold time specifications in a node array 102 with an average synchronous clock.

[0059] The propagation delay along the communication wires 402-408 can be related to the RC delay of the wires 402-408. In some embodiments, the length of the wires 402-408 can be determined by the pitch of the nodes 202, and the height of the wires 402-408 can be determined by the process used to form the wires (e.g., photolithography) and the metal layer. Thus, the width of the wires 402-408 is a design parameter that can be used to adjust the propagation delay introduced by the wires 402-408. In some embodiments, the first horizontal wires 402 and the first vertical wires 406, which are used to communicate signals in the same direction as the clock propagation, can be formed with a relatively small width to increase the propagation delay, while the second horizontal wires 404 and the second vertical wires 408, which are used to communicate signals in the opposite direction as the clock propagation, can be formed with a relatively large width to decrease the propagation delay. The particular width of the wires 402-408 can be formed such that the signals propagating on the wires 402-408 satisfy the setup time and the hold time of the electronic components in the destination nodes 202. In one embodiment, the width of the wires 402-408 can be selected such that the communication signals propagating on the wires 402-408 substantially reach the midpoint between the setup time and the hold time, however, aspects of the present disclosure are not limited thereto.

[0060] In certain embodiments, the nodes 202 can not have a square shape, and thus, the time for a signal to travel vertically through a given node 202 can be different than the time for a signal to travel horizontally through the node 202. For example, in certain embodiments, the length of a node 202 in the horizontal direction can be greater than the length in the vertical direction. In these embodiments, the width of the first horizontal wires 402 can be greater than the width of the first vertical wires 406, while the width of the second horizontal wires 404 can be greater than the width of the second vertical wires 408. However, when the amount of delay introduced by the difference in the relative lengths of the horizontal and vertical lengths of the nodes is negligible, the wires that travel in the same direction as the clock signal (whether horizontal or vertical) can be substantially the same.

[0061] Figure 5A and Figure 5B FIGS. 4A-4D illustrate a plurality of example wires with signal propagation directions for a node 202 of the array of nodes 102, in accordance with aspects of the present disclosure. Referring to FIG. 4A, each node 202 can be connected to its horizontally adjacent nodes 202 by a plurality of horizontal communication wires 402 and 404. As shown, each node 202 can be connected to its horizontally adjacent nodes 202 by a plurality of horizontal communication wires 402 and 404. Figure 5A As shown, each node 202 can be connected to its vertically adjacent nodes 202 by a plurality of vertical communication wires 406 and 408. Figure 5B

[0062] ​Proximity of the communication wires 402-408 can cause crosstalk between the wires 402-408. For example, when two signals are propagating in the same direction, induced currents between the wires 402-408 can cause crosstalk along the length of the wires 402-408. One technique to reduce this source of crosstalk is to place the communication wires 402-408 farther apart. However, increasing the spacing between the communication wires 402-408 can reduce the amount of bandwidth available for communication between the nodes 202. Accordingly, as shown in FIGS. 4A and 4B, aspects of the present disclosure involve interleaving the communication wires 402-408 based on the direction in which signals propagate on the wires. For example, each wire in the first horizontal set of wires 402 is adjacent to one or more wires in the second horizontal set of wires 404, and vice versa, such that signals on any two adjacent wires 402 and 404 propagate in opposite directions. Similarly, each wire in the first vertical set of wires 406 is adjacent to one or more wires in the second vertical set of wires 408, and vice versa, such that signals on any two adjacent wires 406 and 408 propagate in opposite directions. In certain applications, by interleaving the horizontal wires 402, 404 and / or the vertical wires 406, 408 based on the direction of the signals propagating thereon, crosstalk between adjacent wires 402, 404 and / or 406, 408 can be limited to a single location along the propagation path (e.g., the point at which the opposite signals meet as they travel between the nodes 202). Figure 5A and Figure 5B As shown in FIGS. 4A and 4B, aspects of the present disclosure involve interleaving the communication wires 402-408 based on the direction in which signals propagate on the wires. For example, each wire in the first horizontal set of wires 402 is adjacent to one or more wires in the second horizontal set of wires 404, and vice versa, such that signals on any two adjacent wires 402 and 404 propagate in opposite directions. Similarly, each wire in the first vertical set of wires 406 is adjacent to one or more wires in the second vertical set of wires 408, and vice versa, such that signals on any two adjacent wires 406 and 408 propagate in opposite directions. In certain applications, by interleaving the horizontal wires 402, 404 and / or the vertical wires 406, 408 based on the direction of the signals propagating thereon, crosstalk between adjacent wires 402, 404 and / or 406, 408 can be limited to a single location along the propagation path (e.g., the point at which the opposite signals meet as they travel between the nodes 202).

[0063] Depending on the implementation, thousands of wires 402-408 can be used for a tile of a track plan design. These communication wires 402-408 can connect adjacent nodes 202 in a tiled and stepped node array 102. In certain embodiments, the communication wires 402-408 can connect nodes 202 in a lower layer of metal.

[0064] In some implementations, the track plan of the communication wires 402-408 can be generated in an automated manner by redefining the track plan of a design and assigning those tracks (e.g., tracks 402-408) based on the directionality of the signals communicated on the wires. A track plan designed according to aspects of the present disclosure can enable a higher number of wires 402-408 per length of a given node 202 compared to other track plans, which can translate into a higher bandwidth design. Furthermore, the track plan can also address unique clock skew associated with average synchronous timing of a node array by adjusting the delay introduced by the communication wires 402-408. Moreover, using wires of appropriate size can also allow for the use of higher frequency designs, which can provide lower latency and / or higher performance.

[0065] Further, other attempts to address signal delay and / or crosstalk can involve designing wire sizes and / or spacing for worst-case scenarios. This would result in wider wire widths than are needed to satisfy setup time and hold time specifications, and lower wire densities than are achievable according to aspects of the present disclosure. In contrast to such designs, aspects of the present disclosure can provide higher bandwidth (e.g., by using a greater number of communication wires in the same area) and lower latency signals (e.g., by reducing crosstalk via directionally interleaved wires).

[0066] In some embodiments, the clock distribution network can be configured to propagate the clock signal in a row or column direction such that the clock signal does not travel along Figure 2 In these embodiments, the trajectory planning can include wires having different widths when the wires run in the same or opposite direction as the clock signal, and wires having substantially the same width when the wires run in a direction perpendicular to the direction of propagation of the clock signal.

[0067] Conclusion

[0068] The foregoing disclosure is not intended to limit the disclosure to the precise forms or specific uses disclosed. Thus, various alternatives and / or modifications of the disclosure (whether expressly described or implied herein) can be provided in accordance with the disclosure. Having thus described embodiments of the disclosure, a person of ordinary skill in the art will recognize that changes can be made in form and detail without departing from the scope of the disclosure. The disclosure is therefore to be limited only by the claims.

[0069] In the foregoing specification, the disclosure has been described with reference to specific embodiments thereof. It is, however, evident that various modifications and changes can be made thereto without departing from the spirit and scope of the disclosure. The description is, accordingly, to be taken as illustrative and not restrictive, and the disclosure is to be given the broadest interpretation of the various embodiments disclosed. It is to be understood that all the drawings shown and described herein are representative of the present disclosure. Equivalent elements, materials, processes or steps can be substituted for those specifically represented and described herein. Furthermore, certain features of the disclosure can be utilized independently of other features, all of which will be apparent from the description contained herein. Expressions such as "including", "comprising", "incorporating", "consisting of", "having", "is", "are" used herein are to be taken generally as specifying the presence of stated features, integers, components or elements but not the absence thereof, unless the context specifically indicates otherwise. References to singular include plural references and vice versa are to be considered as being addressed by at least one.

[0070] Furthermore, the various embodiments disclosed herein can be used alone or in any combination and are not limited to the specific combinations described herein. Thus, if there is a combination of features, elements, or steps not expressly described or shown, this combination is not excluded from the scope of the disclosure. In addition, the use of "including", "comprising", "having" (and any variations such as "includes", "comprises", "has", "including", "comprising", "containing" etc.) should be interpreted as specifically expressing the possibility of comprising, having, the element, integer or steps but not the exclusion of any other element, integer or step. It is to be understood that the above description and the examples described herein are illustrative of the various embodiments and are not in limitation of the present disclosure. Many modifications and variations of the present disclosure are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the disclosure can be practiced otherwise than as specifically described.

[0071] It will also be understood that one or more elements shown in the drawings / figures can also be implemented in a more separated or integrated manner, or even removed or rendered inoperable in certain cases, as is useful in accordance with a particular application.

Claims

1. A node array having trajectory planning for improved clock skew, the node array comprising: a first node including a computing circuitry and a plurality of wires configured to communicate a communication signal generated by the first node to an adjacent node of the node array; a second node, the second node being one of the adjacent nodes; and a third node, the third node being one of the adjacent nodes, wherein a clock signal propagates from the second node to the first node to the third node in a first direction; and wherein the plurality of wires of the first node includes: a first wire configured to communicate a first communication signal to the second node in a direction opposite the first direction, and a second wire configured to communicate a second communication signal to the third node in the first direction, wherein a width of the first wire is greater than a width of the second wire.

2. The node array of claim 1, wherein the width of the first wire and the width of the second wire contribute to meeting setup time and hold time of electronic components in the second node and the third node.

3. The node array of claim 1, wherein the plurality of wires further includes: a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to communicate a plurality of first communication signals to the second node in the direction opposite the first direction, and a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to communicate a plurality of second communication signals to the third node in the first direction, wherein the plurality of first wires are interleaved with the plurality of second wires.

4. The node array of claim 1, wherein the node array further includes: a fourth node, the fourth node being one of the adjacent nodes; and a fifth node, the fifth node being one of the adjacent nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, wherein the plurality of wires of the first node further includes: a third wire extending in the second direction and configured to communicate a third communication signal to the fourth node in a direction opposite the second direction; and a fourth wire extending in the second direction and configured to communicate a fourth communication signal to the fifth node in the second direction, wherein a width of the third wire is greater than a width of the fourth wire.

5. The node array of claim 4, wherein: a length of each of the first node, the second node, the third node, the fourth node, and the fifth node in the first direction is greater than a length in the second direction, the width of the first wire is greater than the width of the third wire, and the width of the second wire is greater than the width of the fourth wire. The width of the second wire is greater than the width of the fourth wire.

6. The node array of claim 4, wherein the plurality of wires further comprises: a plurality of third wires extending in the second direction and including the third wire, the plurality of third wires configured to communicate a plurality of third communication signals to the fourth node in the direction opposite the second direction, and a plurality of fourth wires extending in the second direction and including the fourth wire, the plurality of fourth wires configured to communicate a plurality of fourth communication signals to the fifth node in the second direction, wherein the plurality of third wires are interleaved with the plurality of fourth wires.

7. The node array of claim 1, wherein the clock signal has a fixed delay when propagating between adjacent nodes.

8. The node array of claim 1, wherein the nodes of the node array are configured to operate with a timing offset compared to other nodes based on a timing at which the node receives the clock signal.

9. A node of a node array having trajectory planning for improving clock skew in the node array, the node comprising: computing circuitry configured to generate a communication signal; and a plurality of wires configured to enable the communication signal to propagate to a neighboring node of the node array, wherein the node of the node array is configured to receive a distributed clock signal that propagates between the neighboring nodes in at least a first direction, wherein the plurality of wires comprises: a first wire configured to communicate a first communication signal in a direction opposite the first direction, and a second wire configured to communicate a second communication signal in the first direction, wherein a width of the first wire is greater than a width of the second wire.

10. The node of claim 9, wherein the width of the first wire and the width of the second wire contribute to satisfying setup time and hold time of electronic components in respective destination nodes of the first and second communication signals.

11. The node of claim 9, wherein the plurality of wires further comprises: a plurality of first wires extending in the first direction and including the first wire, the plurality of first wires configured to communicate a plurality of first communication signals in the direction opposite the first direction, and a plurality of second wires extending in the first direction and including the second wire, the plurality of second wires configured to communicate a plurality of second communication signals in the first direction, wherein the plurality of first wires are interleaved with the plurality of second wires.

12. The node of claim 9, wherein: the clock signal further propagates between the neighboring nodes in a second direction, the second direction being perpendicular to the first direction, and the plurality of wires further comprises: a plurality of third wires extending in the second direction and including the third wire, the plurality of third wires configured to communicate a plurality of third communication signals to the fourth node in the direction opposite the second direction, and a plurality of fourth wires extending in the second direction and including the fourth wire, the plurality of fourth wires configured to communicate a plurality of fourth communication signals to the fifth node in the second direction, wherein the plurality of third wires are interleaved with the plurality of fourth wires. a third wire extending in the second direction and configured to communicate a third communication signal in a direction opposite the second direction; and a fourth wire extending in the second direction and configured to communicate a fourth communication signal in the second direction, wherein a width of the third wire is greater than a width of the fourth wire.

13. The node of claim 12, wherein: a length of the node in the first direction is greater than a length in the second direction, the width of the first wire is greater than the width of the third wire, and the width of the second wire is greater than the width of the fourth wire.

14. The node of claim 12, wherein the plurality of wires further comprises: a plurality of third wires extending in the second direction and including the third wire, the plurality of third wires configured to communicate a plurality of third communication signals in the direction opposite the second direction, and a plurality of fourth wires extending in the second direction and including the fourth wire, the plurality of fourth wires configured to communicate a plurality of fourth communication signals in the second direction, wherein the plurality of third wires are interleaved with the plurality of fourth wires.

15. The node of claim 9, wherein the clock signal is further configured to be distributed with a fixed delay when propagating between adjacent nodes.

16. The node of claim 9, wherein the node is configured to operate with a timing offset compared to other nodes of the array of nodes based on a timing at which the node receives the clock signal.

17. A method of fabricating an array of nodes, the method comprising: forming a first node including a computing circuitry and a plurality of wires configured to communicate communication signals generated by the first node to adjacent nodes of the array of nodes; forming a second node, the second node being one of the adjacent nodes; and forming a third node, the third node being one of the adjacent nodes, wherein a clock signal propagates in a first direction from the second node to the first node to the third node, and wherein the plurality of wires of the first node comprises: a first wire configured to communicate a first communication signal to the second node in a direction opposite the first direction, and a second wire configured to communicate a second communication signal in the first direction, wherein a width of the first wire is greater than a width of the second wire.

18. The method of claim 17, wherein: the width of the first wire and the width of the second wire are selected to satisfy setup time and hold time of electronic components in the second node and the third node.

19. The method of claim 17, wherein the plurality of wires further comprises: a plurality of first conductive lines extending in the first direction and including the first conductive line, the plurality of first conductive lines configured to transmit a plurality of first communication signals to the second node in the direction opposite the first direction, and a plurality of second conductive lines extending in the first direction and including the second conductive line, the plurality of second conductive lines configured to transmit a plurality of second communication signals to the third node in the first direction, wherein the plurality of first conductive lines are interleaved with the plurality of second conductive lines.

20. The method of claim 17, wherein the array of nodes further comprises: a fourth node, the fourth node being one of the adjacent nodes; and a fifth node, the fifth node being one of the adjacent nodes, wherein the clock signal propagates from the fourth node to the first node to the fifth node in a second direction perpendicular to the first direction, the plurality of conductive lines of the first node further comprising: a third conductive line extending in the second direction and configured to transmit a third communication signal to the fourth node in a direction opposite the second direction; and a fourth conductive line extending in the second direction and configured to transmit a fourth communication signal to the fifth node in the second direction, wherein a width of the third conductive line is greater than a width of the fourth conductive line.

Images