Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises: a substrate; the plurality of pixel units are arranged on the substrate base plate, and the plurality of pixel units are arranged on the substrate base plate in an array manner along a first direction and a second direction; the first scanning signal line is arranged on the substrate; the at least one data line is arranged on the substrate; the sensing signal line is arranged on the substrate; wherein the first scanning signal line comprises a plurality of first sub-scanning signal lines; every two adjacent first sub-scanning signal lines are arranged in the first area at intervals; the sensing signal line and the at least one data line respectively extend along a second direction, and the orthographic projection of the sensing signal line and the at least one data line on the substrate is not overlapped with the orthographic projection of the plurality of first sub-scanning signal lines on the substrate, the orthographic projection of the sensing signal line and the at least one data line on the substrate extends through the orthographic projection of the first area on the substrate. The first sub-scanning signal line and the first grid electrode are arranged at an interval in the second direction, and the fourth sub-scanning signal line and the third grid electrode are arranged at an interval in the second direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) devices have attracted much attention due to their advantages such as self-luminescence, rich colors, fast response speed, wide viewing angle, light weight, thin thickness, low power consumption, and flexible display. They are now widely used in mobile phones, TVs, wearable devices, etc. With the development of OLED technology, the size of OLED display panels is getting larger and larger, and the requirements for resolution and brightness are getting higher and higher, which puts higher demands on the design of OLED display panel drive circuits.

[0003] In existing designs, the gate layer is prone to electrostatic breakdown in the area where it overlaps with the active layer or source / drain layer, causing short circuits in the pixel driver circuit and display defects. Designing and optimizing the driver circuits for OLED display panels to improve the quality and yield of OLED display products is a key research topic for researchers.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] In one aspect, a display substrate is provided, comprising: a base substrate; a plurality of pixel units disposed on the base substrate, each pixel unit comprising a plurality of sub-pixels, the plurality of pixel units being arranged in an array on the base substrate along a first direction and a second direction, wherein at least one sub-pixel comprises a light-emitting element and a pixel driving circuit for driving the light-emitting element, the pixel driving circuit comprising a switching transistor and a sensing transistor, the switching transistor comprising a first gate, the sensing transistor comprising a third gate, the first direction and the second direction intersecting; a first scanning signal line disposed on the base substrate, the first scanning signal line being used to supply a first scanning signal to the plurality of pixel units arranged along the first direction; a second scanning signal line disposed on the base substrate, the second scanning signal line being used to supply a second scanning signal to the plurality of pixel units arranged along the first direction; at least one data line disposed on the base substrate, the at least one data line being used to supply a data signal to the plurality of pixel units arranged along the second direction, wherein the at least one data line extends along the second direction; and a sensing signal line disposed on the base substrate, the sensing signal line being used to supply a sensing signal to the plurality of pixel units arranged along the second direction, wherein the sensing signal line extends along the second direction. The first scanning signal line includes a plurality of first sub-scanning signal lines, and the plurality of first sub-scanning signal lines extend respectively along the first direction; the second scanning signal line includes a plurality of fourth sub-scanning signal lines, and the plurality of fourth sub-scanning signal lines extend respectively along the first direction; two adjacent first sub-scanning signal lines are spaced apart in the first region, and the positive projections of the sensing signal line and the at least one data line on the substrate substrate do not overlap with the positive projections of the plurality of first sub-scanning signal lines on the substrate substrate, wherein the positive projections of the sensing signal line and the at least one data line on the substrate substrate extend through the positive projection of the first region on the substrate substrate; two adjacent fourth sub-scanning signal lines are spaced apart in the second region, and the positive projections of the sensing signal line and the at least one data line on the substrate substrate do not overlap with the positive projections of the plurality of fourth sub-scanning signal lines on the substrate substrate, wherein the positive projections of the sensing signal line and the at least one data line on the substrate substrate extend through the positive projection of the second region on the substrate substrate; and the first sub-scanning signal line and the first gate are spaced apart in the second direction; the fourth sub-scanning signal line and the third gate are spaced apart in the second direction.

[0007] According to some exemplary embodiments, the display substrate further includes a first scan signal transfer portion provided on the base substrate, the first scan signal transfer portion extending along the second direction; the first sub-scan signal line is electrically connected to the first gate at least through the first scan signal transfer portion, wherein the first scan signal transfer portion and the first sub-scan signal line are located in different layers, and / or the first scan signal transfer portion and the first gate are located in different layers.

[0008] According to some exemplary embodiments, the display substrate further includes a fourth scan signal transfer portion provided on the base substrate, the fourth scan signal transfer portion extending along the second direction; the fourth sub-scan signal line is electrically connected to the third gate at least through the fourth scan signal transfer portion, wherein the fourth scan signal transfer portion and the fourth sub-scan signal line are located in different layers, and / or the fourth scan signal transfer portion and the third gate are located in different layers.

[0009] According to some exemplary embodiments, the first scan signal line also includes a second sub-scan signal line, the second sub-scan signal line extends along the first direction, and the second sub-scan signal line and the first sub-scan signal line are spaced apart in the second direction; the display substrate also includes a first scan signal transfer portion provided on the base substrate, the first scan signal transfer portion extends along the second direction; and the first sub-scan signal line is electrically connected to the second sub-scan signal line through the first scan signal transfer portion.

[0010] According to some exemplary embodiments, the first scanning signal line also includes a third sub-scanning signal line, the third sub-scanning signal line extends along the first direction, the third sub-scanning signal line and the first sub-scanning signal line are spaced apart in the second direction; and the first sub-scanning signal line is electrically connected to the third sub-scanning signal line through the first scanning signal transfer portion.

[0011] According to some exemplary embodiments, the second scan signal line also includes a plurality of fifth sub-scan signal lines, and the plurality of fifth sub-scan signal lines extend respectively along the first direction; the display substrate also includes: a second power signal line arranged on the base substrate, the second power signal line being used to supply a second power signal to a plurality of pixel units arranged along the second direction, wherein the second power signal line extends along the second direction; and adjacent fourth sub-scan signal lines and fifth sub-scan signal lines are spaced apart in the third area, the orthographic projection of the second power signal line on the base substrate does not overlap with the orthographic projection of the plurality of fourth sub-scan signal lines on the base substrate, and the orthographic projection of the second power signal line on the base substrate does not overlap with the orthographic projection of the plurality of fifth sub-scan signal lines on the base substrate, wherein the orthographic projection of the second power signal line on the base substrate extends through the orthographic projection of the third area on the base substrate.

[0012] According to some exemplary embodiments, the display substrate further includes: a first power signal line arranged on the base substrate, the first power signal line being used to supply a first power signal to a plurality of pixel units arranged along a second direction, wherein the first power signal line extends along the second direction; and adjacent fourth sub-scanning signal lines and fifth sub-scanning signal lines being spaced apart in a fourth region, the orthographic projection of the first power signal line on the base substrate not overlapping with the orthographic projection of the plurality of fourth sub-scanning signal lines on the base substrate, and the orthographic projection of the first power signal line on the base substrate not overlapping with the orthographic projection of the plurality of fifth sub-scanning signal lines on the base substrate, wherein the orthographic projection of the first power signal line on the base substrate extends through the orthographic projection of the fourth region on the base substrate.

[0013] According to some exemplary embodiments, a plurality of the fifth sub-scanning signal lines are arranged between two adjacent fourth sub-scanning signal lines, and the plurality of the fifth sub-scanning signal lines arranged between two adjacent fourth sub-scanning signal lines are spaced apart in the second region, and the orthographic projections of the sensing signal line and the at least one data line on the base substrate do not overlap with the orthographic projections of the plurality of the fifth sub-scanning signal lines on the base substrate.

[0014] According to some exemplary embodiments, the second scan signal line also includes a sixth sub-scan signal line, the sixth sub-scan signal line extends along the first direction, and the sixth sub-scan signal line and the fourth sub-scan signal line are spaced apart in the second direction; the display substrate also includes a third scan signal transfer portion provided on the base substrate, the third scan signal transfer portion extends along the second direction; and the fourth sub-scan signal line is electrically connected to the sixth sub-scan signal line through the third scan signal transfer portion.

[0015] According to some exemplary embodiments, the display substrate further includes a fourth scan signal transfer portion disposed on the base substrate, the fourth scan signal transfer portion extending along the second direction; and the sixth sub-scan signal line is electrically connected to the fifth sub-scan signal line through the fourth scan signal transfer portion.

[0016] According to some exemplary embodiments, at least one of the pixel units includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the first sub-pixel is located in the i-th row and the j-th column, the second sub-pixel is located in the i+1-th row and the j-th column, the third sub-pixel is located in the i-th row and the j+1-th column, and the fourth sub-pixel is located in the i+1-th row and the j+1-th column, where i and j are both positive integers greater than or equal to 1; and in the second direction, the first sub-scanning signal line, the second sub-scanning signal line, the third sub-scanning signal line, the fourth scan signal line, the fifth scan signal line and the sixth scan signal line for supplying scan signals to the i-th row sub-pixels and the i+1-th row sub-pixels are all located between the i-th row sub-pixels and the i+1-th row sub-pixels.

[0017] According to some exemplary embodiments, each sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element, the pixel driving circuit includes at least a switching transistor, the switching transistor includes a first active layer; and the orthographic projection of the second sub-scanning signal line on the substrate overlaps with the orthographic projection of the first active layer of the first sub-pixel and the third sub-pixel on the substrate, respectively, and the parts where the second sub-scanning signal line overlaps with the first active layers of the first sub-pixel and the third sub-pixel respectively form the first gates of the switching transistors of the first sub-pixel and the third sub-pixel.

[0018] According to some exemplary embodiments, the orthographic projections of the third sub-scanning signal line on the substrate overlap with the orthographic projections of the first active layers of the second sub-pixel and the fourth sub-pixel on the substrate, respectively, and the portions where the third sub-scanning signal line overlaps with the first active layers of the second sub-pixel and the fourth sub-pixel form the first gates of the switching transistors of the second sub-pixel and the fourth sub-pixel, respectively.

[0019] According to some exemplary embodiments, one of the two adjacent first sub-scan signal lines is electrically connected to the first end of the second sub-scan signal line and the first end of the third sub-scan signal line through the first scan signal conversion portion; and / or, the display substrate further includes a second scan signal conversion portion provided on the base substrate, the second scan signal conversion portion extends along the second direction, and the other of the two adjacent first sub-scan signal lines is electrically connected to the second end of the second sub-scan signal line and the second end of the third sub-scan signal line through the second scan signal conversion portion.

[0020] According to some exemplary embodiments, the pixel driving circuit also includes a sensing transistor, which includes a third active layer; and the orthographic projection of one of the two adjacent fifth sub-scanning signal lines on the substrate partially overlaps with the orthographic projection of the third active layer of the first sub-pixel on the substrate, and the orthographic projection of the other of the two adjacent fifth sub-scanning signal lines on the substrate partially overlaps with the orthographic projection of the third active layer of the third sub-pixel on the substrate, and the parts where the fifth sub-scanning signal line overlaps with the third active layers of the first sub-pixel and the third sub-pixel respectively form the third gates of the sensing transistors of the first sub-pixel and the third sub-pixel.

[0021] According to some exemplary embodiments, the orthographic projections of the sixth sub-scanning signal line on the substrate overlap with the orthographic projections of the third active layer of the second sub-pixel and the fourth sub-pixel on the substrate, respectively, and the portions where the sixth sub-scanning signal line overlaps with the third active layer of the second sub-pixel and the fourth sub-pixel form the third gates of the sensing transistors of the second sub-pixel and the fourth sub-pixel, respectively.

[0022] According to some exemplary embodiments, the display substrate also includes a fifth scan signal transfer portion and a sixth scan signal transfer portion arranged on the base substrate, and the fifth scan signal transfer portion and the sixth scan signal transfer portion both extend along the second direction; the first end of the third scan signal transfer portion is electrically connected to one of the fourth sub-scan signal lines, and the second end of the third scan signal transfer portion is electrically connected to the first end of the sixth sub-scan signal line; the first end of the fourth scan signal transfer portion is electrically connected to the first middle part of the sixth sub-scan signal line, and the second end of the fourth scan signal transfer portion is electrically connected to the first end of one of the fifth sub-scan signal lines; the first end of the fifth scan signal transfer portion is electrically connected to the second middle part of the sixth sub-scan signal line, and the second end of the fifth scan signal transfer portion is electrically connected to the first end of another fifth sub-scan signal line; and the first end of the sixth scan signal transfer portion is electrically connected to another fourth sub-scan signal line, and the second end of the sixth scan signal transfer portion is electrically connected to the second end of the sixth sub-scan signal line.

[0023] According to some exemplary embodiments, in the second direction, the second sub-scanning signal line is located between the i-th row of sub-pixels and the first sub-scanning signal line; and / or, in the second direction, the third sub-scanning signal line is located between the first sub-scanning signal line and the i+1-th row of sub-pixels; and / or, in the second direction, the fourth sub-scanning signal line is located between the first sub-scanning signal line and the i+1-th row of sub-pixels; and / or, in the second direction, the fourth sub-scanning signal line is aligned with the fifth sub-scanning signal line; and / or in the second direction, the sixth sub-scanning signal line is located between the fourth sub-scanning signal line and the third sub-scanning signal line.

[0024] According to some exemplary embodiments, in the first direction, the first scan signal transfer portion is located between the third scan signal transfer portion and the fourth scan signal transfer portion; and / or, in the first direction, the fourth scan signal transfer portion is located between the first scan signal transfer portion and one of the data lines; and / or, in the first direction, the fifth scan signal transfer portion is located between another of the data lines and the second scan signal transfer portion; and / or, in the first direction, the sixth scan signal transfer portion is located on a side of the first power signal line away from the second scan signal transfer portion.

[0025] According to some exemplary embodiments, the orthographic projections of the sensing signal line and the at least one data line on the base substrate respectively overlap with the orthographic projections of at least one second sub-scanning signal line on the base substrate; and / or the orthographic projections of the sensing signal line and the at least one data line on the base substrate respectively overlap with the orthographic projections of at least one third sub-scanning signal line on the base substrate.

[0026] According to some exemplary embodiments, orthographic projections of the sensing signal line and the at least one data line on the base substrate respectively overlap with orthographic projections of at least one sixth sub-scanning signal line on the base substrate.

[0027] According to some exemplary embodiments, the display substrate includes: a semiconductor layer arranged on the base substrate, wherein the first active layer and the third active layer are both located in the semiconductor layer; a second conductive layer arranged on a side of the semiconductor layer away from the base substrate; and a third conductive layer arranged on a side of the second conductive layer away from the base substrate, wherein the first sub-scanning signal line, the second sub-scanning signal line, the third sub-scanning signal line, the fourth scan signal line, the fifth scan signal line and the sixth scan signal line are all located in the second conductive layer, and the first scan signal switching portion, the second scan signal switching portion, the third scan signal switching portion, the fourth scan signal switching portion, the fifth scan signal switching portion and the sixth scan signal switching portion are all located in the third conductive layer.

[0028] According to some exemplary embodiments, the display substrate further includes a first conductive portion located in the second conductive layer, the pixel driving circuit further includes a driving transistor, the driving transistor includes a second active layer, the orthographic projection of the first conductive portion on the base substrate partially overlaps with the orthographic projection of the second active layer on the base substrate, and the overlapping portion of the first conductive portion and the second active layer forms the second gate of the driving transistor; and the display substrate further includes a first conductive transition portion located in the third conductive layer and a first power signal transition portion located in the second conductive layer, the first end of the first voltage signal transition portion is electrically connected to the first power signal line, the second end of the first voltage signal transition portion is electrically connected to the first end of the first conductive transition portion, and the second end of the first conductive transition portion is electrically connected to the first end of the second active layer.

[0029] According to some exemplary embodiments, the display substrate further includes a second conductive transition portion located in the third conductive layer, a first end of the second conductive transition portion is electrically connected to the first conductive portion, a second end of the second conductive transition portion is electrically connected to the first end of the first active layer, and a second end of the first active layer is electrically connected to one of the data lines.

[0030] According to some exemplary embodiments, the display substrate further includes a second conductive portion located in the third conductive layer, the second conductive portion including a conductive main body portion, a first conductive connecting portion and a second conductive connecting portion, the first conductive connecting portion and the second conductive connecting portion respectively protruding outward from the conductive main body portion; and the first conductive connecting portion is electrically connected to the second end of the second active layer, and the second conductive connecting portion is electrically connected to the first end of the third active layer.

[0031] According to some exemplary embodiments, the display substrate further includes a first conductive layer located on a side of the semiconductor layer close to the base substrate; the display substrate further includes a sensing signal transfer portion located in the first conductive layer, the sensing signal transfer portion extending along a first direction, and an orthographic projection of the sensing signal transfer portion on the base substrate partially overlaps with an orthographic projection of the sensing signal line on the base substrate.

[0032] According to some exemplary embodiments, the third active layers of the sensing transistors of the first sub-pixel and the second sub-pixel are connected as one, and the third active layers connected as one extend along the second direction; and the display substrate also includes a third conductive transition portion located in the third conductive layer, the sensing signal line is electrically connected to the sensing signal transition portion, the first end of the sensing signal transition portion is electrically connected to the first end of the third conductive transition portion, and the second end of the third conductive transition portion is electrically connected to the middle portion of the third active layer.

[0033] According to some exemplary embodiments, the pixel driving circuit also includes a storage capacitor, the storage capacitor includes a first capacitor and a second capacitor, and the second capacitor is connected in parallel with the first capacitor; the display substrate also includes a third conductive part located in the first conductive layer, and the positive projections of any two of the first conductive part, the second conductive part and the third conductive part on the base substrate at least partially overlap, the second conductive part and the third conductive part are electrically connected, the overlapping part of the first conductive part and the second conductive part forms the first capacitor, and the overlapping part of the first conductive part and the third conductive part forms the second capacitor.

[0034] In another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0036] FIG1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0037] 2A is an equivalent circuit diagram of a pixel driving circuit of a plurality of sub-pixels of the display substrate in FIG. 1 , and FIG. 2B is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in FIG. 1 ;

[0038] 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, schematically illustrating a plan view of a pixel driving circuit of a plurality of sub-pixels included in the display substrate;

[0039] FIG4 to FIG8 are plan views of one or more film layers shown in FIG3, wherein:

[0040] FIG4 shows a portion of the first conductive layer 1;

[0041] FIG5 shows a portion of the first conductive layer 1 and the semiconductor layer 8;

[0042] FIG6 shows a portion of the second conductive layer 2;

[0043] FIG7 also shows a portion of the second conductive layer 2 , a portion of the first conductive layer 1 , and a portion of the semiconductor layer 8 ;

[0044] FIG8 shows a portion of the third conductive layer 3;

[0045] 9 is a partial plan view of a display substrate according to some embodiments of the present disclosure, showing a plurality of vias, and also showing lines AA′, BB′, and CC′;

[0046] FIG10 is a schematic cross-sectional view taken along line AA′ in FIG9 ;

[0047] 11 is a schematic cross-sectional view taken along line BB' and line CC' according to FIG. 9 , wherein the left side of SS' is a schematic cross-sectional view taken along line BB', and the right side of SS' is a schematic cross-sectional view taken along line CC'.

[0048] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0050] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0051] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0052] Unless otherwise specified, directional terms such as "upper," "lower," "left," "right," "inner," and "outer" are used herein to indicate positions or relationships based on the figures shown. These terms are intended solely to facilitate the description of the present disclosure and are not intended to indicate or imply that the devices, components, or parts referred to must have, be constructed, or operate in a specific orientation. It should be understood that when the absolute positions of the objects being described change, the relative positions they represent may also change accordingly. Therefore, these directional terms should not be construed as limiting the present disclosure.

[0053] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0054] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0055] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the longitudinal and transverse directions of a pixel unit, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0056] Some exemplary embodiments of the present disclosure provide a display substrate, the display substrate comprising: a base substrate; a plurality of pixel units disposed on the base substrate, each pixel unit comprising a plurality of sub-pixels, the plurality of pixel units being arranged in an array on the base substrate along a first direction and a second direction, wherein at least one sub-pixel comprises a light-emitting element and a pixel driving circuit for driving the light-emitting element, the pixel driving circuit comprising a switching transistor and a sensing transistor, the switching transistor comprising a first gate, the sensing transistor comprising a third gate, the first direction and the second direction intersecting; a first scanning signal line disposed on the base substrate, the first scanning signal line being used to supply a first scanning signal to the plurality of pixel units arranged along the first direction; a second scanning signal line disposed on the base substrate, the second scanning signal line being used to supply a second scanning signal to the plurality of pixel units arranged along the first direction; at least one data line disposed on the base substrate, the at least one data line being used to supply a data signal to the plurality of pixel units arranged along the second direction, wherein the at least one data line extends along the second direction; and a sensing signal line disposed on the base substrate, the sensing signal line being used to supply a sensing signal to the plurality of pixel units arranged along the second direction, wherein the sensing signal line extends along The first scanning signal line includes a plurality of first sub-scanning signal lines, and the plurality of first sub-scanning signal lines extend respectively along the first direction; the second scanning signal line includes a plurality of fourth sub-scanning signal lines, and the plurality of fourth sub-scanning signal lines extend respectively along the first direction; two adjacent first sub-scanning signal lines are spaced apart in the first region, and the orthographic projections of the sensing signal line and the at least one data line on the substrate do not overlap with the orthographic projections of the plurality of first sub-scanning signal lines on the substrate, wherein the orthographic projections of the sensing signal line and the at least one data line on the substrate extend through the orthographic projection of the first region on the substrate; two adjacent fourth sub-scanning signal lines are spaced apart in the second region, and the orthographic projections of the sensing signal line and the at least one data line on the substrate do not overlap with the orthographic projections of the plurality of fourth sub-scanning signal lines on the substrate, wherein the orthographic projections of the sensing signal line and the at least one data line on the substrate extend through the orthographic projection of the second region on the substrate; and the first sub-scanning signal line and the first gate are spaced apart in the second direction; the fourth sub-scanning signal line and the third gate are spaced apart in the second direction.In this way, on the one hand, the length of the gate line can be shortened, reducing the probability of electrostatic breakdown at the end of the gate line overlapping with the active layer, resulting in a short circuit between the gate and the active layer; on the other hand, the overlapping area between the gate and the source and drain can be reduced, reducing the probability of data line and gate line short circuit (Data-Gate Short, DGS defect), thereby reducing the probability of point defects and line defects on the display substrate, and improving the quality and yield of display products.

[0057] FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.

[0058] 1 , a display substrate according to an embodiment of the present disclosure may include a base substrate 100, a pixel unit PX disposed on the base substrate 100, a driving unit DRU disposed on the base substrate 100, and a trace PL electrically connecting the pixel unit PX to the driving unit DRU, wherein the driving unit DRU is used to drive the pixel unit PX.

[0059] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where a pixel unit PX displaying an image is provided. Each pixel unit PX will be described later. The non-display area NA is an area where no pixel unit PX is provided, that is, it may be an area where no image is displayed. A driving unit DRU for driving the pixel unit PX and some traces PL connecting the pixel unit PX to the driving unit DRU may be provided in the non-display area NA. The non-display area NA corresponds to a border in the final display device, and the width of the border may be determined based on the width of the non-display area NA.

[0060] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0061] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0062] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0063] The pixel units PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0064] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include three sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit PX may include four sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel.

[0065] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, a first sub-pixel SP1 may include a first light-emitting element located in a first light-emitting area SPA1 and a first pixel driving circuit SPC1 for driving the first light-emitting element. The first light-emitting element may emit red light. A second sub-pixel SP2 may include a second light-emitting element located in a second light-emitting area SPA2 and a second pixel driving circuit SPC2 for driving the second light-emitting element. The second light-emitting element may emit green light. A third sub-pixel SP3 may include a third light-emitting element located in a third light-emitting area SPA3 and a third pixel driving circuit SPC3 for driving the third light-emitting element. The third light-emitting element may emit blue light.

[0066] The light-emitting region of a sub-pixel may be the region where the light-emitting element of the sub-pixel is located. For example, in an OLED display panel, the light-emitting element of a sub-pixel may include a first electrode (e.g., an anode), a light-emitting material layer, and a second electrode (e.g., a cathode) in a stacked arrangement. Thus, the light-emitting region of a sub-pixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and cathode.

[0067] The sub-pixel also includes a non-emissive area. For example, the pixel driver circuit of the sub-pixel is located in the non-emissive area of ​​the sub-pixel. The ratio of the area of ​​the emissive area of ​​each sub-pixel to the overall area of ​​the sub-pixel (the sum of the areas of the emissive and non-emissive areas) determines the aperture ratio of the sub-pixel.

[0068] The light-emitting device of the OLED (e.g., the light-emitting layer, referred to as the EL layer) may not have good enough consistency during production. For example, when the EL layer is produced by an evaporation process, the limitations of the evaporation process lead to inconsistencies in the EL layers of the produced sub-pixels, resulting in uneven brightness or chromaticity between different sub-pixels. Moreover, as the use time increases, the EL layer will age to varying degrees, which will also lead to inconsistencies in the EL layers of the sub-pixels, resulting in uneven brightness or chromaticity between different sub-pixels. In an embodiment of the present disclosure, the display substrate may further include a photosensitive circuit OSC, which can sense the light actually emitted by the pixel unit. Thus, in an embodiment of the present disclosure, the display substrate can perform optical compensation on the sub-pixels within each pixel unit based on the light actually emitted by the pixel unit sensed by the photosensitive circuit OSC, so as to improve the uniformity of the light emission of the display substrate.

[0069] For example, in some exemplary embodiments of the present disclosure, a light measuring circuit OSC is provided in each pixel unit PX, and each light measuring circuit OSC senses the light actually emitted by the pixel unit PX where it is located.

[0070] For example, in an embodiment of the present disclosure, at least two pixel units PX can share a photosensitive circuit OSC. Referring to Figure 1, among the pixel units in the same column, two pixel units PX located in two adjacent rows can share a photosensitive circuit OSC. In this way, there is no need to set a photosensitive circuit for each pixel unit PX, which can reduce the number of photosensitive circuits and thus improve the aperture ratio. When the display substrate is in a display state, the photosensitive circuit OSC can sense the light actually emitted by the two pixel units adjacent to it. For example, the photosensitive circuit OSC can include at least a photoelectric conversion element. In this way, the photosensitive circuit OSC can be configured to: sense the light actually emitted by the two pixel units adjacent to it; and send a sensing electrical signal based on the sensed light.

[0071] For another example, referring to FIG1 , the light sensing circuit OSC can transmit the sensing electrical signal to an external circuit, such as a control IC of a display device. The control IC can control the control signal sent to the pixel unit PX based on the sensing electrical signal. For example, the control IC can control the data signal (i.e., data signal) sent to the pixel driving circuit of each sub-pixel. Under the control of the data signal, each sub-pixel emits light accordingly.

[0072] In the embodiment shown in FIG. 1 , the sub-pixels SP1 , SP2 , and SP3 are arranged side by side, and each sub-pixel SP1 , SP2 , and SP3 has its own data line DL.

[0073] Figure 2A is an equivalent circuit diagram of a pixel driving circuit for multiple sub-pixels of the display substrate in Figure 1 , and Figure 2B is an equivalent circuit diagram of a pixel driving circuit for a single sub-pixel of the display substrate in Figure 1 . The pixel driving circuit shown in Figure 2B can be any of the aforementioned pixel driving circuits SPC1, SPC2, and SPC3. Referring to Figures 2A and 2B , the pixel driving circuit can include multiple components, such as a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst. This pixel driving circuit can be referred to as a 3T1C structure.

[0074] It should be noted that the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is described here using the 3T1C structure as an example, but the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is not limited to the 3T1C structure.

[0075] Continuing with FIG2B , the gate of the switching transistor T1 is connected to the first scanning signal line GL1, the first electrode of the switching transistor T1 is connected to the data line DL, and the second electrode of the switching transistor T1 is connected to the gate of the driving transistor T2. For example, the second electrode of the switching transistor T1 and the gate of the driving transistor T2 can both be electrically connected to the node GN. The switching transistor T1 is used to control the writing of the voltage signal from the data line DL into the pixel driving circuit.

[0076] It should be noted that each transistor may include an active layer, a gate, a first electrode (e.g., a source electrode), and a second electrode (e.g., a drain electrode). For example, the switching transistor T1 includes a first gate G1 and a first active layer ACT1; the driving transistor T2 includes a second gate G2 and a second active layer ACT2; and the sensing transistor T3 includes a third gate G3 and a third active layer ACT3. In the embodiments of the present disclosure, the active layer of the transistor may be located in a semiconductor layer, and the gate may be located in a different conductive layer.

[0077] It should be noted that, in this document, the first electrode of the transistor may refer to one of the source and the drain of the transistor, and the second electrode of the transistor may refer to the other of the source and the drain of the transistor.

[0078] The gate of the driving transistor T2 is electrically connected to the node GN. The first electrode of the driving transistor T2 is connected to a first power supply signal (e.g., a high voltage level signal VDD). The second electrode of the driving transistor T2 can be connected to the anode of the light-emitting element D1, thereby generating a driving current based on the voltage signal to drive the light-emitting element D1 to emit light. For example, the light-emitting element D1 can be an organic light-emitting diode (OLED).

[0079] The two ends of the storage capacitor Cst are respectively connected to the gate and source of the driving transistor T2, and are used to store the voltage signal input from the data line. For example, one end of the storage capacitor Cst is electrically connected to the node GN, and the other end of the storage capacitor Cst is electrically connected to the node SN. In other words, one end of the storage capacitor Cst, the second electrode of the switching transistor T1, and the gate of the driving transistor T2 are all electrically connected to the node GN, and the other end of the storage capacitor Cst, the second electrode of the driving transistor T2, and the anode of the light-emitting element D1 are all electrically connected to the node SN.

[0080] A gate of the sensing transistor T3 is connected to the second scan signal line GL2 , a first electrode of the sensing transistor T3 is connected to the sensing signal line SL, and a second electrode of the sensing transistor T3 is electrically connected to the node SN.

[0081] The anode of the light emitting element D1 is electrically connected to the node SN, and the cathode of the light emitting element D1 is electrically connected to the low voltage level signal VSS. The level signals VDD and VSS are both DC voltage signals for providing the necessary voltage to drive the light emitting element D1 to emit light.

[0082] Figure 3 is a partial plan view of a display substrate according to some embodiments of the present disclosure, schematically illustrating a plan view of a pixel driving circuit for a plurality of sub-pixels included in the display substrate. Figures 4 to 8 are plan views of one or more film layers shown in Figure 3 , respectively.

[0083] With reference to Figures 3 to 8 , the display substrate may include multiple conductive layers, a semiconductor layer, and multiple insulating layers. For ease of description, the multiple conductive layers are described as a first conductive layer, a second conductive layer, and a third conductive layer. For example, Figure 4 shows a portion of the first conductive layer 1. Figure 5 shows a portion of the first conductive layer 1 and a portion of the semiconductor layer 8, illustrating the spatial relationship between the orthographic projections of the portion of the first conductive layer 1 and the portion of the semiconductor layer 8 perpendicular to the substrate. It should be noted that a portion of the semiconductor layer 8 may have semiconductor properties to form the channel region of each transistor, while other portions of the semiconductor layer 8 may be conductive to form the source region, drain region, and other conductive portions of each transistor. Figure 6 shows a portion of the second conductive layer 2. The gates of some transistors, the first scan signal line GL1, and the like may be located in the second conductive layer 2. For example, the second conductive layer 2 may be a conductive layer composed of gate material. In addition to Figures 5 and 6 , Figure 7 also illustrates the spatial relationship between the orthographic projections of the second conductive layer 2, the first conductive layer 1, and the semiconductor layer 8 perpendicular to the substrate. Figure 8 shows a portion of the third conductive layer 3. The third conductive layer 3 may be a film layer where multiple data lines DL1, DL2, DL3, DL4, a first power signal line VDDL, a second power signal line VSSL, a sense signal line SL, etc. are located. That is, it may be a conductive layer composed of source and drain electrode materials. Figure 3 also shows multiple vias that expose a portion of the first conductive layer 1, a portion of the semiconductor layer 8, and a portion of the second conductive layer 9. The multiple vias can be used to form an electrical connection between a portion of the first conductive layer 1 and a portion of the third conductive layer 3, and / or to form an electrical connection between a portion of the semiconductor layer 8 and a portion of the third conductive layer 3, and / or to form an electrical connection between the second conductive layer 2 and a portion of the third conductive layer 3.

[0084] For example, the first conductive layer 1, semiconductor layer 8, second conductive layer 2, and third conductive layer 3 may be stacked sequentially on a base substrate of a display substrate. Specifically, the first conductive layer 1 may be disposed on the base substrate, the semiconductor layer 8 may be disposed on a side of the first conductive layer 1 away from the base substrate, the second conductive layer 2 may be disposed on a side of the semiconductor layer 8 away from the base substrate, and the third conductive layer 3 may be disposed on a side of the second conductive layer 2 away from the base substrate. The stacking relationship of the various film layers will be described in more detail below with reference to cross-sectional views.

[0085] It should be understood that the display substrate may further include multiple insulating layers between any adjacent two of the base substrate, the first conductive layer 1, the semiconductor layer 8, the second conductive layer 2, and the third conductive layer 3. These insulating layers will be described below with reference to cross-sectional views. Vias or grooves exposing at least a portion of one of the first conductive layer 1, the semiconductor layer 8, the second conductive layer 2, and the third conductive layer 3 may be formed in the insulating layers to enable electrical connection between components located between the different layers.

[0086] For example, the display substrate may include a plurality of signal lines. Referring to FIG. 2B and FIG. 3 , the plurality of signal lines may include a first scan signal line GL1, a second scan signal line GL2, a data line DL, a first power signal line VDDL, and a sensing signal line SL. The first power signal line VDDL, the sensing signal line SL, and the data line DL may be located in the third conductive layer 3, and the first scan signal line GL1 and the second scan signal line GL2 may be located in the second conductive layer 2.

[0087] In some exemplary embodiments of the present disclosure, with reference to Figures 3 and 6, a portion of the first scan signal line GL1 may extend substantially along a first direction X, and the first scan signal line GL1 is used to supply a first scan signal to a plurality of pixel units arranged along the first direction X. For example, the first scan signal line GL1 may supply a first scan signal to a first sub-pixel SP1 and a third sub-pixel SP3. At least one data line DL is provided on the substrate, and the at least one data line DL is used to supply a data signal to a plurality of pixel units arranged along a second direction Y, wherein the at least one data line DL extends along the second direction Y. A sensing signal line SL is provided on the substrate, and the sensing signal line SL is used to supply a sensing signal to a plurality of pixel units arranged along the second direction. The sensing signal is detected by the sensing signal line SL, wherein the sensing signal line SL extends along the second direction Y, wherein the first scanning signal line GL1 includes a plurality of first sub-scanning signal lines GL11, and the plurality of first sub-scanning signal lines GL11 respectively extend along the first direction X; two adjacent first sub-scanning signal lines GL11 are spaced apart in the first area S1, and the orthographic projections of the sensing signal line SL and the at least one data line, such as the first data line DL1, on the base substrate do not overlap with the orthographic projections of the plurality of first sub-scanning signal lines GL11 on the base substrate, wherein the orthographic projections of the sensing signal line SL and the at least one data line, such as the first data line DL1, on the base substrate extend through the orthographic projection of the first area S1 on the base substrate.

[0088] In an exemplary embodiment, the plurality of first sub-scanning signal lines GL11 are aligned in the second direction Y.

[0089] In the above embodiment, the first scanning signal line GL1 adopts a multi-segment design and is arranged at intervals in the middle of the first area S1, which can reduce the overlapping area between the first scanning signal line GL1 and the sensing signal line SL and at least one data line DL, such as the first data line DL1, and reduce the probability of short circuit defects between the first scanning signal line GL1 and the sensing signal line SL and at least one data line DL, thereby reducing the probability of defects in the display substrate and improving the quality and yield of the display product.

[0090] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 6, the display substrate may further include: a second scanning signal line GL2 arranged on the base substrate, the second scanning signal line GL2 being used to supply a second scanning signal to a plurality of pixel units arranged along the first direction, for example, the second scanning signal line GL2 supplies a second scanning signal to the second sub-pixel SP2 and the fourth sub-pixel SP4; the second scanning signal line GL2 includes a plurality of fourth sub-scanning signal lines GL24, and the plurality of fourth sub-scanning signal lines GL24 extend respectively along the first direction X; two adjacent fourth sub-scanning signal lines GL24 are spaced apart in the second area S2, and the orthographic projections of the sensing signal line SL and the at least one data line, for example, the first data line DL1, on the base substrate do not overlap with the orthographic projections of the plurality of fourth sub-scanning signal lines GL24 on the base substrate, wherein the orthographic projections of the sensing signal line SL and the at least one data line, for example, the first data line DL1, on the base substrate extend through the orthographic projection of the second area S2 on the base substrate. The second scanning signal line GL2 adopts a multi-segment design and is arranged at intervals in the middle of the second area S2, which can reduce the overlapping area between the second scanning signal line GL2 and the sensing signal line SL and at least one data line DL, and reduce the probability of short circuit defects between the second scanning signal line GL2 and the sensing signal line SL and at least one data line DL, thereby reducing the probability of defects in the display substrate and improving the quality and yield of the display product.

[0091] In an exemplary embodiment, the plurality of fourth sub-scanning signal lines GL24 are aligned in the second direction Y.

[0092] In some exemplary embodiments of the present disclosure, with reference to FIG3 and FIG6 , the first scan signal line GL1 may further include a second sub-scan signal line GL12, the second sub-scan signal line GL12 extending along a first direction X, and spaced apart from the first sub-scan signal line GL11 in a second direction Y. The display substrate further includes a first scan signal transfer portion 31 disposed on the base substrate, the first scan signal transfer portion 31 extending along the second direction Y. The first sub-scan signal line GL11 is electrically connected to the second sub-scan signal line GL12 via the first scan signal transfer portion 31. The electrical connection via the first scan signal transfer portion 31 allows for serial connection of multiple sub-scan signal lines of the first scan signal line, effectively transmitting scan signals while shortening the design length of the first sub-scan signal line GL11 and / or the second sub-scan signal line GL12 in the first direction X. This reduces the probability of a gate-to-active layer short circuit when the first scan signal line GL1 forms a gate in an overlapping region with a portion of the active layer 8, thereby improving the quality and yield of display products.

[0093] In some exemplary embodiments, the orthographic projections of the sensing signal line SL and the at least one data line DL1 and DL3 on the base substrate respectively overlap with the orthographic projection of the at least one second sub-scanning signal line GL12 on the base substrate. For example, the orthographic projection of the at least one second sub-scanning signal line GL12 on the base substrate extends through the orthographic projections of the sensing signal line SL and the at least one data line DL1 and DL3 on the base substrate.

[0094] In some exemplary embodiments of the present disclosure, with reference to FIG3 and FIG6 , the first scan signal line GL1 may further include a third sub-scan signal line GL13, the third sub-scan signal line GL13 extending along the first direction X, the third sub-scan signal line GL13 and the first sub-scan signal line GL11 being spaced apart in the second direction Y; and the first sub-scan signal line GL11 being electrically connected to the third sub-scan signal line GL13 via the first scan signal adapter 31. The electrical connection via the first scan signal adapter 31 enables the serial connection of multiple sub-scan signal lines of the first scan signal line, thereby effectively transmitting scan signals and shortening the design length of the first sub-scan signal line GL11 and / or the third sub-scan signal line GL13 in the first direction X. This reduces the probability of a gate-to-active layer short circuit when the first scan signal line GL1 forms a gate in an overlapping region with a portion of the active layer 8, thereby improving the quality and yield of display products.

[0095] In some exemplary embodiments, the orthographic projections of the sensing signal line SL and the at least one data line DL1, DL3 on the base substrate respectively overlap with the orthographic projection of the at least one third sub-scanning signal line GL13 on the base substrate. For example, the orthographic projection of the at least one third sub-scanning signal line GL13 on the base substrate extends through the orthographic projections of the sensing signal line SL and the at least one data line DL1, DL3 on the base substrate.

[0096] In some exemplary embodiments of the present disclosure, with reference to Figures 3 and 6, the second scan signal line GL2 may further include a plurality of fifth sub-scan signal lines GL25, and the plurality of fifth sub-scan signal lines GL25 respectively extend along the first direction X; the display substrate further includes: a second power signal line VSSL provided on the base substrate, the second power signal line VSSL being used to supply a second power signal to a plurality of pixel units arranged along the second direction Y, for example, the second power signal line VSSL supplies a second power signal to a first sub-pixel SP1 and a second sub-pixel SP2 arranged along the second direction Y, wherein the second power signal line VSSL extends along the first direction Y. The second scanning signal line GL2 is arranged in a multi-segment design and spaced apart in the middle of the third region S3. The fourth sub-scanning signal line GL24 and the fifth sub-scanning signal line GL25 are adjacently arranged in the third region S3. The orthographic projection of the second power signal line VSSL on the substrate does not overlap with the orthographic projections of the plurality of fourth sub-scanning signal lines GL24 on the substrate, and the orthographic projection of the second power signal line VSSL on the substrate does not overlap with the orthographic projections of the plurality of fifth sub-scanning signal lines GL25 on the substrate. The orthographic projection of the second power signal line VSSL on the substrate extends through the orthographic projection of the third region S3 on the substrate. The second scanning signal line GL2 is designed to be multi-segmented and spaced apart in the middle of the third region S3. This reduces the overlap between the second scanning signal line GL2 and the second power signal line VSSL and at least one data line DL, such as the first data line DL2, and reduces the probability of a short circuit between the second scanning signal line GL2, the second power signal line VSSL, and the at least one data line DL. This reduces the probability of a display substrate defect and improves the quality and yield of display products.

[0097] In an exemplary embodiment, the plurality of fifth sub-scanning signal lines GL25 are aligned in the second direction Y.

[0098] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 6, the display substrate may further include: a first power signal line VDDL arranged on the base substrate, the first power signal line VDDL being used to supply a first power signal to a plurality of pixel units arranged along the second direction Y, wherein the first power signal line VDDL extends along the second direction Y; and the adjacent fourth sub-scanning signal line GL24 and the fifth sub-scanning signal line GL25 being spaced apart in the fourth area S4, the orthographic projection of the first power signal line VDDL on the base substrate not overlapping with the orthographic projection of the plurality of fourth sub-scanning signal lines GL24 on the base substrate, and the orthographic projection of the first power signal line VDDL on the base substrate not overlapping with the orthographic projection of the plurality of fifth sub-scanning signal lines GL25 on the base substrate, wherein the orthographic projection of the first power signal line VDDL on the base substrate extends through the orthographic projection of the fourth area S4 on the base substrate. The second scanning signal line GL2 adopts a multi-segment design and is arranged at intervals in the middle of the fourth area S4, which can reduce the overlapping area between the second scanning signal line GL2 and the second power signal line VSSL and at least one data line DL, such as the fourth data line DL4, and reduce the probability of short circuit defects between the second scanning signal line GL2 and the first power signal line VDDL and at least one data line DL, thereby reducing the probability of defects in the display substrate and improving the quality and yield of the display product.

[0099] In some exemplary embodiments of the present disclosure, with reference to FIG3 and FIG6 , a plurality of fifth sub-scanning signal lines GL25 may be provided between two adjacent fourth sub-scanning signal lines GL24. The plurality of fifth sub-scanning signal lines GL25 provided between the two adjacent fourth sub-scanning signal lines GL24 are spaced apart in the second region S2. The orthographic projections of the sensing signal line SL and the at least one data line DL, such as the first data line DL1, on the substrate do not overlap with the orthographic projections of the plurality of fifth sub-scanning signal lines GL25 on the substrate. The fifth sub-scanning signal lines GL25 are designed in multiple segments and spaced apart in the middle of the second region S2. This can reduce the overlap between the fifth sub-scanning signal lines GL25 and the sensing signal lines SL and the at least one data line DL, thereby reducing the probability of a short circuit defect between the second scanning signal line GL2 and the sensing signal line SL and the at least one data line DL, thereby reducing the probability of a defective display substrate and improving the quality and yield of display products.

[0100] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 6, the second scan signal line GL2 may further include a sixth sub-scan signal line GL26, the sixth sub-scan signal line GL26 extends along the first direction X, and the sixth sub-scan signal line GL26 and the fourth sub-scan signal line GL24 are spaced apart in the second direction Y; the display substrate also includes a third scan signal transfer portion 33 provided on the base substrate, the third scan signal transfer portion 33 extends along the second direction Y; and the fourth sub-scan signal line GL24 is electrically connected to the sixth sub-scan signal line GL26 through the third scan signal transfer portion 33. Through the electrical connection of the third scanning signal switching part 33, the sub-scanning signal lines of multiple segmented second scanning signal lines can be connected in series, which can not only better complete the transmission of the scanning signal, but also shorten the design length of the fourth sub-scanning signal line GL24 and / or the sixth sub-scanning signal line GL26 in the first direction X, thereby reducing the probability of a short circuit between the gate and the active layer when the second scanning signal line GL2 forms a gate in the overlapping area with a part of the active layer 8, thereby improving the quality and yield of the display product.

[0101] In some exemplary embodiments, the orthographic projections of the sensing signal line SL and the at least one data line DL1, DL3 on the base substrate respectively overlap with the orthographic projection of the at least one sixth sub-scanning signal line GL26 on the base substrate. For example, the orthographic projection of the at least one sixth sub-scanning signal line GL26 on the base substrate extends through the orthographic projections of the sensing signal line SL and the at least one data line DL1, DL3 on the base substrate.

[0102] In some exemplary embodiments of the present disclosure, with reference to FIG3 and FIG6 , the display substrate may further include a fourth scan signal transfer portion 34 disposed on the base substrate, the fourth scan signal transfer portion 34 extending along the second direction Y; and the sixth sub-scan signal line GL26 is electrically connected to the fifth sub-scan signal line GL25 via the fourth scan signal transfer portion 34. Through the electrical connection of the fourth scan signal transfer portion 34, a plurality of sub-scan signal lines of the second scan signal line segmented can be connected in series, thereby effectively completing the transmission of the scan signal and shortening the design length of the fifth sub-scan signal line GL25 and / or the sixth sub-scan signal line GL26 in the first direction X, thereby reducing the probability of a gate-to-active layer short circuit when the second scan signal line GL2 forms a gate in an overlapping region with a portion of the active layer 8, thereby improving the quality and yield of the display product.

[0103] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 6, at least one of the pixel units may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3 and a fourth sub-pixel SP4, the first sub-pixel SP1 is located at the i-th row and the j-th column, the second sub-pixel SP2 is located at the i+1-th row and the j-th column, the third sub-pixel SP3 is located at the i-th row and the j+1-th column, and the fourth sub-pixel SP4 is located at the i+1-th row and the j+1-th column, where i and j are both positive integers greater than or equal to 1; and in the second direction Y, the first sub-scanning signal line GL11, the second sub-scanning signal line GL12, the third sub-scanning signal line GL13, the fourth scan signal line GL24, the fifth scan signal line GL25 and the sixth scan signal line GL26 for supplying scan signals to the i-th row sub-pixels and the i+1-th row sub-pixels are all located between the i-th row sub-pixels and the i+1-th row sub-pixels. The multiple sub-pixels can respectively emit one of red light, green light, blue light or white light. The embodiments of the present disclosure do not impose any special limitation on the light-emitting color of each sub-pixel.

[0104] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 7, each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element, the pixel driving circuit at least including a switching transistor T1, the switching transistor T1 including a first active layer ACT1; and the orthographic projections of the second sub-scanning signal line GL12 on the substrate overlap with the orthographic projections of the first active layer ACT1 of the first sub-pixel SP1 and the third sub-pixel SP3 on the substrate, respectively, and the parts where the second sub-scanning signal line GL12 overlaps with the first active layers of the first sub-pixel SP1 and the third sub-pixel SP3 respectively form the first gates G1 of the switching transistors T1 of the first sub-pixel and the third sub-pixel.

[0105] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 7, the orthographic projections of the third sub-scanning signal line GL13 on the base substrate overlap with the orthographic projections of the first active layer ACT1 of the second sub-pixel SP2 and the fourth sub-pixel SP4 on the base substrate, respectively, and the parts where the third sub-scanning signal line GL13 overlaps with the first active layer ACT1 of the second sub-pixel SP2 and the fourth sub-pixel SP4 respectively form the first gate G1 of the switching transistor T1 of the second sub-pixel and the fourth sub-pixel.

[0106] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 6, one of the two adjacent first sub-scan signal lines GL11 is electrically connected to the first end of the second sub-scan signal line GL12 and the first end of the third sub-scan signal line GL13 through the first scan signal conversion portion 31; and / or, the display substrate also includes a second scan signal conversion portion 32 arranged on the base substrate, the second scan signal conversion portion 32 extends along the second direction Y, and the other of the two adjacent first sub-scan signal lines GL11 is electrically connected to the second end of the second sub-scan signal line GL12 and the second end of the third sub-scan signal line GL13 through the second scan signal conversion portion 32. Through the electrical connection between the first scanning signal switching part 31 and the second scanning signal switching part 32, the sub-scanning signal lines of multiple segmented first scanning signal lines can be connected in series, which can not only better complete the transmission of the scanning signal, but also shorten the design length of the first sub-scanning signal line GL11, and / or the second sub-scanning signal line GL12, and / or the third sub-scanning signal line GL13 in the first direction X, reduce the probability of a short circuit between the gate and the active layer when the first scanning signal line GL1 forms a gate in an overlapping area with a part of the active layer 8, and / or reduce the overlapping area between the first scanning signal line GL1 and at least one data line or sensing signal line, reduce the probability of a short circuit between the gate and the source and drain, and improve the quality and yield of the display product.

[0107] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 7, the pixel driving circuit may further include a sensing transistor T3, the sensing transistor T3 including a third active layer ACT3; and the orthographic projection of one of the two adjacent fifth sub-scanning signal lines GL25 on the substrate partially overlaps with the orthographic projection of the third active layer ACT3 of the first sub-pixel SP1 on the substrate, and the orthographic projection of the other of the two adjacent fifth sub-scanning signal lines GL25 on the substrate partially overlaps with the orthographic projection of the third active layer ACT3 of the third sub-pixel on the substrate, and the parts where the fifth sub-scanning signal line GL25 overlaps with the third active layer ACT3 of the first sub-pixel and the third sub-pixel respectively form the third gate G3 of the sensing transistor T3 of the first sub-pixel and the third sub-pixel.

[0108] In some exemplary embodiments of the present disclosure, referring to FIG7 , the orthographic projection of the sixth sub-scanning signal line GL26 on the base substrate partially overlaps with the orthographic projections of the third active layer ACT3 of the second sub-pixel SP2 and the fourth sub-pixel SP4 on the base substrate, respectively. The portions where the sixth sub-scanning signal line GL26 overlaps with the third active layer ACT3 of the second sub-pixel SP2 and the fourth sub-pixel SP4 form the third gates G3 of the sensing transistors T3 of the second sub-pixel SP2 and the fourth sub-pixel SP4, respectively. The third active layer ACT3 of the second sub-pixel SP2 and the fourth sub-pixel SP4 may be the same active layer as the third active layer ACT3 of the first sub-pixel and the third sub-pixel.

[0109] In some exemplary embodiments of the present disclosure, with reference to Figures 3, 6, and 8, the display substrate may further include a fifth scan signal transfer portion 35 and a sixth scan signal transfer portion 36 provided on the base substrate, wherein the fifth scan signal transfer portion 35 and the sixth scan signal transfer portion 36 both extend along the second direction Y; a first end of the third scan signal transfer portion 33 is electrically connected to one of the fourth sub-scan signal lines GL24, a second end of the third scan signal transfer portion 33 is electrically connected to a first end of the sixth sub-scan signal line GL26; a first end of the fourth scan signal transfer portion 34 is electrically connected to the sixth sub-scan signal line GL2 6, the second end of the fourth scan signal transfer portion 34 is electrically connected to the first end of one of the fifth sub-scan signal lines GL25; the first end of the fifth scan signal transfer portion 35 is electrically connected to the second middle portion of the sixth sub-scan signal line GL26, the second end of the fifth scan signal transfer portion 35 is electrically connected to the first end of another fifth sub-scan signal line GL25; and the first end of the sixth scan signal transfer portion 36 is electrically connected to another fourth sub-scan signal line GL24, and the second end of the sixth scan signal transfer portion 36 is electrically connected to the second end of the sixth sub-scan signal line GL26.

[0110] By designing multiple scan signal adapters, multiple sub-scan signal lines of a scan signal line can be connected in series. For example, the fourth sub-scan signal line GL24, the fifth sub-scan signal line GL25, and the sixth sub-scan signal line GL26 of the second scan signal line GL2 can be connected in series. This not only ensures normal signal transmission of the scan signal, but also reduces the design length of at least one sub-scan signal line in the first direction X, reducing the probability of electrostatic breakdown in the overlapping area between the sub-scan signal line and the active layer, thereby improving the yield of the display product. At the same time, this segmented design of the scan signal line also reduces the overlapping area between the gate and the source and drain of at least one transistor, reducing the probability of short circuits between the gate and the source and drain, thereby improving the quality and yield of the display product.

[0111] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 6, in the second direction Y, the second sub-scanning signal line GL12 is located between the i-th row sub-pixels and the first sub-scanning signal line GL11; and / or, in the second direction Y, the third sub-scanning signal line GL13 is located between the first sub-scanning signal line GL11 and the i+1-th row sub-pixels; and / or, in the second direction Y, the fourth sub-scanning signal line GL24 is located between the first sub-scanning signal line GL11 and the i+1-th row sub-pixels; and / or, in the second direction Y, the fourth sub-scanning signal line GL24 is aligned with the fifth sub-scanning signal line GL25; and / or in the second direction Y, the sixth sub-scanning signal line GL26 is located between the fourth sub-scanning signal line GL24 and the third sub-scanning signal line GL13.

[0112] In some exemplary embodiments of the present disclosure, referring to Figures 3 and 8, in the first direction X, the first scan signal switching portion 31 is located between the third scan signal switching portion 33 and the fourth scan signal switching portion 34; and / or, in the first direction X, the fourth scan signal switching portion 34 is located between the first scan signal switching portion 31 and one of the data lines DL; and / or, in the first direction X, the fifth scan signal switching portion 35 is located between another of the data lines and the second scan signal switching portion 32; and / or, in the first direction X, the sixth scan signal switching portion 36 is located on the side of the first power signal line VDDL away from the second scan signal switching portion 32.

[0113] In some exemplary embodiments of the present disclosure, in combination with Figures 3, 7 and 8, the display substrate may include: a semiconductor layer 8 arranged on the base substrate, wherein the first active layer ACT1 and the third active layer ACT3 are both located in the semiconductor layer 8; a second conductive layer 2 arranged on the side of the semiconductor layer 8 away from the base substrate; and a third conductive layer 3 arranged on the side of the second conductive layer 2 away from the base substrate, wherein the first sub-scanning signal line GL11, the second sub-scanning signal line GL12, the third sub-scanning signal line GL13, the fourth scan signal line GL24, the fifth scan signal line GL25 and the sixth scan signal line GL26 are all located in the second conductive layer 2, and the first scan signal switching part 31, the second scan signal switching part 32, the third scan signal switching part 33, the fourth scan signal switching part 34, the fifth scan signal switching part 35 and the sixth scan signal switching part 36 are all located in the third conductive layer 3.

[0114] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 7, the display substrate may further include a first conductive portion 21 located in the second conductive layer 2, the pixel driving circuit further includes a driving transistor T2, the driving transistor T2 includes a second active layer ACT2, the orthographic projection of the first conductive portion 21 on the base substrate partially overlaps with the orthographic projection of the second active layer ACT2 on the base substrate, and the overlapping portion of the first conductive portion 21 and the second active layer ACT2 forms the second gate G2 of the driving transistor; and the display substrate further includes a first conductive transition portion 51 located in the third conductive layer 3 and a first power signal transition portion 61 located in the second conductive layer 2, a first end of the first power signal transition portion 61 is electrically connected to the first power signal line VDDL, a second end of the first power signal transition portion 61 is electrically connected to the first end of the first conductive transition portion 51, and a second end of the first conductive transition portion 51 is electrically connected to the first end of the second active layer ACT2. Through the first conductive transition portion 51 and the first power signal transition portion 61 , electrical connection between the first electrode or the second electrode of the driving transistor T2 and the first power signal line VDDL can be achieved.

[0115] In some exemplary embodiments of the present disclosure, with reference to FIG3 , FIG7 , and FIG8 , the display substrate may further include a second conductive transition portion 52 located in the third conductive layer 3 . The first end of the second conductive transition portion 52 is electrically connected to the first conductive portion 21 , the second end of the second conductive transition portion 52 is electrically connected to the first end of the first active layer ACT1 , and the second end of the first active layer ACT1 is electrically connected to one of the data lines DL1 . This design enables electrical connection between the first electrode or the second electrode of the switching transistor T1 and the data line DL1 , while simultaneously enabling electrical connection between the other of the first electrode or the second electrode of the switching transistor T1 and the second gate G2 of the driving transistor T2 via the second conductive transition portion 52 .

[0116] In some exemplary embodiments of the present disclosure, referring to FIG8 , the display substrate may further include a second conductive portion 30 located in the third conductive layer 3. The second conductive portion 30 includes a conductive body portion 301, a first conductive connection portion 302, and a second conductive connection portion 303. The first conductive connection portion 302 and the second conductive connection portion 303 each extend outwardly from the conductive body portion 301. Referring again to FIG3 and FIG7 , the first conductive connection portion 302 is electrically connected to the second end of the second active layer ACT2, and the second conductive connection portion 303 is electrically connected to the first end of the third active layer ACT3. The connection between the second conductive connection portion 302 and the third conductive connection portion 303 electrically connects the first electrode or the second electrode of the driving transistor T2 to the first electrode or the second electrode of the sensing transistor T3.

[0117] In some exemplary embodiments of the present disclosure, with reference to Figures 3 and 4, the display substrate may further include a first conductive layer 1 located on a side of the semiconductor layer close to the base substrate; the display substrate further includes a sensing signal switching portion 10 located in the first conductive layer 1, the sensing signal switching portion extending along a first direction X, and an orthographic projection of the sensing signal switching portion 10 on the base substrate partially overlaps with an orthographic projection of the sensing signal line SL on the base substrate.

[0118] In some exemplary embodiments of the present disclosure, in combination with Figures 3 and 5, the third active layers ACT3 of the sensing transistors of the first sub-pixel SP1 and the second sub-pixel SP2 are connected as one, and the third active layer ACT3 connected as one extends along the second direction; and the display substrate also includes a third conductive transition portion 53 located in the third conductive layer 3, the sensing signal line SL is electrically connected to the sensing signal transition portion 10, the first end of the sensing signal transition portion 10 is electrically connected to the first end of the third conductive transition portion 53, and the second end of the third conductive transition portion 53 is electrically connected to the middle portion of the third active layer A3.

[0119] In some exemplary embodiments of the present disclosure, in combination with Figures 3, 7 and 8, the pixel driving circuit may further include a storage capacitor Cst, the storage capacitor Cst including a first capacitor Cst1 and a second capacitor Cst2, the second capacitor Cst2 being connected in parallel with the first capacitor Cst1 to increase the capacitance value of the storage capacitor; the display substrate may further include a third conductive portion 11 located in the first conductive layer 1, the orthographic projections of any two of the first conductive portion 21, the second conductive portion 30 and the third conductive portion 11 on the base substrate at least partially overlap, the second conductive portion 30 and the third conductive portion 11 are electrically connected through a via, the overlapping portion of the first conductive portion 21 and the second conductive portion 30 forms the first capacitor Cst1, and the overlapping portion of the first conductive portion 21 and the third conductive portion 11 forms the second capacitor Cst2.

[0120] Figure 9 is a partial plan view of a display substrate according to some embodiments of the present disclosure, showing multiple vias, and also showing line AA', line BB' and line CC'; Figure 10 is a cross-sectional schematic diagram taken along line AA'; Figure 11 is a cross-sectional schematic diagram taken along line BB' and line CC', wherein the area on the left side of SS' is a cross-sectional schematic diagram taken along line BB', and the area on the right side of SS' is a cross-sectional schematic diagram taken along line CC'.

[0121] For example, FIG. 10 may be a cross-sectional view of a portion of the sensing transistor T3 of the first sub-pixel SP1 and a portion of the first scan signal transfer portion 31 taken along line AA′. 10 , the display substrate may include a base substrate 100, a first conductive layer 1 disposed on the base substrate 100, a first insulating layer 71 disposed on a side of the first conductive layer 1 away from the base substrate 100, a semiconductor layer 8 disposed on a side of the first insulating layer 71 away from the base substrate 100, a second insulating layer 72 disposed on a side of the semiconductor layer 8 away from the base substrate 100, a second conductive layer 2 disposed on a side of the second insulating layer 72 away from the base substrate 100, a third insulating layer 73 disposed on a side of the second conductive layer 2 away from the base substrate 100, a third conductive layer 3 disposed on a side of the third insulating layer 73 away from the base substrate 100, a fourth insulating layer 74 disposed on a side of the third conductive layer 3 away from the base substrate 100, a fifth insulating layer 75 disposed on a side of the fourth insulating layer 74 away from the base substrate 100, a first electrode 91 disposed on a side of the fifth insulating layer 75 away from the base substrate 100, and a second electrode 92 disposed on a side of the first electrode 91 away from the base substrate 100. In the embodiment of the present disclosure, the first sub-scanning signal line GL11 and the second sub-scanning signal line GL12 are electrically connected through the first scan signal switching portion 31. The overlapping area of ​​one of the fifth sub-scanning signal lines GL25 and the third active layer ACT3 of the first sub-pixel SP1 forms the third gate G3 of the sensing transistor T3.

[0122] For example, the left side of line SS' in FIG11 is a cross-sectional view of the via hole VH2 region at the electrical connection between the second conductive portion 30 and the third conductive portion 11 in the second sub-pixel SP2, taken along line BB'. The right side of line SS' in FIG11 is a cross-sectional view of the driving transistor T2 in the second sub-pixel SP2, taken along line CC'. It should be noted that the SS' region in FIG11 is merely a schematic structural diagram and may be discontinuous. 9 and 11 , the display substrate may include a base substrate 100, a first conductive layer 1 disposed on the base substrate 100, a first insulating layer 71 disposed on a side of the first conductive layer 1 away from the base substrate 100, a semiconductor layer 8 disposed on a side of the first insulating layer 71 away from the base substrate 100, a second insulating layer 72 disposed on a side of the semiconductor layer 8 away from the base substrate 100, a second conductive layer 2 disposed on a side of the second insulating layer 72 away from the base substrate 100, a third insulating layer 73 disposed on a side of the second conductive layer 2 away from the base substrate 100, a third conductive layer 3 disposed on a side of the third insulating layer 73 away from the base substrate 100, and a third conductive layer 4 disposed on a side of the third conductive layer 73 away from the base substrate 100. The fourth insulating layer 74 disposed on the side of the third conductive layer 3 away from the substrate 100, the fifth insulating layer 75 disposed on the side of the fourth insulating layer 74 away from the substrate 100, the first electrode 91 disposed on the side of the fifth insulating layer 75 away from the substrate 100, the second electrode 92 disposed on the side of the second electrode 92 away from the substrate 100, the pixel definition layer 76 disposed on the side of the third electrode 93 away from the substrate 100, the organic material layer 94 disposed on the side of the pixel definition layer 76 away from the substrate 100, and the fourth electrode 95 disposed on the side of the organic material layer 94 away from the substrate 100. The first electrode 91, the second electrode 92, and the third electrode 93 can be the anode of the pixel unit. The stacked design can enhance the anode conductivity of the pixel unit and improve the luminous efficiency of the pixel unit. The fourth electrode 94 can be the cathode of the pixel unit. Referring to the BB' region in Figure 11, a portion of the third conductive layer 3 can be electrically connected to a portion of the first conductive layer 1 through the via hole VH2. 11 , a portion of the third conductive layer 3 may also contact a portion of the semiconductor layer 8 through the via holes VH3 and VH4 , forming the source and drain of the driving transistor T2 in the second sub-pixel SP2 .

[0123] It should be noted that each of the above insulating layers may include a single layer structure or a stacked layer structure consisting of multiple insulating layers. For example, the fourth insulating layer 74 may include two passivation layers, and the fifth insulating layer 75 may include a passivation layer and a planarization layer.

[0124] With reference to Figures 3 to 11 , in the embodiment of the present disclosure, the drive transistor T2 and the sensing transistor T3 included in the display substrate both have a top-gate structure. That is, the second gate G2 of the drive transistor T2 is located on a side of the second active layer ACT2 away from the base substrate 100, and the third gate G3 of the sensing transistor T3 is located on a side of the third active layer ACT3 away from the base substrate 100. The top-gate structure of the drive transistor T2 and the sensing transistor T3 can reduce the distance between them in the second direction Y, which helps increase the width of the first scan signal line, thereby reducing the load on the first scan signal line and accommodating a higher refresh rate.

[0125] Optionally, embodiments of the present disclosure further provide a display device that may include the aforementioned display substrate. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, monitors, laptop computers, digital photo frames, navigation systems, and any other product or component with a display function. It should be understood that this display device has the same beneficial effects as the display substrate provided in the aforementioned embodiments.

[0126] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: substrate substrate; A plurality of pixel units are provided on the substrate, each pixel unit includes a plurality of sub-pixels, and the plurality of pixel units are arranged in an array on the substrate along a first direction and a second direction, wherein at least one sub-pixel includes a light-emitting element and a pixel driving circuit for driving the light-emitting element, the pixel driving circuit includes a switch transistor and a sensing transistor, the switch transistor includes a first gate, and the sensing transistor includes a third gate, and the first direction and the second direction intersect; A first scanning signal line disposed on the base substrate, the first scanning signal line is used to supply a first scanning signal to a plurality of pixel units arranged along a first direction; A second scanning signal line disposed on the base substrate, the second scanning signal line is used to supply a second scanning signal to a plurality of pixel units arranged along a first direction; At least one data line disposed on the base substrate, the at least one data line is used to supply data signals to a plurality of pixel units arranged along the second direction, wherein the at least one data line extends along the second direction; and A sensing signal line is provided on the base substrate, and the sensing signal line is used to supply a sensing signal to a plurality of pixel units arranged along a second direction, wherein the sensing signal line extends along the second direction, Wherein, the first scanning signal line comprises a plurality of first sub-scanning signal lines, and the plurality of first sub-scanning signal lines respectively extend along the first direction; the second scanning signal line comprises a plurality of fourth sub-scanning signal lines, and the plurality of fourth sub-scanning signal lines respectively extend along the first direction; Two adjacent first sub-scanning signal lines are arranged at intervals in the first region, and the orthographic projections of the sensing signal line and the at least one data line on the substrate substrate do not overlap with the orthographic projections of the plurality of first sub-scanning signal lines on the substrate substrate, wherein the orthographic projections of the sensing signal line and the at least one data line on the substrate substrate extend through the orthographic projection of the first region on the substrate substrate; two adjacent fourth sub-scanning signal lines are arranged at intervals in the second region, and the orthographic projections of the sensing signal line and the at least one data line on the substrate substrate do not overlap with the orthographic projections of the plurality of fourth sub-scanning signal lines on the substrate substrate, wherein the orthographic projections of the sensing signal line and the at least one data line on the substrate substrate extend through the orthographic projection of the second region on the substrate substrate; and The first sub-scanning signal line and the first gate are arranged at intervals in the second direction; the fourth sub-scanning signal line The signal line and the third gate are spaced apart in the second direction.

2. The display substrate according to claim 1, wherein: The display substrate further comprises a first scan signal switching portion disposed on the base substrate, and the first scan signal switching portion extends along a second direction; The first sub-scanning signal line is electrically connected to the first gate at least through the first scan signal switching portion. The first scanning signal switching portion and the first sub-scanning signal line are located in different layers, and / or the first scanning signal switching portion and the first gate are located in different layers.

3. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises a fourth scanning signal switching portion disposed on the base substrate, and the fourth scanning signal switching portion extends along the second direction; The fourth sub-scanning signal line is electrically connected to the third gate at least through the fourth scan signal switching portion. The fourth scanning signal switching portion and the fourth sub-scanning signal line are located in different layers, and / or the fourth scanning signal switching portion and the third gate are located in different layers.

4. The display substrate according to claim 2, wherein: The first scanning signal line further includes a second sub-scanning signal line, the second sub-scanning signal line extends along the first direction, and the second sub-scanning signal line and the first sub-scanning signal line are spaced apart in the second direction; and The first sub-scanning signal line is electrically connected to the second sub-scanning signal line through the first scan signal switching portion.

5. The display substrate according to claim 4, wherein: The first scanning signal line further includes a third sub-scanning signal line, the third sub-scanning signal line extends along the first direction, and the third sub-scanning signal line and the first sub-scanning signal line are spaced apart in the second direction; and The first sub-scanning signal line is electrically connected to the third sub-scanning signal line through the first scan signal switching portion.

6. The display substrate according to any one of claims 1 to 5, wherein: The second scanning signal line further includes a plurality of fifth sub-scanning signal lines, and the plurality of fifth sub-scanning signal lines extend along the first direction respectively; The display substrate further comprises: a second power signal line disposed on the base substrate, the second power signal line being used to supply a second power signal to a plurality of pixel units arranged along a second direction, wherein the second power signal line extends along the second direction; and The adjacent fourth sub-scanning signal line and the fifth sub-scanning signal line are spaced apart in the third region, the orthographic projection of the second power signal line on the substrate does not overlap with the orthographic projections of the plurality of fourth sub-scanning signal lines on the substrate, and the orthographic projection of the second power signal line on the substrate does not overlap with the orthographic projections of the plurality of fifth sub-scanning signal lines on the substrate, wherein the orthographic projection of the second power signal line on the substrate extends through the orthographic projection of the third region on the substrate.

7. The display substrate according to claim 6, wherein: The display substrate further comprises: a first power signal line disposed on the base substrate, the first power signal line being used to supply a first power signal to a plurality of pixel units arranged along a second direction, wherein the first power signal line extends along the second direction; and The adjacent fourth sub-scanning signal line and the fifth sub-scanning signal line are spaced apart in the fourth region, the orthographic projection of the first power signal line on the substrate does not overlap with the orthographic projection of the plurality of fourth sub-scanning signal lines on the substrate, and the orthographic projection of the first power signal line on the substrate does not overlap with the orthographic projection of the plurality of fifth sub-scanning signal lines on the substrate, wherein the orthographic projection of the first power signal line on the substrate extends through the orthographic projection of the fourth region on the substrate.

8. The display substrate according to claim 7, wherein: A plurality of the fifth sub-scanning signal lines are arranged between two adjacent fourth sub-scanning signal lines, and the plurality of the fifth sub-scanning signal lines arranged between two adjacent fourth sub-scanning signal lines are arranged at intervals in the second region, and the orthographic projections of the sensing signal line and the at least one data line on the substrate do not overlap with the orthographic projections of the plurality of the fifth sub-scanning signal lines on the substrate.

9. The display substrate according to any one of claims 6 to 8, wherein: The second scanning signal line further includes a sixth sub-scanning signal line, the sixth sub-scanning signal line extends along the first direction, and the sixth sub-scanning signal line and the fourth sub-scanning signal line are arranged at intervals in the second direction; The display substrate further includes a third scanning signal switching portion disposed on the base substrate, wherein the third scanning signal The signal transfer portion extends along the second direction; and The fourth sub-scanning signal line is electrically connected to the sixth sub-scanning signal line through the third scan signal switching portion.

10. The display substrate according to claim 9, wherein: The sixth sub-scanning signal line is electrically connected to the fifth sub-scanning signal line through the fourth scan signal switching portion.

11. The display substrate according to any one of claims 3 to 10, wherein: At least one of the pixel units includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel, the first sub-pixel is located at the i-th row and the j-th column, the second sub-pixel is located at the i+1-th row and the j-th column, the third sub-pixel is located at the i-th row and the j+1-th column, and the fourth sub-pixel is located at the i+1-th row and the j+1-th column, where i and j are positive integers greater than or equal to 1; as well as In the second direction, the first sub-scanning signal line, the second sub-scanning signal line, the third sub-scanning signal line, the fourth scan signal line, the fifth scan signal line and the sixth scan signal line for supplying scan signals to the i-th row of sub-pixels and the i+1-th row of sub-pixels are all located between the i-th row of sub-pixels and the i+1-th row of sub-pixels.

12. The display substrate according to claim 11, wherein: The orthographic projections of the second sub-scanning signal line on the substrate overlap with the orthographic projections of the first active layers of the first sub-pixel and the third sub-pixel on the substrate, respectively, and the overlapping parts of the second sub-scanning signal line with the first active layers of the first sub-pixel and the third sub-pixel respectively form the first gates of the switching transistors of the first sub-pixel and the third sub-pixel.

13. The display substrate according to claim 12, wherein: The orthographic projections of the third sub-scanning signal line on the substrate overlap with the orthographic projections of the first active layers of the second sub-pixel and the fourth sub-pixel on the substrate, respectively, and the overlapping parts of the third sub-scanning signal line with the first active layers of the second sub-pixel and the fourth sub-pixel respectively form the first gates of the switching transistors of the second sub-pixel and the fourth sub-pixel.

14. The display substrate according to any one of claims 2 to 13, wherein: One of two adjacent first sub-scanning signal lines is electrically connected to the first end of the second sub-scanning signal line and the first end of the third sub-scanning signal line through the first scan signal switching part; and / or, The display substrate also includes a second scan signal switching portion arranged on the base substrate, the second scan signal switching portion extends along a second direction, and the other of the two adjacent first sub-scan signal lines is electrically connected to the second end of the second sub-scan signal line and the second end of the third sub-scan signal line through the second scan signal switching portion.

15. The display substrate according to claim 14, wherein: The orthographic projection of one of the two adjacent fifth sub-scanning signal lines on the substrate overlaps with the orthographic projection of the third active layer of the first sub-pixel on the substrate, and the orthographic projection of the other of the two adjacent fifth sub-scanning signal lines on the substrate overlaps with the orthographic projection of the third active layer of the third sub-pixel on the substrate, and the parts where the fifth sub-scanning signal line overlaps with the third active layers of the first sub-pixel and the third sub-pixel respectively form the third gates of the sensing transistors of the first sub-pixel and the third sub-pixel.

16. The display substrate according to claim 15, wherein: The orthographic projections of the sixth sub-scanning signal line on the substrate overlap with the orthographic projections of the third active layers of the second sub-pixel and the fourth sub-pixel on the substrate, respectively, and the parts where the sixth sub-scanning signal line overlaps with the third active layers of the second sub-pixel and the fourth sub-pixel respectively form the third gates of the sensing transistors of the second sub-pixel and the fourth sub-pixel.

17. The display substrate according to claim 16, wherein: The display substrate further includes a fifth scan signal switching portion and a sixth scan signal switching portion disposed on the base substrate, and the fifth scan signal switching portion and the sixth scan signal switching portion both extend along the second direction; The first end of the third scanning signal switching portion is electrically connected to one of the fourth sub-scanning signal lines, and the second end of the third scanning signal switching portion is electrically connected to the first end of the sixth sub-scanning signal line; The first end of the fourth scanning signal switching portion is electrically connected to the first middle portion of the sixth sub-scanning signal line, and the second end of the fourth scanning signal switching portion is electrically connected to the first end of one of the fifth sub-scanning signal lines; The first end of the fifth scanning signal switching portion is electrically connected to the second middle portion of the sixth sub-scanning signal line, and the second end of the fifth scanning signal switching portion is electrically connected to the first end of another fifth sub-scanning signal line. and The first end of the sixth scan signal switching portion is electrically connected to another of the fourth sub-scan signal lines, and the second end of the sixth scan signal switching portion is electrically connected to the second end of the sixth sub-scan signal line.

18. The display substrate according to any one of claims 11 to 17, wherein: In the second direction, the second sub-scanning signal line is located between the i-th row of sub-pixels and the first sub-scanning signal line; and / or, In the second direction, the third sub-scanning signal line is located between the first sub-scanning signal line and the (i+1)th row of sub-pixels; and / or, In the second direction, the fourth sub-scanning signal line is located between the first sub-scanning signal line and the (i+1)th row of sub-pixels; and / or, In the second direction, the fourth sub-scanning signal line is aligned with the fifth sub-scanning signal line; and / or, In the second direction, the sixth sub-scanning signal line is located between the fourth sub-scanning signal line and the third sub-scanning signal line.

19. The display substrate according to claim 18, wherein: In the first direction, the first scan signal switching portion is located between the third scan signal switching portion and the fourth scan signal switching portion; and / or, In the first direction, the fourth scan signal switching portion is located between the first scan signal switching portion and one of the data lines; and / or, In the first direction, the fifth scan signal switching portion is located between another of the data lines and the second scan signal switching portion; and / or, In the first direction, the sixth scan signal switching portion is located on a side of the first power signal line away from the second scan signal switching portion.

20. The display substrate according to claim 5, wherein: The orthographic projections of the sensing signal line and the at least one data line on the base substrate overlap with the orthographic projections of at least one second sub-scanning signal line on the base substrate respectively; and / or, The orthographic projections of the sensing signal line and the at least one data line on the base substrate respectively overlap with the orthographic projection of at least one third sub-scanning signal line on the base substrate.

21. The display substrate according to claim 9, wherein: The orthographic projections of the sensing signal line and the at least one data line on the base substrate respectively overlap with the orthographic projection of at least one sixth sub-scanning signal line on the base substrate.

22. The display substrate according to any one of claims 1 to 21, wherein: The display substrate comprises: A semiconductor layer disposed on the substrate, wherein the first active layer and the third active layer are both located in the semiconductor layer; A second conductive layer disposed on a side of the semiconductor layer away from the substrate; and a third conductive layer disposed on a side of the second conductive layer away from the base substrate, Among them, the first sub-scanning signal line, the second sub-scanning signal line, the third sub-scanning signal line, the fourth scan signal line, the fifth scan signal line and the sixth scan signal line are all located in the second conductive layer, and the first scan signal switching part, the second scan signal switching part, the third scan signal switching part, the fourth scan signal switching part, the fifth scan signal switching part and the sixth scan signal switching part are all located in the third conductive layer.

23. The display substrate according to claim 22, wherein: The display substrate further includes a first conductive portion located in the second conductive layer, the pixel driving circuit further includes a driving transistor, the driving transistor includes a second active layer, an orthographic projection of the first conductive portion on the base substrate partially overlaps with an orthographic projection of the second active layer on the base substrate, and a portion where the first conductive portion overlaps with the second active layer forms a second gate of the driving transistor; and The display substrate also includes a first conductive transition portion located in the third conductive layer and a first power signal transition portion located in the second conductive layer, a first end of the first voltage signal transition portion is electrically connected to the first power signal line, a second end of the first voltage signal transition portion is electrically connected to the first end of the first conductive transition portion, and a second end of the first conductive transition portion is electrically connected to the first end of the second active layer.

24. The display substrate according to claim 23, wherein: The display substrate also includes a second conductive transition portion located in the third conductive layer, a first end of the second conductive transition portion is electrically connected to the first conductive portion, a second end of the second conductive transition portion is electrically connected to a first end of the first active layer, and a second end of the first active layer is electrically connected to one of the data lines.

25. The display substrate according to claim 24, wherein: The display substrate further includes a second conductive portion located in the third conductive layer, the second conductive portion including a conductive body portion, a first conductive connection portion, and a second conductive connection portion, the first conductive connection portion and the second conductive connection portion respectively protrude outward from the conductive body portion; and The first conductive connection portion is electrically connected to the second end of the second active layer, and the second conductive connection portion is electrically connected to the first end of the third active layer.

26. The display substrate according to claim 25, wherein: The display substrate also includes a first conductive layer located on a side of the semiconductor layer close to the base substrate; the display substrate also includes a sensing signal switching portion located in the first conductive layer, the sensing signal switching portion extends along a first direction, and the orthographic projection of the sensing signal switching portion on the base substrate partially overlaps with the orthographic projection of the sensing signal line on the base substrate.

27. The display substrate according to claim 26, wherein: The third active layers of the sensing transistors of the first sub-pixel and the second sub-pixel are connected as one, and the third active layers connected as one extend along the second direction; and The display substrate also includes a third conductive transition portion located in the third conductive layer, the sensing signal line is electrically connected to the sensing signal transition portion, a first end of the sensing signal transition portion is electrically connected to a first end of the third conductive transition portion, and a second end of the third conductive transition portion is electrically connected to a middle portion of the third active layer.

28. The display substrate according to claim 27, wherein: The pixel driving circuit further includes a storage capacitor, the storage capacitor includes a first capacitor and a second capacitor, and the second capacitor is connected in parallel with the first capacitor; The display substrate also includes a third conductive part located in the first conductive layer, and the orthographic projections of any two of the first conductive part, the second conductive part and the third conductive part on the base substrate at least partially overlap, the second conductive part and the third conductive part are electrically connected, the overlapping part of the first conductive part and the second conductive part forms the first capacitor, and the overlapping part of the first conductive part and the third conductive part forms the second capacitor.

29. A display device, characterized in that: The display device includes the display substrate according to any one of claims 1 to 28.

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