A Bubble Sort Method for Serial-In and Serial-Out Data Based on FPGA
By using an FPGA-based serial-in and serial-out data bubble sorting method, and employing state machines and state jump pointers for data acquisition filtering, the jitter problem in the acquisition of external analog data in airborne equipment was solved, achieving improved data stability and speed, while also saving costs.
Patent Information
- Application Number
- CN202411965512.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2044-12-30
AI Technical Summary
In airborne equipment, existing technologies struggle to ensure data accuracy when FPGAs acquire external analog data, especially to prevent erroneous control signal output caused by occasional jitter.
This paper adopts an FPGA-based serial-in and serial-out data bubble sorting method, uses a state machine for calculation, and controls the steps through state jump pointers to complete data acquisition and filtering, thus avoiding the use of the CPU. It is suitable for 8-bit, 16-bit, or 32-bit wide analog data.
Without relying on the CPU, it achieves stable and accurate data acquisition, reduces data transmission time, improves system operating speed, and saves costs.
Smart Images
Figure CN119902738B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of aviation electrical technology and relates to a bubble sorting method for serial-in and serial-out data based on FPGA. Background Technology
[0002] As airborne equipment becomes increasingly integrated and intelligent, FPGAs are being used more and more widely in airborne equipment. When using FPGAs to acquire external analog data, it is crucial to ensure that the acquired data is accurate and "uninterrupted". The serial-in and serial-out data bubble sorting algorithm in this invention can effectively solve the problem of control signal erroneous output caused by occasional jitter of external analog quantities acquired in actual applications. Summary of the Invention
[0003] (I) Purpose of the Invention
[0004] The purpose of this invention is to provide a bubble sorting method for serial-in and serial-out data based on FPGA. By using FPGA for data bubble sorting and comparison, the system can accurately complete data acquisition and filtering without CPU participation, ensuring the stability of acquisition, saving costs, improving system operating speed, and ensuring that system stability is not affected.
[0005] (II) Technical Solution
[0006] To address the aforementioned technical problems, this invention provides a FPGA-based bubble sorting method for serial-in and serial-out data. The FPGA employs a state machine approach for computation and sets a state transition pointer. At the end of each step, the state transition pointer is set to point to the desired state for the next step. The sorting method includes the following steps:
[0007] Step 1: Initialization
[0008] Initialize the two registers to be used, set the comparison bit register to 2, and set the remaining data register to the total number of data. After initialization, set the status jump pointer to "get value".
[0009] Step 2: Retrieve Values
[0010] The data to be compared is assigned to the comparison register array. The purpose of this step is to prevent new data input during the comparison process from affecting the comparison result. After the assignment is completed, the status jump pointer is pointed to "compare the last two bits".
[0011] Step 3: Compare the last two digits
[0012] The last and second-to-last bits of the comparison register array are compared, and the smaller bit is swapped to the last bit. The value of the remaining data register is decremented by 1. After the comparison is complete, the status jump pointer is pointed to "circular comparison".
[0013] Step 4: Loop Comparison
[0014] Upon entering this step, the "Remaining Data Register" and the "Comparison Bit Register" are compared first, and branching is performed based on the comparison result;
[0015] Step 5: Data Output
[0016] The data in the comparison register array that has completed the comparison is sequentially assigned to the output array. The purpose of this step is to prevent the output of erroneous results that are not completed during the comparison process. After the assignment is completed, the status jump pointer is pointed to "initialization". A new round of data comparison can begin when the next clock edge arrives.
[0017] In the fourth step, if the "Comparison Bit Register" is not greater than the "Remaining Data Register", then the data comparison continues. The bits being compared are the data bits corresponding to the "Remaining Data Register" and the bit preceding it in the comparison register array. The smaller data is swapped to the data bits corresponding to the "Remaining Data Register", and the value of the "Remaining Data Register" is decremented by 1. After the comparison is completed, the status jump pointer is pointed to "Circular Comparison".
[0018] In the fourth step, if the "Compare Bit Register" is greater than the "Remaining Data Register" and the "Compare Bit Register" is less than the total number of data, then the "Compare Bit Register" is incremented by 1, the "Remaining Data Register" is initialized to the total number of data, and after the assignment is completed, the status jump pointer is pointed to "Circular Compare".
[0019] In the fourth step, if the "Compare Bit Register" is greater than the "Remaining Data Register" and the "Compare Bit Register" is not less than the total number of data, it indicates that the loop comparison has been completed, and the status jump pointer is set to "Data Output".
[0020] The minimum operating cycle of the FPGA logic is the clock edge of the crystal oscillator. When each clock edge arrives, the state jump pointer address is read, and then the corresponding step is jumped to according to the state jump pointer address to process the data.
[0021] The total number of comparisons is n. (n-1) That is, n is needed (n-1) The clock cycle completes the data comparison, where n is the number of data items.
[0022] Bubble sort is not affected by the input data bit width and is suitable for analog quantities with 8-bit, 16-bit, or 32-bit width.
[0023] The external data refresh time is less than the time interval T for bubble sorting.
[0024] The system uses a 2V1000 FPGA as its core and an AD7656 AD converter chip as its analog input source.
[0025] (III) Beneficial Effects
[0026] The above-mentioned FPGA-based serial-in and serial-out data bubble sorting method completes analog bubble sorting and filtering within the FPGA. For some smaller systems, it can eliminate the need for CPU, saving costs while reducing the data transmission time between the CPU and FPGA, increasing the speed, and without affecting system stability. Attached Figure Description
[0027] Figure 1 This is a flowchart of the method of the present invention.
[0028] Figure 2 The figure shows the simulation results in an embodiment of the present invention. Detailed Implementation
[0029] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0030] Reference Figure 1 As shown, in this embodiment of the FPGA-based bubble sorting method for serial-in and serial-out data, the FPGA uses a state machine for computation and sets a state transition pointer. At the end of each step, the state transition pointer is set to point to the state to which the next step should be taken. The serial-in and serial-out bubble sorting method includes the following steps:
[0031] Step 1: Initialization
[0032] Initialize the two registers to be used, set the comparison bit register to 2, and set the remaining data register to the total number of data. After initialization, set the status jump pointer to "get value".
[0033] Step 2: Retrieve Values
[0034] The data to be compared is assigned to the comparison register array. The purpose of this step is to prevent new data input during the comparison process from affecting the comparison result. After the assignment is completed, the status jump pointer is pointed to "compare the last two bits".
[0035] Step 3: Compare the last two digits
[0036] The last and second-to-last bits of the comparison register array are compared, and the smaller bit is swapped to the last bit. The value of the remaining data register is decremented by 1. After the comparison is complete, the status jump pointer is pointed to "circular comparison".
[0037] Step 4: Loop Comparison
[0038] Upon entering this step, the "Remaining Data Register" and the "Comparison Bit Register" are compared first, and branching is performed based on the comparison result:
[0039] 1) If the "Compare Bit Register" is not greater than the "Remaining Data Register", then continue the data comparison. The bits to be compared are the data bits corresponding to the "Remaining Data Register" and the bit before it in the comparison register array. The smaller data is swapped to the data bits corresponding to the "Remaining Data Register", and the value of the "Remaining Data Register" is decremented by 1. After the comparison is completed, the status jump pointer is pointed to "Circular Comparison".
[0040] 2) If the "Compare Bit Register" is greater than the "Remaining Data Register" and the "Compare Bit Register" is less than the total number of data, then the "Compare Bit Register" is incremented by 1, the "Remaining Data Register" is initialized to the total number of data, and after the assignment is completed, the status jump pointer is pointed to "Circular Compare".
[0041] 3) If the "Compare Bit Register" is greater than the "Remaining Data Register" and the "Compare Bit Register" is not less than the total number of data, it indicates that the loop comparison has been completed and the status jump pointer is set to "Data Output".
[0042] Step 5: Data Output
[0043] The data in the comparison register array that has completed the comparison is sequentially assigned to the output array. The purpose of this step is to prevent the output of erroneous results that are not completed during the comparison process. After the assignment is completed, the status jump pointer is pointed to "initialization". A new round of data comparison can begin when the next clock edge arrives.
[0044] In this embodiment, the minimum operating cycle of the FPGA logic is the clock edge of the crystal oscillator. When each clock edge arrives, the state jump pointer address is read, and then the corresponding step is jumped to according to the state jump pointer address to process the data.
[0045] In this embodiment, the total number of comparisons required is n. (n-1) That is, n is needed (n-1) Data comparison can be completed in a clock cycle;
[0046] In this embodiment, regardless of the input data bit width, bubble sort can be accurately completed with analog quantities of 8-bit, 16-bit, or 32-bit width.
[0047] In this embodiment, it is important to note that the external data refresh time should be less than T to ensure that the algorithm execution is meaningful.
[0048] Example 1
[0049] Using 2V1000 as the core FPGA, AD7656 as the analog input source, the data width is 16 bits, the AD acquisition frequency is 200KHz, the AD acquisition data is taken once every 0.2ms, and after bubble sorting for 8 consecutive times, A[4] is taken as the output. The simulation code is written and simulated. The initial values of the input data are as follows:
[0050] data_1 = 16'h1234;
[0051] data_2 = 16'h0123;
[0052] data_3 = 16'hc156;
[0053] data_4 = 16'hd378;
[0054] data_5 = 16'hf456;
[0055] data_6 = 16'hb367;
[0056] data_7 = 16'ha234;
[0057] data_8 = 16'h1258;
[0058] data_9 = 16'h3468;
[0059] The comparison results obtained after running the simulation are shown in the appendix. Figure 2 .
[0060] The comparison results are correct, proving that the method is reasonable and effective.
[0061] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A bubble sort method for serial-in and serial-out data based on FPGA, characterized in that, The FPGA uses a state machine approach for computation and sets a state transition pointer. At the end of each step, the state transition pointer is set to point to the desired state for the next step. The sorting method includes the following steps: Step 1: Initialization Initialize the two registers to be used, set the comparison bit register to 2, and set the remaining data register to the total number of data. After initialization, set the status jump pointer to the value. Step 2: Retrieve Values Assign the data to be compared to the comparison register array to prevent new data input during the comparison process from affecting the comparison result. After the assignment is completed, point the status jump pointer to the last two bits for comparison. Step 3: Compare the last two digits The last and second-to-last bits of the comparison register array are compared, and the smaller bit is swapped to the last bit. The value of the remaining data register is decremented by 1. After the comparison is complete, the status jump pointer is pointed to the loop comparison. Step 4: Loop Comparison First, the remaining data register and the comparison bit register are compared, and then branching is performed based on the comparison result; Step 5: Data Output The data in the comparison register array that has completed the comparison is sequentially assigned to the output array to prevent the output of erroneous results of incomplete comparison during the comparison process. After the assignment is completed, the status jump pointer is set to the initialization, and a new round of data comparison can begin when the next clock edge arrives. In the fourth step, if the comparison bit register is not greater than the remaining data register, the data comparison continues. The comparison bits are the data bits corresponding to the remaining data register in the comparison register array and the bit before it. The smaller data is swapped to the data bits corresponding to the remaining data register, and the value of the remaining data register is decremented by 1. After the comparison is completed, the status jump pointer is pointed to the loop comparison. In the fourth step, if the comparison register is greater than the remaining data register and the comparison register is less than the total number of data, then the comparison register is incremented by 1, the remaining data register is initialized to the total number of data, and after the assignment is completed, the status jump pointer is pointed to the loop comparison.
2. The FPGA-based bubble sorting method for serial-in and serial-out data as described in claim 1, characterized in that, In the fourth step, if the comparison bit register is greater than the remaining data register and the comparison bit register is not less than the total number of data, it indicates that the loop comparison has been completed, and the status jump pointer is pointed to the data output.
3. The FPGA-based bubble sorting method for serial-in and serial-out data as described in claim 2, characterized in that, The minimum operating cycle of FPGA logic is the clock edge of the crystal oscillator. When each clock edge arrives, the state jump pointer address is read, and then the corresponding step is jumped to according to the state jump pointer address to process the data.
4. The FPGA-based bubble sorting method for serial-in and serial-out data as described in claim 3, characterized in that, The total number of comparisons is n (n-1) That is, n is needed (n-1) The clock cycle completes the data comparison, where n is the number of data items.
5. The FPGA-based bubble sorting method for serial-in and serial-out data as described in claim 4, characterized in that, Bubble sort is not affected by the input data bit width and is suitable for 8-bit, 16-bit, or 32-bit analog signals.
6. The FPGA-based bubble sorting method for serial-in and serial-out data as described in claim 5, characterized in that, The external data refresh time is less than the time interval T for bubble sorting.
7. The FPGA-based bubble sorting method for serial-in and serial-out data as described in any one of claims 1-6, characterized in that, The FPGA uses a 2V1000 core and an AD7656 AD converter chip as the analog input source.