Processor, method and system for dynamically switching between RISC-V and X86 instruction sets

Abstract

The present invention discloses a processor, a method and a system for dynamically switching between RISC-V and X86 instruction sets. The processor includes an instruction fetch unit, a translation unit and an instruction processing unit. The instruction fetch unit includes a state machine and a trigger circuit. The instruction fetch unit receives an instruction stream and transmits it to the state machine. A target instruction sequence is provided between any adjacent X86 instruction sequences and RISC-V instruction sequences in the instruction stream. When the state machine receives the target instruction sequence, it sends a trigger signal to the trigger circuit, otherwise it does not. When the trigger circuit receives the trigger signal, it switches from the state of currently connecting to one of the translation unit and the instruction processing unit to the state of connecting to the other one. The translation unit is used to translate X86 instruction sequences into RISC-V instruction sequences. The instruction processing unit is used to process RISC-V instruction sequences. The present invention can dynamically switch to process RISC-V instructions and X86 instructions.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a processor, method, and system for dynamically switching between RISC-V and X86 instruction sets. Background Art

[0002] With the continuous development of computer technology, instruction set architectures are also constantly evolving. There are differences in instruction sets between different processor architectures, which may lead to compatibility issues when applications under the same operating system run on processors with different instruction set architectures. Since traditional general-purpose processors usually adopt a fixed instruction set architecture, existing processors generally cannot meet the requirements of running different instruction sets, and there are problems such as insufficient flexibility and difficulty in meeting different application scenarios.

[0003] Currently, for the compatibility issues between different instruction set architectures, mainly two methods of software translation and hardware translation are used to solve them. Software translation technology can achieve cross-instruction set compatibility, but due to the long translation time, it affects the real-time response ability of the system; hardware translation attempts to achieve instant conversion of different instruction sets at the hardware level, but due to the high complexity of hardware design and the difficulty of efficiently supporting multiple instruction sets simultaneously, there are also certain limitations.

[0004] When the prior art solves the compatibility issues between different instruction set architectures, it generally faces problems such as low efficiency and high cost. Although software translation can solve compatibility issues, it introduces additional processing time and reduces the overall performance of the system; while hardware translation, although it can improve compatibility to a certain extent, is limited by the complexity and cost of hardware design and is difficult to be widely applied to various embedded systems.

[0005] The disclosure of the above background art content is only used to assist in understanding the inventive concept and technical solution of the present invention, and it does not necessarily belong to the prior art of this application, nor will it necessarily give technical teachings; in the case where there is no clear evidence indicating that the above content was publicly available before the filing date of this application, the above background art should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0006] The object of the present invention is to provide a processor, method, and system for dynamically switching between RISC-V and X86 instruction sets, which can dynamically switch to process RISC-V instructions and X86 instructions, and achieve fast and efficient processing of instruction streams including RISC-V instructions and X86 instructions.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A processor for dynamically switching between RISC-V and X86 instruction sets, including an instruction fetch unit, a translation unit, and an instruction processing unit;

[0009] The instruction fetch unit includes a state machine and a trigger circuit. The instruction fetch unit is configured to receive an instruction stream to be processed and transmit it to the state machine. The instruction stream includes an X86 instruction sequence and a RISC-V instruction sequence, and a target instruction sequence is configured between any adjacent X86 instruction sequence and RISC-V instruction sequence;

[0010] The state machine is configured to send a trigger signal to the trigger circuit in response to receiving the target instruction sequence, otherwise it does not send a trigger signal to the trigger circuit;

[0011] The trigger circuit is configured to be electrically connected to one of the translation unit and the instruction processing unit. And in response to receiving the trigger signal, the trigger circuit switches from the current state of being connected to one of the translation unit and the instruction processing unit to the state of being connected to the other of the translation unit and the instruction processing unit;

[0012] The translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence;

[0013] The instruction processing unit is configured to process the RISC-V instruction sequence.

[0014] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the instruction fetch unit is further configured to simultaneously transmit the received instruction stream to the state machine and the trigger circuit.

[0015] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the state machine includes a counter. The counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique;

[0016] The state machine sends a trigger signal to the trigger circuit in response to the count of the counter being the target count value.

[0017] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the size of the target instruction sequence is not less than the size of the cache line of the processor. Preferably, the size of the target instruction sequence is equal to the size of the cache line of the processor, or the size of the target instruction sequence is a multiple of the size of the cache line of the processor. A cache line of a processor is a basic unit in the processor cache system for transferring and storing data between the processor and memory. A cache line is the smallest unit for storing data in the processor cache.

[0018] Further, in combination with any one of the foregoing technical solutions or multiple technical solutions, the number of single instructions included in the target instruction sequence is not less than the number of pipeline stages of the processor. Preferably, the number of single instructions included in the target instruction sequence is equal to the number of pipeline stages of the processor, or the number of single instructions included in the target instruction sequence is several times the number of pipeline stages of the processor. The pipeline architecture means that the processor decomposes the execution process of an instruction into several consecutive steps or stages, and each stage performs corresponding tasks by dedicated hardware units in the processor.

[0019] Further, in combination with any one of the foregoing technical solutions or multiple technical solutions, it further includes: for adjacent X86 instruction sequences and RISC-V instruction sequences, determining that the instruction set corresponding to the previous instruction sequence is the target instruction set, and the instruction set includes the RISC-V instruction set and the X86 instruction set;

[0020] The target instruction sequence is configured as the corresponding instruction sequence in the target instruction set, that is, for adjacent different instruction sequences, if the previous instruction sequence is a RISC-V instruction sequence, then the target instruction sequence is an instruction in the RISC-V instruction set, and if the previous instruction sequence is an X86 instruction sequence, then the target instruction sequence is an instruction in the X86 instruction set.

[0021] Further, in combination with any one of the foregoing technical solutions or multiple technical solutions, the target instruction sequence includes a number of consecutive no-op instructions;

[0022] The counter increments by one in response to receiving a no-op instruction, otherwise the counter resets the count.

[0023] Further, in combination with any one of the foregoing technical solutions or multiple technical solutions, if the first instruction sequence received by the state machine is an X86 instruction sequence, the state machine sends a first signal to the trigger circuit, and in response to receiving the first signal, the trigger circuit is electrically connected to the translation unit;

[0024] If the first instruction sequence received by the state machine is a RISC-V instruction sequence, the state machine sends a second signal to the trigger circuit, and in response to receiving the second signal, the trigger circuit is electrically connected to the instruction processing unit.

[0025] Further, in combination with any one of the foregoing technical solutions or multiple technical solutions, after each startup of the processor, the first group of instruction sequences in the instruction stream are all X86 instruction sequences;

[0026] After each startup of the processor, the initial state of the trigger circuit is configured to be electrically connected to the translation unit.

[0027] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, after each startup of the processor, the first set of instruction sequences in the instruction stream are all RISC-V instruction sequences;

[0028] After each startup of the processor, the initial state of the trigger circuit is configured to be electrically connected to the instruction processing unit.

[0029] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the translation unit is configured as a hardware translator, and the hardware translator is configured to translate the X86 instruction sequence into a RISC-V instruction sequence by retrieving the instruction processing results pre-stored in the hardware device;

[0030] The instruction processing results include the mapping relationship from the X86 instruction sequence to the RISC-V instruction sequence.

[0031] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the instruction processing results are obtained in the following manner:

[0032] For any X86 instruction sequence in the target X86 instruction set;

[0033] Determine whether there is an equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence, where the function of the equivalent RISC-V standard instruction sequence is the same as that of the X86 instruction sequence and the difference in execution efficiency between the two is within a preset range. If so, determine the X86 instruction sequence as the first instruction sequence and the equivalent RISC-V standard instruction sequence as the second instruction sequence;

[0034] If not, determine whether there is a non-equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence. If so, determine whether the execution efficiency of the non-equivalent RISC-V standard instruction sequence meets the preset requirements. If it meets, determine the X86 instruction sequence as the third instruction sequence and the non-equivalent RISC-V standard instruction sequence as the fourth instruction sequence;

[0035] If it does not meet, determine the RISC-V custom instruction sequence that replaces the X86 instruction sequence, and determine the X86 instruction sequence as the fifth instruction sequence and the RISC-V custom instruction sequence as the sixth instruction sequence;

[0036] Based on the above steps, the instruction sequence processing result is obtained and stored in a hardware device. The instruction sequence processing result includes:

[0037] Taking the first instruction sequence as the input, the second instruction sequence is taken as the output;

[0038] Taking the third instruction sequence as the input, the fourth instruction sequence is taken as the output;

[0039] Taking the fifth instruction sequence as the input, the sixth instruction sequence is taken as the output.

[0040] Furthermore, continuing with any one of the above technical solutions or a combination of multiple technical solutions, it further includes obtaining the instruction processing result in the following manner:

[0041] For any X86 instruction sequence in the target X86 instruction set;

[0042] If there is no equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence, and there is also no non-equivalent RISC-V standard instruction sequence to replace the X86 instruction sequence;

[0043] Then determine the RISC-V custom instruction sequence to replace the X86 instruction sequence, and determine the X86 instruction sequence as the fifth instruction sequence, and determine the RISC-V custom instruction sequence as the sixth instruction sequence.

[0044] According to another aspect of the present invention, a processing method for dynamically switching between RISC-V and X86 instruction sets is provided. The instruction stream to be processed includes X86 instruction sequences and RISC-V instruction sequences. The method includes the following steps:

[0045] Pre-configure a trigger circuit. The trigger circuit includes an input terminal and two output terminals. The input terminal is selectively electrically connected to the two output terminals. One of the output terminals is electrically connected to the translation unit, and the other output terminal is electrically connected to the instruction processing unit. Among them, the translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence, and the instruction processing unit is configured to process the RISC-V instruction sequence. Thus, the trigger circuit can selectively control the instruction stream to pass through one of the two transmission paths. One transmission path is that the instruction stream is translated by the translation unit and then input into the instruction processing unit, and the other transmission path is that the instruction stream is directly input into the instruction processing unit;

[0046] Configure a target instruction sequence between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream to be processed;

[0047] Monitor the instruction stream to be processed through a state machine. If the state machine detects the target instruction sequence, generate a trigger signal and transmit it to the trigger circuit;

[0048] In response to receiving the trigger signal, the trigger circuit switches the currently connected input terminal to another output terminal, thereby realizing the switching of the transmission / processing path of the instruction stream.

[0049] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the method for dynamically switching between RISC-V and X86 instruction sets further includes the following steps:

[0050] The state machine is configured to detect the target instruction sequence using a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique;

[0051] When the count value of the counter is the target count value, the state machine sends a trigger signal to the trigger circuit.

[0052] Further, based on any one of the foregoing technical solutions or a combination of multiple technical solutions, the method for dynamically switching between RISC-V and X86 instruction sets further includes: the size of the target instruction sequence is equal to the size of the cache line of the processor.

[0053] According to another aspect of the present invention, the present invention provides a computer system, including a processor for dynamically switching between RISC-V and X86 instruction sets according to any one of the foregoing technical solutions or a combination of multiple technical solutions.

[0054] The beneficial effects brought by the technical solutions provided by the present invention are as follows:

[0055] a. By adding a state machine for monitoring the input instruction stream and a trigger circuit for controlling the transmission direction of the instruction stream in the processor, the present invention realizes the dynamic switching of the corresponding instruction stream processing line according to the changes of RISC-V and X86 instructions in the instruction stream, and dynamically switches the instruction set architecture to be processed through hardware, increasing the efficient compatibility of the processor between different instruction set architectures, as well as the portability and versatility of the program, and also reducing the development and maintenance costs of products such as programs and processors;

[0056] b. The technical solution provided by the present invention can implement instruction set switching through a hardware interface by introducing a state machine and a trigger circuit, simplifies the hardware design, reduces the hardware complexity and cost, makes the technology easier to be widely applied, is more suitable for resource-limited embedded systems and Internet of Things devices, and has a wide range of applications;

[0057] c. By setting the size of the target instruction sequence to be the same as the size of the cache line of the processor, and making the number of single instructions included in the target instruction sequence equal to the number of pipeline stages of the processor, the present invention ensures that the data in the registers and the arithmetic logic unit on the processor pipeline is executed and stored in the memory after completion, which can ensure that the instruction set switch will not interrupt the working process of the processor, thereby improving the real-time response ability and overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0059] Figure 1 The working flowchart of a processor for dynamically switching between RISC-V and X86 instruction sets provided by an exemplary embodiment of the present invention;

[0060] Figure 2 The schematic diagram of the processor architecture for dynamically switching between RISC-V and X86 instruction sets provided by an exemplary embodiment of the present invention;

[0061] Figure 3 The schematic diagram of the transmission path of the instruction stream in the processor provided by an exemplary embodiment of the present invention;

[0062] Figure 4 The schematic diagram of the working principle of the state machine provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0063] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0064] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, device, product or equipment comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or equipment.

[0065] In one embodiment of the present invention, a processor for dynamically switching between RISC-V and X86 instruction sets is provided. The processor is configured to dynamically switch between running a RISC-V instruction sequence and an X86 instruction sequence without interrupting the workflow. Based on this, it is possible to quickly and dynamically switch the instruction set architecture being processed by hardware during computer operation to process different instruction sets.

[0066] See Figure 1 and Figure 2 , the processor includes an instruction fetch unit, a translation unit and an instruction processing unit;

[0067] The instruction fetch unit includes a state machine and a trigger circuit. The instruction fetch unit is configured to receive an instruction stream to be processed and transmit it to the state machine. The instruction stream includes an X86 instruction sequence and a RISC-V instruction sequence, and a target instruction sequence is configured between any adjacent X86 instruction sequence and RISC-V instruction sequence;

[0068] The state machine is configured to send a trigger signal to the trigger circuit in response to receiving the target instruction sequence, otherwise it does not send a trigger signal to the trigger circuit;

[0069] The trigger circuit is configured to be electrically connected to one of the translation unit and the instruction processing unit, and when the trigger circuit receives the trigger signal, the trigger circuit switches from the current state of being connected to one of the translation unit and the instruction processing unit to the state of being connected to the other of the translation unit and the instruction processing unit;

[0070] The translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence;

[0071] The instruction processing unit is configured to process the RISC-V instruction sequence.

[0072] Among them, the trigger circuit includes an input end and two output ends. Its input end is selectively electrically connected to one of its two output ends, and when the trigger circuit receives the trigger signal, its input end switches from the state of being currently electrically connected to one output end to the state of being electrically connected to the other output end. One of the two output ends of the trigger circuit is electrically connected to the translation unit, and the other output end is electrically connected to the instruction processing unit; the translation unit is electrically connected to the instruction processing unit.

[0073] In an embodiment of the present invention, referring to Figure 3 , the input port of the instruction reading unit is electrically connected to the state machine and the trigger circuit respectively, and the instruction stream received by the instruction reading unit is simultaneously transmitted to the state machine and the trigger circuit. In this embodiment, the state machine is only configured to monitor the target instruction sequence in the instruction stream, and it is not configured to transmit the instruction stream to the trigger circuit. When the state machine detects the target instruction sequence, it jumps to its sub-state to send a trigger signal to the trigger circuit, prompting the connection state of the trigger circuit to change. In this embodiment, the instruction stream is directly transmitted to the trigger circuit and then through one of the two transmission paths. This method can ensure that the switching of the instruction set can be carried out without interrupting the normal working process of the CPU, improving the compatibility and flexibility of the CPU, and it will not extend the transmission path of the instruction stream, and can ensure the processing efficiency of cross-architecture instruction sets.

[0074] In this embodiment, the working principle of the state machine is as Figure 4 shown. The state machine includes a counter, and the counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique. When the count of the counter in the state machine reaches the target count value, the state machine sends a trigger signal to the trigger circuit.

[0075] Specifically, the target instruction sequence includes several consecutive no-op instructions; the counter increments by one when it receives a no-op instruction, otherwise the counter resets the count. Preferably, the size of the target instruction sequence is equal to the size of the cache line of the processor. And the number of no-op instructions is the same as the number of stages of the pipeline architecture of the processor.

[0076] The state machine synchronously receives the instruction binary code stream and detects a specific string (4-byte NOP instruction) of several cache lines through the counter in the state machine, that is, the target instruction sequence ( Figure 3(the consecutive specific strings in it), the number of digits of the specific string is the ceiling of the pipeline stage number divided by 16 to ensure that it is equal to the size of the cache line of the processor. Through this setting method, it can be ensured that before switching between X86 or RISC-V instructions, the prior RISC-V or X86 instructions are completely executed in the CPU pipeline, thereby avoiding the error of data in the CPU registers due to switching the running instruction set and ensuring the integrity and security of the data.

[0077] As Figure 4 shown, in a 16-stage pipeline architecture, the cache line size is 64 Byte, and the no-operation instructions of the X86 architecture and the RISC-V architecture are 0x0F1F4000 with 4 bytes and 0x00000013 respectively. When the state machine is in the X86 mode and it detects one cache line of no-operation instructions (the target instruction sequence represented by X86 instructions), that is, 16 consecutive (0x0F1F4000), the state machine jumps to the first sub-state to switch to the RISC-V mode, and the state machine sends a trigger signal to the trigger circuit to change the connection state of the trigger circuit, so that the binary code stream directly enters the instruction processing unit after entering the instruction fetch unit.

[0078] When the state machine is in the RISC-V mode and it detects one cache line of no-operation instructions, that is, 16 consecutive (0x00000013), the state machine jumps to the second sub-state to switch to the X86 mode, and the state machine sends a trigger signal to the trigger circuit to change the connection state of the trigger circuit, so that the binary code stream first passes through the translation unit after entering the instruction fetch unit and then enters the instruction processing unit after being translated into RISC-V instructions by the translation unit.

[0079] Among them, the translation unit is preferably a hardware translator, and the hardware translator is configured to translate the X86 instruction sequence into a RISC-V instruction sequence by retrieving the instruction processing results pre-stored in the hardware device; the instruction processing results include the mapping relationship from the X86 instruction sequence to the RISC-V instruction sequence. Adopting this hardware translation method can avoid the delay problem caused by traditional software translation, reduce the problem that existing hardware cannot perform dynamic translation, and reduce the complexity and cost of hardware translation.

[0080] In one embodiment of the present invention, by using the technical solution proposed in the Chinese patent application with the application number 2025101518660, the instruction processing result is obtained in the following manner: for any X86 instruction sequence in the target X86 instruction set; determine whether there is an equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence, the function of the equivalent RISC-V standard instruction sequence is the same as that of the X86 instruction sequence and the difference in execution efficiency between the two is within a preset range. If there is, determine the X86 instruction sequence as the first instruction sequence and the equivalent RISC-V standard instruction sequence as the second instruction sequence.

[0081] If not, determine whether there is a non-equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence. If there is, determine whether the execution efficiency of the non-equivalent RISC-V standard instruction sequence meets the preset requirements. If it meets, determine the X86 instruction sequence as the third instruction sequence and the non-equivalent RISC-V standard instruction sequence as the fourth instruction sequence; if not, determine the RISC-V custom instruction sequence that replaces the X86 instruction sequence, and determine the X86 instruction sequence as the fifth instruction sequence and the RISC-V custom instruction sequence as the sixth instruction sequence.

[0082] If there is no equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence and there is also no non-equivalent RISC-V standard instruction sequence that replaces the X86 instruction sequence; then determine the RISC-V custom instruction sequence that replaces the X86 instruction sequence, and determine the X86 instruction sequence as the fifth instruction sequence and the RISC-V custom instruction sequence as the sixth instruction sequence.

[0083] Based on the above steps, the instruction sequence processing result is obtained and stored in a hardware device. The instruction sequence processing result includes: taking the first instruction sequence as the input, then taking the second instruction sequence as the output; taking the third instruction sequence as the input, then taking the fourth instruction sequence as the output; taking the fifth instruction sequence as the input, then taking the sixth instruction sequence as the output.

[0084] In one embodiment of the present invention, if the instruction sequence first received by the state machine is an X86 instruction sequence, it sends a first signal to the trigger circuit. In response to receiving the first signal, the trigger circuit is electrically connected to the translation unit. If the instruction sequence first received by the state machine is a RISC-V instruction sequence, it sends a second signal to the trigger circuit. In response to receiving the second signal, the trigger circuit is electrically connected to the instruction processing unit. Specifically, the X86 instruction sequence or the RISC-V instruction sequence received by the processor after each startup can be distinguished and determined according to the difference in operands. This embodiment is applicable to the application scenario where it is unclear whether the instruction sequence first processed by the processor after each startup is an X86 instruction sequence or a RISC-V instruction sequence.

[0085] In one embodiment of the present invention, after each startup of the processor, the first set of instruction sequences in the instruction stream are all X86 instruction sequences; after each startup of the processor, the initial state of the trigger circuit is configured to be electrically connected to the translation unit. This embodiment is applicable to the application scenario where the first instruction processed by the processor after each startup is an X86 instruction, and RISC-V instructions may be processed during subsequent operations.

[0086] In one embodiment of the present invention, after each startup of the processor, the first set of instruction sequences in the instruction stream are all RISC-V instruction sequences. After each startup of the processor, the initial state of the trigger circuit is configured to be electrically connected to the instruction processing unit. This embodiment is applicable to the application scenario where the first instruction processed by the processor after each startup is a RISC-V instruction, and X86 instructions may be processed during subsequent operations.

[0087] According to another aspect of the present invention, a processing method for dynamically switching between RISC-V and X86 instruction sets is provided. The instruction stream to be processed includes X86 instruction sequences and RISC-V instruction sequences, as Figure 1 shown. The method includes the following steps:

[0088] Pre-configure a trigger circuit. The trigger circuit includes an input terminal and two output terminals. The input terminal is selectively electrically connected to the two output terminals. One of the output terminals is electrically connected to a translation unit, and the other output terminal is electrically connected to an instruction processing unit. Wherein, the translation unit is configured to translate an X86 instruction sequence into a RISC-V instruction sequence, and the instruction processing unit is configured to process the RISC-V instruction sequence. Thus, the trigger circuit can selectively control the instruction flow to pass through one of two transmission paths. One transmission path is that the instruction flow is translated by the translation unit and then input into the instruction processing unit, and the other transmission path is that the instruction flow is directly input into the instruction processing unit.

[0089] Configure a target instruction sequence between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction flow to be processed.

[0090] Detect the instruction flow to be processed through a state machine. If the state machine detects the target instruction sequence, it generates a trigger signal and transmits it to the trigger circuit.

[0091] In response to receiving the trigger signal, the trigger circuit switches the output terminal currently connected to the input terminal to connect to the other output terminal, thereby switching the transmission path of the instruction flow.

[0092] Preferably, the state machine is configured to detect the target instruction sequence by using a counter. The counter is configured to count according to the target instruction sequence to obtain a target count value, and the target count value is unique. The state machine sends a trigger signal to the trigger circuit in response to the count value of the counter being the target count value.

[0093] In an embodiment of the present invention, a computer system is provided. The computer system includes a processor for dynamically switching between RISC-V and X86 instruction sets as described in any one of the above embodiments or a combination of multiple embodiments.

[0094] It should be noted that the processing method and computer system embodiments for dynamically switching between RISC-V and X86 instruction sets provided by the present invention have the same inventive concept as the processor embodiments for dynamically switching between RISC-V and X86 instruction sets. By way of introduction, all the content of the processor embodiments for dynamically switching between RISC-V and X86 instruction sets is incorporated into the processing method and computer system embodiments for dynamically switching between RISC-V and X86 instruction sets.

[0095] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0096] The above are only specific embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present application.

Claims

1. A processor for dynamically switching between RISC-V and X86 instruction sets, characterized in that, It includes an instruction fetch unit, a translation unit, and an instruction processing unit; The instruction fetch unit includes a state machine and a trigger circuit. The instruction fetch unit is configured to receive an instruction stream to be processed and transmit it to the state machine. The instruction stream includes an X86 instruction sequence and a RISC-V instruction sequence, and a target instruction sequence is configured between any adjacent X86 instruction sequence and RISC-V instruction sequence; The state machine includes a counter. The counter counts according to the target instruction sequence to obtain a target count value, and the target count value is unique. The target instruction sequence includes a plurality of consecutive no-op instructions. The counter increments by one in response to receiving a no-op instruction, otherwise the counter resets the count. The state machine sends a trigger signal to the trigger circuit in response to the count of the counter being the target count value, otherwise it does not send a trigger signal to the trigger circuit; The trigger circuit is selectively electrically connected to one of the translation unit and the instruction processing unit. And in response to receiving the trigger signal, the trigger circuit switches from the current state of being connected to one of the translation unit and the instruction processing unit to the state of being connected to the other of the translation unit and the instruction processing unit; The translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence; The instruction processing unit is configured to process the RISC-V instruction sequence.

2. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein The instruction fetch unit is further configured to simultaneously transmit the received instruction stream to the state machine and the trigger circuit.

3. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein The size of the target instruction sequence is not less than the size of the cache line of the processor; and / or, The number of single instructions included in the target instruction sequence is not less than the number of pipeline stages of the processor.

4. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 3, wherein The size of the target instruction sequence is the same as the size of the cache line of the processor; and / or, The number of single instructions included in the target instruction sequence is equal to the number of pipeline stages of the processor.

5. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein It further includes: For adjacent X86 instruction sequence and RISC-V instruction sequence, determining that the instruction set corresponding to the prior instruction sequence is the target instruction set, and the instruction set includes the RISC-V instruction set and the X86 instruction set; The target instruction sequence is configured as the corresponding instruction sequence in the target instruction set.

6. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein If the instruction sequence first received by the state machine is an X86 instruction sequence, the state machine sends a first signal to the trigger circuit. The trigger circuit is electrically connected to the translation unit in response to receiving the first signal; If the instruction sequence first received by the state machine is a RISC-V instruction sequence, the state machine sends a second signal to the trigger circuit. The trigger circuit is electrically connected to the instruction processing unit in response to receiving the second signal.

7. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein After each startup of the processor, the first group of instruction sequences in the instruction stream are all X86 instruction sequences; After each startup of the processor, the initial state of the trigger circuit is configured to be electrically connected to the translation unit.

8. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein After each startup of the processor, the first set of instruction sequences in the instruction stream is a RISC-V instruction sequence; After each startup of the processor, the initial state of the trigger circuit is configured to be electrically connected to the instruction processing unit.

9. The processor for dynamically switching between RISC-V and X86 instruction sets according to claim 1, wherein The translation unit is configured as a hardware translator, and the hardware translator is configured to translate the X86 instruction sequence into a RISC-V instruction sequence by retrieving the instruction processing result pre-stored in the hardware device; The instruction processing result includes the mapping relationship from the X86 instruction sequence to the RISC-V instruction sequence.

10. A processing method for dynamically switching between RISC-V and X86 instruction sets, characterized in that, The instruction stream to be processed includes an X86 instruction sequence and a RISC-V instruction sequence, and the method includes the following steps: Pre-configure a trigger circuit, the trigger circuit includes an input terminal and two output terminals, the input terminal is selectively electrically connected to the two output terminals, one of the output terminals is electrically connected to the translation unit, and the other output terminal is electrically connected to the instruction processing unit; wherein, the translation unit is configured to translate the X86 instruction sequence into a RISC-V instruction sequence, and the instruction processing unit is configured to process the RISC-V instruction sequence; Configure a target instruction sequence between any adjacent X86 instruction sequence and RISC-V instruction sequence in the instruction stream to be processed; Monitor the instruction stream to be processed through a state machine, the state machine includes a counter, the counter counts according to the target instruction sequence to obtain a target count value, and the target count value is unique; the target instruction sequence includes several consecutive no-op instructions, the counter increments by one in response to receiving a no-op instruction, otherwise the counter resets the count, and the state machine sends a trigger signal to the trigger circuit in response to the count of the counter being the target count value, otherwise does not send a trigger signal to the trigger circuit; In response to receiving the trigger signal, the trigger circuit switches the current connection of the input terminal to one output terminal to the other output terminal.

11. A computer system, characterized in that, Includes a processor for dynamically switching between RISC-V and X86 instruction sets according to any one of claims 1 to 9.

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