Binary translation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the following steps: translating a to-be-processed block to obtain a first sequence, and then adding a first instruction sequence into the first sequence; the first instruction sequence is used for writing a client virtual address of a jump block corresponding to the function call instruction into a preset address record stack; translating the jump block to obtain a host machine virtual address of the jump block, and adding a second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block; if the client instruction to be translated is a return instruction, translating the return instruction to obtain a second sequence, and adding a third instruction sequence in the second sequence; the third instruction sequence is used for acquiring a record address corresponding to a return address of the return instruction from the address record stack as a target address, and skipping to the target address. And the efficiency of the binary translator is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] In the field of computer technology, binary translation technology is usually used, that is, a translator translates client instructions into host instructions so that a program compiled for one instruction set architecture (ISA) can also run on a hardware platform of another instruction set architecture.

[0003] With the application of binary translation technology in various scenarios, there are often a large number of return instructions in client instructions. When translating the return instructions, it is necessary to determine the host machine address corresponding to the return address of the return instruction. Therefore, in order to ensure the efficiency of binary translation, how to determine the host machine address corresponding to the return address has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a binary translation method, device, electronic device and readable storage medium to solve the problem of how to determine the host machine address corresponding to the return address. The specific technical solution is as follows: In a first aspect of the present invention, a binary translation method is first provided, the method comprising: After translating the block to be processed to obtain a first sequence, a first instruction sequence is added to the first sequence; the first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which the function call instruction exists; the jump block is a basic block where the next client instruction of the function call instruction is located; Translating the jump block to obtain a host virtual address of the jump block, and adding a second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; If the client instruction to be translated is a return instruction, the return instruction is translated to obtain a second sequence, and a third instruction sequence is added to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0005] In a second aspect of the present invention, a binary translation device is provided, the device comprising: A first adding module is used for adding a first instruction sequence to a first sequence obtained by translating a block to be processed; the first instruction sequence is used for writing a client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which a function call instruction exists; the jump block is a basic block in which a client instruction next to the function call instruction is located; a first translation module, configured to translate the jump block to obtain a host virtual address of the jump block, and to add a second instruction sequence to a first instruction sequence of a block to be processed corresponding to the jump block; the second instruction sequence is configured to write the host virtual address into the address record stack as a record address corresponding to the client virtual address of the jump block; The second translation module is used to translate the return instruction to obtain a second sequence if the client instruction to be translated is a return instruction, and add a third instruction sequence to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0006] In a third aspect of the present invention, there is also provided an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the method described in the first aspect when executing the program stored in the memory.

[0007] In a fourth aspect of the implementation of the present invention, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect above.

[0008] In a fifth aspect of the implementation of the present invention, there is also provided a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0009] The binary translation method provided by the embodiment of the present invention stores the client virtual address and the host virtual address of the jump block through the address record stack, and by adding the first instruction sequence and the second instruction sequence in the first sequence, when executing the translated block to be processed, the client virtual address and the host virtual address of the jump block can be pre-written into the address record stack through the first instruction sequence and the second instruction sequence, so as to realize the pre-extraction of the jump address. Furthermore, by additionally adding a third instruction sequence for obtaining the target address and jumping when translating the return instruction, when the host executes the return instruction, the host address corresponding to the return address can be directly obtained from the address record stack and jumped, which improves the execution efficiency of the translated instruction to a certain extent, thereby improving the efficiency of the binary translator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0011] Figure 1 is a flowchart of a binary translation method in an embodiment of the present invention; Figure 2 It is a flowchart of binary translation provided by an embodiment of the present invention; Figure 3 It is a jump diagram of a function call instruction and a return instruction provided by an embodiment of the present invention; Figure 4 It is a schematic diagram of translation of a jump block provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of translation of a jump block provided by an embodiment of the present invention; Figure 6 is a schematic diagram of a first instruction sequence in an embodiment of the present invention; Figure 7 is a structural schematic diagram of a binary translation device in an embodiment of the present invention; Figure 8 Schematic diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Figure 1 FIG. 1 is a flowchart of a binary translation method according to an embodiment of the present invention. Figure 1 As shown, the method includes: Step 101, after translating the block to be processed to obtain a first sequence, add a first instruction sequence to the first sequence; the first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which a function call instruction exists; the jump block is a basic block where the next client instruction of the function call instruction is located.

[0015] Step 102: translate the jump block to obtain the host virtual address of the jump block, and add a second instruction sequence to the first instruction sequence of the block to be processed corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack.

[0016] Step 103: If the client instruction to be translated is a return instruction, translate the return instruction to obtain a second sequence, and add a third instruction sequence to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0017] With respect to the above steps 101-103, the embodiment of the present invention can be applied to any translator (also referred to as a binary translator), which can be a user-level translator or a system-level translator, and the embodiment of the present invention does not limit this. Specifically, the binary translation technology can realize the function of making executable files compatible across ISAs. Dynamic binary translators can be divided into user-level binary translators and system-level binary translators. User-level binary translators are mainly limited to the operation of a single user-mode program, and are suitable for executing target programs on different architectures without running the entire operating system. They are often used for software compatibility solutions that are cross-architecture but not cross-operating systems. System-level binary translators cover the operation of the entire system, including the operating system kernel and user-mode programs, and can simulate a complete computer system on different architectures. They are usually used for software compatibility solutions that are both cross-architecture and cross-operating systems, such as being used to run a Microsoft operating system (Windows) with a complex instruction set (CISC) architecture on a Linux system with a reduced instruction set (RISC) architecture, and can also be used to run an Android system (Android) with a RISC architecture on Windows with a CISC architecture. They are not listed here one by one. System-level binary translators can also be used in scenarios such as virtualization, embedded development, and operating system migration.

[0018] The translator is used to translate the source program A in the client (GUEST) into the target program B in the host (HOST), and execute the target program B in the host. The instructions in the source program A can be called client instructions, and the instructions in the target program B can be called host instructions. The client instructions and the host instructions are instructions from different instruction set architectures.

[0019] Furthermore, after reading the binary file, the translator usually translates and executes it in units of basic blocks (TB). Therefore, the basic block in the embodiment of the present invention refers to the translation unit TB of the translator. The processor will execute the instructions in a basic block from the first instruction of the basic block to the last instruction of the basic block in sequence, and will not jump to other places in the middle, nor will there be other places to jump to non-first instructions of the basic block.

[0020] Figure 2 FIG. 1 is a flowchart of a binary translation provided by an embodiment of the present invention. Figure 2As shown in the figure, after the translator reads the executable program (i.e., binary file) of the client platform, it usually translates and executes it at the granularity of basic blocks. Before executing a basic block, the target program is first read from the code cache. If a translated basic block is found, the code block is executed. If the basic block is not found in the code cache, the translation operation is performed and the translated code is placed in the code cache, and then the basic block is executed. After executing a basic block, the code cache is searched for the next basic block, and this cycle is repeated until the program execution ends. Among them, basic block 0~basic block n correspond to the host machine instruction units after the translation of different basic blocks, and each host machine instruction unit contains the translated host machine instructions (Code).

[0021] The above-mentioned pending block refers to a basic block to be translated in which a function call instruction exists. At this time, the pending block contains client instructions that have not been translated. The above-mentioned function call instruction refers to an instruction to call a function or a subroutine. When the processor (Central Processing Unit, CPU) executes the function call instruction, it will jump to the function or subroutine it calls to execute. The function call instruction also depends on the return instruction. The return instruction is the core part of implementing the function call and return mechanism, especially in the scenario that supports recursive or multi-layer function calls. It is used to jump to the caller's code location to continue execution after the called function or subroutine is executed. At present, function call instructions and return instructions are used frequently in most programs, and the return instruction depends on the search of the return address, and its jump overhead is large. Therefore, in the binary translation scenario, the translation of the return instruction has a greater impact on the efficiency of the binary translator.

[0022] The jump block refers to the basic block where the next client instruction of the function call instruction is located. Specifically, since in the instruction set architecture, the next instruction of the function call instruction is the default return address of the return instruction matched with the function call instruction, the next instruction of the function call instruction is the starting TB and the TB to which the corresponding return instruction will jump.

[0023] For example, Figure 3 is a schematic diagram of a jump of a function call instruction and a return instruction provided by an embodiment of the present invention, such as Figure 3 As shown, basic block 1 to basic block 3, basic block x, and basic block y represent different basic blocks. Figure 3 The instructions (inst) in the basic block represent other instructions in the basic block, such as Figure 3As shown in the figure, the function call instruction (call) in TB1 indicates a jump to TB3 for execution, the jump instruction in TB3 indicates a jump to TBx for execution, and the return instruction (ret) in TBy indicates a return to TB2 for execution. Since the address of the function call instruction in TB1 is continuous with the address of instruction 1 in TB2, the TB starting with the next instruction of the call instruction is the target TB of the corresponding ret instruction. Therefore, the default return address of the ret instruction matched by the call instruction is the next instruction of the call instruction, that is, the address of instruction 1.

[0024] The first sequence refers to the host machine instruction sequence obtained after the block to be processed is translated. The guest virtual address (GVA) of the jump block corresponding to the function call instruction refers to the virtual address of the basic block where the next instruction of the function call instruction is located in the client. The address record stack can be pre-set to store the instruction addresses to be recorded. It can be in the form of a data table or a stack. It can be set according to actual needs, and the embodiment of the present invention does not limit this.

[0025] Among them, the above-mentioned first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into the preset address record stack. Specifically, the first instruction sequence may include a plurality of host machine instructions, and these host machine instructions are used to implement writing the GVA of the jump block of the function call instruction into the preset address record stack. Optionally, the number of host machine instructions included in the first instruction sequence can be multiple, of course, it can also be one, which is specifically determined according to the instruction set architecture of the host machine, and the embodiment of the present invention does not limit this. Exemplarily, if the instruction set architecture of the host machine uses at least n instructions to implement writing any GVA into the memory, then the above-mentioned first instruction sequence contains n host machine instructions.

[0026] Specifically, the first instruction sequence may be added to the end position of the first sequence, and may also be added to other positions according to actual conditions, which is not limited in this embodiment of the present invention.

[0027] Among them, the host virtual address (Host Virtual Address, HVA) of the above jump block refers to the virtual address of the first host instruction of the jump block in the host. Further, after the jump block is determined, the jump block can be translated and the HVA of the jump block can be obtained. Further, a second instruction sequence can be added to the first instruction sequence of the block to be processed corresponding to the jump block. The second instruction sequence is used to write the HVA as a record address corresponding to the GVA of the jump block into the above address record stack.

[0028] Specifically, the GVA and the recorded address of the function call instruction may correspond to the same table entry in the address record stack. That is, the address record stack may include multiple table entries, and one table entry is used to record the GVA and HVA of a jump block.

[0029] Among them, the above-mentioned second sequence refers to the host machine instruction sequence obtained by translating the return instruction. The above-mentioned return address refers to the client virtual address corresponding to the instruction to be returned by the return instruction. Furthermore, if the return instruction is translated, a third instruction sequence can be added to the second sequence corresponding to the return instruction, and the third instruction sequence is used to obtain the record address corresponding to the return address of the return instruction from the address record stack as the target address, and jump to the target address. Specifically, after translating the return instruction, the embodiment of the present invention can search from the preset record stack based on the return address of the return instruction. If the record address corresponding to it is found, it indicates that the HVA of the jump block has been obtained, and the third instruction sequence can be added to the second sequence at this time.

[0030] In summary, the binary translation method provided by the embodiment of the present invention, after obtaining a first sequence by translating a block to be processed, adds a first instruction sequence to the first sequence; the first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which a function call instruction exists; the jump block is a basic block where the next client instruction of the function call instruction is located; the jump block is translated to obtain the host virtual address of the jump block, and a second instruction sequence is added to the first instruction sequence of the block to be processed corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; if the client instruction to be translated is a return instruction, the return instruction is translated to obtain a second sequence, and a third instruction sequence is added to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address. In this way, the embodiment of the present invention stores the client virtual address and the host virtual address of the jump block through the address record stack, and by adding the first instruction sequence and the second instruction sequence in the first sequence, when executing the translated block to be processed, the client virtual address and the host virtual address of the jump block can be pre-written into the address record stack through the first instruction sequence and the second instruction sequence, so as to realize the pre-extraction of the jump address. Furthermore, by additionally adding a third instruction sequence for obtaining the target address and jumping when translating the return instruction, when the host executes the return instruction, the host address corresponding to the return address can be directly obtained from the address record stack and jumped, which improves the execution efficiency of the translated instruction to a certain extent, thereby improving the efficiency of the binary translator.

[0031] Optionally, the first instruction sequence at least includes an instruction sequence to be replaced, and the instruction sequence to be replaced at least includes a self-jump instruction; the operation of adding the second instruction sequence to the first instruction sequence of the block to be processed corresponding to the jump block, in this embodiment of the present invention, may specifically include: S21. Use the second instruction sequence to replace the instruction sequence to be replaced in the first instruction sequence.

[0032] The self-jump instruction refers to an instruction that jumps to itself. A loop can be formed through the self-jump instruction, so that the processor continuously executes the instruction.

[0033] Specifically, since there may be other threads executing the to-be-processed blocks before the second instruction sequence is added to the first instruction sequence, and the second instruction sequence has not yet been added to the first instruction sequence at this time, the instructions may fail to execute or may be executed incorrectly or with poor execution efficiency. In order to avoid such problems, an embodiment of the present invention may set a self-jump instruction in the first instruction sequence. The self-jump instruction may be used to intercept subsequent instructions, thereby preventing other threads from continuing to execute backward when the second instruction sequence has not yet been added to the first instruction sequence.

[0034] Furthermore, since the host virtual address of the jump block has not been obtained before the first instruction sequence is added to the first sequence, in order to facilitate the subsequent addition of the second instruction sequence to the first instruction sequence, an embodiment of the present invention can set an instruction sequence to be replaced including a self-jump instruction in the first instruction sequence to implement a placeholder operation.

[0035] Accordingly, when the second instruction sequence is added to the first instruction sequence, the second instruction sequence can be used to replace the instruction sequence to be replaced in the first instruction sequence. Specifically, in the embodiment of the present invention, after adding the first instruction sequence to the first sequence, a variable (for example, inst_ptr) can be set to record the address of the instruction sequence to be replaced, so as to facilitate replacement.

[0036] Optionally, the number of instructions included in the instruction sequence to be replaced in the host architecture can be determined based on the host architecture instruction set. In some cases (for example, the host adopts a RISC instruction set architecture), the host architecture requires multiple instructions to load an immediate value representing an address into the address record stack. In this case, the instruction sequence to be replaced in the embodiment of the present invention may also include at least one no-operation instruction. The no-operation instruction (nop) refers to an instruction that does not have any effect on the state, registers or memory of the processor, and simply consumes one or more clock cycles. It is usually used in the field of binary translation to perform placeholder operations on instructions before determining how a certain instruction should be generated.

[0037] For example, if the host machine architecture assumes that at least n instructions are required to load any 64-bit immediate value HVA representing an address into the memory, then including one self-jump instruction, the instruction sequence to be replaced needs to include n-1 nops.

[0038] In an embodiment of the present invention, the first instruction sequence at least includes an instruction sequence to be replaced, and the instruction sequence to be replaced at least includes a self-jump instruction; the instruction sequence to be replaced in the first instruction sequence is replaced by the second instruction sequence. In this way, the self-jump instruction can be used to avoid the situation where other threads continue to execute backwards when the second instruction sequence has not been added to the first instruction sequence. At the same time, the instruction sequence to be replaced can also be used to realize placeholder, so as to facilitate the subsequent addition of the second instruction sequence to the first instruction sequence.

[0039] Optionally, after adding the first instruction sequence to the first sequence, the embodiment of the present invention may further include: S31. Add a to-be-modified mark to the first sequence.

[0040] After the above operation of replacing the instruction sequence to be replaced in the first instruction sequence with the second instruction sequence, the embodiment of the present invention may further include: S32: Clear the to-be-modified mark of the first sequence.

[0041] Before executing any of the first sequences, the embodiment of the present invention may further include: S33. When the first sequence includes the mark to be modified, modify the self-jump instruction in the first sequence to a no-operation instruction.

[0042] Or, S34, when the first sequence does not include the mark to be modified, execute the first sequence.

[0043] Specifically, since the translation process of the system-level binary translator involves the simulation of the entire client operating system, in the system-level binary translation, the mapping relationship between the client virtual address and the client physical address is directly managed by the client operating system, and a page fault exception will be triggered when the program accesses a virtual address that has not yet been mapped to the physical memory. If an exception such as a page fault is triggered during the translation process, the processor will often jump to the exception handling process to execute, and after the exception handling process is executed, it will jump to the original basic block of this translation to execute, that is, the address pointed to by the current program instruction pointer (IP).

[0044] However, since the modification of the instruction sequence to be replaced in the first instruction sequence depends on the translation of the jump block, on this basis, if an exception such as a page fault is triggered during the translation of the jump block, it will jump to the block to be processed for execution again. At this time, there are instructions to be replaced containing self-jump instructions in the first sequence of the block to be processed. At this time, executing the block to be processed will cause a continuous loop at the self-jump instruction, which may cause the CPU to get stuck.

[0045] In order to avoid the above problems, the embodiment of the present invention can add a to-be-modified mark to the first sequence after adding the first instruction sequence to the first sequence. The above-mentioned to-be-modified mark is used to indicate that there is a self-jump instruction in the first sequence and it needs to be modified. Specifically, the above-mentioned to-be-modified mark can be implemented by setting a mark value for a preset variable. For example, the variable spot=1 can be set for the first sequence of the block to be processed, indicating that the to-be-modified mark is added to the first sequence. Of course, the above-mentioned to-be-modified mark can also be implemented in other ways, which is not limited by the embodiment of the present invention.

[0046] Furthermore, after adding the second instruction sequence to the first instruction sequence of the block to be processed corresponding to the jump block, the to-be-modified mark of the first sequence can be cleared, indicating that there is no self-jump instruction in the first sequence, no modification is required, and normal execution can be performed. Optionally, the above-mentioned to-be-modified mark can be implemented by switching the preset variable from the mark value to the initial value. For example, the variable spot=0 can be set for the first sequence of the block to be processed, indicating that the to-be-modified mark of the first sequence is cleared. Of course, the clearing of the above-mentioned to-be-modified mark can also be implemented in other ways, and the embodiment of the present invention is not limited to this.

[0047] Furthermore, before executing the first sequence of any block to be processed, it can be determined whether the first sequence contains a to-be-modified flag. If so, the self-jump instruction in the first sequence is modified to a no-operation instruction before executing the first sequence. Correspondingly, if not, the first sequence can be directly executed.

[0048] It should be noted that, since a binary translator usually uses multiple threads to translate and execute a client program, on this basis, the binary translation method provided in the embodiment of the present invention can be applied to any thread in the binary translator.

[0049] Furthermore, the embodiment of the present invention can avoid the situation where other threads execute the block to be processed with errors or poor execution efficiency before the current thread adds the second instruction sequence to the first instruction sequence through the self-jump instruction in the above step S21. The self-jump instruction can intercept subsequent instructions to prevent other threads from continuing to execute backward when the second instruction sequence has not been added to the first instruction sequence.

[0050] Furthermore, in the embodiment of the present invention, through the above steps S31~S34, when the jump block translation fails, the current thread can set a to-be-modified mark so that before executing any first sequence, the current thread first identifies whether the first sequence contains the to-be-modified mark, and executes the first sequence if it does not contain it. Accordingly, if it does contain it, the self-jump instruction in the first sequence is modified to a no-operation instruction and then executed, thereby avoiding the problem of the current thread executing the to-be-processed block when an exception such as a page fault is triggered during the translation of the jump block, resulting in a continuous loop at the self-jump instruction.

[0051] In the embodiment of the present invention, after adding the first instruction sequence to the first sequence, a to-be-modified mark is added to the first sequence; after replacing the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence, the to-be-modified mark of the first sequence is cleared; before executing any of the first sequences, if the first sequence contains the to-be-modified mark, the self-jump instruction in the first sequence is modified to a no-operation instruction; or, if the first sequence does not contain the to-be-modified mark, the first sequence is executed. In this way, the execution stuck due to translation abnormality before the to-be-replaced instruction sequence is replaced can be avoided.

[0052] Optionally, after the above operation of adding the second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block, the embodiment of the present invention may further specifically include: S41. If the jump block contains a function call instruction, the jump block is used as a new block to be processed, and the basic block where the next client instruction of the function call instruction of the jump block is located is used as the jump block corresponding to the new block to be processed, and the operation of translating the jump block to obtain the host virtual address of the jump block is performed again until the current jump block does not contain a function call instruction.

[0053] Specifically, since the TB (jump block) where the next instruction of the function call instruction is located may also contain a function call instruction, on this basis, the jump block of the jump block can be translated in a recursive manner.

[0054] Specifically, if the jump block contains a function call instruction, the jump block is used as a new block to be processed, and the basic block where the next client instruction of the function call instruction of the jump block is located is used as the jump block corresponding to the new block to be processed, and the operation of translating the jump block to obtain the host virtual address of the jump block is performed again until the current jump block does not contain a function call instruction.

[0055] Specifically, Figure 4 is a schematic diagram of a jump block translation provided by an embodiment of the present invention, such as Figure 4As shown, for the basic block 1 (TB1) to be executed, first determine whether TB1 has been translated. If so, execute TB1. If not, execute the normal translation process for TB1, and determine whether the TB just translated (i.e., TB1) ends with a function call instruction (i.e., whether there is a function call instruction call). If not, it indicates that TB1 is not a block to be processed, and TB1 can be executed normally. If yes, it indicates that TB1 is a block to be processed, and the host virtual address of its jump block (next TB) needs to be obtained, and the next TB needs to be translated. It can be determined first whether the next TB of the call instruction has been translated. If yes, it indicates that it does not need to be translated, and directly determine whether the TB ends with call. If not, it needs to be pre-translated to obtain the host virtual address. Further, if a pre-translation exception occurs, the exception handling process is executed, and after the exception handling is completed, jump to the original TB1 for execution. Correspondingly, if no pre-translation exception occurs, continue to determine whether the TB ends with call until the current jump block does not contain a function call instruction, and TB1 can be executed normally.

[0056] Optionally, the embodiment of the present invention may further include: S51. When any basic block is updated to an invalid state, obtain a preceding basic block of the basic block.

[0057] S52: If there is a function call instruction in the preceding basic block, replace the first instruction sequence in the first sequence corresponding to the preceding basic block with a no-operation instruction.

[0058] The invalid state refers to the invalid operation of a basic block. When the translated basic block cannot correctly reflect the actual behavior of the program, the block will be marked as invalid, which usually occurs in scenarios such as program self-modification.

[0059] When any basic block is updated to an invalid state, the basic block should no longer be executed. However, if the basic block belongs to a jump block of the block to be processed, since the first instruction sequence is added to the first sequence and the third instruction sequence is added to the second sequence in the aforementioned steps, it will cause a direct jump to the basic block for execution when executing the return instruction, resulting in a program execution error.

[0060] In order to avoid the above situation, the embodiment of the present invention can obtain the predecessor basic block of the basic block updated to the invalid state.

[0061] The preceding basic block refers to the basic block where the previous instruction of the basic block is located. If there is a function call instruction in the preceding basic block, it indicates that the preceding basic block is a pending block, and the current basic block is a jump block. In order to avoid directly jumping to the invalidated basic block when executing the return instruction corresponding to the pending block, the first instruction sequence in the first sequence corresponding to the preceding basic block can be replaced with a no-operation instruction.

[0062] In the embodiment of the present invention, when any basic block is updated to an invalid state, the preceding basic block of the basic block is obtained; if the preceding basic block has a function call instruction, the first instruction sequence in the first sequence corresponding to the preceding basic block is replaced with a no-operation instruction. In this way, it is possible to avoid the situation where the program execution error is caused by directly jumping to the invalidated basic block when executing the return instruction corresponding to the block to be processed.

[0063] Optionally, the embodiment of the present invention may further include: S61. Configure a first parameter for each basic block.

[0064] S62: After translating any of the basic blocks, if a function call instruction exists in a preceding basic block of the basic block, obtain a parameter value of a first parameter of the basic block as a first determination value.

[0065] S63: If the first determination value is an initial value, update the parameter value of the first parameter to the basic block pointer of the preceding basic block.

[0066] The above operation of obtaining the preceding basic block of the basic block may specifically include: S64: Based on the parameter value of the first parameter of the basic block, obtain the preceding basic block.

[0067] Specifically, an embodiment of the present invention can configure a first parameter for each basic block, and after translating any basic block, determine whether there is a function call instruction in its preceding basic block. If so, the parameter value of the first parameter of the basic block can be obtained as the first judgment value.

[0068] Among them, the above-mentioned initial value refers to the initial value when configuring the first parameter, and the initial value can be 0 or empty. The above-mentioned basic block pointer refers to the pointer of the basic block structure, and the basic block structure is used to store basic block-related information. Specifically, if the first judgment value is the initial value, it indicates that there is only one predecessor basic block for the basic block. At this time, the parameter value of the first parameter can be updated to the basic block pointer of the predecessor basic block. Correspondingly, if the first judgment value is not the initial value, it indicates that there are other predecessor basic blocks for the basic block and the translation has been completed before the current predecessor basic block.

[0069] Furthermore, the embodiment of the present invention can obtain the preceding basic block through the parameter value of the first parameter of the basic block.

[0070] In the embodiment of the present invention, a first parameter is configured for each basic block; after translating any basic block, if there is a function call instruction in the preceding basic block of the basic block, the parameter value of the first parameter of the basic block is obtained as the first judgment value; if the first judgment value is an initial value, the parameter value of the first parameter is updated to the basic block pointer of the preceding basic block; based on the parameter value of the first parameter of the basic block, the preceding basic block is obtained. In this way, the basic block pointer of the preceding basic block of each basic block can be stored through the first parameter, which facilitates timely acquisition of the preceding basic block of the basic block and improves processing efficiency.

[0071] Optionally, the embodiment of the present invention may further include: S71. Configure a second parameter for each basic block.

[0072] S72. After translating any of the basic blocks, if the basic block has the same function call instruction as another basic block that has been translated last, obtain a parameter value of a second parameter of the other basic block as a second determination value.

[0073] S73: If the second determination value is an initial value, update the parameter value of the second parameter of the other basic block to the basic block pointer of the basic block.

[0074] The operation of obtaining the preceding basic block based on the parameter value of the first parameter of the basic block may specifically include: S641 obtains a first preceding basic block of the basic block based on the parameter value of the first parameter of the basic block.

[0075] S642: Take the first preceding basic block as an initial basic block, and obtain a linked basic block of the initial basic block based on a parameter value of a second parameter of the initial basic block.

[0076] S643: Take the linked basic block as a new initial basic block, execute the parameter value of the second parameter of the initial basic block again, and obtain the operation of linking the basic block of the initial basic block.

[0077] S644: Determine the first preceding basic block and the obtained linked basic block as preceding basic blocks of the basic block.

[0078] It should be noted that in system-level binary translation, due to self-modification and other reasons, a basic block may jump to the exception handling process before being fully executed. After the exception is handled, the TB is regenerated from an instruction in the middle and executed.

[0079] Figure 5 is a schematic diagram of a jump block translation provided by an embodiment of the present invention, such as Figure 5 As shown in the figure, basic block 1 (TB1) is the TB where the predecessor function call instruction of basic block 2 (TB2) is located, that is, TB1 is the pending block corresponding to TB2, and TB2 is the jump block corresponding to TB1. However, since TB1 jumps to the exception handling process before it is fully executed, there are multiple TBs ending with the same call instruction (basic block 1, basic block 1', basic block 1''), and these multiple TBs will jump to the same jump block for execution through the return instruction, so they all belong to the predecessor basic blocks of basic block TB2.

[0080] On this basis, the embodiment of the present invention can configure the second parameter for each basic block, and after translating any basic block, if the basic block and the other basic blocks that have been translated last have the same function call instruction, it indicates that the basic block and the other basic blocks belong to the same basic block. On this basis, the embodiment of the present invention can obtain the parameter value of the second parameter of the other basic blocks as the second judgment value. If the second judgment value is the initial value, it indicates that the basic block is the first basic block that belongs to the same basic block as the other basic blocks. At this time, the parameter value of the second parameter of the other basic blocks can be updated to the basic block pointer of the basic block, so as to transfer the subordination relationship of the basic blocks through the parameter value of the second parameter.

[0081] Furthermore, the operation of obtaining the preceding basic block may first obtain the first preceding basic block of the basic block based on the parameter value of the first parameter of the basic block. At the same time, the first preceding basic block may be used as the initial basic block, and the linked basic block of the initial basic block may be obtained based on the parameter value of the second parameter of the initial basic block. The above operation is repeatedly performed until the parameter value of the second parameter of the initial basic block is the initial value. At this time, the first preceding basic block and the obtained linked basic block may be determined as the preceding basic blocks.

[0082] Exemplarily, the first parameter may be P, the second parameter may be PList, and the steps may include: Step a, whenever the translation of a TB is finished, it is determined whether the preamble TB1 of the TB ends with a call, if it ends with a call, it is determined whether P in the TB basic block structure is empty, if it is empty, the following step b is executed, if not empty, the following step c is executed; Step b: store the basic block pointer of the preceding TB1 into P of TB, and end the subsequent steps.

[0083] Step c: read whether PList in the basic block TBn pointed to by P is empty. If it is empty, execute the following step e; otherwise, execute the following step d.

[0084] With the above Figure 5 For example, P in TB2 is used to represent the basic block pointer of the first preceding basic block TB1 of the TB. The basic block pointer of TB1' is stored in Plist in TB1. The basic block pointer of TB1' is stored in Plist in TB1'.

[0085] Step d, read the basic block pointer pointed to by PList in the basic block TBn, and determine whether the PList in the basic block is empty. If it is not empty, make TBn = the basic block corresponding to the basic block pointer pointed to by PList in TBn; repeat this step until a basic block with an empty PList is found, and then store the basic block pointer of the current TBn in the PList of the basic block with an empty PList.

[0086] Step e: Store the basic block pointer of TB1 into the PList of the basic block whose PList is empty.

[0087] Furthermore, after the basic block is invalidated, the preceding basic block of the basic block is obtained through the following steps: Step f, determine whether P in the basic block structure of the invalidated TB is empty, if it is empty, end the subsequent steps, otherwise execute the following step g.

[0088] Step g: TBx = the basic block pointed to by P, replace the first instruction sequence in TBx with nop, and set P in TB to NULL.

[0089] Step h: determine whether PList in TBx is empty. If it is empty, end the subsequent steps; otherwise, execute the following step i.

[0090] Step i, read the basic block pointer TBy pointed to by PList in TBx, replace the first instruction sequence in TBy with nop, set PList in TBx to NULL, and determine whether PList in TBy is empty. If it is empty, terminate the execution, otherwise TBx=TBy, and repeat this step until PList is empty.

[0091] In the embodiment of the present invention, all the preceding basic blocks of a basic block can be obtained through the first parameter and the second parameter, thereby avoiding the omission of the preceding basic blocks and further ensuring the accuracy of program execution.

[0092] Optionally, the embodiment of the present invention may further include: S81. When the translation lookaside buffer is refreshed or the storage data in the address record stack reaches a preset storage threshold, clear the storage data in the address record stack.

[0093] The above-mentioned Translation Lookaside Buffer (TLB) refers to the page table cache, which is used by the memory management unit to improve the translation speed of virtual addresses to physical addresses. When the TLB is refreshed, it indicates that a process scheduling switch may have occurred. At this time, in order to avoid jumping to the wrong address during program execution, the stored data in the address record stack can be cleared.

[0094] The preset storage threshold refers to the maximum amount of stored data, which may be preset, and the embodiment of the present invention does not limit this. Accordingly, when the storage data of the address record stack reaches the preset storage threshold, it indicates that the address record stack is full. In order to avoid the address record stack overflow, the storage data in the address record stack may be cleared at this time.

[0095] Optionally, the address record stack can be a stack structure. A stack is a linear data structure that can only perform insertion and deletion operations at one end. This end is called the top of the stack, and the other end is called the base. Its characteristic is that it follows the last-in-first-out principle, that is, the last element put in is taken out first. Correspondingly, the address record stack can also be called the return address stack (RAS). The depth of RAS is N, where N is a power of 2, and each item consists of a GVA and an HVA. GVA refers to the GVA of the target TB returned by the ret instruction, and HVA refers to the HVA of the target TB returned by the ret instruction.

[0096] On this basis, the above-mentioned operation of clearing the data of the address record stack can be achieved by pointing the stack pointer to the initial position. Specifically, in order to avoid stack data overflow, the mask mechanism can be used to automatically clear the RAS stack when the RAS stack is full. Specifically, taking the RAS depth as N as an example, the mask is set to N-1, and the top of the stack when pushing the stack is indexed as n based on the number of items at the bottom of the stack. Then, n = n&mask is set before each stack push, so that the stack pointer can automatically point to the initial position when the stack overflows.

[0097] Furthermore, when the address record stack is a stack structure, the first instruction sequence may also include instructions for loading the top of the RAS stack, instructions for pushing the GVA into the top of the RAS stack, and instructions for updating the RAS stack top pointer. Figure 6 is a schematic diagram of a first instruction sequence in an embodiment of the present invention, such as Figure 6As shown, the first instruction sequence includes: an instruction for loading the top of the return address stack (RAS) (load top), an instruction for pushing the client virtual address (GVA) into the top of the RAS stack (push gva), a self-jump instruction (b0), a no operation instruction (nop), and an instruction for updating the RAS stack top pointer (update top).

[0098] Furthermore, when the address record stack is a stack structure, the second instruction sequence is an instruction sequence of push hva semantics. The third instruction sequence may include instructions for loading the top of the RAS stack, instructions for taking out the GVA in the top of the RAS stack, instructions for taking out the HVA in the top of the RAS stack, instructions for updating the RAS stack top pointer, and instructions for judging whether the GVA is consistent with the client virtual address of the return target, and if consistent, jumping to the HVA to continue executing the subsequent code, and if inconsistent, executing the return instruction operation of the conventional path.

[0099] Figure 7 FIG. 1 is a schematic diagram of the structure of a binary translation device in an embodiment of the present invention. Figure 7 As shown, the device 20 may include: The first adding module 201 is used to add a first instruction sequence to the first sequence after translating the block to be processed; the first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which the function call instruction exists; the jump block is a basic block where the next client instruction of the function call instruction is located; A first translation module 202 is used to translate the jump block to obtain the host virtual address of the jump block, and add a second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; The second translation module 203 is used to translate the return instruction to obtain a second sequence if the client instruction to be translated is a return instruction, and add a third instruction sequence to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

[0100] Optionally, the first instruction sequence includes at least an instruction sequence to be replaced, and the instruction sequence to be replaced includes at least a self-jump instruction; the first translation module includes: The first replacement submodule is used to replace the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence.

[0101] Optionally, the device further comprises: a mark adding module, configured to add a to-be-modified mark to the first sequence after the first adding module adds the first instruction sequence to the first sequence; The device further comprises: a first clearing module, configured to clear a to-be-modified mark of the first instruction sequence after the replacement submodule replaces the to-be-replaced instruction sequence in the first instruction sequence with the second instruction sequence; The device also includes: A modification module is used to modify the self-jump instruction in the first sequence into a no-operation instruction before executing any of the first sequences if the first sequence contains the mark to be modified; or to execute the first sequence if the first sequence does not contain the mark to be modified.

[0102] Optionally, the device further comprises: An execution module is used for, after the first translation module adds the second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block, if the jump block contains a function call instruction, taking the jump block as a new to-be-processed block, taking the basic block where the next client instruction of the function call instruction of the jump block is located as the jump block corresponding to the new to-be-processed block, and again executing the operation of translating the jump block to obtain the host machine virtual address of the jump block until the current jump block does not contain a function call instruction.

[0103] Optionally, the device further comprises: A first acquisition module, configured to acquire a preceding basic block of any basic block when any basic block is updated to an invalid state; The second replacement module is used to replace the first instruction sequence in the first sequence corresponding to the preceding basic block with a no-operation instruction if there is a function call instruction in the preceding basic block.

[0104] Optionally, the device further comprises: a first configuration module, configured to configure a first parameter for each of the basic blocks; A second acquisition module is used for acquiring, after translating any of the basic blocks, a parameter value of a first parameter of the basic block as a first determination value when a function call instruction exists in a preceding basic block of the basic block; A first updating module, configured to update the parameter value of the first parameter to a basic block pointer of the preceding basic block if the first determination value is an initial value; The first acquisition module is specifically used to: The preceding basic block is obtained based on the parameter value of the first parameter of the basic block.

[0105] Optionally, the device further comprises: a second configuration module, configured to configure a second parameter for each of the basic blocks; A third acquisition module is used for, after translating any of the basic blocks, if the basic block and the other basic block that has been translated previously have the same function call instruction, acquiring a parameter value of a second parameter of the other basic block as a second determination value; A second updating module, configured to update the parameter value of the second parameter of the other basic block to the basic block pointer of the basic block if the second determination value is an initial value; The first acquisition module includes: A fourth acquisition submodule, configured to acquire a first preceding basic block of the basic block based on a parameter value of a first parameter of the basic block; A fifth acquisition submodule, configured to use the first preceding basic block as an initial basic block, and based on a parameter value of a second parameter of the initial basic block, acquire a linked basic block of the initial basic block; A sixth acquisition submodule, configured to use the linked basic block as a new initial basic block, and to execute again the parameter value of the second parameter of the initial basic block to acquire the operation of the linked basic block of the initial basic block; The basic block determination module is used to determine the first preceding basic block and the obtained link basic block as preceding basic blocks of the basic block.

[0106] Optionally, the device further comprises: The second clearing module is used to clear the storage data in the address record stack when the translation lookaside buffer is refreshed or the storage data in the address record stack reaches a preset storage threshold.

[0107] In summary, the binary translation device provided by the embodiment of the present invention adds a first instruction sequence to the first sequence after translating the block to be processed to obtain a first sequence; the first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which a function call instruction exists; the jump block is a basic block where the next client instruction of the function call instruction is located; the jump block is translated to obtain the host virtual address of the jump block, and a second instruction sequence is added to the first instruction sequence of the block to be processed corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; if the client instruction to be translated is a return instruction, the return instruction is translated to obtain a second sequence, and a third instruction sequence is added to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address. In this way, the embodiment of the present invention stores the client virtual address and the host virtual address of the jump block through the address record stack, and by adding the first instruction sequence and the second instruction sequence in the first sequence, when executing the translated block to be processed, the client virtual address and the host virtual address of the jump block can be pre-written into the address record stack through the first instruction sequence and the second instruction sequence, so as to realize the pre-extraction of the jump address. Furthermore, by additionally adding a third instruction sequence for obtaining the target address and jumping when translating the return instruction, when the host executes the return instruction, the host address corresponding to the return address can be directly obtained from the address record stack and jumped, which improves the execution efficiency of the translated instruction to a certain extent, thereby improving the efficiency of the binary translator.

[0108] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0109] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0110] Regarding the request processing device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0111] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing instructions executable by the processor, wherein the processor is configured to execute the above binary translation method.

[0112] Reference Figure 8 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the binary translation method of the aforementioned embodiment.

[0113] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0114] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmble Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0115] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0116] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0117] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The binary translation method shown.

[0118] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The binary translation method shown.

[0119] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned binary translation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0120] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0121] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0122] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0123] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0126] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0127] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0128] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0129] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0130] The above is a detailed introduction to a binary translation method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A binary translation method, characterized in that: The method comprises: After translating the block to be processed to obtain a first sequence, a first instruction sequence is added to the first sequence; the first instruction sequence is used to write the client virtual address of the jump block corresponding to the function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which the function call instruction exists; the jump block is a basic block where the next client instruction of the function call instruction is located; Translating the jump block to obtain a host virtual address of the jump block, and adding a second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block; the second instruction sequence is used to write the host virtual address as a record address corresponding to the client virtual address of the jump block into the address record stack; If the client instruction to be translated is a return instruction, the return instruction is translated to obtain a second sequence, and a third instruction sequence is added to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

2. The method according to claim 1, characterized in that The first instruction sequence at least includes an instruction sequence to be replaced, and the instruction sequence to be replaced at least includes a self-jump instruction; and adding a second instruction sequence to the first instruction sequence of the block to be processed corresponding to the jump block includes: The second instruction sequence is used to replace the instruction sequence to be replaced in the first instruction sequence.

3. The method according to claim 2, characterized in that After adding the first instruction sequence to the first sequence, the method further includes: adding a to-be-modified mark to the first sequence; After the second instruction sequence is used to replace the instruction sequence to be replaced in the first instruction sequence, the method further includes: clearing a to-be-modified mark of the first sequence; Before executing any of the first sequences, the method further comprises: In the case where the first sequence includes the to-be-modified mark, modifying the self-jump instruction in the first sequence into a no-operation instruction; Or, when the first sequence does not include the to-be-modified mark, the first sequence is executed.

4. The method according to claim 1, characterized in that: After adding the second instruction sequence to the first instruction sequence of the to-be-processed block corresponding to the jump block, the method further includes: If the jump block contains a function call instruction, the jump block is used as a new block to be processed, and the basic block where the next client instruction of the function call instruction of the jump block is located is used as the jump block corresponding to the new block to be processed, and the operation of translating the jump block to obtain the host virtual address of the jump block is performed again until the current jump block does not contain a function call instruction.

5. The method according to claim 1, characterized in that The method further comprises: When any basic block is updated to an invalid state, obtaining a preceding basic block of the basic block; If the preceding basic block contains a function call instruction, a first instruction sequence in a first sequence corresponding to the preceding basic block is replaced with a no-operation instruction.

6. The method according to claim 5, characterized in that The method further comprises: configuring a first parameter for each of the basic blocks; After translating any of the basic blocks, if a function call instruction exists in a preceding basic block of the basic block, obtaining a parameter value of a first parameter of the basic block as a first determination value; If the first determination value is an initial value, updating the parameter value of the first parameter to the basic block pointer of the preceding basic block; The obtaining of a preceding basic block of the basic block comprises: The preceding basic block is obtained based on the parameter value of the first parameter of the basic block.

7. The method according to claim 6, characterized in that The method further comprises: configuring a second parameter for each of the basic blocks; After translating any of the basic blocks, if the basic block and another basic block that has been translated previously have the same function call instruction, obtaining a parameter value of a second parameter of the other basic block as a second determination value; If the second determination value is an initial value, updating the parameter value of the second parameter of the other basic block to the basic block pointer of the basic block; The obtaining the preceding basic block based on the parameter value of the first parameter of the basic block comprises: Based on the parameter value of the first parameter of the basic block, obtaining a first preceding basic block of the basic block; Taking the first preceding basic block as an initial basic block, and obtaining a linked basic block of the initial basic block based on a parameter value of a second parameter of the initial basic block; Taking the linked basic block as a new initial basic block, executing the parameter value of the second parameter of the initial basic block again, and obtaining the operation of the linked basic block of the initial basic block; The first preceding basic block and the obtained linking basic block are determined as preceding basic blocks of the basic block.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: When the translation lookaside buffer is refreshed or the storage data in the address record stack reaches a preset storage threshold, the storage data in the address record stack is cleared.

9. A binary translation device, characterized in that: The device comprises: A first adding module is used for adding a first instruction sequence to a first sequence obtained by translating a block to be processed; the first instruction sequence is used for writing a client virtual address of a jump block corresponding to a function call instruction into a preset address record stack; the block to be processed is a basic block to be translated in which a function call instruction exists; the jump block is a basic block in which a next client instruction of the function call instruction is located; a first translation module, configured to translate the jump block to obtain a host virtual address of the jump block, and to add a second instruction sequence to a first instruction sequence of a block to be processed corresponding to the jump block; the second instruction sequence is configured to write the host virtual address into the address record stack as a record address corresponding to the client virtual address of the jump block; The second translation module is used to translate the return instruction to obtain a second sequence if the client instruction to be translated is a return instruction, and add a third instruction sequence to the second sequence; the third instruction sequence is used to obtain a record address corresponding to the return address of the return instruction from the address record stack as a target address, and jump to the target address.

10. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-8 when executing a program stored in a memory.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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