Adaptive method, device and medium based on Warp scheduling and cache replacement

Abstract

The present application relates to the field of computer technology, and relates to an adaptive method, device, and medium based on Warp scheduling and cache replacement. The method includes: dynamically monitoring the access behavior of Warp in the L1 data cache through a locality perception unit to identify the locality preference of the workload; adaptively selecting a Warp scheduling algorithm based on the locality preference; periodically collecting cache access counts and cache miss counts through a cache status monitor, calculating the memory access miss rate of the current sampling period, and comparing it with the miss rate of the previous sampling period; if the memory access miss rate of the current sampling period is higher than that of the previous sampling period, switching the cache replacement strategy; if it is lower than or equal to, maintaining the current strategy. The present invention adaptively adjusts the Warp scheduling algorithm and cache replacement strategy to optimize the cache utilization and performance of the GPGPU.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more particularly to a self-adaptive method, device, and medium based on Warp scheduling and cache replacement. Background Art

[0002] Currently, general-purpose graphics processing units (GPGPUs) have become core accelerators in the field of high-performance computing, thanks to their cost-effectiveness and massively parallel computing capabilities. Compared to traditional CPUs, GPGPUs not only offer significant advantages in computational density and energy efficiency, but their architectural characteristics of massive computing cores also make them a key hardware platform supporting exascale computing. However, optimizing their on-chip storage systems still faces significant challenges, particularly in co-optimizing warp scheduling and cache management under dynamic load scenarios.

[0003] Current GPGPU warp schedulers (such as GTO and LRR) generally employ a static, single strategy, making them difficult to adapt to the locality characteristics of diverse programs. This results in low on-chip cache utilization and limited performance. In GPGPUs, the primary task of a warp scheduler is to dispatch instructions from a group of threads to available execution units for scheduling and execution according to a specific algorithm, thereby reducing memory access latency and completing tasks in a shorter timeframe. However, this static, single scheduling approach has several limitations. Uncertainty in memory access patterns and variability in thread execution in GPGPU programs significantly complicate warp scheduling. Static warp schedulers struggle to predict program behavior, making it difficult to effectively capture program locality through scheduling to improve performance. Single scheduling optimization methods typically target specific GPGPU issues. While they can achieve good results in some programs, they do not share the same performance bottlenecks in all programs. Consequently, this single scheduling optimization approach struggles to adapt to the memory access and computational characteristics of diverse GPGPU programs, making it difficult to achieve consistent results across diverse workloads.

[0004] Furthermore, GPGPU performance optimization depends not only on program data locality, warp scheduling, and cache strategies; cache replacement methods also have a significant impact on memory access efficiency. Using different cache management methods can lead to performance differences for the same program. Static, single-purpose cache management also has similar limitations. The core goal of GPGPU cache management is to minimize cache miss rates and maximize data locality within a limited cache capacity through appropriate replacement algorithms. However, static cache replacement algorithms (such as LRU and LFU) use a fixed replacement method, making them difficult to adapt to variations in cache hit rates under varying patterns. Specifically, the LRU algorithm, based on the least recently used principle, may cause data that is frequently accessed but has a long interval to be prematurely replaced. The LFU algorithm, based on access frequency, may not be able to adjust its replacement strategy in response to bursty access patterns. This makes it difficult for the cache to effectively capture data locality within the program, making performance improvements difficult to achieve.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The disclosed embodiments provide an adaptive method, device, and medium based on warp scheduling and cache replacement. By dynamically sensing the data locality characteristics of a program, combined with a locality sensing unit and a cache status monitor, the warp scheduling algorithm and cache replacement strategy are adaptively adjusted to optimize the cache utilization and performance of the GPGPU.

[0008] In some embodiments, the method comprises:

[0009] The locality awareness unit dynamically monitors the access behavior of warps in the L1 data cache and identifies the locality preference of the workload, which includes intra-warp locality and inter-warp locality.

[0010] Adaptively select a Warp scheduling algorithm based on the locality preference: if the locality preference is intra-Warp locality, use the GTO algorithm for scheduling; if the locality preference is inter-Warp locality, use the LRR algorithm for scheduling;

[0011] The cache status monitor periodically collects cache access counts and cache miss counts, calculates the memory miss rate of the current sampling period, and compares it with the miss rate of the previous sampling period;

[0012] If the memory miss rate of the current sampling period is higher than that of the previous sampling period, the cache replacement strategy is switched; if it is lower than or equal to that, the current strategy is maintained and the miss rate of the previous sampling period is updated;

[0013] Repeat the above steps until the program is finished.

[0014] Preferably, the locality awareness unit includes a plurality of entries, each entry corresponding to access information of a sample cache line in the L1 data cache;

[0015] Each entry contains: a flag bit, a warp internal hit counter, an inter-warp hit counter, and three history bits. The flag bit indicates the locality type of the cache line. The warp internal hit counter records the number of re-hits within the same warp. The inter-warp hit counter records the number of re-hits between different warps. The history bit stores the warp ID that most recently accessed the cache line.

[0016] The data cache is composed of a plurality of cache sets, each cache set containing cache lines of the same size;

[0017] When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when a cache miss occurs, a new entry is added and the current WarpID is recorded.

[0018] Preferably, when a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when a cache miss occurs, a new entry is added and the current WarpID is recorded, specifically in the following manner:

[0019] When a memory access request occurs, the target cache tag and the current WarpID are extracted. If the target cache tag is already included in the cache set, the locality awareness unit will look up the entry corresponding to the target cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set; if the WarpID of the current memory access request is included in the historical access set, the locality awareness unit will increase the corresponding Warp internal hit count bit; if the historical access set does not contain the current WarpID, the locality awareness unit will increase the corresponding Warp inter-hit count bit and add the current WarpID to the historical access set; if the current historical access set is full, the locality awareness unit will update the historical access set using a first-in-first-out method; if the cache tag is not in the cache set, the locality awareness unit will fill the cache tag and the current WarpID into a new entry and clear the historical access set.

[0020] Preferably, the local preference is determined by:

[0021] At the end of the sampling period, the intra-Warp hit counter of each entry is compared with the inter-Warp hit counter;

[0022] If the intra-Warp hit counter value is greater than the inter-Warp hit counter value, it is determined to be intra-Warp locality; otherwise, it is determined to be inter-Warp locality.

[0023] Preferably, the switching of the cache replacement strategy includes:

[0024] When the LRU algorithm is currently in use, switch to the LFU algorithm; or when the LFU algorithm is currently in use, switch to the LRU algorithm.

[0025] Preferably, the cache status monitor includes:

[0026] GPGPU memory access counter, used to accumulate the number of cache accesses within the sampling period;

[0027] GPGPU memory miss counter, used to accumulate the number of cache misses within the sampling period;

[0028] The previous sampling period missing rate register is used to store historical missing rate data.

[0029] Preferably, at the end of the sampling period, the locality sensing unit, the GPGPU memory access counter and the GPGPU memory access miss counter are cleared and reset.

[0030] Preferably, the LAU samples only one cache set in the L1 data cache to approximately characterize the overall cache behavior.

[0031] In some embodiments, the apparatus includes a processor and a memory storing program instructions, and the processor is configured to execute the adaptive method based on Warp scheduling and cache replacement when running the program instructions.

[0032] In some embodiments, the storage medium stores a computer program thereon, which, when executed by a processor, implements the adaptive method based on Warp scheduling and cache replacement.

[0033] The embodiments of the present disclosure provide an adaptive method, device, and medium based on Warp scheduling and cache replacement, which can achieve the following technical effects:

[0034] The Locality Awareness Unit (LAU) monitors cache access patterns across warps in real time, intelligently identifying the program's data locality characteristics (intra-warp / inter-warp), and dynamically switching scheduling policies (GTO / LRR). Combined with the cache status monitor's periodic monitoring of memory miss rates, the cache replacement policy (LRU / LFU) is dynamically adjusted, forming a dual adaptive mechanism. This effectively addresses the inability of traditional static policies to adapt to dynamic workloads, ensuring optimal system performance across diverse program characteristics.

[0035] Based on accurate judgment of warp locality types, GTO scheduling is used to strengthen access affinity within a warp, while LRR scheduling is used to promote data reuse between warps. Dynamic selection of LFU / LRU replacement strategies achieves a balance between burst access and regular access patterns, improving cache line reuse efficiency.

[0036] The core value of this invention lies in breaking through the limitations of the split optimization of scheduling and cache management in the traditional GPGPU architecture. By building an intelligent decision-making system with closed-loop feedback, it significantly improves the performance stability and resource utilization efficiency of heterogeneous computing platforms under complex workloads.

[0037] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0039] Figure 1 It is a schematic flow chart of the method of the present invention;

[0040] Figure 2 It is a logical schematic diagram of the method of the present invention;

[0041] Figure 3 This is a schematic diagram of the LAU local perception unit architecture;

[0042] Figure 4 It is a schematic diagram of the structure of the device of the present invention. DETAILED DESCRIPTION

[0043] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0044] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0045] Unless otherwise stated, the term "plurality" means two or more.

[0046] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0047] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0048] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0049] like Figure 1-Figure 2 ,An adaptive method based on Warp scheduling and cache replacement ,dynamically perceives the data locality characteristics of the program, ,combines the locality awareness unit (LAU) and the cache status monitor, and ,adaptively adjusts the Warp scheduling algorithm (GTO or LRR) and the cache replacement policy (LRU or LFU) to optimize the cache ,utilization and performance of GPGPU.

[0050] In some embodiments, the method comprises:

[0051] S1: Dynamically monitor the access behavior of Warps in the L1 data cache through the locality awareness unit to identify the locality preference of the workload, which includes intra-Warp locality and inter-Warp locality.

[0052] The locality awareness unit dynamically monitors warp access behavior, identifying the workload's intra- and inter-warp locality characteristics in real time. Based on these characteristics, it adaptively selects a scheduling algorithm (GTO or LRR), effectively reducing cache line contention caused by a mismatch between scheduling strategies and workload characteristics.

[0053] As a refinement of the above embodiment, the locality awareness unit includes a plurality of entries, each entry corresponding to access information of a sample cache line in the L1 data cache;

[0054] Each entry contains: a flag bit, a warp internal hit counter, an inter-warp hit counter, and three history bits. The flag bit indicates the locality type of the cache line. The warp internal hit counter records the number of re-hits within the same warp. The inter-warp hit counter records the number of re-hits between different warps. The history bit stores the warp ID that most recently accessed the cache line.

[0055] The data cache is composed of a plurality of cache sets, each cache set containing cache lines of the same size;

[0056] When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when a cache miss occurs, a new entry is added and the current WarpID is recorded. The specific method is as follows:

[0057] When a memory access request occurs, the target cache tag and the current WarpID are extracted. If the target cache tag is already included in the cache set, the locality awareness unit will look up the entry corresponding to the target cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set; if the WarpID of the current memory access request is included in the historical access set, the locality awareness unit will increase the corresponding Warp internal hit count bit; if the historical access set does not contain the current WarpID, the locality awareness unit will increase the corresponding Warp inter-hit count bit and add the current WarpID to the historical access set; if the current historical access set is full, the locality awareness unit will update the historical access set using a first-in-first-out method; if the cache tag is not in the cache set, the locality awareness unit will fill the cache tag and the current WarpID into a new entry and clear the historical access set.

[0058] The locality preference is determined by:

[0059] At the end of the sampling period, the intra-Warp hit counter of each entry is compared with the inter-Warp hit counter;

[0060] If the intra-Warp hit counter value is greater than the inter-Warp hit counter value, it is determined to be intra-Warp locality; otherwise, it is determined to be inter-Warp locality.

[0061] S2: Adaptively select a Warp scheduling algorithm based on the locality preference: if the locality preference is intra-Warp locality, use the GTO algorithm for scheduling; if the locality preference is inter-Warp locality, use the LRR algorithm for scheduling.

[0062] As a refinement of the above embodiment, the switching of the cache replacement strategy includes:

[0063] When the LRU algorithm is currently in use, switch to the LFU algorithm; or when the LFU algorithm is currently in use, switch to the LRU algorithm.

[0064] S3: The cache status monitor periodically collects cache access counts and cache miss counts, calculates the memory miss rate of the current sampling period, and compares it with the miss rate of the previous sampling period.

[0065] As a refinement of the above embodiment, the cache status monitor includes:

[0066] GPGPU memory access counter, used to accumulate the number of cache accesses within the sampling period;

[0067] GPGPU memory miss counter, used to accumulate the number of cache misses within the sampling period;

[0068] The previous sampling period missing rate register is used to store historical missing rate data.

[0069] S4: If the memory miss rate of the current sampling period is higher than that of the previous sampling period, the cache replacement strategy is switched; if it is lower than or equal to that of the previous sampling period, the current strategy is maintained and the miss rate of the previous sampling period is updated.

[0070] By periodically collecting cache access counts and miss rates and comparing them with historical data, dynamic feedback control of the cache replacement strategy is achieved.

[0071] S5: Repeat the above steps until the program ends.

[0072] The sampling period reset mechanism ensures the system's ability to respond quickly to periodic load changes.

[0073] At the end of the sampling period, the locality sensing unit, the GPGPU memory access counter and the GPGPU memory access miss counter are cleared and reset.

[0074] As a refinement of the above embodiment, the Locality Aware Unit (LAU) is used to monitor the behavior of Warp in the L1 data cache to identify the locality preference of the workload. The LAU contains multiple entries to store L1 cache access information. When the load instruction of the Warp is sent to the load / store (LD / ST) unit, a memory access request is generated, involving one or more memory transactions. The system first checks the L1 data cache, which consists of multiple cache sets, each cache set containing cache lines of the same size. Each memory transaction is assigned to the corresponding cache set, and the cache tag is checked to determine whether it hits. If the tag matches, it is a cache hit; otherwise, it is a cache miss.

[0075] To save hardware overhead, this embodiment samples only one cache set to approximate the performance of the entire L1 cache. In the LAU, each entry corresponds to a cache line in the sampled cache set and contains the following information: a flag bit indicating the cache line's locality type; two counters, one for recording intrahits within the same warp and one for recording interhits between warps; and three history bits, forming the warp history record, storing the warp IDs of previous accesses to the cache line.

[0076] When a memory access request occurs, if the cache tag is already in the cache set, the LAU searches for the entry corresponding to the cache line and determines the cache hit type based on the current WarpID and the WarpIDs of past accesses in the historical access set. If the historical access set contains the WarpID of the current memory access request, the LAU increments the corresponding intra-warp hit count bit. If the historical access set does not contain the current WarpID, the LAU increments the corresponding inter-warp hit count bit and adds the current WarpID to the historical access set. If the current historical access set is full, the LAU updates the historical access set using a first-in, first-out method. If the cache tag is not in the cache set, the LAU adds the cache tag and the current WarpID to a new entry and clears the historical access set. In this way, the LAU can continuously collect access information for both intra-warp locality and inter-warp locality for each data cache line until the end of the predefined sampling period.

[0077] The LAU categorizes the locality type of each entry into intra-warp locality and inter-warp locality. The LAU determines the locality type of a cache line by comparing the accumulated hit counts within a warp and the inter-warp hit counts for the corresponding cache entry during cache cycle sampling. If the Intra hit counter is greater than the Inter hit counter, the workload exhibits strong intra-warp locality, meaning that different threads within the same warp frequently access the same cache address. This means that multiple threads within the same warp have a higher cache hit rate. In this case, the warp scheduler selects the GTO algorithm to further enhance the workload's intra-warp locality. If the Intra hit counter is less than or equal to the Inter hit counter, the workload exhibits inter-warp locality, meaning that threads across different warps frequently access the same cache address. The warp scheduler selects the LRR algorithm for warp scheduling, allowing all warps to have equal priority.

[0078] In addition, we introduce a cache status monitor to detect the data cache status during the sampling period. The monitor consists of two counters: GPGPU memory access counter and GPGPU memory miss counters And the memory miss rate register of the previous sampling cycle It is composed of,recording the number of cache accesses and cache misses as well as the memory miss rate of the previous sampling period.,During the sampling period, if a memory access request occurs on the GPGPU, Add 1. If a cache request is detected to be missed while the GPGPU is making a cache request, a cache miss occurs. The counter Add 1. Based on the collected GPGPU memory access count information and memory access miss information, calculate the GPGPU memory access miss rate in this sampling period. The calculation formula is as follows:

[0079] ,

[0080] The GPGPU memory miss rate information can reflect the efficiency of cache utilization by the replacement strategy adopted by the GPGPU in the sampling period. Higher than the missing rate information of the previous sampling period , it means that the current cache replacement strategy may not be suitable for the current operating state. A different replacement strategy is needed to increase the GPGPU cache utilization efficiency and keep the miss rate information of the previous sampling cycle unchanged. If it is less than or equal to the miss rate information of the previous sampling cycle, the current strategy is kept unchanged and the miss rate information of the previous sampling cycle is updated. The formula is as follows:

[0081] ,

[0082] When entering the next sampling cycle, the locality awareness unit LAU and two counters GPGPU memory access counter and GPGPU memory miss counters Perform zero reset and repeat the sampling cycle process until the program ends.

[0083] Combine Figure 4 As shown, an embodiment of the present disclosure provides an adaptive device 300 based on warp scheduling and cache replacement, comprising a processor 304 and a memory 301. Optionally, the device may also include a communication interface 302 and a bus 303. The processor 304, communication interface 302, and memory 301 may communicate with each other via bus 303. The communication interface 302 may be used for information transmission. The processor 304 may invoke logic instructions in the memory 301 to execute the adaptive method based on warp scheduling and cache replacement according to the above embodiment.

[0084] In addition, the logic instructions in the memory 301 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0085] Memory 301, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 304 executes the program instructions / modules stored in memory 301 to execute functional applications and data processing, thereby implementing the adaptive method based on warp scheduling and cache replacement in the above-mentioned embodiments.

[0086] The memory 301 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 301 may include high-speed random access memory and non-volatile memory.

[0087] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned adaptive method based on Warp scheduling and cache replacement.

[0088] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

Claims

1. An adaptive method based on Warp scheduling and cache replacement, characterized in that: The following steps are involved: The locality awareness unit dynamically monitors the access behavior of warps in the L1 data cache and identifies the locality preference of the workload, which includes intra-warp locality and inter-warp locality. Adaptively select a Warp scheduling algorithm based on the locality preference: if the locality preference is intra-Warp locality, use the GTO algorithm for scheduling; if the locality preference is inter-Warp locality, use the LRR algorithm for scheduling; The cache status monitor periodically collects cache access counts and cache miss counts, calculates the memory miss rate of the current sampling period, and compares it with the miss rate of the previous sampling period; If the memory miss rate in the current sampling period is higher than that in the previous sampling period, the cache replacement strategy is switched; If it is lower than or equal to, the current strategy is maintained and the missing rate of the previous sampling period is updated; Repeat the above steps until the program is finished; The locality awareness unit includes a plurality of entries, each entry corresponding to access information of a sample cache line in the L1 data cache; Each entry contains: a flag bit, a warp internal hit counter, an inter-warp hit counter, and three history bits. The flag bit indicates the locality type of the cache line. The warp internal hit counter records the number of re-hits within the same warp. The inter-warp hit counter records the number of re-hits between different warps. The history bit stores the warp ID that most recently accessed the cache line. The data cache is composed of a plurality of cache sets, each cache set containing cache lines of the same size; When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set; when a cache miss occurs, a new entry is added and the current WarpID is recorded; When a memory access request occurs, the locality awareness unit updates the corresponding hit counter based on the matching relationship between the current WarpID and the historical access set. When a cache miss occurs, a new entry is added and the current WarpID is recorded. The specific method is as follows: When a memory access request occurs, the target cache tag and the current WarpID are extracted. If the target cache tag is already included in the cache set, the locality awareness unit will look up the entry corresponding to the target cache line and determine the cache hit type based on the current WarpID and the WarpID of the past access in the historical access set; if the WarpID of the current memory access request is included in the historical access set, the locality awareness unit will increase the corresponding Warp internal hit count bit; if the historical access set does not contain the current WarpID, the locality awareness unit will increase the corresponding Warp inter-hit count bit and add the current WarpID to the historical access set; if the current historical access set is full, the locality awareness unit will update the historical access set using a first-in-first-out method; if the cache tag is not in the cache set, the locality awareness unit will fill the cache tag and the current WarpID into a new entry and clear the historical access set.

2. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The locality preference is determined by: At the end of the sampling period, the intra-Warp hit counter of each entry is compared with the inter-Warp hit counter; If the intra-Warp hit counter value is greater than the inter-Warp hit counter value, it is determined to be intra-Warp locality; Otherwise, it is determined to be inter-Warp locality.

3. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The switching of the cache replacement strategy includes: When the LRU algorithm is currently in use, switch to the LFU algorithm; or when the LFU algorithm is currently in use, switch to the LRU algorithm.

4. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The cache status monitor includes: GPGPU memory access counter, used to accumulate the number of cache accesses within the sampling period; GPGPU memory miss counter, used to accumulate the number of cache misses within the sampling period; The previous sampling period missing rate register is used to store historical missing rate data.

5. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: At the end of the sampling period, the locality sensing unit, the GPGPU memory access counter and the GPGPU memory access miss counter are cleared and reset.

6. The adaptive method based on Warp scheduling and cache replacement according to claim 1, characterized in that: The locality awareness unit samples only one cache set in the L1 data cache to approximately characterize the overall cache behavior.

7. An adaptive device based on Warp scheduling and cache replacement, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the adaptive method based on Warp scheduling and cache replacement according to any one of claims 1 to 6 when running the program instructions.

8. A computer-readable storage medium, characterized in that A computer program is stored thereon, and when the program is executed by a processor, the adaptive method based on Warp scheduling and cache replacement as described in any one of claims 1 to 6 above is implemented.

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