Cache access method, cache, chip, storage medium and program product

Abstract

The invention relates to a cache access method and device, a chip, equipment, a storage medium and a program product. The method comprises the following steps: receiving a cached first access request, wherein the first access request comprises a first access address; according to the first access address, tag information stored in a tag memory is inquired, each piece of tag information comprises address information and intermediate state information, and the intermediate state information is used for representing the state of a corresponding cache line in a data memory corresponding to the address information in the tag information; and under the condition that address information in mark information stored in the mark memory fails to be matched with the first access address, determining a target cache line according to intermediate state information in the mark memory, processing the first access request, and updating the intermediate state information of the target cache line, the target cache line is used for caching target data of the first access request. By adopting the method, the cache access efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly relates to a cache access method, a cache, a chip, a storage medium and a program product. BACKGROUND

[0002] Cache is an important component in modern computer architecture, which is used to establish a high-speed buffer layer between a processor and a main memory, so as to reduce the time delay of the processor accessing the main memory and improve the overall performance of the system.

[0003] In the related art, when cache access is performed, if the address in the access request does not hit the address in the tag information of the cache, a cache line in the cache needs to be allocated or replaced. Meanwhile, the tag information of the allocated or replaced cache line needs to be locked until the data is read or written from the allocated or replaced cache line based on the access request, which results in a long access delay of the missed access request.

[0004] However, according to the principle of the cache, the access request of a certain way under the same index group (Set index) cannot operate the access request of other ways under the same index group (Set index) without being completed, and therefore, the access delay of the missed access request affects the overall access delay, thereby resulting in low cache access efficiency. SUMMARY

[0005] Therefore, it is necessary to provide a cache access method, a cache, a chip, a storage medium and a program product capable of improving cache access efficiency in view of the above technical problems.

[0006] In a first aspect, the present application provides a cache access method, wherein the cache comprises a tag memory, a data memory and a processing unit, and the method comprises the following steps:

[0007] The processing unit receives a first access request of the cache, and the first access request comprises a first access address;

[0008] The processing unit queries tag information stored in the tag memory according to the first access address, wherein each tag information comprises address information and intermediate state information, and the intermediate state information is used to represent the state of the corresponding cache line in the data memory corresponding to the address information in the tag information;

[0009] The processing unit determines a target cache line according to the intermediate state information in the tag memory, processes the first access request, and updates the intermediate state information of the target cache line in a case where address information in tag information stored in the tag memory fails to match the first access address, wherein the target cache line is used to cache target data of the first access request.

[0010] In one of the embodiments, the processing unit determines a target cache line according to the intermediate state information in the tag memory, processes the first access request, and updates the intermediate state information of the target cache line, including:

[0011] When the intermediate state information stored in the tag memory is first state information, a cache line is determined as a target cache line from a cache line corresponding to the first state information;

[0012] The address information in tag information corresponding to the target cache line is updated as the first access address, and the intermediate state information is updated as second state information;

[0013] The target data is written into the target cache line;

[0014] After the target data is written into the target cache line, the intermediate state information is updated as third state information;

[0015] The first state information is used to indicate that a corresponding cache line is an idle cache line and that no access request is used to process target data of the cache line; the second state is used to indicate that the target data is written into the target cache line; and the third state information indicates that data cached in the target cache line is in a valid state and is not in a data writing or reading process.

[0016] In one of the embodiments, the method further includes:

[0017] In response to the second state information, locking related access requests of the first access address, the related access requests being other access requests except the first access request;

[0018] In response to the third state information, releasing the related access requests of the first access address.

[0019] In one of the embodiments, the processing unit determines a target cache line according to the intermediate state information in the tag memory, processes the first access request, and updates the intermediate state information of the target cache line, including:

[0020] determining a target cache line from the intermediate state information corresponding to a cache line of third state information, in a case that the intermediate state information stored in the mark storage is not the first state information;

[0021] updating the intermediate state information of the target cache line as fourth state information, and writing data cached in the target cache line into a memory;

[0022] updating the intermediate state information of the target cache line as fifth state information after completing writing data in the target cache line into the memory;

[0023] writing target data of the first access request into the target cache line;

[0024] updating the intermediate state information of the target cache line as the third state information after completing writing the target data into the target cache line;

[0025] The fourth state information is used to indicate that the target cache line is not an idle cache line, and the target cache line is in a process of writing cached data into a corresponding memory; and the fifth state information is used to indicate that the target cache line is in a process of writing target data into the target cache line after writing the cached data into the memory.

[0026] In one of the embodiments, the method further comprises:

[0027] locking related access requests corresponding to the first access address and a second access address in response to the fourth state information, the second access address being address information corresponding to data written into the memory in the target cache line;

[0028] releasing the related access request corresponding to the second access address in response to the fifth state information;

[0029] releasing the related access request corresponding to the first access address in response to the third state information.

[0030] In one of the embodiments, the intermediate state information comprises valid bit information and cache line state information.

[0031] The valid bit information is used to indicate whether the cache line is in a valid state,

[0032] The cache line state information is used to indicate a substate in the valid state and a substate in an invalid state.

[0033] In a second aspect, the application provides a cache comprising a mark storage, a data storage and a processing unit.

[0034] The marking memory is used for storing marking information, each of which includes address information and intermediate state information, and the intermediate state information is used for representing the state of the corresponding cache line in the data memory corresponding to the address information in the marking information.

[0035] The data memory is used for caching target data of the access request.

[0036] The processing unit is used for executing the cache access method in the first aspect.

[0037] In a third aspect, the present application further provides a chip including a memory and a processor, the memory stores a computer program, and the processor executes the computer program to implement the cache access method in the first aspect.

[0038] In a fourth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method steps.

[0039] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the cache access method in the first aspect.

[0040] The cache access method, cache, chip, storage medium and program product are used for receiving a first access request of a cache, the first access request including a first access address; querying marking information stored in a marking memory according to the first access address, each of the marking information including address information and intermediate state information, and the intermediate state information being used for representing the state of a corresponding cache line in a data memory corresponding to the address information in the marking information; in the case that the address information in the marking information stored in the marking memory fails to match the first access address, determining a target cache line according to the intermediate state information in the marking memory, processing the first access request, and updating the intermediate state information of the target cache line, wherein the target cache line is used for caching target data of the first access request. Since the intermediate state information is added in the marking information, and in the case that the access address fails to match, the target cache line caching the target data of the first access request is determined based on the intermediate state information, and the intermediate state information of the target cache line is updated, so that the access request corresponding to different access addresses can be controlled in real time through the intermediate state information, and the access request corresponding to other irrelevant access addresses is no longer affected, thereby effectively improving the cache access efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the cache structure in related technologies;

[0043] Figure 2 This is a schematic diagram of the structure of multi-level caches in related technologies;

[0044] Figure 3 A flowchart illustrating a cache access method provided in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of the marking information in the prior art;

[0046] Figure 5 To and Figure 4 A diagram illustrating the corresponding tagging information;

[0047] Figure 6 A schematic diagram of the marking information provided in the embodiments of this application;

[0048] Figure 7 To and Figure 6 A diagram showing the corresponding marking information in the diagram;

[0049] Figure 8 A flowchart illustrating another cache access method provided in an embodiment of this application;

[0050] Figure 9 This is a structural block diagram of a cache access device provided in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] The relevant technologies will be explained below.

[0053] Cache is an important component of modern computer architecture, used to establish a high-speed buffer layer between the processor and main memory to reduce the time latency of the processor accessing main memory and improve the overall performance of the system.

[0054] Figure 1A structure diagram of a cache in the related art is shown in FIG. 1, which includes a cache control (CacheCtrl) unit, a cache line, and a tag information storage (Tag Ram). Figure 1

[0055] The cache control unit can receive a cache access request, which can be used for a cache operation corresponding to a write data (W data), a read data (R data), or a command prompt (Cmd).

[0056] It should be understood that the cache can be divided into a plurality of fixed-size units, each of which can be the above-mentioned cache line. The cache line is the smallest independently accessible storage unit in the cache, and its size is usually 64 bytes, etc. The cache usually does not use a simple linear storage space, but uses a set-associative or direct-mapped manner to organize. For example, in a set-associative structure, the cache can be divided into a plurality of cache sets / ways, each of which contains a plurality of cache lines. When a main memory address is mapped to the cache, it is determined to which cache set it belongs according to part of the address information, and the cache lines in the cache set can be distinguished by additional address information.

[0057] It should be understood that each cache line can be provided with a Tag Ram in addition to storing data, which includes one or more fields for storing tag information associated with the main memory address to determine whether the data in the cache line matches the data requested by the main memory.

[0058] The tag information in the Tag Ram includes a valid bit and a dirty bit. The valid bit is used to indicate whether the data in the cache line is valid. If the valid bit indicates that the data in the cache line is invalid, it means that the cache line has not been used to store the main memory data, or the previous data in the cache line has been replaced. The dirty bit is used to indicate whether the data in the cache line has been modified, i.e., whether the data in the cache line is inconsistent with the data in the corresponding position of the main memory. If the value of the dirty bit is 0, it indicates that the data in the cache line has not been modified, and if the value of the dirty bit is 1, it indicates that the data in the cache line is inconsistent with the data in the corresponding position of the main memory before the data is written back to the main memory.

[0059] It should be understood that through the above structure of the cache, the cache can hide the main memory access delay to a certain extent, and improve the data acquisition speed of the processor.

[0060] ​With the development of technology, processors can include multi-level cache structures, such as L1 cache, L2 cache, L3 cache, etc. The capacity, speed and structural details of each cache level may be different. The memory access time of each cache level can be determined by formula (1).

[0061] (1)

[0062] in, For average storage access time, The access time when the cache is hit. To mitigate the failure rate of cached access. Additional access latency when the cache expires.

[0063] Figure 2 This is a schematic diagram of the structure of multi-level caches in related technologies, such as... Figure 2 As shown, this multi-level cache is a Level 4 cache. Compared to traditional caches, the L4 cache in this multi-level cache does not use the chip's internal Static Random-Access Memory (SRAM) cells, but instead uses DDR as the data cache area for cache lines. Furthermore, the L4 cache is connected to a Compute Express Link (CXL) solid-state drive (SSD) via a high-speed serial bus root port (Peripheral Component Interconnect Express Root Port, PCIe RP). When accessing the cache in this L4 cache, if a cache hit occurs, the latency for accessing DDR is between 100 nanoseconds (ns) and 200 ns. If a cache miss occurs, access to the CXL SSD is possible, with a latency of approximately 2 microseconds (µs).

[0064] In related technologies, when accessing the cache, if the address in the access request does not match the address in the cache's tag information, a cache line needs to be allocated or replaced in order to write the data from the access request into the allocated or replaced cache line. Simultaneously, the tag information of the allocated or replaced cache line needs to be locked until the data from the access request is written into the allocated or replaced cache line. This results in a longer access delay for missed access requests.

[0065] For example, the access delay of a traditional cache hit is about 10 ns, and the access delay of a cache miss is between 100 ns and ~200 ns. In the L4 Cache structure described above, the delay is 10 times that of a traditional cache, which causes the state update time of the tag information to linearly increase due to the delay of the access. According to the principle of the cache, an access request of a certain way under a set index cannot operate an access request of another way under the set index until the access request of the certain way is completed. Therefore, the access delay of the access request of the cache miss affects the overall access delay, thereby causing low cache access efficiency.

[0066] To solve the above problem, an embodiment of the present application provides a cache access method, a cache, a chip, a storage medium, and a program product. Intermediate state information is added in the tag information, and in the case of a failed access address match, the target cache line of the target data of the first access request of the cache is determined based on the intermediate state information, and the intermediate state information of the target cache line is updated, so that the access requests corresponding to different access addresses can be controlled in real time through the intermediate state information, and the access requests corresponding to other irrelevant access addresses are no longer affected, thereby effectively improving the cache access efficiency.

[0067] In an exemplary embodiment, as shown in Figure 3 A cache access method is provided, including S201 to S203:

[0068] S201, receiving a first access request.

[0069] In the present application, when the cache needs to be accessed, a first access request can be sent to the cache.

[0070] The first access request includes a first access address. The first access request can include a write request, a read request, etc., and the present application does not limit this. The first access address can be the address corresponding to the target write data in the main memory.

[0071] S202, querying the tag information stored in the tag storage according to the first access address.

[0072] In this step, after receiving the first access request of the cache, the cache can query the tag information stored in the tag storage according to the first access address.

[0073] In some embodiments, the cache includes a tag memory and a data memory. The tag memory stores a plurality of tag information, each of which includes address information and intermediate state information, the intermediate state information being used to represent the state of a corresponding cache line in the data memory corresponding to the address information in the tag information. Correspondingly, the data memory includes a plurality of cache lines, each of which corresponds to a tag information in the tag memory.

[0074] It should be understood that embodiments of the present application do not limit the intermediate state information, and in some embodiments, the intermediate state information includes valid bit information and cache line state information. The valid bit information is used to indicate whether the cache line is in a valid state. The cache line state information is used to indicate the substate in the valid state and the substate in the invalid state.

[0075] Exemplarily, Figure 4 and Figure 5 As shown in a schematic diagram of a tag information in the prior art, Figure 4 and Figure 5 The tag information includes valid bit (V) information, address information, dirty bit information and least recently used (LRU) information. The valid bit information is used to indicate whether the data in the corresponding cache line is valid, the address information is used to indicate the address associated with the main memory of the corresponding cache line, the dirty bit information is used to indicate whether the data in the corresponding cache line is modified, and the LRU information is used to indicate whether the data stored in the corresponding cache line is the least recently used data.

[0076] Exemplarily, Figures 6-7 As shown in a schematic diagram of a tag information provided by embodiments of the present application, Figures 6-7 As shown in the tag information shown in Figure 4 An additional cache line state information (P) is added on the basis of the tag information shown in

[0077] Exemplarily, the valid bit information V can be represented by 1 or 0, the valid bit information V being 1 indicates that the cache line is in an invalid state, and the valid bit information V being 0 indicates that the cache line is in a valid state.

[0078] For example, the cache line state information can be represented by two or more bits, such as two bits, 00, 01, 10, 11, etc. For example, the cache line state information 00 represents the no-operation substate when the cache line is in the valid state, and is combined with the valid cache line state information 0 to form the first state information 3b000. For example, the cache line state information 01 represents the cache line write substate when the cache line is in the valid state, and is combined with the valid cache line state information 0 to form the second state information 3b001. For example, the cache line state information 10 and 11 represent the reserved state when the cache line is in the valid state, and are combined with the valid cache line state information 0 to form 3b010 and 3b011.

[0079] For example, the cache line state information 00 represents the no-operation substate when the cache line is in the invalid state, and is combined with the invalid cache line state information 1 to form the third state information 3b100. For example, the cache line state information 01 represents the process of writing the cached data into the corresponding memory when the cache line is in the invalid state, and is combined with the invalid cache line state information 1 to form the fourth state information 3b101. For example, the cache line state information 10 represents the process of writing the target data into the target cache line after writing the cached data into the memory when the cache line is in the invalid state, and is combined with the invalid cache line state information 1 to form the fifth state information 3b101. For example, the cache line state information 11 represents the reserved state when the cache line is in the invalid state, and is combined with the invalid cache line state information 1 to form 3b111.

[0080] In this application, the cache can compare the first access address with the address information in each tag information in the tag memory in sequence to determine whether there is the same address information as the first access address in the tag information in the tag memory. After the same address information is found, the valid bit information can be further determined. If the same address is found and the valid bit information indicates that the cache line is in the valid state, it is determined that the address information in the tag information matches the first access address successfully. If the same address is not found, or the same address is found but the valid bit information indicates that the cache line is in the invalid state, it is determined that the address information in the tag information does not match the first access address.

[0081] S203, in the case that the address information in the tag information stored in the tag memory does not match the first access address, the target cache line is determined according to the intermediate state information in the tag memory, the first access request is processed, and the intermediate state information of the target cache line is updated, wherein the target cache line is used to cache the target data of the first access request.

[0082] It should be understood that the embodiments of the present application do not limit how to determine whether the address information in the tag information stored in the tag memory matches the first access address or not.

[0083] In some embodiments, the tag information stored in the tag memory can be queried according to the first access address, and there can be two query results, including that the address information in the tag information stored in the tag memory does not match the first access address, and that the address information in the tag information stored in the tag memory matches the first access address.

[0084] In some embodiments, if the address information in the target tag information is the same as the first access address and the valid bit information in the tag information corresponding to the target tag information indicates that the corresponding cache line is valid, it is determined that the address information in the tag information stored in the tag memory matches the first access address. That is, the access cache hits.

[0085] The target tag information is any tag information stored in the tag memory.

[0086] For example, the valid bit information in the tag information can be a Valid bit, and when the Valid bit is 0, the data in the cache line is valid. When the Valid bit is 1, the cached data in the cache line is invalid.

[0087] For example, the first access address in the first access request includes a physical address, an index, and an offset. The physical address and the index can be matched with the address information of the tag information, and after the matching is successful, the offset can be used to determine the specific access position in the matched cache line.

[0088] In other embodiments, if the address information in the target tag information is different from the first access address or the valid bit information in the tag information corresponding to the target tag information indicates that the corresponding cache line is invalid, it is determined that the address information in the tag information stored in the tag memory does not match the first access address. That is, the access cache misses.

[0089] It should be understood that in the case that the address information in the tag information stored in the tag memory does not match the first access address, the subsequent access operation can be performed based on the intermediate state information in the tag memory. Generally, there are two ways, including that there is a free cache line and that there is no free cache line.

[0090] The case that there is a free cache line will be described below.

[0091] In some embodiments, when the intermediate state information stored in the tag memory is the first state information, the cache first determines a target cache line of cache behavior from the cache line corresponding to the first state information. Then, the cache updates the address information in the tag information corresponding to the target cache line to the first access address, and updates the intermediate state information to the second state information. Finally, the cache writes the target data into the target cache line, and after completing the writing of the target data into the target cache line, updates the intermediate state information to the third state information.

[0092] The first state information is used to indicate that the corresponding cache line is an idle cache line and that the target data processing of the cache line by the first access request is not performed. The second state is used to indicate that the target data is being written into the target cache line. The third state information indicates that the data cached in the target cache line is in a valid state and is not in the process of data writing or reading.

[0093] For example, if there are multiple idle cache lines, the target cache line can be randomly selected from the multiple idle cache lines, or the target cache line can be selected from the multiple idle cache lines according to the order of the cache lines, or the target cache line can be selected from the multiple idle cache lines according to the usage frequency of the cache lines.

[0094] For example, the idle cache line does not store data, and the corresponding intermediate state information can be 3b000. Second, the cache determines a target cache line of cache behavior from the cache line with the intermediate state information of 3b000. Third, the cache updates the address information in the tag information corresponding to the target cache line to the first access address, and updates the intermediate state information to 3b001 (second state information). Finally, the cache writes the target data into the target cache line, and after completing the writing of the target data into the target cache line, updates the intermediate state information to 3b100 (third state information). In addition, one or more intermediate state information, including 3b010 and 3b011, can be reserved to set the state of more cache lines.

[0095] It should be understood that when there are idle cache lines, the related access request of the first access address can also be locked or released in different intermediate states of the target cache line. The related access request is other access request in addition to the first access request.

[0096] In some embodiments, in response to the second state information, the related access request of the first access address is locked, and the related access request is other access request in addition to the first access request. In response to the third state information, the related access request of the first access address is released.

[0097] That is, in the process of writing the target data of the first access request into the target cache line, after the address information in the tag information corresponding to the target cache line is updated to the first access address, the intermediate state information of the target cache line is changed to the first state information, the related access requests of the first access address except the first access request are locked, and the access requests of other addresses have no effect and can continue to be executed. Correspondingly, after the target data of the first access request is written, the intermediate state information of the target cache line is changed to the second state information, the related access requests of the first access address are released, and the updating process of the target cache line is completed.

[0098] The case where there is no idle cache line will be described below.

[0099] In some embodiments, when the intermediate state information stored in the tag memory does not have the first state information, the cache first determines a target cache line from the cache line whose intermediate state information is the third state information. Secondly, the cache updates the intermediate state information of the target cache line to the fourth state information, and writes the data in the target cache line in the cache into the memory. Thirdly, after the cache completes writing the data in the target cache line into the memory, the cache updates the intermediate state information of the target cache line to the fifth state information, and writes the target data of the first access request into the target cache line. Finally, after the cache completes writing the target data into the target cache line, the cache updates the intermediate state information of the target cache line to the third state information.

[0100] For example, the cache access device can randomly select a target cache line from a plurality of cache lines, or can select a target cache line from a plurality of cache lines according to the order of the cache lines, or can select a target cache line from a plurality of cache lines according to the usage frequency of the cache lines.

[0101] It should be understood that, since the target cache line is not an idle cache line, before writing the target data corresponding to the first access request, the cache invalidation strategy needs to be executed, including reading the data from the target cache line and writing it back to the actual memory, so that the data originally stored in the target cache line is invalidated, and then the target cache line is allocated to the first access request.

[0102] Correspondingly, for the case where there is no idle cache line in the cache, in the process of performing the invalidation operation on the target cache line and performing the access operation corresponding to the first access request, the intermediate state information of the target cache line can be updated in real time, including updating to the fourth state information, the fifth state information and the third state information.

[0103] The fourth state information is used for indicating that the target cache behavior is a non-idle cache line and the target cache line is in the process of writing the cached data into the corresponding memory; the fifth state information is used for indicating that the target data is in the process of being written into the target cache line after the cached data is written into the memory; and the third state information indicates that the data cached in the target cache line is in a valid state and is not in the process of data writing or reading.

[0104] For example, the selected target cache behavior data is in a valid state and is not in the process of data writing or reading, and the corresponding intermediate state information of the cache line can be 3b100 (third state information). After the selection of the target cache line is completed, the intermediate state information of the target cache line can be changed from 3b100 (third state information) to 3b101 (fourth state information) to indicate that the target cache behavior is a non-idle cache line and the target cache line is in the process of writing the cached data into the corresponding memory. After the data in the target cache line is written into the memory, the intermediate state information of the target cache line can be changed from 3b101 (fourth state information) to 3b110 (fifth state information) to indicate that the target data is in the process of being written into the target cache line after the cached data is written into the memory. Finally, after the target data is written into the target cache line, the intermediate state information of the target cache line can be changed from 3b110 (fifth state information) to 3b100 (third state information).

[0105] It should be understood that when there is an idle cache line, the related access requests of the first access address and the second cache line can also be locked or released when the target cache line is in different intermediate states. The second access address is the address information corresponding to the data in the target cache line written into the memory.

[0106] In some embodiments, in response to the fourth state information, the related access requests of the first access address and the second access address are locked, and the second access address is the address information corresponding to the data in the target cache line written into the memory. In response to the fifth state information, the related access request of the second access address is released. In response to the third state information, the related access request of the first access address is released.

[0107] That is, in the process of writing the data cached in the target cache line into the memory, the target cache behavior is in the fourth state information, at this time, the related access requests of the first access address and the second access address are locked, and the access requests of other addresses have no effect and can continue to be executed. After the data in the target cache line is written into the memory, the intermediate state of the target cache line is updated to the fifth state information, at this time, the related access request of the second access address is released. After the target data is written into the target cache line, the intermediate state of the target cache line is updated to the third state information, at this time, the related access request of the first access address is released.

[0108] The cache access method provided by the embodiments of the present application receives a first access request of a cache, and the first access request comprises a first access address. According to the first access address, the tag information stored in a tag storage is queried, wherein each piece of tag information comprises address information and intermediate state information, and the intermediate state information is used to represent the state of the corresponding cache line in the data storage corresponding to the address information in the tag information. In the case that the address information in the tag information stored in the tag storage fails to match the first access address, the target cache line is determined according to the intermediate state information in the tag storage, the first access request is processed, and the intermediate state information of the target cache line is updated, wherein the target cache line is used to cache the target data of the first access request. Since the intermediate state information is added in the tag information, and in the case that the access address fails to match, the target cache line caching the target data of the first access request is determined based on the intermediate state information, and the intermediate state information of the target cache line is updated, so that the access requests corresponding to different access addresses can be controlled in real time through the intermediate state information, and the access requests corresponding to other irrelevant access addresses are no longer affected, thereby effectively improving the cache access efficiency.

[0109] Figure 8 The flowchart of another cache access method provided by the embodiments of the present application is shown in FIG. 3, and the cache access method comprises S301 to S312. Figure 8

[0110] S301, a first access request of a cache is received.

[0111] The first access request comprises a first access address, and the cache comprises a plurality of cache lines, each cache line corresponding to a tag information, and each tag information comprising address information and intermediate state information.

[0112] S302, according to the first access address, the tag information stored in a tag storage is queried.

[0113] Each piece of tag information comprises address information and intermediate state information, and the intermediate state information is used to represent the state of the corresponding cache line in the data storage corresponding to the address information in the tag information.

[0114] S303, in the case that the address information in the tag information stored in the tag storage fails to match the first access address, it is determined whether the cache line of the first state information is stored in the tag storage, if yes, S304 is executed, and if no, S308 is executed.

[0115] The first state information is used to represent that the corresponding cache line is an idle cache line and the cache line is not processed by the target data of the first access request. ​

[0116] S304, determining a target cache line from the cache line corresponding to the first state information.

[0117] S305, updating the address information in the tag information corresponding to the target cache line as the first access address, and updating the intermediate state information as the second state information.

[0118] The second state is used to indicate the process of writing the target data into the target cache line.

[0119] In some embodiments, in response to the second state information, the cache can lock the related access request of the first access address, which is other access request than the first access request.

[0120] S306, writing the target data into the target cache line.

[0121] S307, updating the intermediate state information as the third state information after completing the writing of the target data into the target cache line.

[0122] The third state information indicates that the data cached in the target cache line is in a valid state, and is not in the process of data writing or reading.

[0123] In some embodiments, in response to the third state information, the cache can release the related access request of the first access address.

[0124] S308, determining a target cache line from the cache line corresponding to the third state information of the intermediate state information.

[0125] S309, updating the intermediate state information of the target cache line as the fourth state information, and writing the data cached in the target cache line into the memory.

[0126] The fourth state information is used to indicate that the target cache line is not an idle cache line, and the target cache line is in the process of writing the cached data into the corresponding memory.

[0127] In some embodiments, in response to the fourth state information, the cache locks the related access request corresponding to the first access address and the second access address, and the second access address is the address information corresponding to the data written into the memory in the target cache line.

[0128] S310, updating the intermediate state information of the target cache line as the fifth state information after completing the writing of the data in the target cache line into the memory.

[0129] The fifth state information is used to indicate that the process of writing the target data into the target cache line is in the process of writing the cached data into the memory.

[0130] In some embodiments, in response to the fifth state information, the cache releases the relevant access request corresponding to the second access address.

[0131] S311, write the target data of the first access request into the target cache line.

[0132] S312, after completing the writing of the target data into the target cache line, update the intermediate state information of the target cache line to the third state information, and update the address information of the target cache line to the first access address.

[0133] In some embodiments, in response to the third state information, the cache releases the relevant access request corresponding to the first access address.

[0134] The cache access method provided by the embodiments of the present application receives a first access request of a cache, and the first access request includes a first access address; according to the first access address, the tag information stored in a tag storage is queried, wherein each tag information includes address information and intermediate state information, and the intermediate state information is used to represent the state of the corresponding cache line in the data storage corresponding to the address information in the tag information; in the case that the address information in the tag information stored in the tag storage fails to match the first access address, the target cache line is determined according to the intermediate state information in the tag storage, the first access request is processed, and the intermediate state information of the target cache line is updated, wherein the target cache line is used to cache the target data of the first access request. Since the intermediate state information is added in the tag information, and in the case that the access address fails to match, the target cache line for caching the target data of the first access request is determined based on the intermediate state information, and the intermediate state information of the target cache line is updated, so that the access request corresponding to different access addresses can be controlled in real time through the intermediate state information, and the access request corresponding to other irrelevant access addresses is no longer affected, thereby effectively improving the cache access efficiency.

[0135] It should be understood that, although each step in the flowchart involved in the above embodiments is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0136] Based on the same inventive concept, the embodiments of the present application also provide a cache access device for implementing the cache access method described above. The implementation scheme of the device for solving the problem is similar to the implementation scheme described in the above method, so the specific limitations in one or more cache access device embodiments provided below can refer to the limitations of the cache access method described above, which will not be repeated here.

[0137] In one exemplary embodiment, as shown in Figure 9 a cache 400 is provided, which includes a tag memory 401, a data memory 402 and a processing unit 403:

[0138] The tag memory 401 is used to store tag information.

[0139] The data memory 402 is used to cache target data of a cache access request.

[0140] The processing unit 403 receives a first access request of the cache, the first access request including a first access address; according to the first access address, the tag information stored in the tag memory 401 is queried, wherein each tag information includes address information and intermediate state information, the intermediate state information is used to represent the state of the corresponding cache line in the data memory 402 corresponding to the address information in the tag information; in the case that the address information in the tag information stored in the tag memory 401 fails to match the first access address, the target cache line is determined according to the intermediate state information in the tag memory 401, the first access request is processed, and the intermediate state information of the target cache line is updated, wherein the target cache line is used to cache the target data of the first access request.

[0141] In some embodiments, the target cache line is determined according to the intermediate state information in the tag memory 401, the first access request is processed, and the intermediate state information of the target cache line is updated, including:

[0142] When the intermediate state information stored in the tag memory 401 is first state information, a cache line corresponding to the first state information is determined as the target cache line.

[0143] The address information in the tag information corresponding to the target cache line is updated to the first access address, and the intermediate state information is updated to second state information.

[0144] The target data is written into the target cache line.

[0145] After completing the writing of the target data into the target cache line, the intermediate state information is updated to third state information.

[0146] The first state information is used to indicate that the corresponding cache line is an idle cache line and no access request is used to perform target data processing on the cache line; the second state information is used to indicate that the target data is being written into the target cache line; and the third state information is used to indicate that the data cached in the target cache line is in a valid state and is not in a data writing or reading process.

[0147] In some embodiments, the processing unit 403 is further configured to, in response to the second state information, lock a related access request of the first access address, the related access request being an access request other than the first access request; and in response to the third state information, release the related access request of the first access address.

[0148] In some embodiments, the processing unit 403 is further configured to, in response to the second state information, lock a related access request of the first access address, the related access request being an access request other than the first access request; and in response to the third state information, release the related access request of the first access address.

[0149] In a case where the intermediate state information stored in the tag memory 401 does not include the first state information, a cache line corresponding to third state information from the intermediate state information is determined as a target cache line.

[0150] The intermediate state information of the target cache line is updated to fourth state information, and the data cached in the target cache line is written into the memory.

[0151] After the data in the target cache line is written into the memory, the intermediate state information of the target cache line is updated to fifth state information.

[0152] The target data of the first access request is written into the target cache line.

[0153] After the target data is written into the target cache line, the intermediate state information of the target cache line is updated to the third state information, and the address information of the target cache line is updated to the first access address.

[0154] The fourth state information is used to indicate that the target cache line is a non-idle cache line and is in a process of writing the cached data into a corresponding memory; and the fifth state information is used to indicate that the target data is being written into the target cache line after the cached data is written into the memory.

[0155] In some embodiments, the processing unit 403 is further configured to, in response to the fourth state information, lock a related access request corresponding to the first access address and a second access address, the second access address being address information of the target cache line; in response to the fifth state information, release the related access request corresponding to the second access address; and in response to the third state information, release the related access request corresponding to the first access address.

[0156] In some embodiments, the processing unit 403 is further configured to, in response to the fourth state information, lock a related access request corresponding to the first access address and a second access address, the second access address being address information of the target cache line; in response to the fifth state information, release the related access request corresponding to the second access address; and in response to the third state information, release the related access request corresponding to the first access address.

[0157] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium has stored thereon a computer program. The computer program is executed by a processor to implement the cache access method.

[0158] In one embodiment, a computer program product is provided, and the computer program product includes a computer program. The computer program is executed by a processor to implement the cache access method.

[0159] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the processes of the above-mentioned embodiment methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0160] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present application.

[0161] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A cache access method, characterized by, The cache includes a tag memory, a data memory and a processing unit, and the method comprises: The processing unit receives a first access request of the cache, and the first access request comprises a first access address; The processing unit queries tag information stored in the tag memory according to the first access address, wherein each tag information comprises address information and intermediate state information, and the intermediate state information is used to represent the state of a corresponding cache line in the data memory corresponding to the address information in the tag information; If the address information in the tag information stored in the tag memory does not match the first access address, the processing unit determines a target cache line according to the intermediate state information in the tag memory, processes the first access request, and updates the intermediate state information of the target cache line, wherein the target cache line is used to cache target data of the first access request.

2. The method of claim 1, wherein, The method further comprises: When the intermediate state information stored in the tag memory is first state information, a cache line corresponding to the first state information is determined as a target cache line; The address information in the tag information corresponding to the target cache line is updated to the first access address, and the intermediate state information is updated to second state information; The target data is written into the target cache line; After the target data is written into the target cache line, the intermediate state information is updated to third state information; The first state information is used to represent that the corresponding cache line is an idle cache line and that no access request processes the target data of the cache line; the second state is used to represent that the target data is written into the target cache line; and the third state information represents that the data cached in the target cache line is in a valid state and is not in a data writing or reading process.

3. The method of claim 2, wherein, The method further comprises: In response to the second state information, locking related access requests of the first access address, wherein the related access requests are other access requests except the first access request; In response to the third state information, releasing the related access requests of the first access address.

4. The method of claim 2, wherein, The method further comprises: When the intermediate state information stored in the tag memory does not have the first state information, a cache line corresponding to third state information of the intermediate state information is determined as a target cache line; The intermediate state information of the target cache line is updated to fourth state information, and data cached in the target cache line is written into a memory; After the data in the target cache line is written into the memory, the intermediate state information of the target cache line is updated to fifth state information; The method further comprises: When the intermediate state information stored in the tag memory does not have the first state information, a cache line corresponding to third state information of the intermediate state information is determined as a target cache line; The intermediate state information of the target cache line is updated to fourth state information, and data cached in the target cache line is written into a memory; After the data in the target cache line is written into the memory, the intermediate state information of the target cache line is updated to fifth state information; write the target data of the first access request into the target cache line; after completing the target data writing into the target cache line, update the intermediate state information of the target cache line to the third state information, and update the address information of the target cache line to the first access address; wherein the fourth state information is used to indicate that the target cache line is a non-idle cache line and the target cache line is in the process of writing the cached data into the corresponding memory; and the fifth state information is used to indicate that the target data is in the process of being written into the target cache line after the cached data is written into the memory.

5. The method of claim 4, wherein, The method further comprises: in response to the fourth state information, locking the related access requests corresponding to the first access address and the second access address, the second access address being the address information of the target cache line; in response to the fifth state information, releasing the related access request corresponding to the second access address; in response to the third state information, releasing the related access request corresponding to the first access address.

6. The method of claim 1, wherein, The intermediate state information comprises valid bit information and cache line state information; The valid bit information is used to indicate whether the cache line is in a valid state; The cache line state information is used to indicate the substate in the valid state and the substate in the invalid state of the cache line.

7. A cache, characterized by, comprise a tag memory, a data memory and a processing unit; The tag memory is used to store tag information; The data memory is used to cache target data of an access request; The processing unit is used to execute the steps of the method of any one of claims 1 to 6.

8. A chip comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to realize the steps of the method of any one of claims 1 to 6.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method of any one of claims 1 to 6. The computer program is executed by the processor to realize the steps of the method of any one of claims 1 to 6.

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