A cache method and system for superscalar processor memory access unit

Abstract

The application belongs to the field of integrated circuits and computer architecture, and provides a cache method and system for a superscalar processor memory access unit, which receives multiple memory access instructions in the same cycle, determines the corresponding Bank in the cache to be accessed by using the memory access instruction, generates a missing request when the cache access permission of the memory access instruction is obtained, merges all missing requests, uses a constant step prefetch mode and a complex step prefetch mode fusion method to perform parallel prefetch training on the merged missing requests, obtains a prefetch request and a corresponding prefetch cache address, requests a missing cache line from a level 1 cache to a level 2 cache based on a missing queue, and writes back the cache line in the corresponding data cache of the level 1 cache. The bus coherence request is stored in a sniffing queue, the data in the multi-core cache is judged to be consistent or not by using the coherence request, and the consistency is modified according to the judgment result. The application improves the cache hit rate and bandwidth utilization.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit and computer architecture technology, specifically relating to a caching method and system for superscalar processor memory access units. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] With the rise of high-load applications such as big data, cloud computing, and artificial intelligence, the performance bottleneck of processors is increasingly concentrated in the storage subsystem. Modern high-performance processors mostly adopt multi-level cache structures to alleviate the speed gap between main memory and CPU. Superscalar processors improve instruction throughput through techniques such as out-of-order execution and multiple-issue, but the design and management of their cache subsystem directly affect the overall system performance.

[0004] Traditional memory access units typically employ single-port or limited multi-port cache structures, making it difficult to support superscalar multi-channel concurrent memory access. This leads to cache access bandwidth becoming a bottleneck and insufficient cache concurrency capabilities. During multi-channel concurrent memory access, the cache bank's conflict handling and arbitration mechanisms are inadequate, easily resulting in resource waste and conflict latency, complicating bank management and arbitration. Existing hardware prefetching is mostly fixed-step or simple flow detection, with a single cache replacement strategy and simplistic prefetching and replacement mechanisms, making it difficult to adapt to diverse program behaviors, resulting in low cache hit rates and bandwidth utilization. In multi-core / multi-threaded environments, cache consistency maintenance overhead is high, write-back and cache refill management are inflexible, data consistency and write-back efficiency are low, impacting system performance. Summary of the Invention

[0005] To address the aforementioned issues, this invention proposes a caching method and system for superscalar processor memory access units. This invention mainly includes multi-channel, bank-based concurrent cache access, prefetching and replacement, hierarchical write-back, and consistency queue coordination, achieving multi-channel concurrent cache access, efficient bank-based arbitration, prefetching and dynamic replacement, cache write-back, and consistency coordination optimization, thereby improving the overall throughput and energy efficiency of the memory access unit.

[0006] According to some embodiments, the first aspect of the present invention provides a caching method for memory access units of superscalar processors, employing the following technical solution: A caching method for memory access units in a superscalar processor includes: If multiple memory access instructions are received within the same cycle, the corresponding Bank in the cache to be accessed is determined using the memory access instructions. If multiple memory access instructions access the same Bank, the access permissions of the memory access instructions are determined based on the cache line where the instruction address is located. When a memory access instruction gains cache access, if a cache line is missing, a missing request is generated and stored in the missing queue. The missing queue supports request merging at the cache line level. The merged missing requests are trained in parallel using a combination of constant step size prefetch mode and complex step size prefetch mode to obtain the prefetch requests and their corresponding prefetch cache addresses. Based on the missing queue, first check the write-back queue to see if there is a corresponding replacement cache line for the missing request. If so, wait for the write-back queue to write the missing replacement cache line back to the second-level cache. Then, based on the missing queue, request the missing cache line from the first-level cache to the second-level cache and write it back to the corresponding cache line of the data cache in the first-level cache. The system utilizes sniffing queues to store bus consistency requests, uses these requests to determine whether the data in the multi-core cache is consistent, and makes consistency modifications based on the determination results.

[0007] Furthermore, the step of using memory access instructions to determine the corresponding Bank in the cache to be accessed specifically involves: The target index determines the cache to be accessed, and the cache index is used to determine the cache line address in the address cache and its corresponding cache line in the data cache; at the same time, the Bank index is used to determine the Bank in the cache line. The memory access instructions include the target index, cache index, Bank index, and other basic fields; The cache consists of two parts: an address cache and a data cache. Both the address cache and the data cache are 8-way set-associative, with 256 rows per way and 16 banks per row. In the address cache, each cache address line stores the corresponding cache line address, which is used to determine whether the access address of the memory access instruction is hit. If it is hit, the data in the corresponding Bank in the cache data is valid. The data cache stores each cache line containing the data to be accessed.

[0008] Furthermore, when multiple memory access instructions access the same Bank, the access permissions of the memory access instructions are determined based on the cache line where the Bank is located, specifically as follows: If multiple memory access instructions access the same bank but access different cache lines, only the memory access instruction with the highest priority is allowed to access it. The other memory access instructions do not have access rights and will wait for the next cycle to make a judgment. If multiple memory access instructions access the same bank and the cache line accessed by the multiple memory access instructions is the same, then parallel access is allowed.

[0009] Furthermore, the method of using a fusion of constant step-size prefetching mode and complex step-size prefetching mode to perform parallel prefetching training on the merged missing requests, wherein the training process for each missing request includes: Determine the corresponding constant entry in the constant prefetch queue based on the address index in the missing request; The complex entries in the complex prefetch queue are determined based on the index of the complex entry in the corresponding constant entry. If the step size in the complex entry is equal to the step size of the previous missing request, the confidence level is incremented by 1; if the step size in the complex entry is not equal to the step size of the previous missing request, the confidence level is decremented by 1; if the final confidence level is 0, the step size in the constant entry is updated to the step size in the complex entry, otherwise the constant entry is not updated. After shifting the complex entry index one bit to the left, XOR it with the step size in the complex entry to obtain the corrected complex entry index, which is then returned to the constant entry for updating, thus completing one prefetch training for a missing request. After all missing request prefetch training is completed, prefetch requests to be adjudicated are generated based on all entries with a confidence greater than 1 in the updated constant prefetch queue and complex prefetch entry queue. The decision is made based on the constant prefetch queue, the complex prefetch entry queue, and the sequence number of the entries in both. The priority of the prefetch requests to be decided is obtained. Four prefetch requests to be decided are selected as prefetch requests in descending order of priority, and a prefetch queue is generated.

[0010] Furthermore, the constant prefetch queue has a lower priority than the complex prefetch queue. Both the constant prefetch queue and the complex prefetch queue have 128 entries, and the internal priority is that the smaller the entry number, the higher the priority.

[0011] When none of the cached lines are the data that the access instruction wants to access, the cached line to be replaced is written back to the write queue.

[0012] Furthermore, the step of using consistency requests to determine whether the data in the multi-core cache is consistent, and making consistency modifications based on the determination result, specifically involves: Based on consistency requests, if the data in the cache line accessed by the requester is inconsistent with the data in the cache line of the requested party, it is necessary to determine whether the inconsistent cache line of the requested party is a replaced cache line in the write-back queue or whether the cache line status is dirty. If so, the requested replaced cache line is written back to the L2 cache based on the write-back queue; otherwise, no operation is performed on the cache of the requested party.

[0013] Based on consistency requests, if the data in the cache line cached by the requester is consistent with the data in the cache line cached by the requested party, then the cache of the requested party will not be operated.

[0014] According to some embodiments, a second aspect of the present invention provides a cache system for superscalar processor memory access units, employing the following technical solution: A cache system for superscalar processor memory access units includes: The memory access processing module is configured to receive multiple memory access instructions within the same period, use the memory access instructions to determine the corresponding Bank in the cache to be accessed, and if multiple memory access instructions access the same Bank, determine the access permissions of the memory access instructions based on the cache line where the Bank is located. The prefetch training module is configured to generate a missing request and store it in the missing queue when a cache line is missing after the memory access instruction obtains cache access permission. At the same time, it merges all missing requests and performs parallel prefetch training on the merged missing requests by using a combination of constant step size prefetch mode and complex step size prefetch mode to obtain the prefetch requests and their corresponding prefetch cache addresses. The missing write-back module is configured to first check the write-back queue to see if there is a missing request corresponding to a replaced cache line. If so, it waits for the write-back queue to write the missing replaced cache line back to the second-level cache, and then requests the missing cache line from the first-level cache to the second-level cache based on the missing queue, and writes it back to the cache line of the corresponding data cache in the first-level cache. The consistency detection module is configured to use a sniffing queue to store bus consistency requests, use consistency requests to determine whether the data in the multi-core cache is consistent, and make consistency modifications based on the determination results.

[0015] According to some embodiments, a third aspect of the present invention provides a computer-readable storage medium.

[0016] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a caching method for accessing memory units of a superscalar processor as described in the first aspect above.

[0017] According to some embodiments, a fourth aspect of the present invention provides a computer device.

[0018] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of a caching method for accessing memory units of a superscalar processor as described in the first aspect above.

[0019] According to some embodiments, a fifth aspect of the present invention provides a computer program product or computer program.

[0020] This invention provides a computer program product or computer program comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of a caching method for accessing a superscalar processor memory unit as described in the first aspect above.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention utilizes multi-channel concurrent cache access by bank, prefetching and replacement, hierarchical write-back and consistency queue collaboration, and dynamic cache energy efficiency management. It is applicable to the design and implementation of various chips such as high-performance general-purpose processors, embedded processors, and AI accelerators. It achieves multi-channel concurrent cache access, efficient arbitration by bank, prefetching and dynamic replacement, cache write-back and consistency collaborative optimization, thereby improving the overall memory access unit throughput and energy efficiency.

[0022] This invention improves concurrent cache access bandwidth and increases data throughput by 20%; it also improves cache hit rate and prefetch hit rate by 15%.

[0023] This invention improves cache hit rate and bandwidth utilization through prefetching and dynamic replacement mechanisms; optimizes the write-back and miss management queues to reduce main memory access latency; and supports cache consistency to meet the scalability of multi-core systems. Attached Figure Description

[0024] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0025] Figure 1 This is a block diagram of the overall structure of a cache for a superscalar processor memory access unit according to an embodiment of the present invention; Figure 2 This is the Cache implementation architecture in this embodiment of the invention; Figure 3 This refers to the SPT / CSPT prefetch training process in this embodiment of the invention. Figure 4 This is the pipeline implementation of SPT and CSPT in the embodiments of the present invention. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0028] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0029] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0030] Terminology Explanation: Snoop Queue (SNQ) is a storage bus consistency request mechanism. To ensure data consistency across multiple core caches, the Interconnect sends requests to other cores to access or modify the same cache line. Upon receiving a request, the SNQ creates an Entry and requests L1 DCache access permissions. It then checks or modifies the CSA status bit of the corresponding cache line. If the cache line's status is Dirty, the cache line must be written back to memory, and other cores must be notified of any data modifications at that address.

[0031] The Write Back Queue (WBQ) manages cache lines written back due to the Dirty / Silence Evict. To complete one write operation, i.e., writing back from the L1 cache to the L2 cache, it takes at least 4 clock cycles. To improve write back efficiency, write back operations are completed on a cache line-by-cache basis.

[0032] The Miss Queue (MQ) is used to handle cache misses. When a cache line is missing, a read request is sent to the second-level cache, and instructions in the queue that are sleeping are woken up after the data is populated back into the cache. Special entries are set up for instructions accessing the None Cacheable address space. This queue also supports handling bus errors and other bus-related exceptions.

[0033] Example 1 like Figure 1 As shown, this embodiment provides a caching method for memory access units in superscalar processors. In this embodiment, the method includes the following steps: If multiple memory access instructions are received within the same cycle, the corresponding Bank in the cache to be accessed is determined using the memory access instructions. If multiple memory access instructions access the same Bank, the access permissions of the memory access instructions are determined based on the cache line where the Bank is located. When a memory access instruction gains cache access, if a cache line is missing, a missing request is generated and stored in the missing queue. At the same time, all missing requests are merged, and the merged missing requests are trained in parallel using a combination of constant step size prefetch mode and complex step size prefetch mode to obtain the prefetch requests and their corresponding prefetch cache addresses. Based on the missing queue, first check the write-back queue to see if there is a corresponding replacement cache line for the missing request. If so, wait for the write-back queue to write the missing replacement cache line back to the second-level cache. Then, based on the missing queue, request the missing cache line from the first-level cache to the second-level cache and write it back to the corresponding cache line of the data cache in the first-level cache. The system utilizes sniffing queues to store bus consistency requests, uses these requests to determine whether the data in the multi-core cache is consistent, and makes consistency modifications based on the determination results.

[0034] When none of the cached lines are the data that the access instruction wants to access, the cached line to be replaced is written back to the write queue.

[0035] The process of using memory access instructions to determine the corresponding Bank in the cache to be accessed is as follows: The target index determines the cache to be accessed, and the cache index is used to determine the cache line address in the address cache and its corresponding cache line in the data cache; at the same time, the Bank index is used to determine the Bank in the cache line. The memory access instructions include the target index, cache index, Bank index, and other basic fields; The cache consists of two parts: an address cache and a data cache. Both the address cache and the data cache are 8-way set-associative, with 256 rows per way and 16 banks per row. In the address cache, each cache address line stores the corresponding cache line address, which is used to determine whether the access address of the memory access instruction is hit. If it is hit, the data in the corresponding Bank in the cache data is valid. In the data cache, each cache line stores the data to be accessed.

[0036] like Figure 2As shown, the multi-channel, bank-based concurrent cache access structure employs a set-associative, bank-based structure, supporting multiple memory access instructions entering the access phase concurrently per cycle. The cache arbiter detects instruction address conflicts, allocates cache address space, and enhances multi-channel concurrency capabilities. During cache access, if multiple instructions in the same cycle access the same bank, the arbiter assigns access permissions based on instruction address overlap and age vectors, preventing bank conflicts that could lead to errors.

[0037] The data cache consists of 16 banks (32 bits) per cache line (512 bits). Each bank has an independent read port and write port. Banks are composed of RAM and cannot perform simultaneous read and write operations. During a read operation, eight channels share a single read enable signal (Ren) and read address signal (Raddr). Each channel outputs 32 bits of data, for a total of 256 bits (32 × 8 bits) read. During a write operation, only the write enable signal (Wen) of one channel is pulled high, and 32 bits of data are written to the corresponding bank.

[0038] During read operations, the Tag Cache (address cache) reads eight ways simultaneously and outputs eight tag values. During write operations, it writes only one tag value to each way. The Tag Cache is used to determine if an address is hit; if so, the data in the Data Cache is valid.

[0039] Cache state management is implemented using 8 × 256 status registers. Each cache line has a corresponding status register, which is 2 bits wide and used to record the status information in the MESI protocol. Since the current design supports three states: Invalid, Exclusive, and Modified, each status register needs to encode these three states.

[0040] When multiple memory access instructions access the same Bank, the access permissions of the memory access instructions are determined based on the cache line where the Bank is located, specifically as follows: If multiple memory access instructions access the same bank but access different cache lines, only the memory access instruction with the highest priority is allowed to access it. The other memory access instructions do not have access rights and will wait for the next cycle to make a judgment. If multiple memory access instructions access the same bank and the cache line accessed by the multiple memory access instructions is the same, then parallel access is allowed.

[0041] Specifically, the cache arbitrator allocates instructions to the corresponding bank based on the bank index of the target address. If multiple instructions access the same bank in the same cycle, the arbitration status of the bank arbitrator is shown in Table 1. The bank conflict detection logic ensures that different banks can be accessed in parallel, and conflicts within the same bank can be efficiently arbitrated, thereby improving the overall cache access bandwidth.

[0042] Table 1. Arbitration Status of Bank Arbitrator

[0043] like Figure 3 As shown, the method of using a fusion of constant step size prefetch mode and complex step size prefetch mode to perform parallel prefetch training on merged missing requests includes the following training process for each missing request: Determine the corresponding constant entry in the constant prefetch queue based on the address index in the missing request; The complex entries in the complex prefetch queue are determined based on the index of the complex entry in the corresponding constant entry. If the step size in the complex entry is equal to the step size of the previous missing request, the confidence level is incremented by 1; if the step size in the complex entry is not equal to the step size of the previous missing request, the confidence level is decremented by 1; if the final confidence level is 0, the step size in the constant entry is updated to the step size in the complex entry, otherwise the constant entry is not updated. After shifting the complex entry index one bit to the left, XOR it with the step size in the complex entry to obtain the corrected complex entry index, which is then returned to the constant entry for updating, thus completing one prefetch training for a missing request. After all missing request prefetch training is completed, prefetch requests to be adjudicated are generated based on all entries with a confidence greater than 1 in the updated constant prefetch queue and complex prefetch entry queue. The decision is made based on the constant prefetch queue, the complex prefetch entry queue, and the sequence number of the entries in both. The priority of the prefetch requests to be decided is obtained. Four prefetch requests to be decided are selected as prefetch requests in descending order of priority, and a prefetch queue is generated.

[0044] The constant prefetch queue has a lower priority than the complex prefetch queue. Both the constant prefetch queue and the complex prefetch queue have 128 entries. The internal priority is that the smaller the entry number, the higher the priority.

[0045] When a missing instruction occurs during cache access, the Miss Queue (MQ) records the missing cache line. This missing request is simultaneously sent to the prefetch module for training, aiming to predict potentially accessed addresses in the future. The prefetch module employs the IPCP (Instruction PC Prediction) algorithm, targeting the following two common address access patterns: Sequential access mode: When traversing an array or looping, the memory address shows a continuous increasing pattern.

[0046] Step-by-step access mode: In matrix operations or block computations, memory addresses increment or decrement by a fixed step size.

[0047] Two prefetching modes, SPT and CSPT, are proposed. Stride Prediction Table (SPT): For memory access patterns with a fixed step size, it predicts the next likely memory address to be accessed by recording and learning the step size information of instructions. Complex Stride Prediction Table (CSPT): For memory access behavior with complex step patterns, it uses more complex prediction logic and data structures to record multi-step or nonlinear patterns, thereby improving prediction accuracy.

[0048] In constant step prefetch mode, the number of SPT entries is 128. The entries are indexed by PC[14:6] and the corresponding Addr[13:6] is recorded for PC to calculate the step size. Stride represents the step size and is used to determine whether the step size is constant. Confidence represents the confidence of the current Stride (2 bits). When Confidence is greater than 1, prefetching is triggered, and 3 cache lines are prefetched.

[0049] The complex stride prefetching mode is based on the SPT table entries, with an additional set of training CSPT entries. The CSPT stores stide and confidence information. The CSPT is looked up using the SPT's signature as an index. If the stride is equal, confidence is incremented; if the stride is unequal, confidence is decremented; if confidence is 0, it is updated to the new stride. This new stride is then XORed with the signature << 1 to obtain the new signature, which is then used to update the SPT.

[0050] Figure 2The prefetch training process for instruction addresses first indexes the SPT table entries using instruction PC[14:6]. After calculating the Stride, it determines whether prefetching needs to be triggered based on the confidence level, and simultaneously updates the information of the corresponding table entries. The Signature is used as an index to update the information of the CSPT table entries. If a Miss occurs, the information of the CSPT table entries will be updated.

[0051] Figure 4 The pipeline implementations of SPT and CSPT are demonstrated. A three-stage pipeline structure is used for prefetch training.

[0052] 1. Prefetch0 phase: Receive and merge missing cache requests.

[0053] Once an access request gains cache access, if a cache line is missing, the PF module (prefetch module) collects the missing requests (up to 4) and merges them to prevent the same instruction from being repeatedly triggered by the PC, which could lead to errors in confidence training.

[0054] 2. Prefetch1 stage: Training entries based on requests.

[0055] The merged requests will be used to train entries in the prediction queue. During training, entries in both the SPT and CSPT are updated simultaneously. After training, entries with a confidence level greater than 1 are selected to trigger prefetch requests. Therefore, both constant-step-size and complex-step-size prediction tables may trigger prefetch requests simultaneously, and these requests will be sent to the next-level adjudication module. The confidence level design effectively reduces interference from invalid instructions, providing tolerance for prefetching the address corresponding to the instruction's PC.

[0056] 3. Prefetch2 phase: adjudicate prefetch requests and generate prefetch addresses.

[0057] Since both CSPT and SPT generate prefetch requests, the hardware design specifies that CSPT requests have a higher priority than SPT requests. Requests are sorted according to their entry number priority, with requests having smaller entry numbers (Entry 0-127, priority decreasing from high to low) being satisfied first. The winning prefetch request is placed into the prefetch queue. The prefetch queue has a depth of 16 entries and stores the cache address information for prefetching. The prefetch queue has 16 entries in total. Both SPT and CSPT can trigger prefetch requests, receiving 4 requests per cycle, and selecting 4 after adjudication. The priority is determined as follows: SPT / CSPT each have 128 entries, with internal priorities from 0-127, from high to low (0 being the highest priority and 127 the lowest). Between CSPT and SPT requests, CSPT requests have a higher priority.

[0058] Prefetch address requests enter the Cache Arbiter (arbitration) through the Load channel. When entering the Cache Arbiter, the request has the lowest priority to minimize impact on normal instruction execution. When a cache line is missing, the MQ initiates a prefetch request to the L2 Cache. The prefetched cache line is marked with an additional flag. If a full backpressure decision occurs in the MQ, prefetch requests are stopped, and the training results for this prefetch are discarded.

[0059] Prefetch and cache replacement mechanism: The cache prefetch algorithm based on instruction pointer classification (IPCP) is adopted, which combines two address prefetch modes: constant step size (Stride Predicate Table, SPT) and complex step size (Complex Stride Prediction Table, CSPT). The prefetch length, step size, and confidence are all adjusted according to the address access situation to improve the prefetch hit rate and bandwidth utilization.

[0060] Cache write-back works in conjunction with MQ. The WBQ (Write-back Queue) stores dirty data replaced from the L1 cache, using a FIFO queue. When writing back to the L2 cache, it arbitrates bus bandwidth with MQ. The MQ (Cache Miss Queue) stores cache miss requests and supports collaboration with WBQ and SNQ. Data refill priority can be dynamically adjusted. Cache write-back and refill are performed on a cache line basis, merging multiple writes to the same cache line to reduce bus pressure. The cache uses the Least Recently Used (LRU) replacement algorithm. A linked list records the time order of data access, evicting the least recently accessed data.

[0061] When performing cache line replacement, a set-associative cache first indexes the cache set based on the physical address, and then selects the replacement path from the multiple paths in the cache set according to the replacement algorithm. The hardware uses an 8x8 priority matrix to record the access priority of each way. When a way is accessed, the row corresponding to that way is set to all 1s (indicating that the way has the highest priority), and the column corresponding to that way is set to all 0s (indicating that other ways have lower priorities). During replacement, the way corresponding to all rows in the matrix with values ​​of 0 (i.e., the way with the lowest priority in that row) is selected for replacement.

[0062] When none of the cached lines are the data that the access instruction wants to access, the cached line to be replaced is written back to the write queue.

[0063] A tiered write-back and backfill queue supports write-back and backfill at the cache line level, merging multiple write operations to reduce cache adjudication pressure. During the backfill process, cache replacement occurs when the cache is 8-way full. The cache replacement strategy uses an LRU priority matrix and supports address priority adjustment.

[0064] The process of using consistency requests to determine whether the data in the multi-core cache is consistent, and then making consistency modifications based on the determination result, specifically involves: Based on consistency requests, if the data in the cache line of the requester's cache is inconsistent with the data in the cache line of the requested cache, it is determined whether the inconsistent cache line in the requested cache is the replacement cache line in the write-back queue. If it is, the requested replacement cache line is written back to the requested cache based on the write-back queue; otherwise, the requested cache does not perform any operation.

[0065] Based on consistency requests, if the data in the cache line cached by the requester is consistent with the data in the cache line cached by the requested party, then the cache of the requested party will not be operated.

[0066] Example 4: Cache consistency management. An SNQ queue is designed to store consistency requests. The receiving interface supports the ACE protocol, monitors bus consistency requests, periodically updates cache line status, and triggers invalidation and data write-back when necessary. According to the protocol, the following cache line status transitions occur.

[0067] ReadClean: Reads clean data, ensuring the requester's cache line is consistent with main memory. If the target cache line is dirty, it needs to be written back to main memory or the data should be provided directly. The target cache line may become Shared. Cache line state changes from Modified to Shared or remains unchanged. ReadNotSharedDirty: Reads data, ensuring the target cache line is not shared dirty data. If the target cache line is dirty, provides the data and updates it to Shared. Cache line state changes from Modified to Shared. ReadShared: Reads shared data, allowing multiple caches to share it. Data is read from main memory or other caches, and the target cache line state is updated to Shared. Cache line state changes from Exclusive to Shared or remains unchanged. ReadUnique: Reads data, ensuring the requested cache line is unique. If the target cache line is dirty, it needs to be written back to main memory or the data is provided directly, rendering the target cache line invalid. Cache line state changes from Modified / Shared to Invalid.

[0068] Cache consistency coordination mechanism. The cache uses a Snoop Queue (SNQ) to store multi-core / multi-threaded consistency requests, supporting the ACE protocol and cache line state management. It maintains the cache line state changes according to different consistency requests in a multi-core / multi-threaded environment.

[0069] Example 2 This embodiment provides a cache system for superscalar processor memory access units, including: The memory access processing module is configured to receive multiple memory access instructions within the same period, use the memory access instructions to determine the corresponding Bank in the cache to be accessed, and if multiple memory access instructions access the same Bank, determine the access permissions of the memory access instructions based on the cache line where the Bank is located. The prefetch training module is configured to generate a missing request and store it in the missing queue when a cache line is missing after the memory access instruction obtains cache access permission. At the same time, it merges all missing requests and performs parallel prefetch training on the merged missing requests by using a combination of constant step size prefetch mode and complex step size prefetch mode to obtain the prefetch requests and their corresponding prefetch cache addresses. The missing write-back module is configured to first check the write-back queue to see if there is a missing request corresponding to a replaced cache line. If so, it waits for the write-back queue to write the missing replaced cache line back to the second-level cache, and then requests the missing cache line from the first-level cache to the second-level cache based on the missing queue, and writes it back to the cache line of the corresponding data cache in the first-level cache. The consistency detection module is configured to use a sniffing queue to store bus consistency requests, use consistency requests to determine whether the data in the multi-core cache is consistent, and make consistency modifications based on the determination results.

[0070] The examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in Embodiment 1 above. It should be noted that the above modules, as part of the system, can be executed in a computer system such as a set of computer-executable instructions.

[0071] The descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0072] The proposed system can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and the division of modules described above is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed.

[0073] Example 3 This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in a caching method for accessing memory units of a superscalar processor as described in Embodiment 1 above.

[0074] Example 4 This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the caching method for superscalar processor memory access units as described in Embodiment 1 above.

[0075] Example 5 This embodiment provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in the caching method for a superscalar processor memory access unit described in Embodiment 1 above.

[0076] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0077] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0078] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0079] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0080] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0081] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A caching method for memory access units in superscalar processors, characterized in that, include: If multiple memory access instructions are received within the same cycle, the corresponding Bank in the cache to be accessed is determined using the memory access instructions. If multiple memory access instructions access the same Bank, the access permissions of the memory access instructions are determined based on the cache line where the Bank is located. When a memory access instruction gains cache access, if a cache line is missing, a missing request is generated and stored in the missing queue. Simultaneously, all missing requests are merged, and the merged missing requests are trained in parallel using a fusion of constant-step and complex-step prefetch modes to obtain the prefetch requests and their corresponding prefetch cache addresses. The training process for each missing request includes: Determine the corresponding constant entry in the constant prefetch queue based on the address index in the missing request; The complex entries in the complex prefetch queue are determined based on the index of the complex entry in the corresponding constant entry. If the step size in the complex entry is equal to the step size of the previous missing request, the confidence level is incremented by 1; if the step size in the complex entry is not equal to the step size of the previous missing request, the confidence level is decremented by 1; if the final confidence level is 0, the step size in the constant entry is updated to the step size in the complex entry, otherwise the constant entry is not updated. After shifting the complex entry index one bit to the left, XOR it with the step size in the complex entry to obtain the corrected complex entry index, which is then returned to the constant entry for updating, thus completing one prefetch training for a missing request. After all missing request prefetch training is completed, prefetch requests to be adjudicated are generated based on all entries with a confidence greater than 1 in the updated constant prefetch queue and complex prefetch entry queue. The priority of the prefetch requests to be decided is determined by the constant prefetch queue, the complex prefetch entry queue, and the sequence number of the entries in both. Four prefetch requests to be decided are selected as prefetch requests in descending order of priority, and a prefetch queue is generated. Based on the missing queue, first check the write-back queue to see if there is a corresponding replacement cache line for the missing request. If so, wait for the write-back queue to write the missing replacement cache line back to the second-level cache. Then, based on the missing queue, request the missing cache line from the first-level cache to the second-level cache and write it back to the corresponding cache line of the data cache in the first-level cache. The system utilizes sniffing queues to store bus consistency requests, uses these requests to determine whether the data in the multi-core cache is consistent, and makes consistency modifications based on the determination results.

2. The caching method for superscalar processor memory access units as described in claim 1, characterized in that, The process of using memory access instructions to determine the corresponding Bank in the cache to be accessed is as follows: The target index determines the cache to be accessed, and the cache index is used to determine the cache line address in the address cache and its corresponding cache line in the data cache; at the same time, the Bank index is used to determine the Bank in the cache line. The memory access instructions include the target index, cache index, Bank index, and other basic fields; The cache consists of two parts: an address cache and a data cache. Both the address cache and the data cache are 8-way set-associative, with 256 rows per way and 16 banks per row. In the address cache, each cache address line stores the cache line address, which is used to determine whether the access address of the memory access instruction is hit. If it is hit, the data in the corresponding Bank in the cache data is valid. Each cache line in the data cache stores the data to be accessed.

3. A caching method for superscalar processor memory access units as described in claim 1, characterized in that, When multiple memory access instructions access the same Bank, the access permissions of the memory access instructions are determined based on the cache line where the Bank is located, specifically as follows: If multiple memory access instructions access the same bank but access different cache lines, only the memory access instruction with the highest priority is allowed to access it. The other memory access instructions do not have access rights and will wait for the next cycle to make a judgment. If multiple memory access instructions access the same bank and the cache line accessed by the multiple memory access instructions is the same, then parallel access is allowed.

4. A caching method for superscalar processor memory access units as described in claim 1, characterized in that, The constant prefetch queue has a lower priority than the complex prefetch queue. Both the constant prefetch queue and the complex prefetch queue have 128 entries. The internal priority is that the smaller the entry number, the higher the priority.

5. A caching method for superscalar processor memory access units as described in claim 1, characterized in that, The process of using consistency requests to determine whether the data in the multi-core cache is consistent, and then making consistency modifications based on the determination result, specifically involves: Based on consistency requests, if the data in the cache line of the requester's cache is inconsistent with the data in the cache line of the requested cache, it is determined whether the inconsistent cache line in the requested cache is the replacement cache line in the write-back queue. If it is, the requested replacement cache line is written back to the requested cache based on the write-back queue. If not, the requested cache does not perform any operation. Based on consistency requests, if the data in the cache line cached by the requester is consistent with the data in the cache line cached by the requested party, then the cache of the requested party will not be operated.

6. A cache system for superscalar processor memory access units, characterized in that, include: The memory access processing module is configured to receive multiple memory access instructions within the same period, use the memory access instructions to determine the corresponding Bank in the cache to be accessed, and if multiple memory access instructions access the same Bank, determine the access permissions of the memory access instructions based on the cache line where the Bank is located. The prefetch training module is configured to generate a missing request and store it in a missing queue when a cache line is missing after a memory access instruction gains cache access permission. Simultaneously, it merges all missing requests and performs parallel prefetch training on the merged missing requests using a fusion of constant-step and complex-step prefetch modes to obtain the prefetch requests and their corresponding prefetch cache addresses. The training process for each missing request includes: Determine the corresponding constant entry in the constant prefetch queue based on the address index in the missing request; The complex entries in the complex prefetch queue are determined based on the index of the complex entry in the corresponding constant entry. If the step size in the complex entry is equal to the step size of the previous missing request, the confidence level is incremented by 1; if the step size in the complex entry is not equal to the step size of the previous missing request, the confidence level is decremented by 1; if the final confidence level is 0, the step size in the constant entry is updated to the step size in the complex entry, otherwise the constant entry is not updated. After shifting the complex entry index one bit to the left, XOR it with the step size in the complex entry to obtain the corrected complex entry index, which is then returned to the constant entry for updating, thus completing one prefetch training for a missing request. After all missing request prefetch training is completed, prefetch requests to be adjudicated are generated based on all entries with a confidence greater than 1 in the updated constant prefetch queue and complex prefetch entry queue. The priority of the prefetch requests to be decided is determined by the constant prefetch queue, the complex prefetch entry queue, and the sequence number of the entries in both. Four prefetch requests to be decided are selected as prefetch requests in descending order of priority, and a prefetch queue is generated. The missing write-back module is configured to first check the write-back queue to see if there is a missing request corresponding to a replaced cache line. If so, it waits for the write-back queue to write the missing replaced cache line back to the second-level cache, and then requests the missing cache line from the first-level cache to the second-level cache based on the missing queue, and writes it back to the cache line of the corresponding data cache in the first-level cache. The consistency detection module is configured to use a sniffing queue to store bus consistency requests, use consistency requests to determine whether the data in the multi-core cache is consistent, and make consistency modifications based on the determination results.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in a caching method for accessing memory units of a superscalar processor as described in any one of claims 1-5.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the caching method for superscalar processor memory access units as described in any one of claims 1-5.

9. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of a caching method for accessing memory units of a superscalar processor as described in any one of claims 1-5.

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