Cache access control method, chip and equipment

Abstract

The embodiment of the invention provides a cache access control method, a chip and equipment, and relates to the technical field of artificial intelligence chips, and the method comprises the following steps: statically dividing a first cache region and a second cache region which are physically isolated from a cache through a hardware mechanism; for the data request with the priority higher than the preset level sent by the processing core, hit check is carried out in the first cache region, and a cache line in the first cache region is allocated for the data request according to an obtained first check result; and for the data request of which the priority is not greater than the preset level, hit check is performed in the second cache region, and the cache line in the second cache region is allocated to the data request according to the obtained second check result, so that the data (namely key data) of which the priority is greater than the preset level has exclusive and protected cache resources, and the cache efficiency is improved. The key data is effectively prevented from being expelled out of the cache by the non-key data, and the low access delay of the key data is ensured, so that the overall performance of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chip technology, and in particular to a cache access control method, chip, and device. Background Technology

[0002] Artificial intelligence chip architectures (such as general-purpose graphics processing units (GPGPUs)) typically contain multi-level cache hierarchies, among which the L2 cache, as the shared last-level data cache, is crucial to the overall computing performance of the artificial intelligence chip.

[0003] Under relevant technologies, L2 cache management strategies typically employ a unified cache space and replacement strategy, such as Least Recently Used (LRU), Least Frequently Used (LFU), or their variations. Taking LFU as an example, when the cache receives a data request, if the cache is full, the least frequently used cache line is evicted to main memory.

[0004] In this way, critical data that is sensitive to system performance or specific task latency (such as synchronization data between kernel functions, intermediate results of high-frequency access, etc.) may be evicted from the cache by non-critical data, resulting in higher access latency for critical data and thus affecting the overall performance of the chip. Summary of the Invention

[0005] This application provides a cache access control method, device, and storage medium to reduce the access latency of critical data in the cache, thereby improving the overall performance of the chip.

[0006] On one hand, embodiments of this application provide a cache access control method applied to a cache, wherein the cache includes a first cache region and a second cache region; the method includes: Receive and process data requests sent by the core. When the priority of the data request is greater than the preset level, a hit check is performed in the first cache area to obtain a first check result, and a cache line in the first cache area is allocated to the data request based on the first check result; When the priority of the data request is not greater than the preset level, a hit check is performed in the second cache area to obtain a second check result, and a cache line in the second cache area is allocated to the data request based on the second check result.

[0007] On one hand, embodiments of this application provide a cache access control device applied to a cache, the cache including a first cache region and a second cache region; the device includes: The receiving module is used to receive data requests sent by the processing core. The checking module is used to perform a hit check in the first cache area to obtain a first check result when the priority of the data request is greater than a preset level, and to allocate a cache line in the first cache area to the data request based on the first check result; The checking module is further configured to perform a hit check in the second cache area to obtain a second check result when the priority of the data request is not greater than a preset level, and allocate a cache line in the second cache area to the data request based on the second check result.

[0008] Optionally, the inspection module is further configured to: Obtain the request address carried in the data request; When the requested address is within a preset physical address range, the priority of the data request is determined to be greater than a preset level; When the requested address is not within the preset physical address range, the priority of the data request is determined to be no greater than the preset level.

[0009] Optionally, the inspection module is specifically used for: If the first check result indicates a cache miss, and the first cache region includes free cache lines, then the free cache lines are allocated for the data request; If the first check result indicates a cache miss, and there are no free cache lines in the first cache area, then a cache line is selected from the first cache area as a replacement line according to a preset replacement strategy. The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

[0010] Optionally, the inspection module is specifically used for: If the first cache area contains at least one cache line with a priority no greater than a preset level, then the replacement line is selected from the at least one cache line according to the replacement strategy.

[0011] Optionally, the inspection module is further configured to: If the first check result indicates a cache hit, then the cache line that was hit in the first cache region is allocated to the data request.

[0012] Optionally, the inspection module is specifically used for: If the second check result indicates a cache miss, and the second cache region includes free cache lines, then the free cache lines are allocated for the data request; If the second check result indicates a cache miss, and the second cache region has no free cache lines, then the first cache region is determined to be in a free state. If the idle state of the first cache area is not globally idle, then a cache line is selected from the second cache area as the replacement line according to the preset replacement strategy; The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

[0013] Optionally, the inspection module is further configured to: If the idle state of the first cache region is globally idle, then a cache line in the first cache region is allocated for the data request.

[0014] Optionally, the inspection module is further configured to: If the second check result indicates a cache hit, then the cache line that was hit in the second cache region is allocated to the data request.

[0015] On one hand, embodiments of this application provide a computer device, including a memory, an artificial intelligence chip, and a computer program stored on the memory and running on the artificial intelligence chip, wherein the artificial intelligence chip implements the steps of the above-described cache access control method when executing the computer program.

[0016] On one hand, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the cache access control method described above.

[0017] On one hand, embodiments of this application provide a computer program product, the computer program product including a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the above-described cache access control method.

[0018] In this embodiment, a dedicated, physically isolated first and second cache regions are statically partitioned from the cache using a hardware mechanism. The first cache region corresponds to a priority higher than a preset level, while the second cache region corresponds to a priority lower than the preset level. When a data request is received from the processing core, for data requests with a priority higher than the preset level, a hit check is performed in the first cache region, and a cache line is allocated in the first cache region according to the obtained first check result. For data requests with a priority lower than the preset level, a hit check is performed in the second cache region, and a cache line is allocated in the second cache region according to the obtained second check result. This ensures that data with a priority higher than the preset level (i.e., critical data) has exclusive, protected cache resources, effectively preventing critical data from being evicted from the cache by non-critical data, ensuring low access latency for critical data, and thus improving the overall performance of the chip. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of this application; Figure 2 A flowchart illustrating a cache access control method provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a cache access control device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0022] refer to Figure 1This is a structural diagram of an artificial intelligence chip applicable to an embodiment of this application. The artificial intelligence chip 100 includes at least: a processing core 101, a cache 102, and main memory 103. The processing core 101 possesses artificial intelligence-related computational capabilities, such as matrix multiplication and convolution operations, which are common computational operations in artificial intelligence models. In practical applications, the processing core 101 can be a computing unit (CU); the number of processing cores 101 can be one or more, and this application does not specifically limit the number of processing cores.

[0023] Cache 102 is a small, fast storage area located between processing core 101 and main memory 103. It is used to temporarily store data or instructions that processing core 101 or other hardware devices may frequently access in the near future, with the aim of speeding up access and reducing access latency.

[0024] Cache 102 can be an L1 cache, a shared L2 cache, etc.; the cache access control method in this application is applicable to L1 cache or L2 cache, and can also be applied to other types of cache.

[0025] The internal structure of cache 102 can be set-associative. Cache 102 includes multiple ways, each corresponding to at least one cache line. A cache line is the smallest unit of data stored in cache 102, and the size of a cache line may vary under different hardware architectures; for example, 32 bytes, 64 bytes, 128 bytes, etc.

[0026] The cache line is also the smallest unit of operation in cache 102; when reading data (such as an integer or floating-point number) from cache 102, not only this one piece of data is read, but the entire cache line containing that data (e.g., 64 bytes) is read together.

[0027] Main memory 103 is the next level below cache 102. Main memory 103 is the main memory device directly accessed by processing core 101. Compared to cache 102, main memory 103 generally has a larger capacity but is slower. When processing core 101 accesses data, if the data is not in cache 102 (i.e., cache miss), it loads the data from main memory 103 into cache 102 (usually loaded line by line), and subsequent accesses can directly read from cache 102.

[0028] In this embodiment, during the startup phase, a dedicated, physically isolated first cache region and second cache region are statically partitioned from cache 102 using a hardware mechanism. The first cache region includes at least one physically contiguous or non-contiguous cache line; similarly, the second cache region includes at least one physically contiguous or non-contiguous cache line. In some embodiments, cache 102 may include other cache regions in addition to the first and second cache regions.

[0029] The first cache region and the second cache region have different priorities; for example, the first cache region can be a high-priority cache region (HPCR) and the second cache region can be a normal cache region (NCR).

[0030] In this embodiment of the application, after statically dividing the first cache region and the second cache region, the configuration of the first cache region and the second cache region includes the following operations: During the power-on initialization phase of the AI ​​chip 100, configuration is performed by the firmware (Option ROM). The firmware configures the following parameters for the first and second cache regions through memory-mapped I / O (MMIO) registers: The enabled / disabled status of the first cache region; The way mask for the first cache region is a bitmap where each bit corresponds to a path in the cache. A "1" indicates that the path is assigned to the first cache region, and a "0" indicates that the path belongs to the second cache region. For example, for a 16-way set-associative L2 cache, the way mask "0x00FF" means that the lower 8 paths (Way0-7) are configured as the first cache region, and the higher 8 paths (Way8-15) are configured as the second cache region.

[0031] After configuration, the configuration registers (especially the path selection mask registers) of the first and second cache regions will be locked by hardware mechanisms; for example, a state machine will control the write enable signal, and writing will be prohibited once the system exits the initialization state. Throughout the entire kernel and application runtime, no software (including the operating system kernel and chip drivers) can modify the physical partitioning of the first and second cache regions.

[0032] By statically isolating physical cache paths during the firmware phase, a separate, protected pool of hardware resources (i.e., the first cache region) is provided for high-priority requests. This physical isolation has zero runtime overhead and is unaffected by subsequent software scheduling, thus providing hardware-level, predictable hard guarantees for access latency and cache hit rates of critical data.

[0033] The physical partitioning of the first and second cache regions is completed and locked at system startup, requiring no software intervention for cache partition configuration during runtime. This completely eliminates the software overhead (such as system calls and driver scheduling delays) caused by dynamic partitioning schemes, and avoids the risk of caching strategies being tampered with due to software errors or malicious attacks, thus improving system security and stability.

[0034] After configuration, the operating system and AI chip driver are loaded. The application of AI chip 100 runs and calls the preset Application Programming Interface (API) to declare one or more physical address ranges (e.g., memory areas used for synchronization) as high priority. The AI ​​chip 100 driver processes this API call in processing core 101, generates a descriptor containing the physical address range, and writes the descriptor to the address range comparator register of the cache controller in cache 102 via the MMIO register.

[0035] In this embodiment, high-priority physical address ranges can be flexibly assigned. This logical strategy is decoupled from the physical resource allocation described above. Thus, while providing strong physical isolation, the runtime API and kernel descriptor mechanism endow the software with great flexibility. Developers can dynamically and precisely define which data is critical (corresponding to high priority) without modifying hardware or restarting the system, facilitating application optimization and software adaptation.

[0036] In addition, the method of this application is mainly implemented in the cache controller hardware, and the changes to the architecture of existing artificial intelligence chips are relatively small, mainly focusing on control logic and a small number of register additions and subtractions, which makes it easy to integrate into modern artificial intelligence chip designs.

[0037] In addition to the structure described above, the artificial intelligence chip 100 in this application may also include other structures, and this application does not specifically limit such structures.

[0038] Artificial intelligence chips 100 can be: Graphics Processing Unit (GPU), General-Purpose Graphics Processing Units (GPGPU), Domain Specific Architecture (DSA), etc.

[0039] The following is based on Figure 1 The diagram shown illustrates the architecture of an AI chip and details the flow of a cache access control method. (See also...) Figure 2 This method is executed by a cache, which includes: a first cache region, a second cache region, and a cache controller. The method includes the following steps: Step 201: Receive the data request sent by the processing core.

[0040] Data requests can be either write requests or read requests.

[0041] In some embodiments, the request address carried by the data request is obtained; when the request address is within a preset physical address range, the priority of the data request is determined to be greater than a preset level; when the request address is not within the preset physical address range, the priority of the data request is determined to be no greater than a preset level.

[0042] In practice, after statically configuring the first and second cache regions, the AI ​​chip calls a preset API to declare one or more physical address ranges, whose priorities are higher than preset levels. Then, descriptors containing these physical address ranges are generated and written to the address range comparator register of the cache controller via MMIO.

[0043] The cache controller extracts the request address carried in the data request, and then compares the request address with each physical address range in the address range comparator register.

[0044] If the requested address falls within any of the physical address ranges, the data request is determined to have a higher priority than the preset level, meaning the data request is a high-priority request.

[0045] If the requested address is not within any of the physical address ranges, the priority of the data request is determined to be no greater than the preset level, that is, the data request is a normal priority request.

[0046] Step 202: When the priority of a data request is greater than the preset level, a hit check is performed in the first cache area to obtain the first check result, and a cache line in the first cache area is allocated to the data request based on the first check result.

[0047] Specifically, when a data request has a priority higher than a preset level, it indicates that the data request is a high-priority request. Therefore, the cache controller performs a hit check on the data request in the first cache area. In practical applications, the tag carried by the data request is compared one by one with the tag information of each cache line in the first cache area to obtain the first check result.

[0048] In some embodiments, if the tag carried by the data request hits the tag information of any cache line, that is, there exists a cache line whose tag information contains the tag carried by the data request and the cache line is valid, then the first check result is a cache hit. Therefore, the cache line that hits in the first cache area is allocated to the data request, and the data request is processed through the cache line.

[0049] Specifically, when the data request is a write request, the data carried by the write request is written to the cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, data is read from the cache line, and the read data is returned to the processing core.

[0050] In some embodiments, if the tag carried by the data request does not match the tag information of any cache line, that is, if the tag information of no cache line contains the tag carried by the data request, then a cache miss is indicated. In this case, it is checked whether the first cache area contains a free cache line; If a free cache line is included, the first check result is: cache miss, and the first cache region includes a free cache line; accordingly, a free cache line is allocated for the data request, and the priority of the allocated cache line is configured to the priority of the data request (i.e., high priority), and the data request is processed through the cache line.

[0051] Specifically, when the data request is a write request, the data carried by the write request is written to the allocated cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from main memory into the cache line, then the data is read from the cache line, and the read data is returned to the processing core.

[0052] In some embodiments, if a cache miss occurs and the first cache region does not contain any free cache lines, the first check result is: cache miss occurs and the first cache region does not contain any free cache lines. In this case, a cache line is selected from the first cache region as a replacement line according to a preset replacement strategy; then the data in the replacement line is evicted to main memory, and the replacement line is allocated to the data request. At the same time, the priority of the replacement line is configured to the priority of the data request.

[0053] In practice, the replacement strategy can be: selecting the cache line with the longest interval since the last access as the replacement line; the replacement strategy can also be LRU strategy, LFU strategy, etc., and this application does not make specific limitations on this.

[0054] After evicting the data from the replacement line to main memory, the replacement line is allocated to the data request and processed through it. Specifically, when the data request is a write request, the data carried by the write request is written to the replacement line, and a write completion message is returned to the processing core after the write is complete. When the data request is a read request, the data to be read is loaded from main memory into the replacement line, then the data is read from the replacement line, and the read data is returned to the processing core.

[0055] In some embodiments, if the first cache area contains at least one cache line with a priority no greater than a preset level, a replacement line is selected from the at least one cache line according to the replacement strategy.

[0056] Specifically, in addition to cache lines with a priority higher than the preset level (i.e., high priority), the first cache area may also contain cache lines with a priority no higher than the preset level (i.e., normal priority). Among them, the cache lines with normal priority may be cache lines that were previously assigned to normal priority requests; or they may be cache lines that were previously assigned to high priority requests and then had their priority reset (e.g., adjusted from high priority to normal priority).

[0057] When the first check result is: cache miss, and there is no free cache line in the first cache area, first check whether the first cache area contains a cache line with a priority no higher than the preset level.

[0058] If the cache line is included, a cache line is selected as the replacement line from these cache lines (i.e., cache lines with normal priority) according to the replacement policy; if the cache line is not included, a cache line is selected as the replacement line from the cache lines with a priority greater than the preset level (i.e., cache lines with high priority) according to the replacement policy.

[0059] In this embodiment, when there are cache lines with normal priority in the first cache area, these cache lines will gradually "cool down" over time or when new data requests (high priority or normal priority) occur. In this way, when a new high priority request is received and cache line replacement is required, these cache lines with normal priority will be selected first as replacement lines, so as to achieve intelligent and low-impact cache line replacement, thereby ensuring the access performance of critical data.

[0060] Step 203: When the priority of the data request is not greater than the preset level, a hit check is performed in the second cache area to obtain the second check result, and a cache line in the second cache area is allocated to the data request based on the second check result.

[0061] Specifically, when the priority of a data request is not greater than a preset level, it indicates that the data request is a normal priority request. Therefore, the cache controller performs a hit check on the data request in the second cache area. In practical applications, the tag carried by the data request is compared one by one with the tag information of each cache line in the second cache area to obtain the second check result.

[0062] In this embodiment, a dedicated, physically isolated first and second cache regions are statically partitioned from the cache using a hardware mechanism. The first cache region corresponds to a priority higher than a preset level, while the second cache region corresponds to a priority lower than the preset level. When a data request is received from the processing core, for data requests with a priority higher than the preset level, a hit check is performed in the first cache region, and a cache line is allocated in the first cache region according to the obtained first check result. For data requests with a priority lower than the preset level, a hit check is performed in the second cache region, and a cache line is allocated in the second cache region according to the obtained second check result. This ensures that data with a priority higher than the preset level (i.e., critical data) has exclusive, protected cache resources, effectively preventing critical data from being evicted from the cache by non-critical data, ensuring low access latency for critical data, and thus improving the overall performance of the chip.

[0063] In some embodiments, if the tag carried by the data request hits the tag information of any cache line, that is, there exists a cache line whose tag information contains the tag carried by the data request and the cache line is valid, then the second check result is a cache hit. Therefore, the data request is allocated a cache line that hits in the second cache region and the data request is processed through the cache line.

[0064] Specifically, when the data request is a write request, the data carried by the write request is written to the cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, data is read from the cache line, and the read data is returned to the processing core.

[0065] In some embodiments, if the tag carried by the data request does not match the tag information of any cache line, that is, if the tag information of no cache line contains the tag carried by the data request, then it is considered a cache miss.

[0066] At this point, check whether the second cache area includes a free cache line; if the second cache area includes a free cache line, the second check result is: cache miss, and the second cache area includes a free cache line; accordingly, allocate a free cache line for the data request, and configure the priority of the allocated cache line to the priority of the data request (i.e., normal priority), and process the data request through the cache line.

[0067] Specifically, when the data request is a write request, the data carried by the write request is written to the allocated cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from main memory into the cache line, then the data is read from the cache line, and the read data is returned to the processing core.

[0068] In some embodiments, if a cache miss occurs and the second cache region does not contain any free cache lines, the free state of the first cache region is further determined. If the free state of the first cache area is not globally free, a cache line is selected from the second cache area as a replacement line according to the preset replacement strategy; then the data in the replacement line is evicted to main memory, and the replacement line is allocated to the data request.

[0069] In practice, the replacement strategy can be: selecting the cache line with the longest interval since the last access as the replacement line; the replacement strategy can also be LRU, LFU, etc. Furthermore, the replacement strategies used in the first cache region and the second cache region can be the same or different; this application does not impose specific limitations on this.

[0070] After evicting the data from the replacement line to main memory, the replacement line is allocated to the data request and processed through it. Specifically, when the data request is a write request, the data carried by the write request is written to the replacement line, and a write completion message is returned to the processing core after the write is complete. When the data request is a read request, the data to be read is loaded from main memory into the replacement line, then the data is read from the replacement line, and the read data is returned to the processing core.

[0071] In some embodiments, if a cache miss occurs, and the second cache region does not contain any free cache lines, while the first cache region is in a globally free state, then a cache line from the first cache region is allocated for the data request, and the priority of the allocated cache line is configured to the priority of the data request (i.e., normal priority), and the data request is processed through that cache line.

[0072] Specifically, when the data request is a write request, the data carried by the write request is written to the allocated cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from main memory into the cache line, then the data is read from the cache line, and the read data is returned to the processing core.

[0073] In this embodiment, the first cache region (i.e., HPCR) is allowed to be effectively utilized by ordinary priority requests when the global cache is idle, avoiding the waste of resources caused by static partitioning. At the same time, when a high-priority request occurs, cache resources can be intelligently and immediately reclaimed with low impact through a replacement strategy. This design maximizes the utilization efficiency of the entire L2 cache while ensuring the performance of high-priority requests.

[0074] Based on the same technical concept, this application provides a schematic diagram of a cache access control device applied to a cache, wherein the cache includes a first cache region and a second cache region; as shown Figure 3 As shown, the cache access control device 300 includes: The receiving module 301 is used to receive data requests sent by the processing core; The checking module 302 is used to perform a hit check in the first cache area to obtain a first check result when the priority of the data request is greater than a preset level, and to allocate a cache line in the first cache area to the data request based on the first check result; The checking module 302 is further configured to perform a hit check in the second cache area to obtain a second check result when the priority of the data request is not greater than a preset level, and allocate a cache line in the second cache area to the data request based on the second check result.

[0075] Optionally, the inspection module 302 is further configured to: Obtain the request address carried in the data request; When the requested address is within a preset physical address range, the priority of the data request is determined to be greater than a preset level; When the requested address is not within the preset physical address range, the priority of the data request is determined to be no greater than the preset level.

[0076] Optionally, the inspection module 302 is specifically used for: If the first check result indicates a cache miss, and the first cache region includes free cache lines, then the free cache lines are allocated for the data request; If the first check result indicates a cache miss, and there are no free cache lines in the first cache area, then a cache line is selected from the first cache area as a replacement line according to a preset replacement strategy. The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

[0077] Optionally, the inspection module 302 is specifically used for: If the first cache area contains at least one cache line with a priority no greater than a preset level, then the replacement line is selected from the at least one cache line according to the replacement strategy.

[0078] Optionally, the inspection module 302 is further configured to: If the first check result indicates a cache hit, then the cache line that was hit in the first cache region is allocated to the data request.

[0079] Optionally, the inspection module 302 is specifically used for: If the second check result indicates a cache miss, and the second cache region includes free cache lines, then the free cache lines are allocated for the data request; If the second check result indicates a cache miss, and the second cache region has no free cache lines, then the first cache region is determined to be in a free state. If the idle state of the first cache area is not globally idle, then a cache line is selected from the second cache area as the replacement line according to the preset replacement strategy; The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

[0080] Optionally, the inspection module 302 is further configured to: If the idle state of the first cache region is globally idle, then a cache line in the first cache region is allocated for the data request.

[0081] Optionally, the inspection module 302 is further configured to: If the second check result indicates a cache hit, then the cache line that was hit in the second cache region is allocated to the data request.

[0082] In this embodiment, a dedicated, physically isolated first and second cache regions are statically partitioned from the cache using a hardware mechanism. The first cache region corresponds to a priority higher than a preset level, while the second cache region corresponds to a priority lower than the preset level. When a data request is received from the processing core, for data requests with a priority higher than the preset level, a hit check is performed in the first cache region, and a cache line is allocated in the first cache region according to the obtained first check result. For data requests with a priority lower than the preset level, a hit check is performed in the second cache region, and a cache line is allocated in the second cache region according to the obtained second check result. This ensures that data with a priority higher than the preset level (i.e., critical data) has exclusive, protected cache resources, effectively preventing critical data from being evicted from the cache by non-critical data, ensuring low access latency for critical data, and thus improving the overall performance of the chip.

[0083] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0084] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 4 As shown, it includes at least one artificial intelligence chip 100 and a memory 401 connected to at least one artificial intelligence chip 100. In this embodiment, the specific connection medium between the artificial intelligence chip 100 and the memory 401 is not limited. Figure 4 Taking the connection between the AI ​​chip 100 and the memory 401 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0085] In this embodiment of the application, the memory 401 stores instructions that can be executed by at least one artificial intelligence chip 100. By executing the instructions stored in the memory 401, at least one artificial intelligence chip 100 can perform the steps of the cache access control method described above.

[0086] The artificial intelligence chip 100 serves as the control center of the computer device. It connects to various parts of the computer device via various interfaces and lines, and performs cache access control by running or executing instructions stored in the memory 401 and accessing data stored in the memory 401. Optionally, the artificial intelligence chip 100 may include one or more processing units. The artificial intelligence chip 100 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 401 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0087] The artificial intelligence chip 100 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0088] Memory 401, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 401 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 401 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 401 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0089] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described cache access control method.

[0090] Based on the same inventive concept, this application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the above-described cache access control method.

[0091] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0092] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0093] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0094] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0095] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0096] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A cache access control method, characterized in that, Applied to a cache, wherein the cache includes a first cache region and a second cache region, the method includes: Receive and process data requests sent by the core. When the priority of the data request is greater than the preset level, a hit check is performed in the first cache area to obtain a first check result, and a cache line in the first cache area is allocated to the data request based on the first check result; When the priority of the data request is not greater than the preset level, a hit check is performed in the second cache area to obtain a second check result, and a cache line in the second cache area is allocated to the data request based on the second check result.

2. The method as described in claim 1, characterized in that, The priority of the data request is determined in the following manner: Obtain the request address carried in the data request; When the requested address is within a preset physical address range, the priority of the data request is determined to be greater than a preset level; When the requested address is not within the preset physical address range, the priority of the data request is determined to be no greater than the preset level.

3. The method as described in claim 1, characterized in that, The step of allocating a cache line in the first cache region to the data request based on the first check result includes: If the first check result indicates a cache miss, and the first cache region includes free cache lines, then the free cache lines are allocated for the data request; If the first check result indicates a cache miss, and there are no free cache lines in the first cache area, then a cache line is selected from the first cache area as a replacement line according to a preset replacement strategy. The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

4. The method as described in claim 3, characterized in that, The step of selecting a cache line from the first cache region as a replacement line according to a preset replacement strategy includes: If the first cache area contains at least one cache line with a priority no greater than a preset level, then the replacement line is selected from the at least one cache line according to the replacement strategy.

5. The method as described in claim 3, characterized in that, Also includes: If the first check result indicates a cache hit, then the cache line that was hit in the first cache region is allocated to the data request.

6. The method as described in claim 1, characterized in that, The step of allocating a cache line in the second cache region for the data request based on the second check result includes: If the second check result indicates a cache miss, and the second cache region includes free cache lines, then the free cache lines are allocated for the data request; If the second check result indicates a cache miss, and the second cache region has no free cache lines, then the first cache region is determined to be in a free state. If the idle state of the first cache area is not globally idle, then a cache line is selected from the second cache area as the replacement line according to the preset replacement strategy; The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

7. The method as described in claim 6, characterized in that, Also includes: If the idle state of the first cache region is globally idle, then a cache line in the first cache region is allocated for the data request.

8. The method as described in claim 6, characterized in that, Also includes: If the second check result indicates a cache hit, then the cache line that was hit in the second cache region is allocated to the data request.

9. An artificial intelligence chip, characterized in that, include: Processes the core, cache, and main memory; The cache is used to perform the method according to any one of claims 1 to 8.

10. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored on the memory and running on the artificial intelligence chip, characterized in that, When the artificial intelligence chip executes the computer program, it implements the steps of the method as described in any one of claims 1 to 8.

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