Cache access control method, chip and device

Abstract

Embodiments of the present application provide a cache access control method, a chip and a device, and relate to the technical field of artificial intelligence chips. The method comprises: statically dividing a first cache region and a second cache region which are physically isolated from each other from a cache through a hardware mechanism. For a data request sent by a processing core and having a priority greater than a preset level, a hit check is performed in the first cache region, and a cache line in the first cache region is allocated to the data request according to a first check result obtained; for a data request having a priority not greater than the preset level, a hit check is performed in the second cache region, and a cache line in the second cache region is allocated to the data request according to a second check result obtained. The method ensures that data (i.e., critical data) having a priority greater than the preset level has exclusive and protected cache resources, effectively avoids the critical data from being evicted from the cache by non-critical data, ensures a low access delay of the critical data, and thus improves the overall performance of the chip.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of artificial intelligence chip, and in particular to a cache access control method, a chip and a device. BACKGROUND

[0002] An artificial intelligence chip (such as a general-purpose graphics processing unit (GPGPU)) architecture usually contains a multi-level cache hierarchy, in which the L2 cache as the shared last level data cache is crucial to the computing performance of the entire artificial intelligence chip.

[0003] Under the related art, the L2 cache management strategy usually adopts a unified cache space and a replacement strategy, such as least recently used (LRU), least frequently used (LFU) or a variant thereof. In the case of LFU, when the cache receives a data request, if the cache is full, the cache line least frequently used in the cache is evicted to the main memory.

[0004] In this way, key data (such as inter-core function synchronization data, high-frequency access intermediate results, etc.) sensitive to system performance or specific task latency may be evicted from the cache by non-key data, resulting in high access latency of the key data and thus affecting the overall performance of the chip. SUMMARY

[0005] Embodiments of the present application provide a cache access control method, a device and a storage medium, for reducing the access latency of key data in the cache and thus improving the overall performance of the chip.

[0006] In one aspect, the present application provides a cache access control method applied to a cache, the cache comprising a first cache region and a second cache region; the method comprising:

[0007] receiving a data request sent by a processing core;

[0008] when the priority of the data request is greater than a preset level, performing a hit check in the first cache region to obtain a first check result, and allocating a cache line in the first cache region for the data request based on the first check result;

[0009] when the priority of the data request is not greater than the preset level, performing a hit check in the second cache region to obtain a second check result, and allocating a cache line in the second cache region for the data request based on the second check result.

[0010] In one aspect, the embodiment of the present application provides a cache access control device, which is applied to a cache, and the cache comprises a first cache area and a second cache area; the device comprises:

[0011] a receiving module, configured to receive a data request sent by a processing core;

[0012] a checking module, configured to perform a hit check in the first cache area to obtain a first checking result when a priority of the data request is greater than a preset level, and allocate a cache line in the first cache area to the data request based on the first checking result;

[0013] The checking module is further configured to perform a hit check in the second cache area to obtain a second checking result when the priority of the data request is not greater than the preset level, and allocate a cache line in the second cache area to the data request based on the second checking result.

[0014] Optionally, the checking module is further configured to:

[0015] obtain a request address carried by the data request;

[0016] determine that the priority of the data request is greater than the preset level when the request address is located in a preset physical address range;

[0017] determine that the priority of the data request is not greater than the preset level when the request address is not located in the preset physical address range.

[0018] Optionally, the checking module is specifically configured to:

[0019] allocate an idle cache line to the data request if the first checking result represents cache miss and the first cache area comprises the idle cache line;

[0020] select a cache line as a replacement line from the first cache area according to a preset replacement strategy if the first checking result represents cache miss and the first cache area does not comprise the idle cache line;

[0021] evict data in the replacement line to a main memory, and allocate the replacement line to the data request.

[0022] Optionally, the checking module is specifically configured to:

[0023] select the replacement line from at least one cache line in the first cache area according to the replacement strategy if the at least one cache line comprises a priority not greater than the preset level.

[0024] Optionally, the checking module is further configured to:

[0025] If the first check result represents a cache hit, a cache line in the first cache region that hits the data request is allocated for the data request.

[0026] Optionally, the checking module is specifically configured to:

[0027] If the second check result represents a cache miss, and the second cache region includes a free cache line, the free cache line in the second cache region is allocated for the data request.

[0028] If the second check result represents a cache miss, and the second cache region does not include a free cache line, a free state of the first cache region is determined.

[0029] If the free state of the first cache region is not globally free, a cache line in the second cache region is selected as a replacement line according to a preset replacement policy.

[0030] Data in the replacement line is evicted to a main memory, and the replacement line is allocated to the data request.

[0031] Optionally, the checking module is further configured to:

[0032] If the free state of the first cache region is globally free, a cache line in the first cache region is allocated for the data request.

[0033] Optionally, the checking module is further configured to:

[0034] If the second check result represents a cache hit, a cache line in the second cache region that hits the data request is allocated for the data request.

[0035] In an aspect, an embodiment of the present application provides a computer device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and running on the artificial intelligence chip, the artificial intelligence chip implementing the steps of the above cache access control method when executing the computer program.

[0036] In an aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program executable by a computer device, when the computer program runs on the computer device, the computer device executes the steps of the above cache access control method.

[0037] In an aspect, an embodiment of the present application provides a computer program product, the computer program product includes a computer program stored on a computer readable storage medium, the computer program includes program instructions, when the program instructions are executed by a computer device, the computer device executes the steps of the above cache access control method.

[0038] In the embodiments of the present application, a dedicated and physically isolated first cache region and a second cache region are statically divided from the cache through a hardware mechanism, wherein the first cache region corresponds to a priority greater than a preset level, and the second cache region corresponds to a priority not greater than the preset level; in this way, when a data request sent by a processing core is received, for a data request with a priority greater than the preset level, a hit check is performed in the first cache region, and a cache line in the first cache region is allocated to the data request according to the obtained first check result; for a data request with a priority not greater than the preset level, a hit check is performed in the second cache region, and a cache line in the second cache region is allocated to the data request according to the obtained second check result, so as to ensure that data with a priority greater than the preset level (i.e., critical data) has exclusive and protected cache resources, effectively avoids the critical data from being evicted from the cache by non-critical data, ensures a low access delay of the critical data, and thus improves the overall performance of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 A structure schematic diagram of an artificial intelligence chip provided by the embodiments of the present application is provided.

[0041] Figure 2 A flowchart of a cache access control method provided by the embodiments of the present application is provided.

[0042] Figure 3 A structure schematic diagram of a cache access control device provided by the embodiments of the present application is provided.

[0043] Figure 4 A structure schematic diagram of a computer device provided by the embodiments of the present application is provided. DETAILED DESCRIPTION

[0044] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] REFERENCE Figure 1Fig. 1 is a structural diagram of an artificial intelligence chip applicable to an embodiment of the present application. The artificial intelligence chip 100 at least includes a processing core 101, a cache 102, and a main memory 103. The processing core 101 has the capability of artificial intelligence related calculations, such as matrix multiplication, convolution operation, etc. These operations are common calculation operations in artificial intelligence models. In actual applications, the processing core 101 can be a compute unit (CU). The number of processing cores 101 can be one or more, and the present application does not make a specific limitation on the number of processing cores.

[0046] The cache 102 is a small and fast storage area between the processing core 101 and the main memory 103, used to temporarily store data or instructions that the processing core 101 or other hardware devices are likely to frequently access in the near future, with the purpose of speeding up access and reducing access delay.

[0047] The cache 102 can be an L1 cache, a shared L2 cache, etc. The cache access control method in the present application is applicable to an L1 cache or an L2 cache, and can also be applicable to other types of caches.

[0048] The cache 102 can be a set-associative structure. The cache 102 includes multiple ways, and each way corresponds to at least one cache line. The cache line is the smallest unit of data stored in the cache 102, and the size of the cache line can be different under different hardware architectures. For example, 32 bytes, 64 bytes, 128 bytes, etc.

[0049] The cache line is also the smallest operation unit of the cache 102. When reading a certain data (such as an integer or a floating point number) from the cache 102, the entire cache line (for example, 64 bytes) where the data is located will be read together, instead of only reading the one data.

[0050] The main memory 103 is the next level of the cache 102. The main memory 103 is a main memory device directly accessed by the processing core 101. Compared with the cache 102, the main memory 103 generally has a larger capacity but is slower. When the processing core 101 performs data access, if the data is not in the cache 102 (i.e., cache miss), the data is loaded from the main memory 103 to the cache 102 (usually by cache line), and subsequent access can be directly read from the cache 102.

[0051] In the present embodiment, in the startup phase, a dedicated, physically isolated first cache area and a second cache area are statically divided from the cache 102 by a hardware mechanism. The first cache area includes at least one physically continuous or non-continuous cache line. Similarly, the second cache area includes at least one physically continuous or non-continuous cache line. In some embodiments, the cache 102 can include other cache areas in addition to the first cache area and the second cache area.

[0052] The priority corresponding to the first cache region and the second cache region is different; for example, the first cache region can be a high-priority cache region (HPCR for short); and the second cache region can be a normal cache region (NCR for short).

[0053] In the embodiment of the application, after the first cache region and the second cache region are statically divided, the first cache region and the second cache region are configured, specifically including the following operations:

[0054] In the power-on initialization stage of the artificial intelligence chip 100, the configuration is performed by a firmware (Option ROM). The firmware configures the following parameters for the first cache region and the second cache region through a memory mapping (Memory-Mapped I / O, MMIO for short) register:

[0055] The enable / disable state of the first cache region;

[0056] The way selection mask of the first cache region, wherein the way selection mask is a bitmap, and each bit in the bitmap corresponds to a way in the cache, and is “1” to indicate that the way is divided into the first cache region, and is “0” to indicate that the way belongs to the second cache region. For example, for a 16-way set associative L2 cache, the way selection mask “0x00FF” indicates that the low 8 ways (Way0-7) are configured as the first cache region, and the high 8 ways (Way 8-15) are configured as the second cache region.

[0057] After the configuration is completed, the configuration registers of the first cache region and the second cache region (especially the way selection mask register) will be locked by a hardware mechanism; for example, a state machine controls a write enable signal, and once the system is out of the initialization state, the write is prohibited. During the entire kernel and application program running, any software (including the operating system kernel and the chip driver) cannot modify the physical division of the first cache region and the second cache region.

[0058] By statically isolating the physical cache way in the firmware stage, a separate and protected hardware resource pool (that is, the first cache region) is provided for high-priority requests. This physical isolation is zero runtime overhead and is not affected by subsequent software scheduling, thereby providing a hardware-level and predictable hard guarantee for the access delay and cache hit rate of critical data.

[0059] The physical division of the first cache area and the second cache area is completed at one time and locked at system startup, and no software intervention is required for cache partition configuration at runtime; this completely eliminates the software overhead (such as system calls, driver scheduling delays) brought by the dynamic partitioning scheme, and avoids the risk of cache strategy tampering due to software errors or malicious attacks, improving the security and stability of the system.

[0060] After the configuration is completed, the operating system and the artificial intelligence chip driver are loaded. The application of the artificial intelligence chip 100 runs and calls a preset application programming interface (API), declares one or more physical address ranges (for example, a memory area for synchronization) as high priority. The artificial intelligence chip 100 driver processes the API call in the processing core 101, generates a descriptor containing the physical address range, and writes the descriptor into the address range comparator register of the cache controller in the cache 102 through the MMIO register.

[0061] In the embodiments of the present application, the physical address range with high priority can be assigned flexibly. This logical strategy is decoupled from the physical resource division described above, so that while providing strong physical isolation protection, the software is given great flexibility through the runtime API and kernel descriptor mechanism. Developers can dynamically and finely define which data is critical data (corresponding to high priority) without modifying the hardware or restarting the system, facilitating application optimization and software adaptation.

[0062] In addition, the method of the present application is mainly implemented in the cache controller hardware, and the modification to the existing artificial intelligence chip architecture is relatively small, mainly focusing on control logic and a small number of register additions and reductions, which is easy to integrate into modern artificial intelligence chip design.

[0063] In addition to the above structure, the artificial intelligence chip 100 in the present application can also include other structures, which are not limited in the present application.

[0064] The artificial intelligence chip 100 can be a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a domain specific architecture (DSA), etc.

[0065] The following will be based on the architecture diagram of the artificial intelligence chip shown in Figure 1 to specifically introduce the process of providing a cache access control method, refer toFigure 2 The method is executed by a cache including a first cache area and a second cache area, and a cache controller, and includes the following steps:

[0066] Step 201, receiving a data request sent by a processing core.

[0067] The data request can be a write request or a read request.

[0068] In some embodiments, the request address carried by the data request is obtained; when the request address is located in a preset physical address range, it is determined that the priority of the data request is greater than a preset level; when the request address is not located in the preset physical address range, it is determined that the priority of the data request is not greater than the preset level.

[0069] In a specific implementation, after the first cache area and the second cache area are statically configured, the artificial intelligence chip calls a preset API to declare one or more physical address ranges, and the priorities corresponding to the physical address ranges are greater than a preset level. Then, descriptors containing the physical address ranges are generated and written into an address range comparator register of the cache controller through MMIO.

[0070] The cache controller extracts the request address carried by the data request, and then compares the request address with each physical address range in the address range comparator register.

[0071] If the request address is located in any one of the physical address ranges, it is determined that the priority of the data request is greater than the preset level, that is, the data request is a high-priority request.

[0072] If the request address is not located in any one of the physical address ranges, it is determined that the priority of the data request is not greater than the preset level, that is, the data request is a normal-priority request.

[0073] Step 202, when the priority of the data request is greater than the preset level, performing a hit check in the first cache area to obtain a first check result, and allocating a cache line in the first cache area for the data request based on the first check result.

[0074] Specifically, when the priority of the data request is greater than the preset level, it means that the data request is a high-priority request, and therefore, the cache controller performs a hit check on the data request in the first cache area. In actual application, the tag carried by the data request is compared with the tag information of each cache line under the first cache area one by one to obtain a first check result.

[0075] In some embodiments, if the tag carried by the data request hits the tag information of any cache line, i.e. there is a cache line whose tag information contains the tag carried by the data request and the cache line is valid, the first check result is cache hit, thus, the cache line hit in the first cache area is allocated to the data request, and the data request is processed through the cache line.

[0076] Specifically, when the data request is a write request, the data carried by the write request is written into the cache line, and after the writing is completed, a write completion message is returned to the processing core. When the data request is a read request, data is read from the cache line, and the read data is returned to the processing core.

[0077] In some embodiments, if the tag carried by the data request does not hit the tag information of any cache line, i.e. there is no cache line whose tag information contains the tag carried by the data request, it indicates cache miss. At this time, it is checked whether the first cache area includes a free cache line;

[0078] If the first cache area includes a free cache line, the first check result obtained is that the cache is missed, and the first cache area includes a free cache line; accordingly, the free cache line is allocated to the data request, and the priority of the allocated cache line is configured as the priority of the data request (i.e. high priority), and the data request is processed through the cache line.

[0079] Specifically, when the data request is a write request, the data carried by the write request is written into the allocated cache line, and after the writing is completed, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from the main memory to the cache line, then data is read from the cache line, and the read data is returned to the processing core.

[0080] In some embodiments, if the cache is missed and the first cache area does not include a free cache line, the first check result obtained is that the cache is missed, and the first cache area does not include a free cache line, at this time, a cache line is selected as a replacement line from the first cache area according to a preset replacement policy; then the data in the replacement line is evicted to the main memory, and the replacement line is allocated to the data request, and the priority of the replacement line is configured as the priority of the data request.

[0081] In specific implementation, the replacement policy can be that a cache line with the longest interval time from the last access is selected as the replacement line; the replacement policy can also be LRU policy, LFU policy, etc., which is not limited by the present application.

[0082] After the data in the replacement line is evicted to the main memory, the replacement line is allocated to the data request and the data request is processed through the replacement line. Specifically, when the data request is a write request, the data carried by the write request is written into the replacement line, and after the writing is completed, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from the main memory to the replacement line, and then the data is read from the replacement line, and the read data is returned to the processing core.

[0083] In some embodiments, if the first cache area contains at least one cache line with a priority not greater than the preset level, a replacement line is selected from the at least one cache line according to a replacement policy.

[0084] Specifically, in addition to containing cache lines with a priority greater than the preset level (i.e., high priority), the first cache area can also contain cache lines with a priority not greater than the preset level (i.e., normal priority), where the cache lines with normal priority can be cache lines previously allocated to normal priority requests, or can be cache lines whose priority is reset (e.g., from high priority to normal priority) after being previously allocated to high priority requests.

[0085] When the first check result is cache miss and the first cache area has no free cache line, it is first checked whether the first cache area contains cache lines with a priority not greater than the preset level.

[0086] If yes, a cache line is selected as the replacement line from these cache lines (i.e., cache lines with normal priority) according to the replacement policy; if no, a cache line is selected as the replacement line from cache lines with a priority greater than the preset level (i.e., cache lines with high priority) according to the replacement policy.

[0087] In the embodiments of the present application, when the first cache area contains cache lines with normal priority, these cache lines will gradually become "cold" over time or when new data requests (high priority or normal priority) occur. Therefore, when a new high priority request is received and cache line replacement is needed, these cache lines with normal priority will be preferentially selected as the replacement line, realizing intelligent and low-impact cache line replacement, thereby ensuring the access performance of critical data.

[0088] Step 203: When the priority of the data request is not greater than the preset level, a hit check is performed in the second cache area to obtain a second check result, and a cache line in the second cache area is allocated to the data request based on the second check result.

[0089] Specifically, when the priority of the data request is not greater than the preset level, it indicates that the data request is a common priority request, and thus the cache controller performs a hit check on the data request in the second cache area. In actual application, the tag carried by the data request is compared with the tag information of each cache line under the second cache area one by one to obtain a second check result.

[0090] In the embodiments of the present application, a dedicated, physically isolated first cache area and a second cache area are statically divided from the cache by a hardware mechanism, wherein the first cache area corresponds to a priority greater than a preset level, and the second cache area corresponds to a priority not greater than the preset level; in this way, when receiving the data request sent by the processing core, for the data request with a priority greater than the preset level, a hit check is performed in the first cache area, and a cache line in the first cache area is allocated to the data request according to the obtained first check result; for the data request with a priority not greater than the preset level, a hit check is performed in the second cache area, and a cache line in the second cache area is allocated to the data request according to the obtained second check result, which ensures that the data with a priority greater than the preset level (i.e., critical data) has exclusive and protected cache resources, effectively avoids the critical data from being evicted from the cache by non-critical data, ensures the low access delay of the critical data, and thus improves the overall performance of the chip.

[0091] In some embodiments, if the tag carried by the data request hits the tag information of any cache line, i.e., the tag information of a cache line contains the tag carried by the data request, and the cache line is valid, the second check result is a cache hit, and thus a cache line that hits in the second cache area is allocated to the data request, and the data request is processed through the cache line.

[0092] Specifically, when the data request is a write request, the data carried by the write request is written into the cache line, and after writing, a write completion message is returned to the processing core. When the data request is a read request, data is read from the cache line, and the read data is returned to the processing core.

[0093] In some embodiments, if the tag carried by the data request does not hit the tag information of any cache line, i.e., none of the tag information of any cache line contains the tag carried by the data request, it indicates that the cache is a miss.

[0094] At this time, it is checked whether the second cache area includes an idle cache line; if the second cache area includes an idle cache line, the obtained second check result is that the cache is a miss, and the second cache area includes an idle cache line; accordingly, an idle cache line is allocated to the data request, the priority of the allocated cache line is configured as the priority of the data request (i.e., common priority), and the data request is processed through the cache line.

[0095] Specifically, when the data request is a write request, the data carried by the write request is written to the allocated cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from main memory into the cache line, then the data is read from the cache line, and the read data is returned to the processing core.

[0096] In some embodiments, if a cache miss occurs and the second cache region does not contain any free cache lines, the free state of the first cache region is further determined.

[0097] If the free state of the first cache area is not globally free, a cache line is selected from the second cache area as a replacement line according to the preset replacement strategy; then the data in the replacement line is evicted to main memory, and the replacement line is allocated to the data request.

[0098] In practice, the replacement strategy can be: selecting the cache line with the longest interval since the last access as the replacement line; the replacement strategy can also be LRU, LFU, etc. Furthermore, the replacement strategies used in the first cache region and the second cache region can be the same or different; this application does not impose specific limitations on this.

[0099] After evicting the data from the replacement line to main memory, the replacement line is allocated to the data request and processed through it. Specifically, when the data request is a write request, the data carried by the write request is written to the replacement line, and a write completion message is returned to the processing core after the write is complete. When the data request is a read request, the data to be read is loaded from main memory into the replacement line, then the data is read from the replacement line, and the read data is returned to the processing core.

[0100] In some embodiments, if a cache miss occurs, and the second cache region does not contain any free cache lines, while the first cache region is in a globally free state, then a cache line from the first cache region is allocated for the data request, and the priority of the allocated cache line is configured to the priority of the data request (i.e., normal priority), and the data request is processed through that cache line.

[0101] Specifically, when the data request is a write request, the data carried by the write request is written to the allocated cache line, and after the write is complete, a write completion message is returned to the processing core. When the data request is a read request, the data to be read is loaded from main memory into the cache line, then the data is read from the cache line, and the read data is returned to the processing core.

[0102] In the embodiments of the present application, the first cache area (i.e. HPCR) is allowed to be effectively utilized by a common priority request when the global cache is idle, thereby avoiding resource waste caused by static partitioning; meanwhile, when a high priority request appears, cache resources can be intelligently and low-impactly recovered immediately through a replacement strategy, which ensures the performance of the high priority request while maximizing the utilization efficiency of the entire L2 cache.

[0103] Based on the same technical concept, the embodiments of the present application provide a structural diagram of a cache access control device, which is applied to a cache including a first cache area and a second cache area; as shown in the figure, the cache access control device 300 includes: Figure 3

[0104] a receiving module 301 configured to receive a data request sent by a processing core;

[0105] a checking module 302 configured to, when the priority of the data request is greater than a preset level, perform a hit check in the first cache area to obtain a first checking result, and allocate a cache line in the first cache area to the data request based on the first checking result;

[0106] The checking module 302 is further configured to, when the priority of the data request is not greater than the preset level, perform a hit check in the second cache area to obtain a second checking result, and allocate a cache line in the second cache area to the data request based on the second checking result.

[0107] Optionally, the checking module 302 is further configured to:

[0108] obtain a request address carried by the data request;

[0109] when the request address is located in a preset physical address range, determine that the priority of the data request is greater than the preset level;

[0110] when the request address is not located in the preset physical address range, determine that the priority of the data request is not greater than the preset level.

[0111] Optionally, the checking module 302 is specifically configured to:

[0112] if the first checking result represents cache miss, and the first cache area includes a free cache line, allocate the free cache line to the data request;

[0113] if the first checking result represents cache miss, and the first cache area does not include a free cache line, select a cache line from the first cache area as a replacement line according to a preset replacement strategy;

[0114] ​evict data in the replacement line to the main memory, and allocate the replacement line to the data request.

[0115] Optionally, the checking module 302 is specifically configured to:

[0116] If the first cache area contains at least one cache line with a priority not greater than a preset level, the replacement line is selected from the at least one cache line according to the replacement strategy.

[0117] Optionally, the checking module 302 is further configured to:

[0118] If the first checking result represents cache hit, the cache line hit in the first cache area is allocated to the data request.

[0119] Optionally, the checking module 302 is specifically configured to:

[0120] If the second checking result represents cache miss, and the second cache area includes a free cache line, the free cache line is allocated to the data request.

[0121] If the second checking result represents cache miss, and the second cache area does not include a free cache line, the free state of the first cache area is determined.

[0122] If the free state of the first cache area is not global free, a cache line in the second cache area is selected as a replacement line according to a preset replacement strategy.

[0123] Evict data in the replacement line to the main memory, and allocate the replacement line to the data request.

[0124] Optionally, the checking module 302 is further configured to:

[0125] If the free state of the first cache area is global free, a cache line in the first cache area is allocated to the data request.

[0126] Optionally, the checking module 302 is further configured to:

[0127] If the second checking result represents cache hit, the cache line hit in the second cache area is allocated to the data request.

[0128] In this embodiment, a dedicated, physically isolated first and second cache regions are statically partitioned from the cache using a hardware mechanism. The first cache region corresponds to a priority higher than a preset level, while the second cache region corresponds to a priority lower than the preset level. When a data request is received from the processing core, for data requests with a priority higher than the preset level, a hit check is performed in the first cache region, and a cache line is allocated in the first cache region according to the obtained first check result. For data requests with a priority lower than the preset level, a hit check is performed in the second cache region, and a cache line is allocated in the second cache region according to the obtained second check result. This ensures that data with a priority higher than the preset level (i.e., critical data) has exclusive, protected cache resources, effectively preventing critical data from being evicted from the cache by non-critical data, ensuring low access latency for critical data, and thus improving the overall performance of the chip.

[0129] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0130] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 4 As shown, it includes at least one artificial intelligence chip 100 and a memory 401 connected to at least one artificial intelligence chip 100. In this embodiment, the specific connection medium between the artificial intelligence chip 100 and the memory 401 is not limited. Figure 4 Taking the connection between the AI ​​chip 100 and the memory 401 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0131] In this embodiment of the application, the memory 401 stores instructions that can be executed by at least one artificial intelligence chip 100. By executing the instructions stored in the memory 401, at least one artificial intelligence chip 100 can perform the steps of the cache access control method described above.

[0132] The artificial intelligence chip 100 is a control center of the computer device, can connect various parts of the computer device through various interfaces and lines, and can realize cache access control by running or executing instructions stored in the memory 401 and calling data stored in the memory 401. Optionally, the artificial intelligence chip 100 can include one or more processing units, and the artificial intelligence chip 100 can integrate an application processor and a modem processor. The application processor mainly processes an operating system, a user interface, and an application program, and the modem processor mainly processes wireless communication. It can be understood that the above-mentioned modem processor can also not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 401 can be implemented on the same chip, and in some embodiments, they can also be implemented on independent chips respectively.

[0133] The artificial intelligence chip 100 can be a general processor, such as a central processing unit (CPU), a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly embodied as hardware processor execution or executed by a combination of hardware and software modules in the processor.

[0134] The memory 401, as a non-volatile computer readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 401 can include at least one type of storage medium, for example, can include flash memory, hard disk, multimedia card, card type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. The memory 401 is any other medium capable of carrying or storing desired program codes in the form of instructions or data structures and capable of being accessed by a computer device, but is not limited thereto. The memory 401 in the embodiments of the present application can also be a circuit or any other device capable of realizing a storage function, used to store program instructions and / or data.

[0135] Based on the same inventive concept, the embodiments of the present application provide a computer readable storage medium storing a computer program executable by a computer device, which, when executed on the computer device, causes the computer device to perform the steps of the cache access control method.

[0136] Based on the same inventive concept, the embodiments of the present application provide a computer program product, which comprises a computer program stored on a computer readable storage medium, the computer program comprising program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the cache access control method.

[0137] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0138] The present application is described in reference to the flowchart and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0139] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0140] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0141] While preferred embodiments of the application have been described, modifications and variations can be apparent to those skilled in the art once aware of the general underlying concepts. Accordingly, the appended claims intend to embrace all such modifications and variations as fall within the scope of the application.

[0142] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A cache access control method, characterized in that, Applied to caching, the cache includes a statically partitioned and physically isolated first cache region and second cache region, wherein the priority of the first cache region is greater than a preset level, and the priority of the second cache region is not greater than the preset level; the method includes: Receive data requests sent by the processing core, wherein the data requests carry a request address; When the requested address is within a preset physical address range, the priority of the data request is determined to be greater than the preset level. A hit check is performed in the first cache area to obtain a first check result, and a cache line in the first cache area is allocated to the data request based on the first check result. When the requested address is not within the preset physical address range, the priority of the data request is determined to be no greater than the preset level. A hit check is performed in the second cache area to obtain a second check result, and a cache line in the second cache area is allocated to the data request based on the second check result.

2. The method as described in claim 1, characterized in that, The step of allocating a cache line in the first cache region to the data request based on the first check result includes: If the first check result indicates a cache miss, and the first cache region includes free cache lines, then the free cache lines are allocated for the data request; If the first check result indicates a cache miss, and there are no free cache lines in the first cache area, then a cache line is selected from the first cache area as a replacement line according to a preset replacement strategy. The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

3. The method as described in claim 2, characterized in that, The step of selecting a cache line from the first cache region as a replacement line according to a preset replacement strategy includes: If the first cache area contains at least one cache line with a priority no greater than a preset level, then the replacement line is selected from the at least one cache line according to the replacement strategy.

4. The method as described in claim 2, characterized in that, Also includes: If the first check result indicates a cache hit, then the cache line that was hit in the first cache region is allocated to the data request.

5. The method as described in claim 1, characterized in that, The step of allocating a cache line in the second cache region for the data request based on the second check result includes: If the second check result indicates a cache miss, and the second cache region includes free cache lines, then the free cache lines are allocated for the data request; If the second check result indicates a cache miss, and the second cache region has no free cache lines, then the first cache region is determined to be in a free state. If the idle state of the first cache area is not globally idle, then a cache line is selected from the second cache area as the replacement line according to the preset replacement strategy; The data in the replacement row is evicted to main memory, and the replacement row is assigned to the data request.

6. The method as described in claim 5, characterized in that, Also includes: If the idle state of the first cache region is globally idle, then a cache line in the first cache region is allocated for the data request.

7. The method as described in claim 5, characterized in that, Also includes: If the second check result indicates a cache hit, then the cache line that was hit in the second cache region is allocated to the data request.

8. An artificial intelligence chip, characterized in that, include: Processes the core, cache, and main memory; The cache is used to perform the method according to any one of claims 1 to 7.

9. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and running on the artificial intelligence chip, characterized in that, When the artificial intelligence chip executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

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