High-speed and low-power differential driver based on tri-state gate MUX and complementary CML

Abstract

The present invention provides a high-speed, low-power differential driver based on a three-state gate multiplexer (MUX) and complementary CML circuits. The driver comprises a three-state gate multiplexer (MUX) and a complementary CML driver. The output of the three-state gate multiplexer (MUX) is connected to the input of the complementary CML driver via a buffer circuit. The multiple input signals of the three-state gate multiplexer (MUX) are selected and multiplexed through a high-impedance and on-state switching mechanism, outputting a high-speed differential signal. The complementary CML driver converts the high-speed differential signal into a high-speed, large-swing differential signal and drives an external load. The present invention can reduce full-rate nodes, improve signal integrity, and suppress glitches caused by switching delay mismatches. The differential signal swing is larger, and noise immunity is enhanced. By adding a buffer to the output of the MUX and designing the complementary CML driver's branches symmetrically, timing competition in signal switching is resolved, improving signal integrity.

Description

Technical Field

[0001] The present invention relates to the technical field of drivers, in particular to a high-speed and low-power differential driver based on a tri-state gate MUX and a complementary CML. Background Art

[0002] In high-speed communication systems, the serializer / deserializer (SerDes) transmitter (TX) is one of the key modules in the system. Its main task is to convert high-speed digital signals into differential analog signals suitable for the transmission channel. With the rapid increase in data rates, such as reaching 100Gbps or even higher in PAM4 or NRZ signals, the performance of the driver directly determines the signal integrity and system reliability. In current technologies, tri-state gate multiplexers (MUX) and current mode logic (CML) drivers are widely used for signal processing and signal driving, respectively. However, traditional drivers face many challenges in high-speed applications.

[0003] 1. In existing TX circuits, signals after passing through the MUX often require additional driver circuit processing, significantly increasing circuit complexity and power consumption. This can also easily cause signal reflections or interference. Furthermore, the inability to effectively control the swing amplitude requires additional swing control circuits or level shifting circuits in the subsequent driver, further increasing power consumption and latency.

[0004] 2. Driver reliability is a key factor in high-speed SerDes driver design. Transistor voltage stress is a particularly prominent issue when the supply voltage is gradually increased to increase the swing.

[0005] 1) When the driver is off, the drain voltage of the output transistor is close to the supply voltage, while the gate voltage remains constant, which may cause excessive Vgd stress and thus cause oxide breakdown.

[0006] 2) Under high-voltage and high-frequency environments, the reliability of transistors is further reduced, and long-term performance degradation or failure may occur.

[0007] 3. Traditional three-state gate MUXs offer signal multiplexing capabilities, allowing them to select one output from multiple input signals by selecting a control signal. However, this type of MUX primarily focuses on selective signal multiplexing, resulting in weak output drive capability and difficulty meeting the drive requirements of high-speed signal transmission. Especially at high frequencies, the signal swing at the MUX output is small and its noise immunity is poor, increasing the design complexity of subsequent driver stages.

[0008] 4. Traditional CML drivers are essentially fixed differential signal amplification units and lack multiplexing capabilities. In scenarios requiring multiple signal input selection, CML drivers typically require an external MUX module for signal selection, which not only increases circuit complexity but also may introduce additional signal delays and switching glitches. Summary of the Invention

[0009] To address the shortcomings of the existing technology, the present invention provides a high-speed, low-power differential driver based on a tri-state gate MUX and complementary CML. By organically combining the signal selection function of the tri-state gate MUX with the high swing and high-speed driving capabilities of the CML driver, the present invention solves technical problems such as signal integrity, power consumption, output swing, and reliability in existing high-speed SerDes TX drivers.

[0010] The technical solution of the present invention is: a high-speed, low-power differential driver based on a three-state gate MUX and complementary CML, comprising a three-state gate multiplexer MUX and a complementary CML driver; the output end of the three-state gate multiplexer MUX is connected to the input end of the complementary CML driver via a buffer circuit; the multiple input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-impedance state and a conduction state switching mechanism to output a high-speed differential signal; the complementary CML driver amplifies the high-speed differential signal into a high-speed, large-swing differential signal and drives an external load.

[0011] Preferably, the three-state gate multiplexer MUX includes two groups of three-state gates arranged in parallel, and the output ends of the two groups of three-state gates are connected to complementary CML drivers through buffer circuits; the two groups of three-state gates of the three-state gate multiplexer MUX respectively control the input signal to enter the high-impedance state or the on state to realize signal selection and multiplexing functions.

[0012] Preferably, each group of three-state gates of the three-state gate multiplexer MUX includes an upper branch and a lower branch, and the upper and lower branches are symmetrically arranged.

[0013] Preferably, the buffer circuit is composed of a plurality of inverters, the input ends of the inverters are connected to the outputs of the tri-state gate multiplexer MUX; and the output ends of the inverters are connected to the complementary CML drivers.

[0014] Preferably, the complementary CML driver includes a symmetrically arranged first branch and a second branch, wherein the first branch includes transistors D1, D2, D5, and D6; and the second branch includes transistors D3, D4, D7, and D8. The source of transistor D1 is connected to the input power supply VDD; the gate of transistor D1 is connected to the NAND gate of the first group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the first group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of transistor D4 through an inverter; the drain of transistor D1 is connected to the source of transistor D2; the drain of transistor D2 is connected to the drain of transistor D3; the source of transistor D3 is connected to the drain of transistor D4; the source of transistor D4 is grounded; and the gates of transistors D2 and D3 are also connected to gate voltages VC_P and VC_N.

[0015] The source of the transistor D5 is connected to the input power supply VDD; the gate of the transistor D5 is connected to the NAND gate of the second group of tri-state gates of the tri-state gate multiplexer MUX through an inverter; the NOR gate of the second group of tri-state gates of the tri-state gate multiplexer MUX is connected to the gate of the transistor D8 through an inverter; the drain of the transistor D5 is connected to the source of the transistor D6; the drain of the transistor D6 is connected to the drain of the transistor D7; the source of the transistor D7 is connected to the drain of the transistor D8; and the source of the transistor D8 is grounded;

[0016] The gates of the transistors D6 and D7 are connected to gate voltages VC_P and VC_N respectively;

[0017] The drains of the transistors D2 and D6 and the drains of the transistors D3 and D7 are connected together and serve as the output terminals of the complementary CML driver.

[0018] Preferably, the output end of the complementary CML driver is further connected to a common mode power supply VCM, and the output end of the complementary CML driver is further connected to resistors R1 and R2.

[0019] Preferably, when transistors D1 and D5 are turned on, transistors D2 and D4 are turned off, or when transistors D1 and D5 are turned off, transistors D2 and D4 are turned on; by adjusting the gate DC voltage of the transistors, the gate voltage of D2, D3, D6, and D7 is finally fixed to adjust the driving state of the driver, thereby optimizing the voltage distribution and reducing voltage stress.

[0020] Preferably, the complementary CML driver input signal controls the conduction state of the differential pair to generate a high-swing, high-speed differential output signal.

[0021] The beneficial effects of the present invention are:

[0022] 1. This invention organically combines the signal selection function of a tri-state gate MUX with the high swing and high-speed drive capabilities of a CML driver to form an integrated structure with multiplexing and drive capabilities. This reduces full-rate nodes, improves signal integrity, and suppresses glitches caused by switching delay mismatches. It also provides a larger differential signal swing and enhanced noise immunity. Furthermore, it reduces the circuit area required to design two separate modules and significantly reduces overall power consumption by reducing the number of inter-stage buffers.

[0023] 2. The present invention achieves efficient integration of signal multiplexing and driving capabilities by introducing a buffer circuit between the MUX output and the CML driver input. Furthermore, the branches of the MUX and CML driver are symmetrically designed, achieving high-swing output of high-speed signals, resolving timing competition in signal switching, and improving signal integrity.

[0024] 3. The present invention optimizes the signal switching matching between the MUX and CML driver through a buffer circuit, thereby improving overall signal integrity and suppressing glitches caused by switching delay mismatch. This addresses the limitations of both MUX and CML drivers in traditional technologies and provides an integrated differential driver solution suitable for high-speed communications.

[0025] 4. The present invention can reduce the voltage stress of the output transistor, especially the Vgd stress, and extend the life of the device. By properly selecting the current source and load resistor, a larger differential swing is achieved, and the removal of the buffer stage significantly reduces power consumption.

[0026] 5. The present invention achieves a larger differential signal swing output and enhanced noise immunity through the efficient design of complementary CML drivers, making it suitable for high-frequency and high-speed application scenarios, such as PAM4 or NRZ signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural framework diagram of the driver of the present invention;

[0028] Figure 2 This is an application framework diagram for achieving balancing of the driver according to Example 1 of the present invention;

[0029] Figure 3 This is an eye diagram simulation result diagram of Example 1 of the present invention with input data of 28 Gbps and output data of 56 Gbps, but without passing through the channel;

[0030] Figure 4 This is the eye diagram simulation result of Example 1 of the present invention with 28Gbps input data and 56Gbps output data passing through the channel but without equalization enabled;

[0031] Figure 5This is an eye diagram simulation result diagram of Example 1 of the present invention with input data of 28 Gbps and output data of 56 Gbps, passing through the channel with equalization turned on. DETAILED DESCRIPTION

[0032] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings:

[0033] Example 1

[0034] like Figure 1 As shown, this embodiment provides a high-speed, low-power differential driver based on a three-state gate MUX and complementary CML. The device includes a three-state gate multiplexer MUX and a complementary CML driver. The output of the three-state gate multiplexer MUX is connected to the complementary CML driver via a buffer circuit. The multiple input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-impedance state and conduction state switching mechanism, outputting a high-speed differential signal. The complementary CML driver converts the high-speed differential signal into a high-speed, large-swing differential signal to drive an external load. This embodiment uses a buffer circuit to improve the driving capability of the output signal of the three-state gate multiplexer MUX.

[0035] As a preferred embodiment of this invention, the three-state gate multiplexer MUX can realize two or more differential input signals. In this embodiment, the three-state gate multiplexer MUX includes two groups of three-state gates arranged in parallel. Each group of three-state gates of the three-state gate multiplexer MUX includes an upper branch and a lower branch. The upper and lower branches are symmetrically arranged to further reduce signal competition. IN1 and F IN2 Serving as the input ends of the two groups of three-state gates of the three-state gate multiplexer MUX.

[0036] Moreover, this embodiment adjusts the on-resistance of the tri-state gate to keep the on and off speeds consistent, thus avoiding delay differences causing glitches. IN1 and F IN2 connected to the signal input terminal; the output terminals of the two tri-state gates are connected to the complementary CML driver through a buffer circuit; the two tri-state gates of the tri-state gate multiplexer MUX respectively enter the high-impedance state or the conduction state by controlling the input signal to realize the signal selection and multiplexing function.

[0037] As a preferred embodiment, this embodiment optimizes signal switching timing matching by providing a buffer circuit between the tri-state gate multiplexer MUX and the complementary CML driver. This embodiment can control the signal switching transition time to a relatively short time. The buffer circuit comprises a plurality of inverters, the inputs of which are connected to the outputs of the tri-state gate multiplexer MUX, and the outputs of which are connected to the complementary CML driver.

[0038] As a preferred embodiment of the present invention, the complementary CML driver includes a symmetrically arranged first branch and a second branch, wherein the first branch includes transistors D1, D2, D5, and D6; the second branch includes transistors D3, D4, D7, and D8; the source of the transistor D1 is connected to the input power supply VDD; the gate of the transistor D1 is connected to the NAND gate of the first group of tri-state gates of the tri-state gate multiplexer MUX via an inverter; the NOR gate of the first group of tri-state gates of the tri-state gate multiplexer MUX is connected to the gate of the transistor D4 via an inverter; the drain of the transistor D1 is connected to the source of the transistor D2; the drain of the transistor D2 is connected to the drain of the transistor D3; the source of the transistor D3 is connected to the drain of the transistor D4; the source of the transistor D4 is grounded; and the gates of the transistors D2 and D3 are also connected to gate voltages VC_P and VC_N.

[0039] The source of the transistor D5 is connected to the input power supply VDD; the gate of the transistor D5 is connected to the NAND gate of the second group of tri-state gates of the tri-state gate multiplexer MUX through an inverter; the NOR gate of the second group of tri-state gates of the tri-state gate multiplexer MUX is connected to the gate of the transistor D8 through an inverter; the drain of the transistor D5 is connected to the source of the transistor D6; the drain of the transistor D6 is connected to the drain of the transistor D7; the source of the transistor D7 is connected to the drain of the transistor D8; and the source of the transistor D8 is grounded;

[0040] The gates of the transistors D6 and D7 are connected to gate voltages VC_P and VC_N respectively;

[0041] The drains of the transistors D2 and D6 and the drains of the transistors D3 and D7 are connected together and serve as the output terminals of the complementary CML driver.

[0042] As a preferred embodiment of the present invention, the output end of the complementary CML driver is further connected to a common-mode power supply VCM, and the output end of the complementary CML driver is further connected to resistors R1 and R2.

[0043] As a preferred embodiment of this invention, when transistors D1 and D5 are turned on, transistors D2 and D4 are turned off, or when transistors D1 and D5 are turned off, transistors D2 and D4 are turned on; by adjusting the gate DC voltage of the transistors, the gate voltages of D2, D3, D6, and D7 are finally fixed, and the driving state is adjusted by controlling the input power supply VDD, thereby optimizing the voltage distribution and reducing the voltage stress.

[0044] As a preferred embodiment of the present invention, the complementary CML driver input signal controls the conduction state of the differential pair to generate a high-swing, high-speed differential output signal.

[0045] In this embodiment, CK / CKB is a clock input to the tri-state gate multiplexer MUX.

[0046] In this embodiment, Figure 2 As shown, this embodiment can implement 3-tap (Pre-Tap, Main-Tap, Post-Tap) FFE equalization. The Main-Tap adopts a tailless CML structure, while the Pre-Tap and Post-Tap adopt a cascode CML structure. This structure has a wide tuning range and high output resistance, and a large intensity control range can be achieved by adjusting its bias current source. In this embodiment, Id is the CML tail current source.

[0047] like Figure 3 As shown, this embodiment can output 56 Gbps data and drive a certain load by inputting 28 Gbps data, and its function is normal as can be verified by observing the eye diagram.

[0048] like Figure 4 As shown in the figure, the output signal has passed a certain channel attenuation (6dB), and the eye diagram can be used to determine that the signal integrity has been severely damaged. Figure 5 The eye diagram after equalization shows that this embodiment has a good equalization effect.

[0049] Example 2

[0050] This embodiment, based on Example 1, eliminates the buffer circuit. Instead, the output of the tri-state gate multiplexer MUX is directly connected to the input of the complementary CML driver. The structures of the tri-state gate multiplexer MUX and complementary CML driver in this embodiment are consistent with those in Example 1. This embodiment is suitable for scenarios with lower signal integrity requirements, such as medium- and low-speed signal multiplexing.

[0051] At the same time, this embodiment can also be expanded to more input signals according to needs, such as 4 or 8 channels; after expansion, the selection logic of the three-state gate can be generated by a simple logic circuit, or combined with a decoder design to reduce the number of control signals.

[0052] The above embodiments and descriptions are only for explaining the principles and best embodiments of the present invention. Without departing from the spirit and scope of the present invention, the present invention may be subject to various changes and improvements, which shall fall within the scope of the invention to be protected.

Claims

1. High-speed, low-power differential driver based on tri-state gate MUX and complementary CML, characterized by: The invention comprises a three-state gate multiplexer MUX and a complementary CML driver; the output end of the three-state gate multiplexer MUX is connected to the input end of the complementary CML driver through a buffer circuit; the multiple input signals of the three-state gate multiplexer MUX are selected and multiplexed through a high-impedance state and a conduction state switching mechanism, and a high-speed differential signal is output; the complementary CML driver converts the high-speed differential signal into a high-speed, large-swing differential signal and drives an external load; The three-state gate multiplexer MUX includes two sets of three-state gates arranged in parallel, and the output ends of the two sets of three-state gates are connected to complementary CML drivers through buffer circuits; the two sets of three-state gates of the three-state gate multiplexer MUX respectively control the input signal to enter the high-impedance state or the conductive state to realize signal selection and multiplexing functions; The buffer circuit is composed of a plurality of inverters, the input end of the inverter is connected to the output end of the tri-state gate multiplexer MUX; the output end of the inverter is connected to the input end of the complementary CML driver; The complementary CML driver includes a first branch and a second branch that are symmetrically arranged, wherein the first branch includes transistors D1, D2, D5, and D6; the second branch includes transistors D3, D4, D7, and D8; the gate of transistor D1 is connected to the NAND gate of a first group of tri-state gates of a tri-state gate multiplexer MUX via an inverter; the NOR gate of the first group of tri-state gates of the tri-state gate multiplexer MUX is connected to the gate of transistor D4 via an inverter; the drain of transistor D1 is connected to the source of transistor D2; the drain of transistor D2 is connected to the drain of transistor D3; the source of transistor D3 is connected to the drain of transistor D4; and the source of transistor D4 is grounded. The gate of the transistor D5 is connected to the NAND gate of the second group of three-state gates of the three-state gate multiplexer MUX through an inverter; the NOR gate of the second group of three-state gates of the three-state gate multiplexer MUX is connected to the gate of the transistor D8 through an inverter; the drain of the transistor D5 is connected to the source of the transistor D6; the drain of the transistor D6 is connected to the drain of the transistor D7; the source of the transistor D7 is connected to the drain of the transistor D8; and the source of the transistor D8 is grounded.

2. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 1, characterized in that: Each group of three-state gates of the three-state gate multiplexer MUX includes an upper branch and a lower branch, and the upper and lower branches are symmetrically arranged.

3. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 1, characterized in that: The sources of the transistor D1 and the transistor D5 are connected to the input power supply VDD.

4. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 1, characterized in that: The gates of the transistors D2 , D3 , D6 , and D7 are also connected to gate voltages VC_P and VC_N.

5. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 4, characterized in that: The drains of the transistors D2 and D6 and the drains of the transistors D3 and D7 are connected together and serve as the output terminals of the complementary CML driver.

6. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 5, characterized in that: When transistors D1 and D5 are turned on, transistors D2 and D4 are turned off, or when transistors D1 and D5 are turned off, transistors D2 and D4 are turned on; by adjusting the DC gate voltage of the transistors, the gate voltage of D2, D3, D6, and D7 is finally fixed to adjust the driving state of the driver, thereby optimizing the voltage distribution and reducing voltage stress.

7. The high-speed, low-power differential driver based on tri-state gate MUX and complementary CML according to claim 1, characterized in that: The complementary CML driver input signal controls the conduction state of the differential pair to generate a high-swing, high-speed differential output signal.

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