Chip test data display method and device and electronic equipment

Abstract

The embodiment of the invention discloses a chip test data display method and device and electronic equipment, and the method comprises the steps: obtaining first target data and second target data, generating first Hash mapping corresponding to the first target data, storing the second target data in the first Hash mapping, and when a data display instruction is received, obtaining target expected waveform data and target sampling waveform data corresponding to the data display instruction from the second Hash mapping, and displaying the target expected waveform data and the target sampling waveform data in the second Hash mapping. And displaying the target expected waveform data and the target sampling waveform data on a visual interaction interface. Therefore, the expected waveform data and the adopted waveform data corresponding to each period of each pin are stored through the data structure of the Hash mapping, the conditions of frequently exchanging data memories and reading data are avoided, the calculated amount is reduced, and the stability of the system is improved.

Description

Technical Field

[0001] The present application relates to chip testing technology, and in particular to a chip testing data display method, device and electronic equipment. Background Art

[0002] As the functions of chips continue to increase, the number of chip pins also increases. In related technologies, the data information corresponding to each pin is often stored through a linked list data structure. When the data information corresponding to the pin needs to be displayed, all the data information corresponding to the pin is obtained from the linked list and displayed on the display interface.

[0003] In the process of implementing the present application, it was discovered through research that in the related technology, when the number of pins of a chip is large, the use of a linked list data structure to store and search for data information corresponding to the pins will result in the need to frequently exchange data memory and read data, resulting in an increase in the amount of calculation and affecting system performance. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a chip test data display method, device and electronic device.

[0005] One aspect of an embodiment of the present application provides a chip test data display method, which is applied to a chip test device, and the method includes: obtaining first target data and second target data from a test vector and sampled data, respectively, the first target data including multiple cycles and expected waveform data of each pin in each cycle, and the second target data including multiple cycles and sampled waveform data of each pin in each cycle; generating a first hash map corresponding to the first target data, the first hash map including the first target data; storing the second target data in the first hash map to merge the first target data and the second target data to obtain a second hash map, the second hash map including the first target data and the second target data; in response to receiving a data display instruction, obtaining target expected waveform data and target sampled waveform data corresponding to the data display instruction from the second hash map, and displaying the target expected waveform data and the target sampled waveform data on a visual interactive interface.

[0006] Another aspect of an embodiment of the present application provides a chip test data display device, which is applied to a chip test device, and the device includes: a waveform data acquisition module, which is used to obtain first target data and second target data from a test vector and sampled data respectively, the first target data includes multiple cycles and expected waveform data of each pin in each cycle, and the second target data includes multiple cycles and sampled waveform data of each pin in each cycle; a first hash map generation module, which is used to generate a first hash map corresponding to the first target data, the first hash map includes the first target data; a second hash map generation module, which is used to store the second target data in the first hash map to merge the first target data and the second target data to obtain a second hash map, the second hash map includes the first target data and the second target data; a display module, which is used to obtain target expected waveform data and target sampled waveform data corresponding to the data display instruction from the second hash map in response to receiving a data display instruction, and display the target expected waveform data and the target sampled waveform data on a visual interactive interface.

[0007] Another aspect of an embodiment of the present application provides an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the above-mentioned chip test data display method is implemented.

[0008] In another aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned chip test data display method is implemented.

[0009] In another aspect of the embodiments of the present application, a computer program product is provided, including computer program instructions, which implement the above-mentioned chip test data display method when executed by a processor.

[0010] The chip test data display method, device and electronic device in the embodiments of the present application, the chip test data display method includes: obtaining first target data and second target data, the first target data includes multiple cycles, and expected waveform data of each pin in each cycle, the second target data includes multiple cycles, and sampled waveform data of each pin in each cycle, then generating a first hash map corresponding to the first target data, and then storing the second target data in the first hash map, fusing the first target data and the second target data to obtain a second hash map, and when a data display instruction is received, obtaining the target expected waveform data and target sampled waveform data corresponding to the data display instruction from the second hash map, and displaying them on a visual interactive interface. Therefore, in the embodiment of the present application, the expected waveform data corresponding to each pin in the test vector in each cycle is stored through the first hash map, and the sampled waveform data corresponding to each pin in the sampled data in each cycle is merged with the expected waveform data (first target data) corresponding to each pin in the first hash map, forming a second hash map storing the expected waveform data and adopted waveform data corresponding to each pin in each cycle, thereby realizing the storage of the expected waveform data and adopted waveform data corresponding to each pin in each cycle through the data structure of the hash map, avoiding the situation of frequent exchange of data memory and reading of data, reducing the amount of calculation, and improving the stability of the system. In addition, the expected waveform data and adopted waveform data corresponding to each pin in each cycle are stored by the second hash map, which improves the storage efficiency and query efficiency of the expected waveform data and sampled waveform data corresponding to each pin in each cycle, thereby improving the speed of obtaining the target expected waveform data and the target sampled waveform data, so that the target expected waveform data and the target sampled waveform data can be quickly passed to the graphics framework for display on the visual interactive interface, avoiding the phenomenon of freeze or jamming of the visual interactive interface when displaying.

[0011] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0013] The present application can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0014] Figure 1 It is a flowchart of a chip test data display method provided by an exemplary embodiment of the present application.

[0015] Figure 2 It is a flowchart of step S120 provided by an exemplary embodiment of the present application.

[0016] Figure 3 It is a flowchart of step S130 provided by an exemplary embodiment of the present application.

[0017] Figure 4 It is a flowchart of a chip test data display method provided by another exemplary embodiment of the present application.

[0018] Figure 5 It is a flowchart of step S140 provided by an exemplary embodiment of the present application.

[0019] Figure 6 It is a schematic diagram of a visual interactive interface provided by an exemplary embodiment of the present application.

[0020] Figure 7 It is a schematic diagram of a chip test data display method provided in an application example of the present application.

[0021] Figure 8 It is an interactive timing diagram of a chip test data display method provided in an application example of the present application.

[0022] Fig. 9 It is a structural block diagram of a chip test data display device provided by an exemplary embodiment of the present application.

[0023] Fig.10 This is a schematic diagram of the structure of an application embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0024] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0025] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0026] It should also be understood that in the embodiments of the present application, "plurality" may refer to two or more than two, and "at least one" may refer to one, two or more than two.

[0027] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0028] In addition, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0029] It should also be understood that the description of the various embodiments in this application focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0030] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0031] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present application, its application, or uses.

[0032] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0033] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0034] The embodiments of the present application can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0035] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0036] In the process of implementing the present application, it was found through research that as the functions of liquid crystal display (Liquid Crystal Display, LCD) continue to increase, the number of pins of LCD chips (liquid crystal display driver chips) also increases to support the functions of LCD. Therefore, when the data information corresponding to each pin in the LCD chip is stored using a linked list data structure, it will require frequent exchange of data memory and reading of data, resulting in an increase in calculation amount and affecting system performance.

[0037] Figure 1 FIG. 1 is a flow chart of a chip test data display method provided by an exemplary embodiment of the present application. This embodiment can be applied to chip test equipment, such as Figure 1 As shown, the chip test data display method may include the following steps:

[0038] Step S110, obtaining first target data and second target data from the test vector and the sampled data respectively.

[0039] The chip testing equipment is used to test the function and / or performance of a chip, a wafer or an integrated circuit, etc. For example, the chip testing equipment may be an integrated circuit automatic test equipment (ATE).

[0040] The first target data includes multiple cycles and expected waveform data of each pin in each cycle, and the second target data includes multiple cycles and sampled waveform data of each pin in each cycle. Each cycle may include the duration of executing one cycle.

[0041] In one embodiment, the first target data is obtained from the test vector, and the second target data is obtained from the sampled data. The test vector may include the expected waveform data of each pin in each cycle. Specifically, the test vector (Pattern) is a very long string of binary codes, which stores the input timing waveform and the expected timing waveform (expected waveform data). The chip testing equipment can send a series of timing stimuli to the pins of the chip under test according to the input timing waveform. At this time, the pins of the chip will output a series of actual timing waveforms (sampled waveform data). These actual timing waveforms are compared with the expected timing waveforms. If they are the same, the chip meets its function, otherwise there is a problem with the chip. That is, the expected waveform data of each pin in the first target data in each cycle may include the expected timing waveform corresponding to the pin in the test vector in each cycle.

[0042] The sampling data can be obtained by executing the test vector on the chip under test by a chip testing device. In one embodiment, the sampling data may include, for example, pin information, pin combination information, and sampling point voltage value, and the sampling point voltage value may include a high voltage value (High) and a low voltage value (Low). Based on the pin information, the pin combination information, and the sampling point voltage value, a logic analyzer may be used to generate sampling waveform data corresponding to each pin in each cycle. Exemplarily, a logic analyzer is an instrument for analyzing a digital logic system, and usually only displays two voltages (logic 1 and 0). Therefore, a reference voltage is set in the logic analyzer. The logic analyzer determines the sampling voltage value in the sampling data through a comparator in the logic analyzer, and determines the value higher than the reference voltage as a high voltage value, and determines the value lower than the reference voltage as a low voltage value, and forms the sampling waveform data between the high voltage value and the low voltage value. The sampling waveform data corresponding to each pin in each cycle in the second target data may include the actual timing waveform corresponding to each pin in each cycle.

[0043] Step S120: Generate a first hash map corresponding to the first target data.

[0044] The first hash map includes first target data.

[0045] Hash Map is a data storage structure. Hash Map can be understood as an extension of array. Hash Map is internally implemented as array + linked list + red-black tree transformation, and data is stored and searched in the form of key-value pairs. Specifically, in hash map, when storing data, the key is used as the index, and the value corresponding to the key is stored in the hash map. When searching, the key is brought into the hash map. The hash map checks whether there is an index with the same key in all indexes. If so, the value corresponding to the key is used as the search result.

[0046] In one embodiment, the hash map storing the first target data may be referred to as a first hash map. The first target data may be converted into corresponding key-value pairs, and then the first hash map may be generated through the key-value pairs corresponding to the first target data.

[0047] Step S130: store the second target data in the first hash map to merge the first target data and the second target data to obtain a second hash map.

[0048] The second hash map includes the first target data and the second target data.

[0049] In one embodiment, in the first hash map, the expected waveform data and the sampled waveform data corresponding to the same period and pin in the first target data and the second target data can be mapped and merged to fuse the first target data and the second target data, that is, the expected waveform data and the sampled waveform data corresponding to the period of each pin are stored in the second hash map.

[0050] Step S140, in response to receiving the data display instruction, obtaining the target expected waveform data and the target sampled waveform data corresponding to the data display instruction from the second hash map, and displaying the target expected waveform data and the target sampled waveform data on the visual interactive interface.

[0051] Among them, the expected waveform data and the sampled waveform data corresponding to the data display instruction can be called target expected waveform data and target sampled waveform data.

[0052] In one embodiment, a data display instruction can be generated according to the pin and cycle selected by the user on the visual interactive interface, that is, the data display instruction can include the pin and cycle, and can be retrieved in the second hash map to determine the expected waveform data and the sampled waveform data corresponding to the pin and cycle in the data display instruction, and the expected waveform data and the sampled waveform data are determined as the target expected waveform data and the target sampled waveform data, and the target expected waveform data and the target sampled waveform data can be visualized and then displayed on the visual interactive interface.

[0053] In the embodiment of the present application, the expected waveform data corresponding to each pin in each cycle is stored through the first hash map, and the sampled waveform data corresponding to each pin in each cycle is merged with the expected waveform data (first target data) corresponding to each pin in each cycle in the first hash map to form a second hash map storing the expected waveform data and adopted waveform data corresponding to each pin in each cycle, thereby realizing the storage of the expected waveform data and adopted waveform data corresponding to each pin in each cycle through the data structure of the hash map, avoiding the situation of frequent exchange of data memory and reading of data, reducing the amount of calculation, and improving the stability of the system. In addition, the expected waveform data and adopted waveform data corresponding to each pin in each cycle are stored by the second hash map, which improves the storage efficiency and query efficiency of the expected waveform data and sampled waveform data corresponding to each pin in each cycle, thereby improving the speed of obtaining the target expected waveform data and the target sampled waveform data, so that the target expected waveform data and the target sampled waveform data can be quickly passed to the graphics framework for display on the visual interactive interface, avoiding the phenomenon of freeze or jamming of the visual interactive interface when displaying.

[0054] In some optional implementations, step S110 in the embodiment of the present application may include: parsing the test vector to obtain parsed data corresponding to the test vector, and then obtaining the first target data from the parsed data.

[0055] The parsed data may include each pin and each cycle, and the expected waveform data corresponding to each pin in each cycle. In one embodiment, the binary code of the test vector may be parsed in a binary format to obtain identifiable parsed data.

[0056] In an embodiment of the present application, the binary test vector is first parsed to obtain corresponding parsed data, and the expected waveform data corresponding to each pin in each cycle is obtained from the parsed data. This avoids the need to parse the test vector each time the expected waveform data corresponding to different pins in different cycles is directly obtained from the test vector, thereby improving the efficiency of obtaining the expected waveform data, thereby ensuring the smoothness of displaying the expected waveform data, and further avoiding the phenomenon of freeze or freezing of the visual interactive interface during display.

[0057] Figure 2 is a flow chart of step S120 provided by an exemplary embodiment of the present application. In some optional implementations, such as Figure 2 As shown, step S120 may include the following steps:

[0058] Step S121: determining a plurality of first key-value pairs based on the first target data.

[0059] Among them, multiple first key-value pairs include first target data, the key in any first key-value pair includes any pin and any cycle, and the value in any first key-value pair includes expected waveform data corresponding to any pin in any cycle.

[0060] In one embodiment, the key-value pair including the first target data may be referred to as a first key-value pair. Each first key-value pair includes a key (Key) and a value (Value) corresponding to the key. A first key-value pair may be generated based on the expected waveform data corresponding to each pin in each cycle.

[0061] Exemplarily, "a pin name+a cycle" may be used as a key in a first key-value pair, and the expected waveform data corresponding to the pin in the cycle may be used as the value corresponding to the key.

[0062] Step S122: Generate a first hash map based on multiple first key-value pairs.

[0063] The first hash map includes a plurality of first key-value pairs, that is, the first target data is stored in the first hash map in the form of a plurality of first key-value pairs.

[0064] In some optional implementations, the first hash map includes: an array, a linked list, and a red-black tree.

[0065] Among them, the red-black tree is a self-balancing binary search tree containing red and black nodes. The number of black nodes contained in the path from the root node to the leaf node can be called the black height of the red-black tree. The characteristics of the red-black tree can include: 1) the node is red or black, 2) the root node is black, 3) all leaf nodes (NIL nodes, empty nodes) are black, 4) the two child nodes of each red node are black. In the red-black tree, the path from any node to each leaf node contains the same number of black nodes, thereby ensuring that the time complexity of the red-black tree is O (logn). When the red-black tree stores a large amount of data, the search efficiency is improved compared to the linked list structure.

[0066] Correspondingly, in an embodiment of the present application, step S122 may include: storing multiple first key-value pairs in an array, a linked list, and a red-black tree, and when the total amount of data in the linked list reaches a preset quantity threshold, adding the first key-value pairs stored in the linked list to the red-black tree for storage.

[0067] The total data volume represents the number of all nodes storing data in the linked list, and each node in the linked list is used to store a key-value pair. The preset quantity threshold includes a node quantity threshold, and the node quantity threshold may be 8, for example.

[0068] In one embodiment, for each first key-value pair, based on the key in the first key-value pair, the storage position of the first key-value pair in the first hash map is determined, and when the storage position does not store data, the first key-value pair is stored in the first hash map; when the storage position has stored data and there is a key in the first hash map that is the same as the key in the first key-value pair, the first key-value pair is not stored in the first hash map, thereby avoiding the situation where the first hash map has an infinite loop due to duplicate data that may exist in the test vector, and plays a fool-proof role for the first hash map; when the storage position has stored data and there is no key in the first hash map that is the same as the key in the first key-value pair, and the total amount of data in the linked list is less than a preset quantity threshold, the first key-value pair is stored in the linked list; when the storage position has stored data and there is no key in the first hash map that is the same as the key in the first key-value pair, and the total amount of data in the linked list is the preset quantity threshold, the first key-value pair and the first key-value pair stored in the linked list are added to the red-black tree for storage.

[0069] Specifically, the key in the first key-value pair can be substituted into a preset hash function to obtain a hash value corresponding to the key, and the subscript (storage location) of the array can be determined based on the hash value. Exemplarily, a number smaller than the length of the current array in the first hash map can be determined based on the hash value corresponding to the key by using the hash value (key.hash)% array length method, and the number is used as the subscript (storage location) of the array, that is, the subscript of the array is obtained by taking the hash value of the key in the first key-value pair modulo the array length.

[0070] When the subscript of the array is empty, the first key-value pair is inserted into the array to store the first key-value pair; when data is already stored at the subscript of the array, the key in the first key-value pair is compared with all the current keys in the first hash map to determine whether there are identical keys. If there are identical keys, the first key-value pair is not stored in the first hash map; if there are no identical keys, the number of nodes in the linked list storing data (total amount of data) is determined. When the number of nodes in the linked list storing data is less than a preset number threshold, the first key-value pair is inserted into the linked list to store the first key-value pair in the first hash map; when the number of nodes in the linked list storing data is a preset number threshold, all first key-value pairs in the linked list are removed, and the first key-value pair and the removed first key-value pair are inserted into the red-black tree to add the first key-value pair stored in the linked list to the red-black tree for storage, and the first key-value pair is stored in the first hash map.

[0071] In an embodiment of the present application, a first hash map consisting of an array, a linked list, and a red-black tree is used to store a first key-value pair. During the storage process, when the total data volume of the linked list reaches a preset data volume threshold, the first key-value pair stored in the linked list is added to the red-black tree for storage, thereby replacing the linked list with the data form of the red-black tree. This can improve the query efficiency of the expected waveform data and the sampled waveform data corresponding to each pin in each cycle.

[0072] Figure 3 is a flow chart of step S130 provided by an exemplary embodiment of the present application. In some optional implementations, such as Figure 3 As shown, step S130 may include the following steps:

[0073] Step S131, determining a plurality of second key-value pairs based on the second target data.

[0074] Among them, multiple second key-value pairs include second target data, the key in any second key-value pair includes any pin and any cycle, and the value in any second key-value pair includes sampling waveform data corresponding to any pin in any cycle.

[0075] The key-value pair including the second target data may be referred to as a second key-value pair. Each second key-value pair includes a key and a value corresponding to the key. A second key-value pair may be generated based on the sampled waveform data corresponding to each pin in each cycle.

[0076] Exemplarily, "a pin name+a cycle" may be used as a key in a second key-value pair, and the sampled waveform data corresponding to the pin in the cycle may be used as the value corresponding to the key.

[0077] Step S132: Map the plurality of second key-value pairs into the first hash map to merge the first target data and the second target data to obtain a second hash map.

[0078] Among them, the key-value pair in the second hash map can be called a target key-value pair, the key in the target key-value pair can be called a target key, and the value in the target key-value pair can be called a target value.

[0079] The second hash map includes multiple target key-value pairs, the target key in any target key-value pair includes any pin and any cycle, and the target value in any target key-value pair includes the expected waveform data and the sampled waveform data corresponding to any pin in any cycle. That is, the second hash map includes the first target data and the second target data.

[0080] In one embodiment, for each second key-value pair, the second key-value pair is merged with the first key-value pair of the same key as the second key-value pair in the first hash map. Specifically, based on the key in the second key-value pair, a search is performed in the first hash map to determine the key that is the same as the key in the second key-value pair, and the key that is the same as the key in the second key-value pair is determined as the target key, and the value in the second key-value pair is mapped to the value corresponding to the target key to obtain the target value. Each second key-value pair performs the above-mentioned operation of merging the second key-value pair with the first key-value pair of the same key as the second key-value pair to merge the first target data and the second target data to obtain a second hash map including multiple target key-value pairs.

[0081] In an embodiment of the present application, the first target data and the second target data are fused using multiple first key-value pairs and multiple second key-value pairs to integrate the expected waveform data and the sampled waveform data corresponding to each pin in each cycle, thereby enabling the corresponding expected waveform data and the sampled waveform data to be obtained at one time through the pin and cycle subsequently, thereby improving the efficiency of obtaining the data corresponding to the pin.

[0082] Figure 4 FIG. 1 is a flow chart of a chip test data display method provided by another exemplary embodiment of the present application. In some optional implementations, such as Figure 4 As shown, the chip test data display method also includes the following steps:

[0083] Step S210, obtaining third target data from parsed data corresponding to the test vector.

[0084] The third target data includes at least one of the following: a file version of a test vector, pin information, pin combination information, timing information, microinstruction information, and a timing set number.

[0085] File version: The file version used to define the test vector. Test vectors in a specified format can be written and parsed based on this file version.

[0086] Pin information: Pins are the wiring leads from the internal circuit of the chip. Pin information may include pin name, pin attributes and pin number. Pin attributes include input and output. When the pin attribute is input, it means that stimulus can be input through the pin. When the pin attribute is output, it means that the pin inputs the corresponding signal.

[0087] Pin combination information: may include multiple pin groups, wherein a pin group may be: multiple pins are combined and used to form a pin group.

[0088] Timing file information (timing information): Timing information required during the execution of the test vector, that is, the Timing file information can include the Timing file name, pin name and cycle (the time to execute a cycle), as well as the drive timing (drive delay, drive offset and return delay) and signal format required when used as an input pin, and the drive shutdown delay and comparison time required when used as an output pin.

[0089] Microinstruction information: the smallest unit used for each timing manipulation. The microinstruction information may include multiple microinstructions. For example, the microinstruction information may include: LOOP (ENDLOOP), STOP, REPEATE, SCANNORM, etc., where LOOP (ENDLOOP) is a loop microinstruction, STOP is a stop microinstruction, REPEATE is a repeat microinstruction, SCAN is a scan microinstruction, and NORM is a normalization instruction.

[0090] Timing set number: includes the correspondence between the Timing file information and the timing, that is, different Timing file information is allocated according to the timing during the execution of the test vector.

[0091] Step S220, storing the third target data in a linked list data structure.

[0092] A preset linked list may be created in advance, and the third target data may be stored in the preset linked list.

[0093] In an embodiment of the present application, the data in the test vector is classified and stored, the third target data with a smaller data size is stored using a linked list data structure, and the first target data with a larger data size is stored in the form of a hash map, thereby increasing the flexibility of data storage and ensuring the efficiency of storing and querying test vectors.

[0094] In some optional implementations, the data display instruction includes a target key to be retrieved, wherein the pin and cycle selected by the user on the visual interactive interface can be used as the target key to be retrieved.

[0095] Accordingly, in the embodiment of the present application, step S140 may include: based on the target key to be retrieved, obtaining the target expected waveform data and the target sampled waveform data in the second hash map. The target key to be retrieved includes a cycle and a pin.

[0096] In one embodiment, a target key identical to a target key to be retrieved is retrieved in a second hash map, and a target value corresponding to the target key identical to the target key to be retrieved in the second hash map is obtained, and the expected waveform data and sampled waveform data in the target value are used as target expected waveform data and target sampled waveform data, respectively.

[0097] In an embodiment of the present application, the corresponding target expected waveform data and target sampled waveform data are obtained in the second hash map according to the target key to be retrieved in the data display instruction, thereby improving the flexibility of obtaining the expected waveform data and sampled waveform data corresponding to the pin, avoiding the situation in the prior art where only all waveform data of the pin can be obtained at one time, and improving data acquisition efficiency.

[0098] Figure 5 is a flow chart of step S140 provided by an exemplary embodiment of the present application. In some optional implementations, such as Figure 5 As shown, step S140 may include the following steps:

[0099] Step S141, obtaining refresh information of the visual interactive interface.

[0100] The refresh information includes the pins and cycles displayed on the visual interactive interface.

[0101] In one implementation, the pins and cycles currently displayed on the visual interaction interface may be used as the displayed cycles and pins.

[0102] Step S142, obtaining the display expected waveform data and display sampled waveform data corresponding to the displayed pin and period from the target expected waveform data and the target sampled waveform data, and displaying the display expected waveform data and the display sampled waveform data on the visual interactive interface.

[0103] Among them, based on the displayed pin and period, the expected waveform data and sampling waveform data corresponding to the displayed pin and period can be obtained in the target expected waveform data and the target sampling waveform data, and the expected waveform data and the sampling waveform data can be determined as the displayed expected waveform data and the displayed sampling waveform data. The displayed expected waveform data and the displayed sampling waveform data can be visualized and then displayed on the visualization interactive interface.

[0104] In one embodiment, the test vector can be displayed in rows according to the pin order in the test vector and in columns according to the time sequence of the timing on the visual interactive interface. Fixed pins and cycles (target keys to be retrieved) can be displayed on the visual interactive interface to increase the readability of the test vector and the sampled data. On the visual interactive interface, the user can trigger a horizontal slide with the mouse to change the displayed pins and trigger a vertical slide to change the displayed cycle (the displayed pins and cycles). When a mouse slide signal is received, the corresponding display expected waveform data and display sampled waveform data are obtained from the target expected waveform data and the target sampled waveform data according to the position before and after the mouse slide for display.

[0105] For example, Figure 6is a schematic diagram of a visual interactive interface provided by an exemplary embodiment of the present application. Figure 6 As shown in the figure, Frist Cycle indicates the starting cycle, Cycle Count indicates the maximum number of cycles displayed in the waveform display area. You can select the displayed pins and test the corresponding data in the Include option. Pin1 to pin5 indicate pins 1 to 5. You can determine the target key to be retrieved, including cycles and pins, by setting the Frist Cycle, Cycle Count and pins in the Include option. Figure 5 The target keys include pin1, LCD1, LCD2, LCD3, LCD4 and LCD5, and cycle 0 to cycle 10; the pins and cycles displayed are pin1, LCD1, LCD2, LCD3, LCD4 and LCD5, and cycle 0 to cycle 9. Figure 5 The yellow waveform is the sampled waveform data, and the blue waveform is the expected waveform data. Opcode indicates microinstructions, Timingset indicates timing settings, Span indicates setting the interval size of the waveform display area, and ShowPinCount indicates setting the maximum number of pins to be displayed, ranging from 10 to 100. Show Expected Wave indicates displaying the expected waveform, ShowAcquired Wave indicates displaying the actual waveform, Show Samples indicates displaying the sampled data in a dot graph, ShowConnecting Link indicates displaying the sampled data in a line graph, and Show Hex indicates the conversion between HSD hexadecimal and waveform.

[0106] In an embodiment of the present application, the expected waveform data and the display sampling waveform data currently required to be displayed on the visual interactive interface are obtained from the target expected waveform data and the target sampled waveform data by refreshing information. Therefore, only the expected waveform data and the display sampling waveform data on the visual interactive interface need to be rendered and displayed, which reduces the time for data rendering and improves display efficiency.

[0107] Figure 7 Schematic diagram of a chip test data display method provided in an application example of the present application. Figure 7 In the method, the test vector and the sampling data are used as external data, the software executes the chip test data display method, and the terminal includes a visual interactive interface.

[0108] A test vector can be obtained, and the test vector can be executed to test the chip under test, and sampling data can be obtained. The sampling data can be received, and the test vector can be parsed, and the first target data and the second target data can be obtained from the parsed data and the sampling data. A plurality of first key-value pairs are generated based on the first target data, and a plurality of second key-value pairs are generated based on the second target data. A first hash map is generated based on the plurality of first key-value pairs, and the plurality of second key-value pairs are mapped to the first hash map to perform structured processing on the first target data and the first target data to obtain a second hash map, receive a refresh display (data display instruction), and obtain the target expected waveform data and the target sampling waveform data corresponding to the target key to be retrieved in the data display instruction in the second hash map, and return to the terminal, and the visual interactive interface of the terminal displays the corresponding UI data (displaying the expected waveform data and displaying the sampling waveform data).

[0109] Figure 8 This is an interactive timing diagram of a chip test data display method provided by an application example of this application. Figure 8 In the present invention, the data management layer serves as a server, the server executes the chip test data display method, and the client includes a visual interactive interface.

[0110] At the data management layer, vector data acquisition: requesting a test vector (request pattern) from external data, and obtaining the file name (pattern file name) and test vector of the test vector, and resolving the test vector (resolve pattern) to obtain resolved data; sampling data acquisition: requesting sampling data (request sampling) from external data, and receiving the feedback sampling data (sampling data), and resolving the sampling data (resolve sampling), which is also understood as constructing multiple second key-value pairs. The chip test data display method in the embodiment of the present application is executed to generate a second hash map.

[0111] Refresh display: display (show) the visual interactive interface, and receive data display instructions, perform data matching (data matching) in the second hash map to obtain the target expected waveform data and the target sampled waveform data, and feedback to the client. The client obtains the corresponding interface display data (display expected waveform data and display sampled waveform data, UI data), and then displays (show) on the client's visual interactive interface.

[0112] Fig. 9 1 is a block diagram of a chip test data display device provided by an exemplary embodiment of the present application. The chip test data display device is applied to a chip test device, and the chip test data display device includes:

[0113] The waveform data acquisition module 310 is used to acquire first target data and second target data from the test vector and the sampled data respectively, wherein the first target data includes multiple cycles and expected waveform data of each pin in each cycle, and the second target data includes multiple cycles and sampled waveform data of each pin in each cycle;

[0114] A first hash map generating module 320, configured to generate a first hash map corresponding to the first target data, wherein the first hash map includes the first target data;

[0115] A second hash map generating module 330, configured to store the second target data in the first hash map, so as to merge the first target data and the second target data to obtain a second hash map, wherein the second hash map includes the first target data and the second target data;

[0116] The display module 340 is used to obtain the target expected waveform data and the target sampled waveform data corresponding to the data display instruction from the second hash map in response to receiving the data display instruction, and display the target expected waveform data and the target sampled waveform data on the visual interactive interface.

[0117] In some optional implementations, obtaining the first target data from the test vector is further used to: parse the test vector to obtain parsed data corresponding to the test vector; and obtain the first target data from the parsed data.

[0118] In some optional implementations, the first hash map generation module 320 includes:

[0119] A first key-value pair generating submodule is used to determine a plurality of first key-value pairs based on the first target data, wherein the plurality of first key-value pairs include the first target data, a key in any first key-value pair includes any pin and any cycle, and a value in any first key-value pair includes expected waveform data corresponding to any pin in any cycle;

[0120] The first hash map generating submodule is used to generate the first hash map based on the multiple first key-value pairs, where the first hash map includes the multiple first key-value pairs.

[0121] In some optional implementations, the first hash map includes an array, a linked list, and a red-black tree;

[0122] The first hash map generation submodule is specifically used to store the multiple first key-value pairs in the array, the linked list and the red-black tree, and when the total amount of data in the linked list reaches a preset quantity threshold, add the first key-value pairs stored in the linked list to the red-black tree for storage.

[0123] In some optional implementations, the second hash map generation module 330 includes:

[0124] A second key-value pair generating submodule is used to determine a plurality of second key-value pairs based on the second target data, wherein the plurality of second key-value pairs include the second target data, the key in any second key-value pair includes any pin and any cycle, and the value in any second key-value pair includes sampling waveform data corresponding to any pin in any cycle;

[0125] The second hash map generation submodule is used to map the multiple second key-value pairs into the first hash map to merge the first target data and the second target data to obtain the second hash map, wherein the second hash map includes multiple target key-value pairs, the target key in any target key-value pair includes any pin and any cycle, and the target value in any target key-value pair includes expected waveform data and sampled waveform data corresponding to any pin in any cycle.

[0126] In some optional implementations, the chip test data display device further includes:

[0127] A vector data acquisition module, used to acquire third target data from the parsed data corresponding to the test vector, wherein the third target data includes at least one of the following: a file version of the test vector, pin information, pin combination information, timing information, microinstruction information, and a timing set number;

[0128] The linked list storage module is used to store the third target data in a linked list data structure.

[0129] In some optional embodiments, the data display instruction includes a target key to be retrieved;

[0130] The display module 340 includes:

[0131] The first data acquisition submodule is used to acquire the target expected waveform data and the target sampled waveform data in the second hash map based on the target key to be retrieved.

[0132] In some optional implementations, the display module 340 further includes:

[0133] A second data acquisition submodule is used to acquire refresh information of the visual interaction interface, wherein the refresh information includes pins and cycles displayed on the visual interaction interface;

[0134] The display submodule is used to obtain the display expected waveform data and the display sampled waveform data corresponding to the displayed pin and period from the target expected waveform data and the target sampled waveform data, and to display the display expected waveform data and the display sampled waveform data on the visual interactive interface.

[0135] The chip test data display device of the embodiment of the present application corresponds to the embodiment of the chip test data display method of the present application mentioned above, and the relevant contents can be referenced to each other and will not be repeated here.

[0136] The beneficial technical effects corresponding to the exemplary embodiment of the chip test data display device of the embodiment of the present application can be found in the corresponding beneficial technical effects of the above-mentioned corresponding exemplary method part, which will not be repeated here.

[0137] In addition, an embodiment of the present application further provides an electronic device, including:

[0138] Memory for storing computer programs;

[0139] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip test data display method described in any of the above embodiments of the present application is implemented.

[0140] Fig.10 This is a schematic diagram of the structure of an application embodiment of the electronic device of the present application. Fig.10 The electronic device according to the embodiment of the present application is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signal from them.

[0141] like Fig.10 As shown, the electronic device includes one or more processors and memory.

[0142] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0143] The memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the chip test data display method of each embodiment of the present application described above and / or other desired functions.

[0144] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0145] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0146] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0147] Of course, to simplify, Fig.10 Only some of the components in the electronic device related to the present application are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, the electronic device may further include any other appropriate components according to specific application conditions.

[0148] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the chip test data display method according to various embodiments of the present application described in the above part of this specification.

[0149] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages, such as Java, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0150] In addition, an embodiment of the present application may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the chip test data display method according to various embodiments of the present application described in the above part of this specification.

[0151] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0152] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0153] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0154] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0155] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0156] The method and apparatus of the present application may be implemented in many ways. For example, the method and apparatus of the present application may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present application are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present application may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present application. Therefore, the present application also covers a recording medium storing a program for executing the method according to the present application.

[0157] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0158] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0159] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip test data display method, characterized in that: Applied to chip testing equipment, the method comprises: Acquire first target data and second target data from the test vector and the sampled data respectively, wherein the first target data includes a plurality of cycles and expected waveform data of each pin in each cycle, and the second target data includes a plurality of cycles and sampled waveform data of each pin in each cycle; Generate a first hash map corresponding to the first target data, where the first hash map includes the first target data; storing the second target data in the first hash map to merge the first target data and the second target data to obtain a second hash map, wherein the second hash map includes the first target data and the second target data; In response to receiving the data display instruction, the target expected waveform data and the target sampled waveform data corresponding to the data display instruction are obtained from the second hash map, and the target expected waveform data and the target sampled waveform data are displayed on a visual interactive interface.

2. The method according to claim 1, characterized in that: Obtaining first target data from a test vector includes: Parsing the test vector to obtain parsed data corresponding to the test vector; The first target data is acquired from the parsed data.

3. The method according to claim 1 or 2, characterized in that: The generating a first hash map corresponding to the first target data includes: Based on the first target data, determine a plurality of first key-value pairs, wherein the plurality of first key-value pairs include the first target data, a key in any first key-value pair includes any pin and any cycle, and a value in any first key-value pair includes expected waveform data corresponding to any pin in any cycle; The first hash map is generated based on the plurality of first key-value pairs, the first hash map including the plurality of first key-value pairs.

4. The method according to claim 3, characterized in that The first hash map includes an array, a linked list and a red-black tree; The generating the first hash map based on the plurality of first key-value pairs comprises: The multiple first key-value pairs are stored in the array, the linked list and the red-black tree, and when the total amount of data in the linked list reaches a preset quantity threshold, the first key-value pairs stored in the linked list are added to the red-black tree for storage.

5. The method according to claim 4, characterized in that Storing the second target data in the first hash map to merge the first target data and the second target data includes: Based on the second target data, determine a plurality of second key-value pairs, wherein the plurality of second key-value pairs include the second target data, a key in any second key-value pair includes any pin and any cycle, and a value in any second key-value pair includes sampling waveform data corresponding to any pin in any cycle; The multiple second key-value pairs are mapped into the first hash map to fuse the first target data and the second target data to obtain the second hash map, wherein the second hash map includes multiple target key-value pairs, the target key in any target key-value pair includes any pin and any cycle, and the target value in any target key-value pair includes the expected waveform data and the sampled waveform data corresponding to any pin in the any cycle.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: Acquire third target data from the parsed data corresponding to the test vector, wherein the third target data includes at least one of the following: a file version of the test vector, pin information, pin combination information, timing information, microinstruction information, and a timing set number; The third target data is stored in a linked list data structure.

7. The method according to any one of claims 1 to 6, characterized in that: The data display instruction includes a target key to be retrieved; The acquiring the target expected waveform data and the target sampled waveform data corresponding to the data display instruction from the second hash map includes: Based on the target key to be retrieved, the target expected waveform data and the target sampled waveform data are obtained in the second hash map.

8. The method according to claim 7, characterized in that The displaying of the target expected waveform data and the target sampled waveform data on the visual interactive interface includes: Acquire refresh information of the visual interaction interface, wherein the refresh information includes pins and cycles displayed on the visual interaction interface; Among the target expected waveform data and the target sampled waveform data, the expected display waveform data and the sampled display waveform data corresponding to the displayed pin and period are obtained, and the expected display waveform data and the sampled display waveform data are displayed on the visual interactive interface.

9. A chip test data display device, characterized in that: Applied to chip testing equipment, the device comprises: A waveform data acquisition module, used to acquire first target data and second target data from the test vector and the sampled data respectively, wherein the first target data includes a plurality of cycles and expected waveform data of each pin in each cycle, and the second target data includes a plurality of cycles and sampled waveform data of each pin in each cycle; A first hash map generating module, configured to generate a first hash map corresponding to the first target data, wherein the first hash map includes the first target data; A second hash map generating module, configured to store the second target data in the first hash map, so as to merge the first target data and the second target data to obtain a second hash map, wherein the second hash map includes the first target data and the second target data; A display module is used to, in response to receiving a data display instruction, obtain the target expected waveform data and the target sampled waveform data corresponding to the data display instruction from the second hash map, and display the target expected waveform data and the target sampled waveform data on a visual interactive interface.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program stored in the memory, and when the computer program is executed, the chip test data display method described in any one of claims 1 to 8 is implemented.

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