PUF (Physical Unclonable Function) code generation device and generation method

Abstract

The invention relates to a PUF (Physical Unclonable Function) code generation device and a PUF code generation method. The device comprises N PUF cores which are arranged in parallel, each PUF core is used for generating a PUF code of 1Bit, and the N PUF cores generate a PUF code of N Bits in total; each PUF core comprises a monostable feedback module, an enhanced verification module, a digital module and a critical controllable module; the generation method comprises the following steps: the monostable feedback module is used for generating a voltage value T of a PUF code source of 1Bit of the PUF core; the enhanced verification module is used for driving the voltage value T step by step to obtain an output voltage Y; the digitization module is used for digitizing the output voltage Y and outputting a PUF code serving as 1Bit of the PUF core; the critical controllable module is used for performing stability marking on the PUF code of 1Bit output by the PUF core; and when the output voltage Y is out of a set critical voltage range, marking the PUF code of 1Bit as a stable Bit bit, and otherwise, marking the PUF code of 1Bit as an unstable Bit bit. The PUF architecture provided by the invention has good uniqueness and stability at the same time, and the stability can be flexibly adjusted.

Description

Technical Field

[0001] The present invention relates to the technical field of information security, and in particular to a PUF code generating device and a generating method. Background Art

[0002] With the rapid development of technologies such as the Internet of Things, big data, and artificial intelligence, information security has become a key issue that must be addressed and solved in the current era. Physically Unclonable Functions (PUF), also known as "physical fingerprints", are a new type of security foundation technology that can be used in security scenarios such as key generation, authorization, and authentication. They have been widely concerned in the field of information security for more than 20 years since they were proposed.

[0003] In the process of PUF design and application, the focus is on the two indicators of "stability" and "uniqueness". Among them, "stability" refers to the similarity of the response of the same PUF chip to the same stimulus at different times and spaces, which is often quantified by the intra-chip Hamming distance. The quality of this indicator mainly depends on the stability of the PUF chip to changes in environmental conditions such as temperature and voltage; "uniqueness" refers to the difference in the response of different PUF chips to the same stimulus at the same time and space, which is often quantified by the inter-chip Hamming distance. The quality of this indicator mainly depends on the sensitivity of the PUF chip to process changes.

[0004] At present, there are many PUF circuit structures at home and abroad. According to the different types of units, they can be divided into two categories: one is based on delay units, such as thyristor PUF and double stack PUF. Thyristor PUF has good stability because it is insensitive to voltage changes, but poor uniqueness, and double stack PUF has good uniqueness because it is more sensitive to process changes, but poor stability; the other is based on voltage divider units, such as power line grid PUF and SRAM PUF. Power line grid PUF has good stability because its resistance ratio remains basically unchanged with temperature changes, but poor uniqueness; SRAM PUF has good uniqueness because it is more sensitive to process changes, but poor stability. Therefore, it is difficult for traditional PUF circuits to have good stability and uniqueness at the same time.

[0005] In order to solve this problem, there are currently solutions that enhance stability based on PUF circuits with better uniqueness. For example, PARAL et al. proposed a pattern matching technology to correct erroneous PUF response sequences, but it is necessary to implement complex error correction code decoding logic; VIVEKRAJA et al. proposed a method to monitor the operating temperature of the chip, and according to the feedback of different temperature information, the PUF circuit works at different voltages to improve the stability of the PUF circuit relative to temperature changes, but it is ineffective for voltage changes. Therefore, the solution to make the traditional PUF circuit have both good stability and uniqueness is highly complex, and the stability improvement effect is limited.

[0006] Based on the above analysis, it is urgent to design a PUF architecture that has both good stability and uniqueness. Summary of the invention

[0007] The present invention aims to provide a PUF code generation device and generation method, so that the PUF architecture has good uniqueness and stability. At the same time, a critical controllable circuit is proposed to achieve adjustable stability as needed.

[0008] The present invention discloses a PUF code generating device, comprising: N PUF cores arranged in parallel; each PUF core is used to generate a 1-bit PUF code; the N PUF cores generate a total of N-bit PUF codes;

[0009] Each PUF core includes: a monostable feedback module, an enhanced verification module, a digital module and a critical controllable module; among them,

[0010] The monostable feedback module is used to generate the voltage value T of the 1-bit PUF code source of the PUF core; the voltage value T in each PUF core is distributed in a nonlinear pattern;

[0011] Strengthen the verification module, used to drive the voltage value T step by step, and output the voltage Y;

[0012] The digitization module is used to digitize the output voltage Y and output the 1-bit PUF code of the PUF core;

[0013] The critical controllable module is used to mark the stability of the 1-bit PUF code output by the PUF core; when it is judged that the output voltage Y is within the set critical voltage range, the 1-bit PUF code is marked as an unstable bit, otherwise it is marked as a stable bit.

[0014] Further, the monostable feedback module includes a bit unit circuit and a double-open single-control switch;

[0015] The bit unit circuit is used to achieve voltage inversion, and the voltage at the input end is inverted and then output from the output end;

[0016] The second connection terminal of the first switch of the double-open single-control switch S and the first connection terminal of the second switch are respectively connected to the input end and the output end of the bit unit circuit; the first connection terminal of the first switch of the double-open single-control switch S is connected to the second connection terminal of the second switch, and the connection node serves as the output end of the monostable feedback module.

[0017] Further, the bit unit circuit includes: an inverter circuit INV, a first auxiliary regulation circuit and a second auxiliary regulation circuit;

[0018] The inverter circuit INV includes a voltage input terminal, a voltage output terminal, a node connected to the first auxiliary regulation circuit, and a node connected to the second auxiliary regulation circuit;

[0019] A first auxiliary regulating circuit is connected between the node of the inverter circuit connected to the first auxiliary regulating circuit and the power supply VDD; a second auxiliary regulating circuit is connected between the node connected to the second auxiliary regulating circuit and the ground GND;

[0020] The input voltage Vin connected to the voltage input terminal is inverted by the inverter circuit INV and then outputs a voltage Vout from the voltage output terminal;

[0021] The first auxiliary regulating circuit and the second auxiliary regulating circuit are used to limit current and divide voltage of the bit unit circuit.

[0022] Furthermore, the first auxiliary regulating circuit and the second auxiliary regulating circuit are electronic devices or circuits including resistors, MOS diodes, etc. with current limiting and voltage dividing functions, and are used for current limiting and voltage dividing of the bit unit circuit.

[0023] Furthermore, the enhanced verification module includes a multi-stage cascaded bit unit circuit; the input end of the first stage bit unit circuit of the cascade is connected to the output end T of the monostable feedback module, and the output end of the last stage bit unit of the cascade outputs a voltage Y;

[0024] Each level of bit unit circuit can be used as a single-ended comparator to compare its input voltage with its own flip voltage V trip For comparison; the cascaded bit unit circuit gradually amplifies its input voltage relative to its own flip voltage V trip The final output voltage is Y close to VDD or GND.

[0025] Furthermore, the digitization module circuit includes a Buf module; the input end of the Buf module is connected to the output end Y of the enhanced verification module, and the output end outputs a 1-bit PUF code OUT;

[0026] When the voltage value of the output voltage Y is close to VDD, the Buf module outputs "1";

[0027] When the voltage value of the output voltage Y is close to GND, the Buf module outputs "0".

[0028] Furthermore, the critical controllable module includes M critical submodule circuits, and each critical submodule circuit corresponds to a critical voltage range;

[0029] By controlling the gating of different critical ranges, the output voltage Y is connected to the input end of a selected critical sub-module circuit, and the critical sub-module determines whether the output voltage Y is within the critical voltage range; if so, the Tag of the output end of the critical sub-module of this path is 1, and the 1-bit PUF code output after the output voltage Y is digitized is marked as an unstable bit; otherwise, the Tag of the output end of the critical sub-module of this path is 0, and the PUF code is marked as a stable bit.

[0030] Furthermore, the i-th critical submodule circuit in the M critical submodule circuits includes a single-open single-control switch S i 、Inverter NOT i,1 、Inverter NOT i,2 AND two-input XOR gate i ;

[0031] Among them, single-open single-control switch S i The first switch terminal is connected to the output voltage Y, and the second switch terminal is connected to the inverter NOT i,1 and inverter NOT i,2 The input terminal of the inverter NOT i,1 and inverter NOT i,2 The output of the two-input XOR gate i The two input terminals of the two-input XOR gate are connected; i The output end of is used as the output end of the i-th critical sub-module circuit.

[0032] Furthermore, in the critical submodule circuit of the i-th path, an inverter NOT is set i,1 、Inverter NOT i,2 The critical voltage range is set by the flip voltage;

[0033] Set the inverter NOT i,1 The turn-on voltage of the PMOS tube is greater than the turn-on voltage of the NMOS tube, and the flip voltage is less than VDD / 2. i,trip_l , which is taken as the lower limit of the critical voltage range of the i-th critical submodule;

[0034] Set the inverter NOT i,2The turn-on voltage of the PMOS tube is lower than the turn-on voltage of the NMOS tube, and the flip voltage V is greater than VDD / 2. i,trip_h , which is used as the upper limit of the critical voltage range of the i-th critical submodule.

[0035] The present invention also discloses a PUF code generation method using the PUF code generation device as described above, comprising:

[0036] Step S1, initializing the PUF device and setting PUF working conditions including the power supply voltage VDD;

[0037] Step S2: After the power supply is stable, the double-open single-control switch S of the monostable feedback module in the N PUF cores in the PUF device is controlled to be closed; after each PUF core is working, an N-bit PUF code is output;

[0038] Step S3, according to the set critical voltage range, the corresponding critical submodule circuits in the critical controllable modules of the N PUF cores are enabled; the enabled critical submodule circuit in each PUF core performs stability marking on the 1-bit PUF code output by the PUF core; the critical submodule circuit outputs "1" to indicate that the PUF code is unstable, and the critical submodule circuit outputs "0" to indicate that the PUF code is stable;

[0039] Step S4: extract the N-bit PUF code output in step S2 and the N-bit marker code output in step S3.

[0040] The present invention can achieve one of the following beneficial effects:

[0041] The PUF code generation device and generation method disclosed in the present invention; the monostable feedback loop outputs of different PUF cores are monostable states concentrated near VDD / 2; these monostable outputs are used as PUF code sources to ensure that the architecture PUF has good process sensitivity, and at the same time, can resist the influence of environmental factors such as temperature and power supply voltage, so that the PUF architecture has good uniqueness and stability. Due to the influence of process deviation, the bit unit circuits in the monostable feedback loops of different PUF cores all work in a metastable state with nonlinear rules, so that the PUF architecture has anti-attack capabilities.

[0042] The N-bit PUF code is marked through critical sub-modules with different critical voltage ranges contained in the critical controllable module circuit; when the voltage range of the critical sub-module is larger, more unstable bits can be marked, the closer the on-chip Hamming distance is to 0%, and the higher the PUF stability is, thereby achieving flexible adjustment of the "stability" in the chip application stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0044] Figure 1 A schematic diagram showing the connection components of a PUF code generating device in an embodiment of the present invention;

[0045] Figure 2 It is a schematic diagram of the connection of the monostable feedback module in the embodiment of the present invention;

[0046] Figure 3 It is a schematic diagram of the connection of the bit unit circuit in the monostable feedback module in the embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of a specific bit unit circuit in an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the connection of the enhanced verification module in an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of the connection of the digital module circuit in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the connection of critical controllable modules in an embodiment of the present invention;

[0051] Figure 8 Schematic diagram of a specific critical controllable module circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0053] An embodiment of the present invention discloses a PUF code generating device, such as Figure 1 As shown, including:

[0054] N PUF cores are arranged in parallel; each PUF core is used to generate a 1-bit PUF code; the N PUF cores generate a total of N-bit PUF codes [OUT_1, ..., OUT_N];

[0055] Each PUF core includes: a monostable feedback module, an enhanced verification module, a digital module and a critical controllable module; among them,

[0056] The monostable feedback module is used to generate the voltage value T of the 1-bit PUF code source of the PUF core; the voltage value T in each PUF core is distributed in a nonlinear pattern;

[0057] Strengthen the verification module, used to drive the voltage value T step by step, and output the voltage Y;

[0058] The digitization module is used to digitize the output voltage Y and output the 1-bit PUF code of the PUF core;

[0059] The critical controllable module is used to mark the stability of the 1-bit PUF code output by the PUF core; when it is judged that the output voltage Y is outside the set critical voltage range, the 1-bit PUF code is marked as a stable bit, otherwise it is marked as an unstable bit.

[0060] The critical controllable modules of N PUF cores output N-bit PUF code tag bits [Tag_1, ..., Tag_N].

[0061] The larger the set critical voltage range is, the more unstable bits that can be marked in the N-bit PUF code are, the closer the on-chip Hamming distance is to 0%, and the higher the stability of the architecture PUF is.

[0062] Specifically, Figure 2 As shown, the monostable feedback module includes a bit unit circuit and a double-open single-control switch;

[0063] The bit unit circuit can realize voltage inversion, and the voltage at the input end is inverted and then output from the output end.

[0064] The second connection terminal of the first switch of the double-open single-control switch S and the first connection terminal of the second switch are respectively connected to the input terminal and the output terminal of the bit unit circuit; the first connection terminal of the first switch of the double-open single-control switch S is connected to the second connection terminal of the second switch, and the connection node serves as the output terminal of the monostable feedback module.

[0065] The bit unit circuit forms a feedback loop through a double-open single-control switch S. After normal operation, the output terminals T of the monostable feedback modules of different PUF cores are monostable concentrated at VDD / 2.

[0066] After the power supply VDD is stable, the first switch and the second switch of the double-open single-control switch S are turned on at the same time, the input end and the output end of the bit unit circuit are connected, and the output end voltage is fed back to the input end to form a monostable state, and the output voltage T; the output voltage T≈VDD / 2.

[0067] Specifically, Figure 3 As shown, the bit unit circuit in the monostable feedback module includes an inverter circuit INV, a first auxiliary regulation circuit and a second auxiliary regulation circuit;

[0068] The inverter circuit INV includes a voltage input terminal, a voltage output terminal, a node connected to the first auxiliary regulation circuit, and a node connected to the second auxiliary regulation circuit.

[0069] The inverter circuit has a first auxiliary regulating circuit connected between a node connected to the first auxiliary regulating circuit and a power supply VDD; and a second auxiliary regulating circuit connected between a node connected to the second auxiliary regulating circuit and a ground GND;

[0070] The input voltage Vin connected to the voltage input terminal is inverted by the inverter circuit INV and then outputs a voltage Vout from the voltage output terminal;

[0071] The first auxiliary regulating circuit and the second auxiliary regulating circuit are used to limit current and divide voltage of the bit unit circuit.

[0072] After the power supply is stable, the first switch and the second switch of the double-open single-control switch S are turned on at the same time, the input end and the output end of the bit unit circuit are connected, and under the regulation of the first auxiliary regulation circuit and the second auxiliary regulation circuit, the PMOS tube and the NMOS tube in the inverter circuit both work in the subthreshold region; the output voltage T≈VDD / 2.

[0073] At the same time, the first auxiliary regulation circuit and the second auxiliary regulation circuit have current limiting and voltage dividing functions, so that the PUF core of the architecture has the advantages of low power consumption and low leakage.

[0074] In actual design, the first auxiliary regulating circuit and the second auxiliary regulating circuit can be implemented by electronic devices or circuits having the above functions, such as resistors, MOS diodes, etc.

[0075] Specifically, Figure 4 As shown, an example of a bit unit circuit provided in this embodiment includes diodes D1, D2, a PMOS transistor MP1 and an NMOS transistor MN1;

[0076] Among them, the voltage input terminal VIN is connected to the gates of the PMOS tube MP1 and the NMOS tube MN1 respectively; the drain of the PMOS tube MP1 and the drain of the NMOS tube MN1 are connected to serve as the voltage output terminal VOUT; the power supply VDD is connected to the source of the PMOS tube MP1 through the anode and cathode of the diode D1; the source of the NMOS tube MN1 is connected to the GND ground through the anode and cathode of the diode D2.

[0077] When a high voltage is input to the voltage input terminal VIN to turn off the PMOS tube MP1 and turn on the NMOS tube MN1, the input high voltage is transferred to GND through the turned-on diode D2, so that the output of the output terminal VOUT is a low voltage equal to the sum of the conduction voltage drops of the diode D2 and the NMOS tube MN1, which is approximately equal to GND.

[0078] When the low voltage PMOS tube MP1 is turned on at the voltage input terminal VIN and the NMOS tube MN1 is turned off, the power supply VDD passes through the turned-on diode D1 and the turned-on PMOS tube MP1, so that the output of the output terminal VOUT is a high voltage obtained by subtracting the voltage drop of the turned-on diode D1 and the PMOS tube MP1 from the power supply VDD, which is approximately equal to the power supply VDD.

[0079] When the input terminal VIN and the output terminal VOUT are connected, the output voltage of the output terminal VOUT is approximately VDD / 2.

[0080] Due to the influence of process deviation, the output of the bit unit circuit in each PUF core is a metastable state concentrated near VDD / 2 with a nonlinear pattern, making the PUF architecture resistant to attacks.

[0081] Specifically, Figure 5 As shown, the enhanced verification module includes a multi-stage cascaded bit unit circuit; the input end of the first stage bit unit circuit of the cascade is connected to the output end T of the monostable feedback module, and the output end of the last stage bit unit of the cascade outputs a voltage Y;

[0082] Each level of bit unit circuit can be used as a single-ended comparator to compare its input voltage with its own flip voltage V trip For comparison; the cascaded bit unit circuit gradually amplifies its input voltage relative to its own flip voltage V trip The final output voltage Y is close to VDD or GND.

[0083] In a specific solution of this embodiment, the enhanced verification module includes at least 5 levels of bit unit circuits, so that the voltage value of the output voltage Y of the enhanced verification module of almost all PUF cores meets: near VDD or GND, and the proportion of Y values ​​of different PUF cores distributed near VDD or GND is close to 50%.

[0084] Specifically, Figure 6 As shown, the digitization module circuit includes a Buf module; the input end of the Buf module is connected to the output end Y of the enhanced verification module, and the output end outputs a 1-bit PUF code OUT;

[0085] When the voltage value of the output voltage Y is close to VDD, the Buf module outputs "1";

[0086] When the voltage value of the output voltage Y is close to GND, the Buf module outputs "0".

[0087] Specifically, the critical controllable module can mark the stability of the 1-bit PUF code output by the PUF core by setting a critical voltage range;

[0088] In a more preferred solution, the critical controllable module can set multiple critical voltage ranges, select one of the critical voltage ranges by gating, and mark the stability of the 1-bit PUF code output by the PUF core; the stability of the architecture PUF can be flexibly adjusted by selecting the critical voltage range.

[0089] Specifically, Figure 7 As shown, the critical controllable module includes M critical submodule circuits, and each critical submodule circuit corresponds to a critical voltage range;

[0090] By controlling the selection of different critical ranges, the output voltage Y is connected to the input end of a selected critical sub-module circuit. The critical sub-module determines whether the output voltage Y is within the critical voltage range. If so, the Tag of the output end of the critical sub-module of this path is 1. At this time, the 1-bit PUF code output after the output voltage Y is digitized is marked as an unstable bit; otherwise, the Tag of the output end of the critical sub-module of this path is 0, and the PUF code is marked as a stable bit.

[0091] More specific critical controllable modules such as Figure 8 As shown, the i-th critical submodule circuit in the M-way critical submodule circuit includes a single-open single-control switch S i 、Inverter NOT i,1 、Inverter NOT i,2 AND two-input XOR gate i ;

[0092] Among them, single-open single-control switch S i The first switch terminal is connected to the output voltage Y, and the second switch terminal is connected to the inverter NOT i,1 and inverter NOT i,2 The input terminal of the inverter NOT i,1 and inverter NOT i,2 The output of the two-input XOR gate i The two input terminals of the two-input XOR gate are connected; i The output end of is used as the output end of the i-th critical sub-module circuit.

[0093] In the critical submodule circuit of the i-th path, by setting the inverter NOT i,1 、Inverter NOT i,2 The critical voltage range is set by the flip voltage;

[0094] Set the inverter NOT i,1 The turn-on voltage of the PMOS tube is greater than the turn-on voltage of the NMOS tube, and the flip voltage is less than VDD / 2.i,trip_l , which is taken as the lower limit of the critical voltage range of the i-th critical submodule.

[0095] Set the inverter NOT i,2 The turn-on voltage of the PMOS tube is lower than the turn-on voltage of the NMOS tube, and the flip voltage V is greater than VDD / 2. i,trip_h , which is used as the upper limit of the critical voltage range of the i-th critical submodule.

[0096] When the output voltage Y of the enhanced verification module is less than V i,,trip_l , or greater than V i,trip_h When , the critical submodule Tag outputs 0; the 1-bit PUF code output after the output voltage Y is digitized is marked as a stable bit;

[0097] When the output voltage Y of the enhanced verification module is at V trip_l -V trip_h When the critical submodule Tag outputs 1, the 1-bit PUF code output after the output voltage Y is digitized is marked as an unstable bit;

[0098] The critical voltage range V of each circuit in the critical submodule circuit of M circuits in the critical controllable module is trip_l -V trip_h Set to different voltage ranges, and mark the N-bit PUF code by selecting the critical sub-module circuit of the corresponding branch to determine the PUF stability of the PUF core in different voltage ranges.

[0099] In the preferred solution, M is set to 8, and an 8-way critical submodule circuit is used to judge the stability of the PUF. The larger the voltage range of the critical submodule, the more unstable bits can be marked, the closer the on-chip Hamming distance is to 0%, and the higher the PUF stability, thereby achieving flexible adjustment of the PUF "stability".

[0100] This embodiment also discloses a PUF generation method using the PUF code generation device in the above embodiment; specifically, it includes the following steps:

[0101] Step S1, initializing the PUF device and setting PUF working conditions including the power supply voltage VDD;

[0102] Step S2: After the power supply is stable, the double-open single-control switch S of the monostable feedback module in the N PUF cores in the PUF device is controlled to be closed; after each PUF core is working, an N-bit PUF code is output;

[0103] Step S3, according to the set critical voltage range, the corresponding critical submodule circuits in the critical controllable modules of the N PUF cores are selected; the selected critical submodule circuit in each PUF core marks the stability of the 1-bit PUF code output by the PUF core; the critical submodule circuit outputs "1" to indicate that the PUF code is unstable, and the critical submodule circuit outputs "0" to indicate that the PUF code is stable;

[0104] Step S4: extract the N-bit PUF code output in step S2 and the N-bit marker code output in step S3.

[0105] In summary, the PUF code generation device and generation method of this embodiment; the outputs of the monostable feedback loops of different PUF cores are all monostable states concentrated near VDD / 2; these monostable outputs, as the source of PUF codes, can ensure that the architecture PUF has good process sensitivity, and at the same time, can resist the influence of environmental factors such as temperature and power supply voltage, so that the architecture PUF has good uniqueness and stability. Due to the influence of process deviation, the bit unit circuits in the monostable feedback loops of different PUF cores all work in a metastable state with nonlinear rules, which makes the architecture PUF have anti-attack capabilities.

[0106] The N-bit PUF code is marked through critical sub-modules with different critical voltage ranges contained in the critical controllable module circuit; when the voltage range of the critical sub-module is larger, more unstable bits can be marked, the closer the on-chip Hamming distance is to 0%, and the higher the PUF stability is, thereby achieving flexible adjustment of the "stability" in the chip application stage.

[0107] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A PUF code generating device, characterized in that: include: N PUF cores are set in parallel; each PUF core is used to generate a 1-bit PUF code; the N PUF cores generate a total of N-bit PUF codes; Each PUF core includes: a monostable feedback module, an enhanced verification module, a digital module and a critical controllable module; among them, The monostable feedback module is used to generate the voltage value T of the 1-bit PUF code source of the PUF core; the voltage value T in each PUF core is distributed in a nonlinear pattern; Strengthen the verification module, used to drive the voltage value T step by step, and output the voltage Y; The digitization module is used to digitize the output voltage Y and output the 1-bit PUF code of the PUF core; The critical controllable module is used to mark the stability of the 1-bit PUF code output by the PUF core; when it is judged that the output voltage Y is outside the set critical voltage range, the 1-bit PUF code is marked as a stable bit, otherwise it is marked as an unstable bit.

2. The PUF code generating device according to claim 1, characterized in that: The monostable feedback module includes a bit unit circuit and a double-open single-control switch; The bit unit circuit is used to achieve voltage inversion, and the voltage at the input end is inverted and then output from the output end; The second connection terminal of the first switch of the double-open single-control switch S and the first connection terminal of the second switch are respectively connected to the input terminal and the output terminal of the bit unit circuit; the first connection terminal of the first switch of the double-open single-control switch S is connected to the second connection terminal of the second switch, and the connection node serves as the output terminal of the monostable feedback module.

3. The PUF code generating device according to claim 2, characterized in that: The bit unit circuit comprises: an inverter circuit INV, a first auxiliary regulating circuit and a second auxiliary regulating circuit; The inverter circuit INV includes a voltage input terminal, a voltage output terminal, a node connected to the first auxiliary regulation circuit, and a node connected to the second auxiliary regulation circuit; A first auxiliary regulating circuit is connected between the node of the inverter circuit connected to the first auxiliary regulating circuit and the power supply VDD; a second auxiliary regulating circuit is connected between the node connected to the second auxiliary regulating circuit and the ground GND; The input voltage Vin connected to the voltage input terminal is inverted by the inverter circuit INV and then outputs a voltage Vout from the voltage output terminal; The first auxiliary regulating circuit and the second auxiliary regulating circuit are used to limit current and divide voltage of the bit unit circuit.

4. The PUF code generating device according to claim 3, characterized in that: The first auxiliary regulation circuit and the second auxiliary regulation circuit are electronic devices or circuits including resistors, MOS diodes, etc. with current limiting and voltage dividing functions, and are used for current limiting and voltage dividing of the bit unit circuit.

5. The PUF code generating device according to claim 1, characterized in that: The enhanced verification module includes a multi-stage cascaded bit unit circuit; the input end of the first stage bit unit circuit of the cascade is connected to the output end T of the monostable feedback module, and the output end of the last stage bit unit of the cascade outputs a voltage Y; Each level of bit unit circuit can be used as a single-ended comparator to compare its input voltage with its own flip voltage V trip For comparison; the cascaded bit unit circuit gradually amplifies its input voltage relative to its own flip voltage V trip The final output voltage is Y close to VDD or GND.

6. The PUF code generating device according to claim 1, characterized in that: The digitization module circuit includes a Buf module; the input end of the Buf module is connected to the output end Y of the enhanced verification module, and the output end outputs a 1-bit PUF code OUT; When the voltage value of the output voltage Y is close to VDD, the Buf module outputs "1"; When the voltage value of the output voltage Y is close to GND, the Buf module outputs "0".

7. The PUF code generating device according to claim 1, characterized in that: The critical controllable module includes M critical submodule circuits, each critical submodule circuit corresponds to a critical voltage range; By controlling the gating of different critical ranges, the output voltage Y is connected to the input end of a selected critical sub-module circuit, and the critical sub-module determines whether the output voltage Y is within the critical voltage range; if so, the Tag of the output end of the critical sub-module of this path is 1, and the 1-bit PUF code output after the output voltage Y is digitized is marked as an unstable bit; otherwise, the Tag of the output end of the critical sub-module of this path is 0, and the PUF code is marked as a stable bit.

8. The PUF code generating device according to claim 7, characterized in that: The i-th critical submodule circuit in the M critical submodule circuits includes a single-open single-control switch S i 、Inverter NOT i,1 、Inverter NOT i,2 AND two-input XOR gate i ; Among them, single-open single-control switch S i The first switch terminal is connected to the output voltage Y, and the second switch terminal is connected to the inverter NOT i,1 and inverter NOT i,2 The input terminal of the inverter NOT i,1 and inverter NOT i,2 The output of the two-input XOR gate i The two input terminals of the two-input XOR gate are connected; i The output end of is used as the output end of the i-th critical sub-module circuit.

9. The PUF code generating device according to claim 8, characterized in that: In the critical submodule circuit of the i-th path, by setting the inverter NOT i,1 、Inverter NOT i,2 The critical voltage range is set by the flip voltage; Set the inverter NOT i,1 The turn-on voltage of the PMOS tube is greater than the turn-on voltage of the NMOS tube, and the flip voltage is less than VDD / 2. i,trip_l , which is taken as the lower limit of the critical voltage range of the i-th critical submodule; Set the inverter NOT i,2 The turn-on voltage of the PMOS tube is lower than the turn-on voltage of the NMOS tube, and the flip voltage V is greater than VDD / 2. i,trip_h , which is used as the upper limit of the critical voltage range of the i-th critical submodule.

10. A PUF code generation method using the PUF code generation device according to any one of claims 1 to 9, characterized in that: include: Step S1, initializing the PUF device and setting PUF working conditions including the power supply voltage VDD; Step S2: After the power supply is stable, the double-open single-control switch S of the monostable feedback module in the N PUF cores in the PUF device is controlled to be closed; after each PUF core is working, an N-bit PUF code is output; Step S3, according to the set critical voltage range, the corresponding critical submodule circuits in the critical controllable modules of the N PUF cores are enabled; the enabled critical submodule circuit in each PUF core performs stability marking on the 1-bit PUF code output by the PUF core; the critical submodule circuit outputs "1" to indicate that the PUF code is unstable, and the critical submodule circuit outputs "0" to indicate that the PUF code is stable; Step S4: extract the N-bit PUF code output in step S2 and the N-bit marker code output in step S3.

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