Video memory management method, system, chip and electronic device

Abstract

The application discloses a video memory management method and system, a chip and electronic equipment, and belongs to the technical field of storage. The method comprises the following steps: acquiring, by a first logic unit, heat information of a plurality of storage units included in a first chip, wherein the heat information is used for indicating the use condition of the storage units; and compressing, by a second logic unit, data in at least one target storage unit, wherein the target storage unit is determined from the plurality of storage units by a second chip based on the acquired heat information of the plurality of storage units. The first chip is different from the second chip. According to the method, the target storage unit can be determined from the plurality of storage units based on the use condition of the storage units, and the data in the target storage unit can be compressed, so that the storage space occupied by the data in the video memory is reduced, and the available storage capacity of the video memory is effectively expanded.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a video memory management method, system, chip, and electronic device. Background Technology

[0002] Video memory (VRAM) is a crucial resource for GPUs (Graphics Processing Units). In vGPU (Virtual GPU) environments, VRAM resources are often scarce, making their full and efficient utilization extremely important.

[0003] In related technologies, video memory is allocated upon application launch and released as the application terminates. In practice, some applications enter the background after launch. Since these background applications are not actually running, the operating system swaps the data from the background application's video memory to system memory. When the background application returns to the foreground, the data swapped to system memory needs to be reloaded from system memory back into video memory.

[0004] The method described above, which saves video memory space by swapping video memory data from background applications to system memory, involves data copying across PCIe (Peripheral Component Interconnect Express). On one hand, PCIe bandwidth is limited. When a large amount of data needs to be exchanged between video memory and system memory, it may exceed the processing capacity of the PCIe channel, leading to data exchange failures and preventing timely and effective expansion of video memory. On the other hand, data inconsistencies may occur during data transfer between video memory and system memory, resulting in data loss or errors. Summary of the Invention

[0005] This application provides a video memory management method, system, chip, and electronic device. The technical solutions provided by this application include the following aspects.

[0006] According to one aspect of the embodiments of this application, a video memory management method is provided, the method being applied to a first chip, the first chip being configured with a first logic unit and a second logic unit; the method includes:

[0007] The first logic unit obtains the heat information of each of the multiple memory units included in the first chip, and the heat information is used to indicate the usage status of the memory unit;

[0008] The second logic unit compresses data in at least one target storage unit, wherein the target storage unit is determined by the second chip from the plurality of storage units based on the acquired heat information of each of the plurality of storage units;

[0009] The first chip is different from the second chip.

[0010] According to one aspect of the embodiments of this application, a video memory management system is provided, the system comprising: a first chip and a second chip, wherein the first chip is configured with a first logic unit and a second logic unit;

[0011] The first logic unit is used to acquire heat information of each of the multiple memory units included in the first chip, and the heat information is used to indicate the usage status of the memory units;

[0012] The second chip is used to determine at least one target memory cell from the plurality of memory cells based on the heat information of each of the plurality of memory cells;

[0013] The second logic unit is used to compress the data in the target storage unit.

[0014] According to one aspect of the embodiments of this application, a chip is provided, the chip being configured with a first logic unit and a second logic unit;

[0015] The first logic unit is used to acquire heat information of each of the multiple memory units included in the chip, and the heat information is used to indicate the usage status of the memory units;

[0016] The second logic unit is used to compress data in at least one target storage unit in the chip, the target storage unit being determined from the plurality of storage units based on the heat information of each of the plurality of storage units.

[0017] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including the above-described video memory management system.

[0018] According to one aspect of the embodiments of this application, a video memory management method is provided, the method comprising:

[0019] Obtain the heat information of each of the multiple storage units included in the video memory, and the heat information is used to indicate the usage status of the storage units;

[0020] Based on the heat information of each of the plurality of storage units, at least one target storage unit is determined from the plurality of storage units;

[0021] Compress the data in the target storage unit.

[0022] According to one aspect of the embodiments of this application, a video memory management device is provided, the device comprising:

[0023] The acquisition module is used to acquire the heat information of each of the multiple storage units included in the video memory, and the heat information is used to indicate the usage status of the storage units;

[0024] The determining module is used to determine at least one target storage unit from the plurality of storage units based on the heat information of each of the plurality of storage units;

[0025] A compression module is used to compress the data in the target storage unit.

[0026] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described video memory management method.

[0027] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, the computer program being loaded and executed by a processor to implement the above-described video memory management method.

[0028] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, the computer program being loaded and executed by a processor to implement the above-described video memory management method.

[0029] The technical solutions provided in this application have at least the following beneficial effects:

[0030] This method can identify a target memory cell from multiple memory cells based on the usage of each memory cell in the video memory of the first chip, and compress the data in that target memory cell, thereby reducing the storage space occupied by the data in the video memory. This method effectively expands the available storage capacity of the video memory. Furthermore, by directly compressing the data in the video memory to reduce its space usage, it avoids the data exchange process between the video memory and system memory involved in related technologies, thus preventing data exchange failures due to PCIe bandwidth limitations and avoiding data loss or errors during the data exchange process. Attached Figure Description

[0031] Figure 1 This is a flowchart of a possible implementation of the video memory management method provided in this application;

[0032] Figure 2 This is a schematic diagram of a video memory management system including a first chip and a second chip, provided in one possible implementation of this application;

[0033] Figure 3 This is a flowchart of a video memory management method provided in another possible implementation of this application;

[0034] Figure 4 This is a flowchart of a video memory management method provided in another possible implementation of this application;

[0035] Figure 5 This is a flowchart of a video memory management method provided in another possible implementation of this application;

[0036] Figure 6 This is a block diagram of a video memory management device provided in one possible implementation of this application;

[0037] Figure 7 This is a structural block diagram of an electronic device provided in one possible implementation of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0039] Before introducing and explaining the technical solution of this application, some concepts involved in this application will be defined and explained.

[0040] A GPU is a processor specifically designed for processing and rendering graphics and images. It possesses highly parallel computing capabilities, enabling it to process large amounts of data simultaneously, and is therefore widely used in fields such as graphics rendering, game development, video processing, and deep learning.

[0041] Video memory (VRAM) refers to the memory used to store data that the GPU needs to process. During graphics processing and rendering, VRAM can be used to store graphics data (such as textures, vertex data, frame buffers, render targets, etc.). The GPU can directly access the data in VRAM to perform tasks such as image processing and computation. The size and speed of VRAM directly affect the amount of data the GPU can process and its processing speed. When VRAM space is insufficient, the data required to perform a task cannot be stored, causing the GPU to be unable to perform the corresponding task, resulting in computational failure or performance degradation. Therefore, expanding the available VRAM space is crucial. The technical solution proposed in this application compresses infrequently used data in VRAM to reduce the storage space occupied by data in VRAM, thereby expanding the available VRAM space.

[0042] Please refer to Figure 1The diagram illustrates a flowchart of a memory management method provided in one possible implementation of this application. The method is applied to a first chip, which is configured with a first logic unit and a second logic unit. The method may include at least one of the following steps 110-120.

[0043] Step 110: Obtain the heat information of each of the multiple memory cells included in the first chip through the first logic unit. The heat information is used to indicate the usage status of the memory cells.

[0044] Figure 2 This is a schematic diagram of a video memory management system including a first chip and a second chip, provided in one possible implementation of this application.

[0045] In some embodiments, this application uses a GPU chip as the first chip for illustrative purposes. The first chip may also be other types of processor chips, and this application does not limit this to any particular type.

[0046] A storage unit refers to the basic unit used for storing data in video memory. For example, a storage unit in video memory can be a video memory page. A video memory page can be divided into fixed sizes; for example, the size of a video memory page can be 4KB (KiloByte), 8KB, 16KB, etc., depending on the GPU design, and this application does not limit this. For example, a storage unit in video memory can also be a union page, which refers to a collection of multiple video memory pages; for example, two consecutive video memory pages can be considered as a union page. The granularity of the above-mentioned storage unit divisions in video memory is merely exemplary, and this application does not limit this.

[0047] Storage unit usage information indicates the frequency of storage unit usage and may include the number of times the storage unit is used. Storage unit usage information may also include the time of the most recent access to the storage unit, the duration of use within a recent period, etc., but this application does not limit this. Popularity information is a quantitative representation of storage unit usage, which can be expressed numerically.

[0048] In some embodiments, when a process calls the first chip 20, the first logic unit 21 adds marking information to the page table of the first chip 20. The page table is used to record the mapping relationship between the virtual address and physical address of the memory unit, and the marking information is used to indicate the memory unit used in the first chip 20.

[0049] In some embodiments, in the page table of the first chip 20, such as the page table of the GPU, when a memory unit is used, it can be marked. Unused memory units are not marked. The usage count of a memory unit is determined based on the marking. Specifically, each time a process needs to use the GPU's video memory, the used memory unit is marked. The driver can read the marking from the page table and update the usage count of each memory unit in the GPU, that is, increment the usage count of the marked memory unit by one. Exemplarily, the marking can be bit 0, bit 1, or other markings; this application does not limit this. In some embodiments, the driver can read the marking information in the GPU page table at fixed time intervals to update the usage count of the memory unit, such as every 5 minutes; this application does not limit this.

[0050] The aforementioned driver refers to the driver for the first chip (such as a GPU driver). This GPU driver manages GPU resource allocation, task scheduling, and data transfer, thereby enabling efficient GPU access and utilization. Managing GPU resource allocation includes allocating and optimizing resources such as GPU memory and computing cores. Task scheduling involves instructing the GPU on the order and timing of various tasks (such as graphics rendering or computational tasks). The driver determines which tasks are prioritized and how computation time is allocated to ensure timely task completion and maintain system responsiveness. Data transfer involves data transfer between the CPU and GPU, and between different components within the GPU. More information about drivers can be found below. In some embodiments, each memory unit may correspond to a tag, using different identifiers for used and unused memory units to distinguish their usage. For example, as shown in Table 1 below, bit 1 can indicate that a memory unit is used, while bit 0 or an empty bit indicates that the memory unit is not used. Alternatively, bit 0 can indicate that a memory unit is used, while bit 1 or an empty bit indicates that the memory unit is not used. If bit 1 indicates that a storage unit is in use, and bit 0 indicates that a storage unit is not in use, then based on the tagging information, the usage count of storage unit 1 is incremented by 1, the usage count of storage unit 2 does not need to be updated, and the usage count of storage unit 3 also does not need to be updated. In this example, the tagging method is merely exemplary, and this application does not limit the specific implementation method of tagging.

[0051] Table 1

[0052] storage unit Virtual address physical address Tagging information Storage Unit 1 Virtual address 1 Physical address A 1 Storage Unit 2 Virtual address 2 Physical address A 0 Storage unit 3 Virtual address 3 Physical address B 0

[0053] In some embodiments, in the page table of the first chip, each memory cell may correspond to a fixed number of bits of tag information. When the memory cell is used, the value of the tag information can be incremented by 1; the value of the tag information is determined as the number of times the memory cell is used. This application does not limit the method for determining the number of times the memory cell is used based on the tag information.

[0054] The above method marks the used memory units, making it easier for subsequent drivers to identify the usage of each memory unit based on the marks.

[0055] In some embodiments, the usage frequency of each storage unit can be used to determine its own "heat information." That is, the usage frequency of each storage unit is used as the numerical value of the heat information. The usage frequency of a storage unit refers to the total number of read and write operations performed on the storage unit within a certain period, representing the activity level or access frequency of that storage unit in the system. It can be understood that the more times a storage unit is used, the higher the heat information value, indicating that the storage unit is more active, meaning that the first chip 20 (e.g., GPU) will access the data in that storage unit more frequently during operation; conversely, the fewer times a storage unit is used, the lower the heat information value, indicating that the storage unit is less active, meaning that the first chip 20 (e.g., GPU) will access the data in that storage unit less frequently during operation. By obtaining the heat information of the storage units, the above method can distinguish between frequently used and less frequently used storage units, facilitating subsequent compression of data in less frequently used storage units.

[0056] In some embodiments, the heat information of a storage cell includes the number of times the storage cell has been used, and the tagging information is used to determine the number of times each of the multiple storage cells has been used.

[0057] In some embodiments, the specific implementation of determining the popularity information of a storage unit may include the following steps: the first logic unit 21 reads the tag information from the page table; based on the tag information, determines the usage count of each of the multiple storage units; based on the usage count of each of the multiple storage units, determines the popularity information of each of the multiple storage units.

[0058] The above method determines the usage based on the number of times the storage unit is used (such as read operations and write operations) to distinguish between storage units that are used more frequently and those that are used less frequently, so that the data in the storage units that are used less frequently can be compressed later.

[0059] In some embodiments, the specific method for determining the popularity information may also be based on other usage information of the storage unit. For example, when the usage information of the storage unit represents the most recent usage time, the popularity information may be a specific timestamp. For example, when the usage information of the storage unit represents the usage duration, the popularity information may be several seconds or several minutes. This application does not limit this.

[0060] In some embodiments, when a process calls the first chip 20, the tag information already added to the page table of the first chip 20 is cleared by the first logic unit 21.

[0061] In some embodiments, the first logic unit 21 is further configured to clear the added tag information in the page table of the first chip 20 (e.g., GPU) when a process calls the first chip 20 (e.g., GPU). Clearing the added tag information in the page table of the first chip 20 (e.g., GPU) means resetting the tag information, such as resetting it to empty. This method ensures that the tag information in the page table is only used when the current process's memory units are used.

[0062] In some embodiments, the marker information added to the page table of the first chip 20 (such as the GPU) can be cleared during system restart or power failure. Alternatively, the marker information added to the page table of the first chip 20 (such as the GPU) can be cleared at fixed time intervals. This application does not limit this approach.

[0063] The above method resets the marking information when the process calls the first chip 20 (such as the GPU) to ensure that the marking information in the page table only includes the usage of each memory unit of the current process.

[0064] Step 120: Compress data in at least one target storage unit using the second logic unit. The target storage unit is determined by the second chip from multiple storage units based on the acquired heat information of each storage unit. The first chip and the second chip are different.

[0065] In some embodiments, the second chip 24 is a chip including the aforementioned driver. This application uses a CPU chip as an example, but the second chip can also be other types of processor chips, and this application does not limit its application to these types. In some embodiments, the processing logic of the first logic unit 21 and the second logic unit 22 is configured by the driver in the second chip 24. Through the driver in the second chip 24, the system can flexibly configure the processing logic of the first logic unit 21 and the second logic unit 22, such as configuring the first logic unit 21 to add and clear marker information in the page table of the first chip as described above, and configuring the second logic unit 22 to perform data compression in the target storage unit as described in step 120.

[0066] In some embodiments, the heat information of the target storage unit satisfies a first condition, and the process to which the target storage unit belongs does not belong to a first process set; wherein, the first condition includes at least one of the following: the heat information is less than or equal to a first threshold, the heat information is one of the smaller N heat information among the heat information of each of the multiple storage units, where N is a positive integer; the first process set includes at least one pre-defined process.

[0067] In some embodiments, the popularity information may represent the number of times or the duration of use. Popularity information less than or equal to a first threshold may mean that the number of times or the duration of use of the storage unit is lower than a preset standard value (i.e., the first threshold). The first threshold may be set based on the historical usage of the storage units. Specifically, the average number of times or the average duration of use of all storage units can be calculated; storage units with usage values ​​below this average are considered less active, and therefore the first threshold can be set lower than this average. The first threshold can also be set based on the experience of the personnel, and this application does not limit this.

[0068] In some embodiments, the N storage units corresponding to the smallest amounts of "hotness" information among all storage units can be identified as target storage units. Specifically, the storage units can be sorted from largest to smallest based on their "hotness" information, and the storage units with the lowest "hotness" information are identified as target storage units. Alternatively, the storage units can be sorted from smallest to largest based on their "hotness" information, and the storage units with the highest "hotness" information are identified as target storage units. This method can identify the N least active storage units from a pool of storage units.

[0069] In some embodiments, when the popularity information is the most recent usage time, the N storage units with the earliest timestamps can be identified as at least one target storage unit. Specifically, each storage unit can be sorted from earliest to latest based on its most recent access time, and the N storage units with the highest access times can be identified as target storage units. This method can effectively identify storage units that have not been accessed for a relatively long time among multiple storage units.

[0070] In some embodiments, the pre-defined processes may include at least one of the following: system processes and latency-sensitive processes. System processes are processes that run within the operating system and are used to manage system resources, provide basic service functions, and perform specific tasks. System processes typically have high priority and are crucial to the stability and security of the system. For example, system processes may include operating system kernel processes, system call handling processes, system service processes, etc., wherein the operating system kernel process is used for internal kernel task scheduling and management, the system call handling process is used to handle system call requests issued by user-space programs, and the system service process is used for process creation, destruction, and thread management.

[0071] Latency-sensitive processes are those that are highly sensitive to time delays and require rapid response and data processing. For example, latency-sensitive processes may include real-time control processes, such as real-time control and monitoring used in industrial automation. They may also include multimedia processing processes, such as audio / video encoding / decoding processes and media player processes. Furthermore, they may include user interaction processes, such as graphical user interface processes and instant messaging applications, which require rapid response to user actions.

[0072] The above method identifies target storage units by determining those that meet specific conditions regarding both popularity information and the process to which the storage unit belongs. This ensures that the target storage units have low popularity (i.e., infrequently used) and do not belong to any pre-defined processes (i.e., critical processes). This method, on the one hand, identifies less active storage units from a pool of available storage units. On the other hand, it fully considers critical processes in the system, ensuring that pre-defined critical processes (such as system processes or latency-sensitive processes) are not compressed during data compression. In this way, while effectively reducing the amount of video memory occupied by data, it ensures that the normal operation of the system remains unaffected.

[0073] In some embodiments, compressing data in at least one target storage unit by means of the second logic unit 22 includes: compressing data in at least one target storage unit by means of the second logic unit 22 upon receiving a compression instruction sent by the driver.

[0074] In some embodiments, the driver sends a compression command to the second logic unit 22. The second logic unit 22 is configured to compress data in at least one target storage unit in the video memory upon receiving the compression command from the driver.

[0075] A driver provides the necessary software interface and control functions for a hardware device, enabling the operating system and applications to interact correctly with the hardware. In some embodiments, the program code implementing the memory management method flow of a first chip 20 (such as a GPU) can be implemented as a driver, which is executed by a second chip 24 (such as a CPU) of the electronic device to implement the method flow.

[0076] In some embodiments, when the driver detects that the utilization of the first chip 20 (such as a GPU) is less than or equal to a first threshold and the utilization of the video memory is greater than or equal to a second threshold, it may send a compression instruction to the second logic unit 22 after determining the target storage unit through the steps in the GPU video memory management method described above.

[0077] In some embodiments, the compression instruction includes a virtual address of at least one target storage unit, a page table of the first chip 20 (such as a GPU), and a compression algorithm, wherein the compression algorithm is used to instruct how to convert the raw data into compressed data. The second logic unit 22 reads the physical address corresponding to the virtual address of the target storage unit from the page table of the first chip 20 (such as a GPU); thereby accessing the data in the target storage unit based on the physical address; and compressing the data in the target storage unit based on the compression algorithm.

[0078] In the above method, after receiving the compression command sent by the driver, the second logic unit can compress the data in the target storage unit.

[0079] In some embodiments, data in the target storage unit is compressed based on a data compression algorithm. This data compression algorithm can be a lossless compression algorithm. For example, the data compression algorithm may include Huffman coding, arithmetic coding, LZW (Lempel-Ziv-Welch) algorithm, etc., and this application does not limit it to these methods.

[0080] For example, assume that the video memory includes storage unit 1, storage unit 2, and storage unit 3. Storage unit 1 contains 2MB (megabyte) of data, occupying 2MB of video memory. Storage unit 2 contains 3MB of data, and storage unit 3 contains 4MB of data. Before compression, the data in video memory occupies 9MB of storage space. If the target storage unit includes storage unit 3, after compressing the data in storage unit 3, the compressed data occupies 2MB of video memory. After compression, the data in video memory occupies only 7MB of storage space. In this case, by compressing the data in the target storage unit, 2MB of video memory storage space is saved. This saved 2MB of storage space is now free and not occupied by any data. In this situation, the operating system's memory management module can reallocate this free storage space to other programs or processes that require memory.

[0081] In some embodiments, the operating system can track and manage video memory usage, including allocated and free video memory, through a video memory management mechanism. When some storage space is saved by compressing data, the operating system determines the specific address range of the video memory in that portion of storage space so that it can be marked as available and allocated to other programs or processes when needed. Specifically, the operating system can maintain a video memory mapping table or a similar structure, recording the usage status of each region in the video memory, such as which regions have been allocated to which processes and which regions are free. After a video memory compression operation, the operating system updates this mapping table, marking the video memory regions originally occupied by compressed data as unused, and recording the starting address and size of these free regions. For example, in the above example, assuming that storage unit 3 originally occupied a video memory address range from 0x100000 to 0x13FFFF (4MB in total), after compression, the data only occupies 2MB, then the video memory between 0x120000 and 0x13FFFF becomes free. The operating system will mark this address range as available and record it in the free video memory list. When a new video memory request is received, the operating system's video memory management module searches for a suitable address range in the list of free video memory and allocates it to the requesting process.

[0082] In some embodiments, the second logic unit 22 decompresses the data in the storage unit that is in a compressed state upon receiving a decompression instruction sent by the driver.

[0083] In some embodiments, the driver sends a decompression command to the second logic unit 22. The second logic unit 22 is further configured to decompress data in a compressed storage unit upon receiving the decompression command from the driver.

[0084] In some embodiments, when a process calls the first chip 20 (such as a GPU), the driver can send a decompression instruction to the second logic unit 22 when the storage unit associated with the process is in a compressed state.

[0085] In some embodiments, the decompression instruction includes the virtual address of the compressed storage unit, the page table of the first chip 20 (e.g., GPU), and a decompression algorithm, wherein the decompression algorithm is used to instruct how to restore the compressed data to its original format. The second logic unit 22 reads the physical address corresponding to the virtual address of the compressed storage unit from the page table of the first chip 20 (e.g., GPU); thereby accessing the data in the compressed storage unit based on the physical address; and using the decompression algorithm to decompress the data in the compressed storage unit.

[0086] In the above method, after receiving the decompression command sent by the driver, the second logic unit can decompress the data in the storage unit that is in a compressed state.

[0087] In some embodiments, the first chip 20 is further configured with an MMU (Memory Management Unit) 23; the method further includes: obtaining operation instructions sent by the driver through the MMU 23, the operation instructions including the virtual address of the first memory unit to be accessed and the page table of the first chip 20; reading the physical address corresponding to the virtual address of the first memory unit from the page table of the first chip 20 according to the virtual address of the first memory unit through the MMU 23, as the first physical address; and accessing the first memory unit based on the first physical address through the MMU 23. In some embodiments, the processing logic of the MMU 23 is configured by the driver in the second chip 24.

[0088] In some embodiments, when the driver determines that the memory units associated with the first process are in an uncompressed state, the driver may send an operation instruction to the MMU 23.

[0089] The first storage unit refers to the storage unit associated with the first process. In memory management, the first physical address refers to the actual address obtained from the virtual address translation, used to locate and access the first storage unit in physical memory. Accessing the first storage unit means performing read and write operations on the first storage unit based on the first physical address. Specifically, read and write operations can include reading data from physical memory or writing data to the corresponding location in physical memory to complete the operation on the first storage unit.

[0090] In a vGPU environment, virtual addresses refer to the addresses used by a virtual machine or application when accessing resources of the first chip 20 (such as a GPU). These addresses are virtualized video memory addresses. Virtual addresses are allocated and managed by the virtualization hypervisor or operating system. Applications and virtual machines use these virtual addresses to access video memory without needing to know the specific physical video memory location. Physical addresses refer to the actual addresses within the physical video memory of the first chip 20 (such as a GPU).

[0091] In some embodiments, a one-to-one correspondence may exist between storage units and virtual addresses. That is, one storage unit corresponds to one virtual address, and different storage units correspond to different virtual addresses. In some embodiments, a many-to-one correspondence may exist between virtual addresses and physical addresses. That is, multiple virtual addresses may correspond to one physical address. Different virtual addresses may correspond to the same physical address or different physical addresses. For example, as shown in Table 1 above, it illustrates an example table of the page table of a first chip 20 (such as a GPU) provided in an embodiment of this application. Storage unit 1 and virtual address 1 have a one-to-one correspondence, storage unit 2 and virtual address 2 have a one-to-one correspondence, and storage unit 3 and virtual address 3 have a one-to-one correspondence. Among them, storage unit 1, storage unit 2, and storage unit 3 are different storage units, and virtual address 1, virtual address 2, and virtual address 3 are different virtual addresses. Virtual address 1 and virtual address 2 correspond to the same physical address A, and virtual address 3 corresponds to another physical address B.

[0092] The above method, by setting the MMU, can receive the operation instructions of the driver and access the corresponding memory unit based on the received operation instructions, thereby realizing read and write operations.

[0093] The technical solution provided in this application can determine a target storage unit from multiple storage units based on the usage of each storage unit in the first chip, and compress the data in the target storage unit, thereby reducing the storage space occupied by data in the first chip. This method effectively expands the available storage capacity of the first chip, and since it reduces the space occupied by the first chip by directly compressing the data in the first chip, it does not involve the data exchange process between the first chip and system memory as included in related technologies, thus avoiding data exchange failures caused by PCIe bandwidth limitations, and avoiding data loss or errors during the data exchange process.

[0094] Please refer to Figure 3 The diagram illustrates a flowchart of a video memory management method provided in one possible implementation of this application. The execution entity for each step of this method can be an electronic device. The method may include at least one of the following steps 310 to 330.

[0095] Step 310: Obtain the heat information of each of the multiple storage units included in the video memory. The heat information is used to indicate the usage status of the storage units.

[0096] It should be noted that the first chip is described here only as an example of a GPU, and this application does not limit the type of the first chip.

[0097] In some embodiments, the specific implementation of determining the number of times a memory cell is used may include the following steps: reading marking information from the page table of the first chip, the page table being used to record the mapping relationship between the virtual address and physical address of the memory cell, and the marking information being used to indicate the memory cell used in the video memory; and determining the number of times each of the multiple memory cells is used based on the marking information.

[0098] Step 320: Based on the heat information of each of the multiple storage units, determine at least one target storage unit from the multiple storage units.

[0099] In some embodiments, at least one storage cell whose heat information satisfies a first condition is determined as at least one target storage cell. The first condition includes at least one of the following: the heat information is less than or equal to a first threshold, or the heat information is one of the smaller N heat information among the heat information of each of the plurality of storage cells, where N is a positive integer.

[0100] In some embodiments, at least one storage unit whose heat information satisfies a first condition and whose process does not belong to a first process set is determined as at least one target storage unit; wherein, the first condition includes at least one of the following: the heat information is less than or equal to a first threshold, the heat information is one of the smaller N heat information among the heat information of each of the multiple storage units, where N is a positive integer; the first process set includes at least one pre-defined process.

[0101] In some embodiments, this application also provides another method for determining the specific implementation of a target storage unit by combining the process to which the storage unit belongs. In some embodiments, at least one target storage unit is determined from multiple storage units based on the popularity information of each of the multiple storage units and the process to which each of the multiple storage units belongs.

[0102] The process to which a storage unit belongs indicates which process the storage unit is allocated to or used by. In some embodiments, a storage unit may belong to one process or multiple processes. When a storage unit belongs to multiple processes, it is a shared storage unit, allowing multiple processes to access the same data by calling the shared storage unit.

[0103] The method described above determines the target storage unit by combining heat information with the process to which the storage unit belongs. This method fully considers critical processes in the system, ensuring that pre-defined critical processes (such as system processes or latency-sensitive processes) are not compressed during data compression. In this way, while effectively reducing the amount of video memory occupied by data, the normal operation of the system remains unaffected.

[0104] Step 330: Compress the data in the target storage unit.

[0105] In some embodiments, after compressing the data in the target storage unit, the information table is further updated. Specifically, the address information and compression status information of the target storage unit are updated, wherein the information table is used to store the address information and compression status information of multiple storage units, the address information is used to indicate the mapping relationship between the virtual address and physical address of the storage unit, and the compression status information is used to indicate whether the storage unit is in a compressed state.

[0106] In some embodiments, updating the address information of the target memory unit refers to updating the physical address of the target memory unit. In some embodiments, the virtual address of the target memory unit remains unchanged, while the physical address of the target memory unit is updated. The updated physical address may be the same as or different from the physical address before the update, and this application does not limit this. In some embodiments, the updated physical address may be determined based on the operating system's memory management algorithm. Specifically, in a paging-based memory management strategy, the virtual address space is divided into fixed-size pages, and the physical address is also divided into page frames. The operating system maintains the page table of the first chip 20 (such as a GPU) to manage the mapping relationship between virtual pages and physical page frames. When data is compressed, the operating system needs to select a physical page frame for the compressed data. The operating system may execute a memory allocation algorithm (such as first-fit, best-fit, or worst-fit) to select a suitable physical page frame to ensure that memory fragmentation is not caused. When a new physical page frame is allocated to the compressed data, the operating system updates the page table of the first chip 20 (such as a GPU) to record the mapping relationship between the virtual address and the updated physical address, thereby ensuring that the driver can correctly access the data. The method for determining the updated physical address described above can also be based on segmented memory management strategies, etc., and this application does not limit this to such methods.

[0107] In some embodiments, updating the compression status information of a target storage unit means updating the target storage unit from an uncompressed state to a compressed state. Each storage unit can correspond to a fixed number of bits for compression status information, such as using 1 bit to indicate the compression status information of the storage unit. Bit 1 can be used to indicate that the storage unit is in a compressed state, and bit 0 can be used to indicate that the storage unit is not in a compressed state; alternatively, bit 0 can be used to indicate that the storage unit is in a compressed state, and bit 1 can be used to indicate that the storage unit is not in a compressed state.

[0108] For example, as shown in Table 2 below, it illustrates an example information table provided in one embodiment of this application. Assuming the target storage units are storage unit 2 and storage unit 3, the data in storage units 2 and 3 needs to be compressed. The updated physical address can be the same as the physical address before the update. Referring to Tables 1 and 2, for example, for storage unit 2, the updated physical address is still physical address A; the updated physical address can also be different from the physical address before the update. For example, for storage unit 3, the physical address before the update was physical address B, and the updated physical address is physical address A. Assuming bit 1 is used to indicate that the storage unit is in a compressed state, the compression status information of storage units 2 and 3 is updated from bit 0 to bit 1, while the compression status information of storage unit 1 remains bit 0.

[0109] Table 2

[0110] storage unit Virtual address physical address Compression status information Storage Unit 1 Virtual address 1 Physical address A 0 Storage Unit 2 Virtual address 2 Physical address A 1 Storage unit 3 Virtual address 3 Physical address A 1

[0111] In the above method, after the target storage unit is compressed, the address information and compression status information of the target storage unit are updated in a timely manner to make the information more accurate and consistent. This facilitates the easy determination of the compression status information of the compressed unit related to the first process from the information table during subsequent calls to the first process, so as to determine whether the target storage unit needs to be decompressed.

[0112] In some embodiments, the information table stores the address information and compression status information of the storage unit using the hash value of the identification information related to the storage unit as the key. The identification information related to the storage unit includes at least one of the following: the identifier of the process to which the storage unit belongs, and the context identifier of the page table to which the storage unit belongs.

[0113] The identifier of the process to which a storage unit belongs can be a process identifier (PID), used to distinguish different processes. Different storage units may have the same or different process identifiers.

[0114] The context identifier of the page table to which a memory unit belongs is called the page table context identifier, used to distinguish different processes. That is, the context identifier of the page table corresponding to the same process is the same, while the context identifiers of the page tables corresponding to different processes are different. A process can correspond to one page table or multiple page tables. When a process corresponds to a page table, it means that all memory units included in that page table belong to that process. Through the page table context identifier, the operating system can provide each process with an independent virtual memory space, ensuring that they do not interfere with each other.

[0115] For example, as shown in Table 3 below, it illustrates an example table of a hash-based information table provided in one embodiment of this application.

[0116] Table 3

[0117] key Virtual address physical address Compression status information Hash1 Virtual address 1 Physical address A 0 Hash2 Virtual address 2 Physical address A 1 Hash3 Virtual address 3 Physical address A 1

[0118] Hash1 is determined based on at least one of the identifier of the process to which storage unit 1 belongs and the context identifier of the page table to which storage unit 1 belongs. Hash2 is determined based on at least one of the identifier of the process to which storage unit 2 belongs and the context identifier of the page table to which storage unit 2 belongs. Hash3 is determined based on at least one of the identifier of the process to which storage unit 3 belongs and the context identifier of the page table to which storage unit 3 belongs. The identifier of the process to which storage unit 1 belongs and the context identifier of its page table, the identifier of the process to which storage unit 2 belongs and the context identifier of its page table, and the identifier of the process to which storage unit 3 belongs and the context identifier of its page table can all be the same or different. This application does not limit this.

[0119] In some embodiments, a hash value can be obtained based on the identification information related to the storage unit using a hash algorithm. The identification information related to the storage unit includes at least one of the following: the identifier of the process to which the storage unit belongs, and the context identifier of the page table to which the storage unit belongs. The hash algorithm can include SHA-256 (Secure Hash Algorithm 256-bit), MD5 (Message Digest Algorithm 5), MurmurHash, etc. Taking the MD5 hash algorithm as an example, specifically, an MD5 hash operation can be performed on the process to which the storage unit belongs, or on the context identifier of the page table to which the storage unit belongs, or on the sum of the identifier of the process to which the storage unit belongs and the context identifier of the page table to which the storage unit belongs, thereby obtaining a 128-bit hash value for identifying and retrieving the storage unit. It is understood that the hash values ​​can be the same or different. It is assumed that the hash value is determined based on the identifier of the process to which the storage unit belongs. If the process identifiers of storage unit 1 and storage unit 2 are the same, then Hash1 and Hash2 are the same; if the process identifiers of storage unit 1 and storage unit 2 are different, then Hash1 and Hash2 are different.

[0120] The method described above, by storing information tables as hash values, provides an efficient and flexible data organization and retrieval mechanism. Using hash values ​​as indexes allows for rapid location of storage units, thereby improving data access speed. Furthermore, since the hash value is determined based on at least one of the identifier of the process to which the storage unit belongs and the context identifier of the page table to which it belongs, this method can adapt well to different storage needs and scenarios. Whether it's multiple storage units within the same process or storage units between different processes, they can be accessed accurately and quickly using the corresponding hash values.

[0121] The technical solution provided in this application can determine a target storage unit from multiple storage units based on the usage of each storage unit in the video memory of the first chip, and compress the data in the target storage unit, thereby reducing the storage space occupied by the data in the video memory. This method effectively expands the available storage capacity of the video memory, and since this method reduces the video memory space occupied by directly compressing the data in the video memory, it does not involve the data exchange process between the video memory and system memory included in related technologies, avoiding the data exchange failure problem caused by PCIe bandwidth limitations, and avoiding the data loss or error problem caused during the data exchange process.

[0122] The following describes the specific implementation method of the decompression process.

[0123] When the first process calls the first chip, based on the information table, it is determined whether the storage unit related to the first process contains a storage unit in a compressed state; if the storage unit related to the first process contains a storage unit in a compressed state, the data in the storage unit in the compressed state is decompressed.

[0124] The first process refers to the process currently requesting resources from the first chip 20 (such as a GPU). In this case, the process involves the use of video memory storage units, which may be in a compressed state. Therefore, the system needs to determine the state of these storage units through an information table and, if necessary, decompress the compressed storage units to ensure that the first chip 20 (such as a GPU) can correctly read the data from the storage units.

[0125] In some embodiments, decompressing data in compressed storage units refers to decompressing storage units related to the first process, that is, decompressing compressed storage units associated with the first process. Storage units for other processes, even if they are also compressed, do not need to be decompressed.

[0126] In some embodiments, if the storage unit associated with the first process includes a storage unit in a compressed state, the data in all storage units in a compressed state may also be decompressed, and this application does not limit this.

[0127] In some embodiments, a corresponding decompression algorithm can be determined based on the compression algorithm selected during the compression process to decompress the data in the compressed storage unit. For example, when Huffman encoding is selected during compression, the Huffman decoder restores the compressed data stream to the original data based on a pre-built Huffman tree during decompression.

[0128] In some embodiments, determining whether the storage units related to the first process contain storage units in a compressed state may include the following steps: calculating a first hash value based on the identifier of the first process and the context identifier of the first page table, where the first page table refers to the page table to which the first process belongs; querying the compression status information of each storage unit stored corresponding to the first hash value from the information table; and determining whether the storage units related to the first process contain storage units in a compressed state based on the compression status information of each storage unit stored corresponding to the first hash value.

[0129] Understandably, when the hash value in the information table is determined by the identifier of the process to which the storage unit belongs, the first hash value is determined based on the identifier of the first process; when the hash value in the information table is determined by the context identifier of the page table to which the storage unit belongs, the first hash value is determined based on the context identifier of the first page table; when the hash value in the information table is determined by both the identifier of the process to which the storage unit belongs and the context identifier of the page table to which it belongs, the first hash value is determined based on both the identifier of the first process and the context identifier of the first page table.

[0130] For example, as shown in Table 3 above, assuming the first hash value is Hash1, and storage unit 1 corresponding to Hash1 is in an uncompressed state, then it is determined that the storage units related to the first process do not include storage units in a compressed state. Assuming the first hash value is Hash2, where Hash3 is the hash value of another process, and storage unit 2 corresponding to Hash2 is in a compressed state, then it is determined that the storage units related to the first process include storage units in a compressed state. In this case, the data in storage unit 2 is decompressed. Although storage unit 3 corresponding to Hash3 is also in a compressed state, since it does not belong to the first process, it does not need to be decompressed.

[0131] The above method, based on the identifier of the first process and the context identifier of the first page table, can quickly and accurately determine the compression status of the storage unit in the information table.

[0132] In some embodiments, after decompressing the data in the compressed storage unit, the process further includes updating the page table and information table of the first chip. In some embodiments, the mapping relationship between the virtual address and physical address of the storage unit recorded in the page table of the first chip is updated based on the physical address of the storage unit occupied by the decompressed data.

[0133] In some embodiments, the physical address of the storage unit occupied by the decompressed data may be the same as or different from the physical address of the storage unit occupied when the data is compressed.

[0134] For example, as shown in Table 4 below, it illustrates an example table of the page table of a decompressed first chip 20 (such as a GPU) provided in one embodiment of this application. Assuming that the storage unit associated with the first process is storage unit 2, the physical address of the storage unit occupied by the data decompressed in storage unit 2 is physical address C, where physical address C is different from physical address A.

[0135] Table 4

[0136] storage unit Virtual address physical address Tagging information Storage Unit 1 Virtual address 1 Physical address A 1 Storage Unit 2 Virtual address 2 Physical address C 0 Storage unit 3 Virtual address 3 Physical address A 0

[0137] In some embodiments, the address information and compression status information of the storage unit recorded in the information table are updated based on the physical address of the storage unit occupied by the decompressed data.

[0138] For example, as shown in Table 5 below, it illustrates an example table of decompressed information provided in one embodiment of this application. Assuming the storage unit associated with the first process is storage unit 2, the physical address of the storage unit occupied by the decompressed data in storage unit 2 is physical address C, where physical address C is different from physical address A. The compression status information of storage unit 2 is then updated to an uncompressed state, that is, bit 1 is updated to bit 0.

[0139] Table 5

[0140] storage unit Virtual address physical address Compression status information Storage Unit 1 Virtual address 1 Physical address A 0 Storage Unit 2 Virtual address 2 Physical address C 0 Storage unit 3 Virtual address 3 Physical address A 1

[0141] The above method can determine the compression status of the storage units related to the first process by using the compression status information in the information table. When the storage units related to the first process are in a compressed state, the data in the compressed storage units can be decompressed, thereby ensuring the normal execution of the first process.

[0142] Furthermore, after decompressing the compressed storage unit, the page table and information table of the first chip 20 (such as the GPU) are updated to ensure the correct mapping between virtual addresses and physical addresses, thus avoiding data access errors caused by improper address mapping when the first chip 20 (such as the GPU) is subsequently invoked.

[0143] Please refer to Figure 4 The diagram illustrates a flowchart of a video memory management method provided in another possible implementation of this application. Before obtaining the heat information of each of the multiple storage units included in the video memory, the method further includes: obtaining the utilization rate of a first chip and the utilization rate of the video memory; and, if a second condition is met, starting execution from the step of obtaining the heat information of each of the multiple storage units included in the video memory, wherein the second condition includes: the utilization rate of the first chip is less than or equal to a first threshold, and the utilization rate of the video memory is greater than or equal to a second threshold.

[0144] Taking the GPU as an example, GPU utilization refers to the proportion of the GPU actually used for computation at a certain moment or time period, usually expressed as a percentage. GPU utilization indicates the degree to which the GPU's computing resources are occupied, that is, the ratio of the GPU's computing power for executing tasks to its maximum computing power. In other words, a higher GPU utilization indicates a higher computational demand in the system, meaning a higher GPU workload; a lower GPU utilization indicates a lower computational demand in the system, meaning the GPU is relatively idle.

[0145] Video memory utilization refers to the percentage of video memory actually used at a given moment or time interval, usually expressed as a percentage. It represents the ratio of current video memory usage to total video memory capacity. For example, if the video memory utilization is 75%, it means that 75% of the video memory space has been allocated and used, while the remaining 25% is still idle.

[0146] In some embodiments, the setting of the first threshold and the second threshold can be set according to the experience of those skilled in the art, and this application does not limit this.

[0147] In the above method, when the utilization rate of the first chip is low, it indicates that the first chip is in a relatively idle state. At this time, compressing the data in the storage unit will not compete for resources with the ongoing computing task, thus avoiding negative impacts on the ongoing computing task. High utilization rate of the video memory indicates that the video memory is close to full load. At this time, it is necessary to compress the target storage unit to reduce the storage space occupied by data in the video memory.

[0148] like Figure 3 As shown, after obtaining the utilization rate of the first chip and the utilization rate of the video memory, it is determined whether the utilization rate of the first chip is less than or equal to a first threshold, and whether the utilization rate of the video memory is greater than or equal to a second threshold. When the above conditions are met, the scheme for compressing infrequently used video memory data proposed in this application is executed. Specifically, combining the heat information and the process to which the storage unit belongs, it is determined whether the first condition is met. For example, if the heat information of the storage unit is low and it does not belong to a preset process (such as a system process), then the storage unit is determined as the target storage unit, and the data in the target storage unit is compressed. After the compression is completed, the address information and compression status information of the target storage unit in the information table can be updated. Furthermore, some of the occupied video memory space is released, thereby effectively reducing the storage requirements of the video memory and expanding the available storage space of the video memory.

[0149] When the first process calls the first chip, it first checks the information table to see if there are any memory units in a compressed state among the memory units related to the first process. If so, it decompresses the compressed memory units. Then, it updates the physical address and compression status information in the information table and the page table of the first chip. Finally, it can call the first chip to execute the first process normally.

[0150] The above method requires data compression in the storage units when the utilization of the first chip is low and the utilization of the video memory is high. When the utilization of the first chip is low, it is relatively idle, and compressing the data in the storage units at this time will not compete for computing resources with the ongoing computing tasks. When the utilization of the video memory is high, indicating that the video memory is nearing full load, the target storage units need to be compressed to reduce the storage space occupied by data in the video memory, thereby expanding the available video memory space.

[0151] Please refer to Figure 5 The diagram illustrates a flowchart of a memory management method provided in another possible implementation of this application. This method may include at least one of the steps 510 to 530 below.

[0152] Step 510: Obtain the heat information of each of the multiple memory cells included in the first chip through the first logic unit. The heat information is used to indicate the usage status of the memory cells.

[0153] In some embodiments, the specific implementation of determining the heat information of each of the multiple storage units may include: when a process calls the first chip 20, the first logic unit 21 adds marking information to the page table of the first chip 20. The page table is used to record the mapping relationship between the virtual address and the physical address of the storage unit, and the marking information is used to indicate the storage unit used in the first chip 20.

[0154] The second chip 24 reads the tag information from the page table, determines the usage count of each of the multiple storage units based on the tag information, and determines the heat information of each of the multiple storage units based on the usage count of each of the multiple storage units.

[0155] In some embodiments, when a process calls the first chip 20, the first logic unit 21 may add marker information, such as bit 0 or bit 1, to the page table of the first chip 20. This application does not limit this.

[0156] In the above method, the first logic unit 21 can track the usage of storage units in the first chip 20 in real time by adding marking information to the page table; the second chip 24 can read the marking information in the page table, count the number of times the storage units are used, and calculate the heat information of the storage units based on the number of uses. In this way, the system can accurately determine the heat information of multiple storage units and provide a basis for subsequent storage space optimization (i.e., target storage unit compression).

[0157] Step 520: Based on the heat information of each of the multiple memory cells, the second chip determines at least one target memory cell from the multiple memory cells. For details on how to determine the target memory cell, please refer to the relevant content above.

[0158] Step 530: Compress the data in the target storage unit through the second logic unit.

[0159] In some embodiments, the second chip 24 updates the address information and compression status information of the target storage cell in the information table. The information table is used to store the address information and compression status information of multiple storage cells. The address information is used to indicate the mapping relationship between the virtual address and the physical address of the storage cell, and the compression status information is used to indicate whether the storage cell is in a compressed state.

[0160] In some embodiments, when the physical address of the target storage unit changes, the second chip 24 updates the address information in the information table to ensure that the mapping relationship between the virtual address and the physical address is correct.

[0161] In some embodiments, when the target storage unit is compressed or decompressed, the second chip 24 updates the compression status information in the information table to reflect the current status of the storage unit.

[0162] For example, suppose the original physical address of the target storage unit is 0x1000, the virtual address is 0x2000, and it is in an uncompressed state. After compression, the physical address becomes 0x1500, the virtual address remains 0x2000, and the compression state changes to compressed. The second chip 24 will update the address information and compression state information in the information table as follows: Address information: Virtual address 0x2000 is mapped to physical address 0x1500. Compression state information: The target storage unit is in a compressed state.

[0163] In some embodiments, the information table stores the address information and compression status information of the storage unit using the hash value of the identification information related to the storage unit as the key. The identification information related to the storage unit includes at least one of the following: the identifier of the process to which the storage unit belongs, and the context identifier of the page table to which the storage unit belongs.

[0164] In some embodiments, the decompression process may include: when the first process calls the first chip 20, the second chip 24 determines, based on an information table, whether the storage unit related to the first process contains a storage unit in a compressed state; if the storage unit related to the first process contains a storage unit in a compressed state, the second chip 24 sends a decompression command to the second logic unit 22, the decompression command being used to decompress the data in the storage unit in a compressed state; and the second logic unit 22 decompresses the data in the storage unit in a compressed state upon receiving the decompression command.

[0165] In some embodiments, when the first process calls the first chip 20, the second chip 24 checks, based on an information table, whether there are any compressed memory units among the memory units associated with the first process. The information table stores the address information and compression status information of each memory unit, so the second chip 24 can quickly determine which memory units are compressed by querying the information table. If the second chip 24 identifies a compressed memory unit among the memory units associated with the first process, it sends a decompression command to the second logic unit 22. For details on the specific information included in the decompression command, please refer to the corresponding content above.

[0166] In some embodiments, after receiving a decompression command, the second logic unit 22 locates the target storage unit according to the address information in the decompression command. Then, the second logic unit 22 decompresses the data in the target storage unit and restores it to its uncompressed state.

[0167] In some embodiments, the second chip 24 calculates a first hash value based on the identifier of the first process and the context identifier of the first page table, where the first page table refers to the page table to which the first process belongs; the second chip 24 queries the information table for the compression status information of each storage unit stored corresponding to the first hash value; and the second chip 24 determines whether the storage units related to the first process contain storage units in a compressed state based on the compression status information of each storage unit stored corresponding to the first hash value.

[0168] In some embodiments, the second chip 24 updates the mapping relationship between the virtual address and physical address of the storage unit recorded in the page table of the first chip 20 based on the physical address of the storage unit occupied by the decompressed data; the second chip 24 updates the address information and compression status information of the storage unit recorded in the information table based on the physical address of the storage unit occupied by the decompressed data.

[0169] In some embodiments, after decompression is complete, the second chip 24 updates the compression status information of the target storage cell in the information table, marking it as uncompressed. Simultaneously, if decompression causes a change in the physical address of the storage cell, the second chip 24 also updates the address information in the information table.

[0170] In some embodiments, before obtaining the heat information of each of the plurality of memory cells included in the first chip, the method further includes: obtaining the utilization rate of the first chip 20 and the utilization rate of the video memory through the second chip 24; and, if a second condition is met, determining at least one target memory cell from the plurality of memory cells based on the heat information of each of the plurality of memory cells through the second chip 24, wherein the second condition includes: the utilization rate of the first chip 20 is less than or equal to a first threshold, and the utilization rate of the video memory is greater than or equal to a second threshold.

[0171] For any descriptions not explained in detail in the above embodiments, please refer to the corresponding content above.

[0172] The following is the memory management system of this application. For details not disclosed in the embodiments of the memory management system of this application, please refer to the method embodiments of this application above.

[0173] In some embodiments, this application provides a video memory management system, the system comprising: a first chip and a second chip, wherein the first chip is configured with a first logic unit and a second logic unit.

[0174] The first logic unit is used to acquire heat information of each of the multiple memory units included in the first chip, and the heat information is used to indicate the usage status of the memory units.

[0175] The second chip is used to determine at least one target storage cell from the plurality of storage cells based on the heat information of each of the plurality of storage cells.

[0176] The second logic unit is used to compress the data in the target storage unit.

[0177] In some embodiments, the first logic unit is configured to add marking information to the page table of the first chip when a process calls the first chip. The page table is used to record the mapping relationship between the virtual address and physical address of the memory unit, and the marking information is used to indicate the memory unit used in the first chip. The second chip is configured to read the marking information from the page table, determine the usage count of each of the plurality of memory units based on the marking information, and determine the popularity information of each of the plurality of memory units based on the usage count of each of the plurality of memory units.

[0178] In some embodiments, the second chip is further configured to update the address information and compression status information of the target storage unit in an information table, wherein the information table is configured to store the address information and compression status information of each of the plurality of storage units, the address information is configured to indicate the mapping relationship between the virtual address and the physical address of the storage unit, and the compression status information is configured to indicate whether the storage unit is in a compressed state.

[0179] In some embodiments, the information table stores the address information and compression status information of the storage unit using the hash value of the identification information related to the storage unit as the key. The identification information related to the storage unit includes at least one of the following: the identifier of the process to which the storage unit belongs, and the context identifier of the page table to which the storage unit belongs.

[0180] In some embodiments, the second chip is further configured to, when the first process calls the first chip, determine, based on the information table, whether the storage unit related to the first process contains a storage unit in the compressed state; if the storage unit related to the first process contains a storage unit in the compressed state, send a decompression instruction to the second logic unit, the decompression instruction being used to decompress the data in the storage unit in the compressed state; the second logic unit is further configured to, upon receiving the decompression instruction, decompress the data in the storage unit in the compressed state.

[0181] In some embodiments, the second chip is configured to: calculate a first hash value based on the identifier of the first process and the context identifier of the first page table, wherein the first page table refers to the page table to which the first process belongs; query the information table for compression status information of each storage unit stored corresponding to the first hash value; and determine, based on the compression status information of each storage unit stored corresponding to the first hash value, whether the storage units related to the first process include storage units in the compression state.

[0182] In some embodiments, the second chip is further configured to: update the mapping relationship between the virtual address and physical address of the storage unit recorded in the page table of the first chip based on the physical address of the storage unit occupied by the decompressed data; and update the address information and compression status information of the storage unit recorded in the information table based on the physical address of the storage unit occupied by the decompressed data.

[0183] In some embodiments, the second chip is further configured to: obtain the utilization rate of the first chip and the utilization rate of the video memory; and, if a second condition is met, determine the at least one target memory cell from the plurality of memory cells based on the heat information of each of the plurality of memory cells, wherein the second condition includes: the utilization rate of the first chip is less than or equal to a first threshold, and the utilization rate of the video memory is greater than or equal to a second threshold.

[0184] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0185] Please refer to Figure 6 This diagram illustrates a block diagram of a video memory management device provided in one possible implementation of this application. The device has the function of implementing the aforementioned video memory management method; this function can be implemented in hardware or by hardware executing corresponding software. The device can be an electronic device or can be installed within an electronic device. The device 600 may include: an acquisition module 610, a determination module 620, and a compression module 630.

[0186] The acquisition module 610 is used to acquire the heat information of each of the multiple storage units included in the video memory, and the heat information is used to indicate the usage status of the storage units.

[0187] The determining module 620 is used to determine at least one target storage unit from the plurality of storage units based on the heat information of each of the plurality of storage units.

[0188] Compression module 630 is used to compress the data in the target storage unit.

[0189] In some embodiments, the acquisition module 610 is used to determine the popularity information of each of the plurality of storage units based on the number of times each of the plurality of storage units is used.

[0190] In some embodiments, the acquisition module 610 is used to read tag information from the page table of the first chip, the page table is used to record the mapping relationship between the virtual address and physical address of the memory cell, and the tag information is used to indicate the memory cell used in the video memory; based on the tag information, the usage count of each of the plurality of memory cells is determined.

[0191] In some embodiments, the determining module 620 is used to determine the at least one target storage unit from the plurality of storage units based on the heat information of each of the plurality of storage units and the process to which each of the plurality of storage units belongs.

[0192] In some embodiments, the determining module 620 is used to determine at least one storage unit that satisfies a first condition and whose process does not belong to a first process set as the at least one target storage unit; wherein, the first condition includes at least one of the following: the heat information is less than or equal to a first threshold, the heat information is one of the smaller N heat information among the heat information of each of the plurality of storage units, where N is a positive integer; the first process set includes at least one pre-set process.

[0193] In some embodiments, the device 600 further includes: a first update module ( Figure 6 (Not shown in the image).

[0194] The first update module is used to update the address information and compression status information of the target storage unit in the information table. The information table is used to store the address information and compression status information of each of the plurality of storage units. The address information is used to indicate the mapping relationship between the virtual address and the physical address of the storage unit, and the compression status information is used to indicate whether the storage unit is in a compressed state.

[0195] In some embodiments, the first update module is used to store the address information and compression status information of the storage unit in the information table, with the hash value of the identification information related to the storage unit as the key, wherein the identification information related to the storage unit includes at least one of the following: the identifier of the process to which the storage unit belongs, and the context identifier of the page table to which the storage unit belongs.

[0196] In some embodiments, the device 600 further includes: a decompression module ( Figure 6 (Not shown in the image).

[0197] The decompression module is used to, when the first process calls the first chip, determine, based on the information table, whether the storage units related to the first process contain storage units in the compressed state; and if the storage units related to the first process contain storage units in the compressed state, decompress the data in the storage units in the compressed state.

[0198] In some embodiments, the decompression module is configured to calculate a first hash value based on the identifier of the first process and the context identifier of the first page table, wherein the first page table refers to the page table to which the first process belongs; query the information table for the compression status information of each storage unit stored corresponding to the first hash value; and determine, based on the compression status information of each storage unit stored corresponding to the first hash value, whether the storage units related to the first process contain storage units in the compression state.

[0199] In some embodiments, the device 600 further includes: a second update module ( Figure 6 (Not shown in the image).

[0200] The second update module is used to update the mapping relationship between the virtual address and physical address of the storage unit recorded in the page table of the first chip based on the physical address of the storage unit occupied by the decompressed data; and to update the address information and compression status information of the storage unit recorded in the information table based on the physical address of the storage unit occupied by the decompressed data.

[0201] In some embodiments, the device 600 further includes: an execution module ( Figure 6 (Not shown in the image).

[0202] An execution module is configured to obtain the utilization rate of the first chip and the utilization rate of the video memory; and, if a second condition is met, to begin execution from the step of obtaining the heat information of each of the multiple storage units included in the video memory, wherein the second condition includes: the utilization rate of the first chip is less than or equal to a first threshold, and the utilization rate of the video memory is greater than or equal to a second threshold.

[0203] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0204] Please refer to Figure 7 The diagram shows a structural block diagram of an electronic device 700 provided in one possible implementation of this application.

[0205] Typically, electronic device 700 includes a processor 710 and a memory 720.

[0206] Processor 710 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 710 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 710 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 510 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 510 may also include an AI processor for handling computational operations related to machine learning.

[0207] The memory 720 may include one or more computer-readable storage media, which may be non-transitory. The memory 720 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 720 are used to store a computer program configured to be executed by one or more processors to implement the above-described video memory management method.

[0208] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the electronic device 700, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0209] In some embodiments, a computer-readable storage medium is also provided, wherein a computer program is stored in the storage medium, the computer program being loaded and executed by a processor to implement the above-described video memory management method.

[0210] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0211] In some embodiments, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the above-described video memory management method.

[0212] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "Greater than or equal to" as used herein can mean greater than or equal to, or greater than; "less than or equal to" can mean less than or equal to. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in the order shown in the numbers, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0213] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A video memory management method, characterized in that, The method is applied to a first chip, the first chip being configured with a first logic unit and a second logic unit; the method includes: The first logic unit obtains the heat information of each of the multiple memory units included in the first chip, and the heat information is used to indicate the usage status of the memory unit; The second logic unit compresses data in at least one target storage unit, wherein the target storage unit is determined by the second chip from the plurality of storage units based on the acquired heat information of each of the plurality of storage units; The first chip is different from the second chip.

2. The method according to claim 1, characterized in that, The method includes: When a process calls the first chip, the first logic unit adds marking information to the page table of the first chip. The page table is used to record the mapping relationship between the virtual address and physical address of the memory unit, and the marking information is used to indicate the memory unit used in the first chip.

3. The method according to claim 2, characterized in that, The heat information of the storage unit includes the number of times the storage unit has been used, and the tagging information is used to determine the number of times each of the plurality of storage units has been used.

4. The method according to claim 2, characterized in that, The method further includes: When a process calls the first chip, the first logic unit clears the tag information that has been added to the page table of the first chip.

5. The method according to claim 1, characterized in that, The heat information of the target storage unit satisfies the first condition, and the process to which the target storage unit belongs does not belong to the first process set; The first condition includes at least one of the following: the heat information is less than or equal to a first threshold; the heat information is one of the smaller N heat information among the heat information of each of the plurality of storage units, where N is a positive integer; and the first process set includes at least one pre-set process.

6. The method according to claim 1, characterized in that, The step of compressing data in at least one target storage unit through the second logic unit includes: Upon receiving a compression command from the driver, the second logic unit compresses the data in the at least one target storage unit.

7. The method according to claim 1, characterized in that, The method further includes: Upon receiving a decompression command from the driver, the second logic unit decompresses the data in the compressed storage unit.

8. The method according to claim 1, characterized in that, The first chip is also equipped with a memory management unit (MMU); the method further includes: The operation instructions sent by the driver are obtained through the MMU. The operation instructions include the virtual address of the first memory unit to be accessed and the page table of the first chip. The MMU reads the physical address corresponding to the virtual address of the first memory cell from the page table of the first chip, based on the virtual address of the first memory cell, and uses it as the first physical address. The MMU accesses the first storage unit based on the first physical address.

9. A video memory management system, characterized in that, The system includes: a first chip and a second chip, wherein the first chip is configured with a first logic unit and a second logic unit; wherein the first chip and the second chip are different; The first logic unit is used to acquire heat information of each of the multiple memory units included in the first chip, and the heat information is used to indicate the usage status of the memory units; The second chip is used to determine at least one target memory cell from the plurality of memory cells based on the heat information of each of the plurality of memory cells; The second logic unit is used to compress the data in the target storage unit.

10. The system according to claim 9, characterized in that, The first logic unit is used to add marking information to the page table of the first chip when a process calls the first chip. The page table is used to record the mapping relationship between the virtual address and physical address of the memory unit. The marking information is used to indicate the memory unit used in the first chip. The second chip is used to read the tag information from the page table, determine the usage count of each of the plurality of storage units based on the tag information, and determine the popularity information of each of the plurality of storage units based on the usage count of each of the plurality of storage units.

11. The system according to claim 9, characterized in that, The second chip is further configured to update the address information and compression status information of the target storage unit in an information table, wherein the information table is configured to store the address information and compression status information of each of the plurality of storage units, the address information is configured to indicate the mapping relationship between the virtual address and the physical address of the storage unit, and the compression status information is configured to indicate whether the storage unit is in a compressed state.

12. The system according to claim 11, characterized in that, In the information table, the address information and compression status information of the storage unit are stored with the hash value of the identification information related to the storage unit as the key. The identification information related to the storage unit includes at least one of the following: the identifier of the process to which the storage unit belongs, and the context identifier of the page table to which the storage unit belongs.

13. The system according to claim 11, characterized in that, The second chip is further configured to, when the first process calls the first chip, determine, based on the information table, whether the storage unit related to the first process contains a storage unit in the compressed state; if the storage unit related to the first process contains a storage unit in the compressed state, send a decompression instruction to the second logic unit, the decompression instruction being used to decompress the data in the storage unit in the compressed state; The second logic unit is further configured to decompress the data in the storage unit that is in a compressed state upon receiving the decompression command.

14. The system according to claim 13, characterized in that, The second chip is used for: The first hash value is calculated based on the identifier of the first process and the context identifier of the first page table, where the first page table refers to the page table to which the first process belongs. From the information table, query the compression status information of each storage unit corresponding to the first hash value; Based on the compression status information of each storage unit stored corresponding to the first hash value, determine whether the storage units related to the first process include storage units in the compression state.

15. The system according to claim 13, characterized in that, The second chip is also used for: Based on the physical address of the storage unit occupied by the decompressed data, update the mapping relationship between the virtual address and physical address of the storage unit recorded in the page table of the first chip; Based on the physical address of the storage unit occupied by the decompressed data, update the address information and compression status information of the storage unit recorded in the information table.

16. The system according to any one of claims 9 to 15, characterized in that, The second chip is also used for: Obtain the utilization rate of the first chip and the utilization rate of the video memory; If the second condition is met, at least one target memory cell is determined from the plurality of memory cells based on the heat information of each of the plurality of memory cells, wherein the second condition includes: the utilization rate of the first chip is less than or equal to a first threshold, and the utilization rate of the video memory is greater than or equal to a second threshold.

17. A first chip, characterized in that, The first chip is configured with a first logic unit and a second logic unit; The first logic unit is used to acquire heat information of each of the multiple memory units included in the video memory of the first chip, and the heat information is used to indicate the usage status of the memory units; The second logic unit is used to compress data in at least one target storage unit, which is determined by the second chip from the plurality of storage units based on the acquired heat information of each of the plurality of storage units; wherein the first chip and the second chip are different.

18. An electronic device, characterized in that, The electronic device includes a video memory management system as described in any one of claims 9 to 16.

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