Shift register, gate driving circuit, display panel, and driving method and device

Abstract

The application relates to a shift register, a gate driving circuit, a display panel, a driving method and a device, and relates to the technical field of display. The shift register comprises a driving module configured to output an initial scanning signal; a control module connected with the driving module and configured to receive at least the initial scanning signal, a first power supply signal, a second power supply signal, a third power supply signal, a first frequency control signal and a second frequency control signal; the control module is further configured to output the first power supply signal as a gate scanning signal when the initial scanning signal and the first frequency control signal are both effective and the second frequency control signal is ineffective; or output the second power supply signal as the gate scanning signal when the first frequency control signal is ineffective and the initial scanning signal and the second frequency control signal are both effective. The application can output the first power supply signal or the second power supply signal as the gate scanning signal, which helps to improve display uniformity.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel, and a driving method and apparatus. Background Technology

[0002] With the continuous advancement of display technology, the application scenarios for display devices are increasing, and users' demands for display devices are becoming more diversified. In some application scenarios, using segmented frequency display can effectively reduce power consumption and extend lifespan. However, existing display devices suffer from uneven display when implementing segmented frequency display. Summary of the Invention

[0003] This application provides a shift register, a gate driving circuit, a display panel, and a driving method and apparatus, which helps to improve display uniformity.

[0004] In a first aspect, embodiments of this application provide a shift register, including:

[0005] The drive module is used to output the initial scan signal;

[0006] A control module, connected to the drive module, is used to receive at least the initial scan signal, a first power signal, a second power signal, a third power signal, a first frequency control signal, and a second frequency control signal; the first power signal, the second power signal, and the third power signal are all different.

[0007] The control module is further configured to output the first power supply signal as a gate scan signal when both the initial scan signal and the first frequency control signal are valid and the second frequency control signal is invalid; or, when the first frequency control signal is invalid and both the initial scan signal and the second frequency control signal are valid, output the second power supply signal as a gate scan signal.

[0008] Secondly, embodiments of this application provide a gate driving circuit including a plurality of cascaded shift registers as described above.

[0009] Thirdly, embodiments of this application provide a display panel including at least one gate driving circuit and a pixel circuit as described above, wherein the gate driving circuit is connected to the pixel circuit.

[0010] Fourthly, embodiments of this application provide a driving method for a display panel, applied to the display panel as described above, the display panel including a first display area and a second display area, the method comprising:

[0011] By controlling a portion of the shift register in the gate drive circuit to output a first power signal, the pixel circuit of the first display area is driven to drive the first display area to display at a first frequency;

[0012] By controlling the output of the second power supply signal from the remaining shift register in the gate drive circuit, the pixel circuit of the second display area is driven to drive the second display area to display at a second frequency; wherein the first frequency is different from the second frequency, and the first power supply signal is different from the second power supply signal.

[0013] Fifthly, embodiments of this application provide a display device, which includes the display panel as described above.

[0014] The shift register, gate driving circuit, display panel, and driving method and apparatus provided in this application, by controlling a first frequency control signal and a second frequency control signal, control the shift register to select either a first power supply signal or a second power supply signal as the gate scan signal. Since the first power supply signal and the second power supply signal are different, this application can provide gate scan signals with different potentials for pixel circuits in display areas of different frequencies. Specifically, by controlling the initial scan signal and the first frequency control signal to be valid while the second frequency control signal is invalid, the shift register outputs the first power supply signal as the gate scan signal, and by controlling the first frequency control signal to be invalid while the initial scan signal is invalid... With both the second and second frequency control signals active, the shift register outputs the second power supply signal as the gate scan signal. Thus, the same shift register can provide different power supply signals as gate scan signals for different refresh frequencies or different display scenarios. Furthermore, different shift registers can provide different power supply signals as gate scan signals for display areas of different frequencies. In other words, by using gate scan signals with different potentials, the characteristic drift differences of transistors in segmented frequency display scenarios are compensated, thereby compensating for the display brightness differences between different display areas in segmented frequency scenarios. This balances the display brightness of different display areas, thereby improving display uniformity. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0016] Figure 2 A timing diagram of multiple signals provided for an embodiment of this application;

[0017] Figure 3 A timing diagram of another set of signals provided in an embodiment of this application;

[0018] Figure 4A timing diagram of multiple signals provided in another embodiment of this application;

[0019] Figure 5 A timing diagram of another set of multiple signals provided in an embodiment of this application;

[0020] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of this application;

[0021] Figure 7 This is a schematic diagram of the structure of a control module provided in an embodiment of this application;

[0022] Figure 8 This is a schematic diagram of another control module provided in an embodiment of this application;

[0023] Figure 9 This is a schematic diagram of the structure of another control module provided in an embodiment of this application;

[0024] Figure 10 This is a schematic diagram of another control module provided in an embodiment of this application;

[0025] Figure 11 This is a schematic diagram of the structure of a drive module provided in an embodiment of this application;

[0026] Figure 12 This is a schematic diagram of another driving module provided in an embodiment of this application;

[0027] Figure 13 This is a schematic diagram of another driving module provided in an embodiment of this application;

[0028] Figure 14 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0029] Figure 15 A timing diagram of multiple signals provided for an embodiment of this application;

[0030] Figure 16 A timing diagram of another set of signals provided in an embodiment of this application;

[0031] Figure 17 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0032] Figure 18 A timing diagram of multiple signals provided for an embodiment of this application;

[0033] Figure 19 A timing diagram of multiple signals provided for an embodiment of this application;

[0034] Figure 20 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0035] Figure 21 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0036] Figure 22 This application provides a schematic diagram of the structure of a pixel circuit and a light-emitting element according to an embodiment of the present application.

[0037] Figure 23 A schematic flowchart illustrating a driving method for a display panel provided in an embodiment of this application;

[0038] Figure 24 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0039] Figure 25 A timing diagram of multiple signals provided for an embodiment of this application;

[0040] Figure 26 A graph showing the relationship between a first power signal and a second power signal and time, provided for an embodiment of this application;

[0041] Figure 27 Another graph showing the relationship between the first power signal and the second power signal and time, provided for an embodiment of this application;

[0042] Figure 28 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0043] Explanation of reference numerals in the attached figures:

[0044] 1. First display area; 2. Second display area; 10. Drive module; 11. Input module; 12. First drive module; 13. Second drive module; 20. Control module; 21. First control module; 22. Second control module; 23. Output module; 210. First control unit; 211. First control unit; 212. First control unit; 220. Second control unit; 221. Second control unit; 222. Second control unit; 230. Third control unit; 231. Third control unit; 232. Third control unit; 240. Fourth control unit; 241. Fourth control unit; 242. Fourth control unit; 30. Gate drive circuit; 301. Shift register; 31. First gate drive circuit; 311. Shift register; 32. Second gate drive circuit; 321. Shift register; 40. Pixel circuit; 51. First display area; 52. Second display area; 60. Display panel; 70. Display device. Detailed Implementation

[0045] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0048] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0049] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0050] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0051] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0052] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0053] As described in the background section, display devices suffer from uneven display when displaying at different frequencies. For example, the brightness of areas displayed at different frequencies (referred to as different display areas) varies, resulting in poor display quality. Figure 1 In the display panel shown, the display brightness of the first display area 1 is lower than that of the second display area 2, and the refresh rates of the first display area 1 and the second display area 2 are different.

[0054] As is understood, the display panel is the core component of a display device that enables its display function. The display panel uses pixel circuits to drive light-emitting elements to emit light, thus achieving the display function. Based on the aforementioned technical problems, the inventors discovered that when a display panel is used for long-term segmented frequency display, the characteristics of the transistors in the pixel circuits of different display areas drift differently, resulting in differences in display brightness between different display areas, leading to uneven display and affecting the display effect. Taking the pixel circuit of the display panel, which includes oxide thin-film transistors, as an example, when the display panel is used for long-term segmented frequency display, because the refresh rates of the high and low frequency display areas are different, the oxide thin-film transistors in the high-frequency display area are more prone to drift than those in the low-frequency display area. This results in differences in display brightness between the high-frequency and low-frequency display areas, leading to the problem of split-screen display.

[0055] Based on the above, the inventors further developed the technical solution of the embodiments of this application. Specifically, the shift register provided in the embodiments of this application includes a driving module and a control module. The driving module is used to output an initial scan signal; the control module is used to receive at least the initial scan signal, a first power signal, a second power signal, a third power signal, a first frequency control signal, and a second frequency control signal; the control module is also used to output the first power signal as a gate scan signal when both the initial scan signal and the first frequency control signal are valid and the second frequency control signal is invalid; or, when the first frequency control signal is invalid and both the initial scan signal and the second frequency control signal are valid, output the second power signal as a gate scan signal; wherein the first power signal, the second power signal, and the third power signal are all different. Thus, by controlling the first frequency control signal and the second frequency control signal, this application controls the shift register to select the output of the first power signal or the second power signal as the gate scan signal, thereby providing gate scan signals with different potentials for the pixel circuits of different display areas, realizing compensation for the differences in transistor characteristic drift in the pixel circuits of different display areas, and thus compensating for the differences in display brightness of different display areas, which helps to improve display uniformity.

[0056] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0057] Figure 2 This is a schematic diagram of a shift register provided in an embodiment of this application. Figure 3 This is a timing diagram of multiple signals provided in an embodiment of this application. Figure 4 This is a timing diagram of another set of signals provided in an embodiment of this application.

[0058] Combination Figures 2 to 4 As shown, in some embodiments, this application provides a shift register including a driver module 10 and a control module 20. The driver module 10 is used to output an initial scan signal Next. The driver module 10 can receive a start signal STV, a first clock signal CK, a second clock signal XCK, a first power signal VGH1, and a third power signal VGL, and output the initial scan signal Next.

[0059] The control module 20 is connected to the drive module 10. The control module 20 receives at least the initial scan signal Next, a first power signal VGH1, a second power signal VGH2, a third power signal VGL, a first frequency control signal Ctrl1, and a second frequency control signal Ctrl2. The first power signal VGH1, the second power signal VGH2, and the third power signal VGL are all different. For example, the first power signal VGH1 and the second power signal VGH2 are different, and both are greater than the third power signal VGL. For instance, the first power signal VGH1 and the second power signal VGH2 are both high-level signals, and the third power signal VGL is a low-level signal. The first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 have different frequencies. The first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are used to control the driving frequency of the pixel circuits connected to the corresponding shift registers, thereby controlling the refresh frequency of the corresponding display area.

[0060] For ease of explanation, in this embodiment, the example given is that the first power signal VGH1 is greater than the second power signal VGH2, the second power signal VGH2 is greater than the third power signal VGL, and the frequency of the first frequency control signal Ctrl1 is greater than the frequency of the second frequency control signal Ctrl2. It should be noted that in some embodiments, the first power signal VGH1 may be less than the second power signal VGH2, and the first power signal VGH1 may be greater than the third power signal VGL; the frequency of the first frequency control signal Ctrl1 may be less than the frequency of the second frequency control signal Ctrl2. Specifically, the relationship between the power signals and the frequency control signals can be set according to application requirements.

[0061] The control module 20 is also used to output a first power supply signal VGH1 as the gate scan signal OUT when both the initial scan signal Next and the first frequency control signal Ctrl1 are valid and the second frequency control signal Ctrl2 is invalid; or, when the first frequency control signal Ctrl1 is invalid and both the initial scan signal Next and the second frequency control signal Ctrl2 are valid, to output a second power supply signal VGH2 as the gate scan signal OUT. Figure 3 As shown, when the initial scan signal Next and the first frequency control signal Ctrl1 are valid pulses and the second frequency control signal Ctrl2 is an invalid pulse, the gate scan signal OUT output by the control module 20 is the first power supply signal VGH1; Figure 4 As shown, when the first frequency control signal Ctrl1 is an invalid pulse and the initial scan signal Next and the second frequency control signal Ctrl2 are valid pulses, the gate scan signal OUT output by the control module 20 is the second power supply signal VGH2.

[0062] For example, the effective pulses of the initial scan signal Next and the first frequency control signal Ctrl1 are different, while the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are the same. For instance, the effective pulse of the initial scan signal Next is high, while the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both low. Correspondingly, when the first frequency control signal Ctrl1 is low and the initial scan signal Next and the second frequency control signal Ctrl2 are both high, the gate scan signal OUT output by the control module 20 is the first power supply signal VGH1; when the initial scan signal Next and the first frequency control signal Ctrl1 are both high and the second frequency control signal Ctrl2 is low, the gate scan signal OUT output by the control module 20 is the second power supply signal VGH2.

[0063] In another example, the effective pulses of the initial scan signal Next, the first frequency control signal Ctrl1, and the second frequency control signal Ctrl2 are all the same. For instance, the effective pulses of the initial scan signal Next, the first frequency control signal Ctrl1, and the second frequency control signal Ctrl2 are all high-level; correspondingly, when the initial scan signal Next and the first frequency control signal Ctrl1 are both high-level, and the second frequency control signal Ctrl2 is low-level, the gate scan signal OUT output by the control module 20 is the first power supply signal VGH1; when the first frequency control signal Ctrl1 is low-level, and the initial scan signal Next and the second frequency control signal Ctrl2 are both high-level, the gate scan signal OUT output by the control module 20 is the second power supply signal VGH2.

[0064] It should be noted that in some other examples, the valid pulse of the initial scan signal Next can be low. In application, the level type of the valid pulses of the initial scan signal Next, the first frequency control signal Ctrl1, and the second frequency control signal Ctrl2 can be set according to specific requirements, and will not be limited here.

[0065] When both the initial scan signal Next and the first frequency control signal Ctrl1 are valid pulses, and the second frequency control signal Ctrl2 is an invalid pulse, the pixel circuit connected to the shift register drives the light-emitting element D to emit light at the first frequency under the action of the gate scan signal OUT (i.e., the first power supply signal VGH1), so that the display area driven by the pixel circuit displays at the first frequency. When the first frequency control signal Ctrl1 is an invalid pulse, and both the initial scan signal Next and the second frequency control signal Ctrl2 are valid pulses, the pixel circuit connected to the shift register drives the light-emitting element D to emit light at the second frequency under the action of the gate scan signal OUT (i.e., the second power supply signal VGH2), so that the display area driven by the pixel circuit displays at the second frequency.

[0066] In the application, the control module 20 in the shift register is connected to the pixel circuit, which drives the light-emitting element D connected to the pixel circuit to emit light. When the display area corresponding to the pixel circuit connected to the shift register operates in the first mode (i.e., the refresh rate of the display area is the first frequency), the initial scan signal Next and the first frequency control signal Ctrl1 can be enabled, while the second frequency control signal Ctrl2 is disabled. In this case, the shift register outputs the first power supply signal VGH1 as the gate scan signal OUT to drive the pixel circuit, thereby causing the pixel circuit to drive the light-emitting element D to emit light at the first frequency, thus enabling the corresponding display area to display at the first frequency. When the display area corresponding to the pixel circuit connected to the shift register operates in the second mode (i.e., the refresh rate of the display area is the second frequency), the first frequency control signal Ctrl1 can be disabled, while the initial scan signal Next and the second frequency control signal Ctrl2 can be enabled. In this case, the shift register outputs the second power supply signal VGH2 as the gate scan signal OUT to drive the pixel circuit, thereby causing the pixel circuit to drive the light-emitting element D to emit light at the second frequency, thus enabling the corresponding display area to display at the second frequency.

[0067] Taking a display panel with frequency division and segmentation capabilities as an example, the display panel includes a first display area and a second display area. If the first display area operates in a first mode and the second display area operates in a second mode, the shift register connected to the pixel circuit of the first display area can output a first power signal VGH1 as the gate scan signal OUT, causing the pixel circuit of the first display area to drive the first display area to display at a first frequency under the drive of the first power signal VGH1. Similarly, the shift register connected to the pixel circuit of the second display area can output a second power signal VGH2 as the gate scan signal OUT, causing the pixel circuit of the second display area to drive the second display area to display at a second frequency under the drive of the second power signal VGH2. For example, if the first frequency is greater than the second frequency, that is, the first display area displaying at a higher frequency uses the first power signal VGH1 as the gate scan signal OUT, and the second display area displaying at a lower frequency uses the second power signal VGH2 as the gate scan signal OUT.

[0068] The shift register provided in this application embodiment controls the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 to select either the first power supply signal VGH1 or the second power supply signal VGH2 as the gate scan signal OUT. Since the first power supply signal VGH1 and the second power supply signal VGH2 are different, this application can provide gate scan signals OUT with different potentials for pixel circuits in different display areas. By controlling the initial scan signal Next and the first frequency control signal Ctrl1 to be valid while the second frequency control signal Ctrl2 is invalid, the shift register outputs the first power supply signal VGH1 as the gate scan signal OUT, and controls the first frequency control signal Ctrl1 to be invalid while the initial scan signal Next is invalid. With both the Next signal and the second frequency control signal Ctrl2 active, the shift register outputs the second power supply signal VGH2 as the gate scan signal OUT. Thus, the same shift register can provide different power supply signals as the gate scan signal OUT for different refresh frequencies or different display modes. Furthermore, different shift registers can provide different power supply signals as the gate scan signal OUT for different display areas. In other words, by using gate scan signals OUT with different potentials, the characteristic drift differences of transistors in segmented frequency display scenarios are compensated, thereby compensating for the display brightness differences between different display areas in segmented frequency display scenarios. This balances the display brightness of different display areas, thereby improving display uniformity.

[0069] Figure 5 This is a timing diagram of multiple signals provided in an embodiment of this application. (In conjunction with...) Figure 2 and Figure 5 As shown, in some embodiments, the control module 20 is further configured to output a third power supply signal VGL as the gate scan signal OUT when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid. That is, when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid pulses, the gate scan signal OUT output by the control module 20 is the third power supply signal VGL. Specifically, when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid pulses, regardless of whether the initial scan signal Next is a valid pulse or an invalid pulse, the gate scan signal OUT output by the control module 20 is always the third power supply signal VGL.

[0070] For example, the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are the same, for example, both are low level. Correspondingly, when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are low level, the gate scan signal OUT output by the control module 20 is the third power supply signal VGL. In this case, the control module 20 does not output the first power supply signal VGH1, nor does it output the second power supply signal VGH2. This can be understood as the control module 20 maintaining a default low level state. In another example, the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both high level. Correspondingly, when both the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are high level, the gate scan signal OUT output by the control module 20 is the third power supply signal VGL. It should be noted that in applications, the level type of the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 can be set separately according to the specific application scenario. No further limitations are imposed here.

[0071] In the application, the control module 20 in the shift register is connected to the pixel circuit, which drives the light-emitting element D connected to the pixel circuit to emit light. When the display area corresponding to the pixel circuit connected to the shift register is in the maintenance phase, by invalidating the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2, the gate scan signal OUT output by the shift register remains unchanged, thus keeping the display brightness of the display area corresponding to the pixel circuit driven by the shift register constant.

[0072] The shift register provided in this application embodiment controls the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 to be invalid, so that the control module 20 outputs a third power signal VGL as a gate scan signal OUT. In this way, the shift register provides a third power signal VGL to the pixel circuit, so that the pixel circuit drives the corresponding display area to maintain a constant display brightness under the drive of the third power signal VGL, which helps to realize the segmented frequency display function of the display panel.

[0073] Figure 6 This is a schematic diagram of a shift register provided in an embodiment of this application. (In conjunction with...) Figures 3 to 6 As shown, in some embodiments, the control module 20 includes a first control module 21, a second control module 22, and an output module 23.

[0074] The first control module 21 is connected to both the output module 23 and the drive module 10. The first control module 21 can be connected to the first output node SOUT of the output module 23 and the second output node NEXT of the drive module 10. The first control module 21 is used to receive at least the initial scan signal Next, the first power supply signal VGH1, the third power supply signal VGL, and the first frequency control signal Ctrl1, and to control the gate scan signal OUT output by the first output node SOUT of the output module 23. Under the influence of the initial scan signal Next, the first power supply signal VGH1, the third power supply signal VGL, and the first frequency control signal Ctrl1, the first control module 21 can select to output the first power supply signal VGH1.

[0075] The second control module 22 is connected to both the output module 23 and the drive module 10. The second control module 22 can be connected to the first output node SOUT of the output module 23 and the drive module 10, respectively. The second control module 22 is used to receive at least the second power supply signal VGH2, the third power supply signal VGL, and the second frequency control signal Ctrl2, and to control the gate scan signal OUT output by the first output node SOUT. Under the influence of the initial scan signal Next, the second power supply signal VGH2, the third power supply signal VGL, and the second frequency control signal Ctrl2, the second control module 22 can select to output the second power supply signal VGH2.

[0076] Output module 23 is connected to drive module 10. Output module 23 can be connected to the third node N3 of drive module 10. Output module 23 is used to receive at least the third power supply signal VGL and control the gate scan signal OUT output by the first output node SOUT. Specifically, output module 23 can receive the third node signal and the third power supply signal VGL from the third node N3 and select to output the third power supply signal VGL.

[0077] When the initial scan signal Next and the first frequency control signal Ctrl1 are both valid, and the second frequency control signal Ctrl2 is invalid, for example... Figure 3 As shown, when the initial scan signal Next and the second frequency control signal Ctrl2 are both high and the first frequency control signal Ctrl1 is low, the first control module 21 outputs the first power supply signal VGH1, while the second control module 22 and the output module 23 do not output. In this case, the shift register outputs the first power supply signal VGH1 as the gate scan signal OUT.

[0078] When the first frequency control signal Ctrl1 is invalid, and the initial scan signal Next and the second frequency control signal Ctrl2 are both valid, for example... Figure 4As shown, when the second frequency control signal Ctrl2 is low and the initial scan signal Next and the first frequency control signal Ctrl1 are both high, the second control module 22 outputs the second power supply signal VGH2, while the first control module 21 and the output module 23 do not output. In this case, the shift register outputs the second power supply signal VGH2 as the gate scan signal OUT.

[0079] When both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid, for example Figure 5 As shown, when both the second frequency control signal Ctrl2 and the first frequency control signal Ctrl1 are high, the output module 23 outputs the third power supply signal VGL, and the first control module 21 and the second control module 22 do not output. In this case, the shift register outputs the third power supply signal VGL as the gate scan signal OUT.

[0080] In the shift register provided in this application embodiment, the control module 20 controls the gate scan signal OUT output by the first output node SOUT of the output module 23 through the first control module 21, the second control module 22 and the output module 23 respectively. This realizes the switching of the first power signal VGH1, the second power signal VGH2 or the third power signal VGL output by the gate scan signal OUT according to the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2. This is to compensate for the display brightness difference of different display areas through the gate scan signal OUT with different potentials, thereby achieving the purpose of balancing display brightness and improving display uniformity.

[0081] Figure 7 This is a schematic diagram of the structure of a control module 20 provided in an embodiment of this application. Figure 8 This is a schematic diagram of another control module 20 provided in an embodiment of this application. Figure 9 This is a schematic diagram of the structure of another control module 20 provided in an embodiment of this application.

[0082] Combination Figures 7 to 9 As shown, in some embodiments, both the first control module 21 and the second control module 22 include a first control unit 210 and a second control unit 220, that is, the first control module 21 includes a first control unit 210 and a second control unit 220, and the second control module 22 includes a first control unit 210 and a second control unit 220.

[0083] The first control unit 210 is connected to the target node of the drive module 10. The first control unit 210 is used to receive the target node signal, the target frequency control signal, and the third power supply signal VGL from the target node, and to control the output of a first control signal. The first control unit 210 can control the output of the first control signal under the action of the target node signal, the target frequency control signal, and the third power supply signal VGL.

[0084] The second control unit 220 is connected to the first control unit 210, the first output node SOUT, the first node N1 of the drive module 10, and the second node N2 of the drive module 10. The second control unit 220 receives a first control signal, a first node signal of the first node N1, a second node signal of the second node N2, and a target power signal, and controls the gate scan signal OUT output by the first output node SOUT. The first control unit 210, under the influence of the first control signal, the first node signal, the second node signal, and the target power signal, controls the first output node SOUT to select and output the first power signal VGH1.

[0085] In the first control module 21, the target node is the second output node NEXT of the drive module 10, the target node signal is the initial scan signal Next, the target frequency control signal is the first frequency control signal Ctrl1, and the target power signal is the first power signal VGH1. Specifically, in the first control module 21, the first control unit 211 is connected to the second output node NEXT of the drive module 10. The first control unit 211 is used to receive the initial scan signal Next, the first frequency control signal Ctrl1, and the third power signal VGL, and control the first control signal output by the first control node R1. The second control unit 221 is connected to the first control node R1, the first output node SOUT, the first node N1, and the second node N2, respectively. The second control unit 221 is used to receive the first control signal, the first node signal, the second node signal, and the first power signal VGH1 output by the first control node R1, and control the gate scan signal OUT output by the first output node SOUT.

[0086] In the second control module 22, the target node is the first node N1, the target node signal is the first node signal, the target frequency control signal is the second frequency control signal Ctrl2, and the target power signal is the second power signal VGH2. Specifically, in the second control module 22, the first control unit 212 is connected to the first node N1. The first control unit 212 is used to receive the first node signal, the second frequency control signal Ctrl2, and the third power signal VGL, and control the first control signal output by the second control node R2. The second control unit 222 is connected to the second control node R2, the first output node SOUT, the first node N1, and the second node N2. The second control unit 222 is used to receive the first control signal, the first node signal, the second node signal, and the second power signal VGH2 output by the second control node R2, and control the gate scan signal OUT output by the first output node SOUT.

[0087] In the shift register provided in this application embodiment, the first control module 21, through the first control unit 211 and the second control unit 221, effectively controls the gate scan signal OUT output by the first output node SOUT according to the first frequency control signal Ctrl1. The second control module 22, through the first control unit 212 and the second control unit 222, effectively controls the gate scan signal OUT output by the first output node SOUT according to the second frequency control signal Ctrl2. In this way, the gate scan signal OUT can be switched between the first power signal VGH1 and the second power signal VGH2 to compensate for the difference in display brightness, thereby improving display uniformity.

[0088] Please continue reading. Figures 7 to 9 In some embodiments, the first control unit 210 includes a first transistor T1 and a first capacitor C1. The gate of the first transistor T1 is connected to the target node. The first terminal of the first transistor T1 is connected to the second control unit 220 and the first terminal of the first capacitor C1, respectively, and the first terminal of the first transistor T1 is used to output a first control signal. The second terminal of the first transistor T1 is used to receive a target frequency control signal. The second terminal of the first capacitor C1 is used to receive a third power supply signal VGL.

[0089] In the first control module 21, the first control unit 211 includes a first transistor T1_1 and a first capacitor C1_1. The gate of the first transistor T1_1 is connected to the second output node NEXT, the first terminal of the first transistor T1_1 is connected to the first terminal of the first capacitor C1_1, the first terminal of the first transistor T1_1 serves as the first control node R1 of the first control module 21, the second terminal of the first transistor T1_1 is used to receive the first frequency control signal Ctrl1, and the second terminal of the first capacitor C1_1 is used to receive the third power supply signal VGL.

[0090] In the second control module 22, the first control unit 212 includes a first transistor T1_2 and a first capacitor C1_2. The gate of the first transistor T1_2 is connected to the first node N1, the first terminal of the first transistor T1_2 is connected to the first terminal of the first capacitor C1_2, the first terminal of the first transistor T1_2 serves as the second control node R2 of the second control module 22, the second terminal of the first transistor T1_2 is used to receive the second frequency control signal Ctrl2, and the second terminal of the first capacitor C1_2 is used to receive the third power supply signal VGL.

[0091] In the shift register provided in this application embodiment, the first control unit 210, through the first transistor T1 and the first capacitor C1, effectively controls the first control signal according to the target node signal, the target frequency control signal and the third power supply signal VGL. In combination with the second control unit 220, the output of the gate scan signal OUT is switched according to the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 to compensate for the difference in display brightness and improve the uniformity of display.

[0092] Please continue reading. Figure 9 In some embodiments, the first transistor T1 includes a dual-gate transistor. Exemplarily, the first transistor T1 includes a first sub-transistor and a second sub-transistor, wherein the gates of the first and second sub-transistors are respectively connected to the target node, the first terminal of the first sub-transistor is respectively connected to the first terminal of the second control unit 220 and the first capacitor C1, the second terminal of the first sub-transistor is connected to the first terminal of the second sub-transistor, and the second terminal of the second sub-transistor is used to receive a target frequency control signal.

[0093] In the first control module 21, the first transistor T1_1 includes a first sub-transistor T1_11 and a second sub-transistor T1_12. The gates of the first sub-transistor T1_11 and the second sub-transistor T1_12 are respectively connected to the second output node NEXT. The first terminal of the first sub-transistor T1_11 is connected to the first terminal of the first capacitor C1_1. The first terminal of the first sub-transistor T1_11 serves as the first control node R1 of the first control module 21. The second terminal of the first sub-transistor T1_11 is connected to the first terminal of the second sub-transistor T1_12 of the first control module 21. The second terminal of the second sub-transistor T1_12 is used to receive the first frequency control signal Ctrl1.

[0094] In the second control module 22, the first transistor T1_2 includes a first sub-transistor T1_21 and a second sub-transistor T1_22. The gates of the first sub-transistor T1_21 and the second sub-transistor T1_22 are respectively connected to the first node N1. The first terminal of the first sub-transistor T1_21 is connected to the first terminal of the first capacitor C1_2, and the first terminal of the first sub-transistor T1_21 serves as the second control node R2 of the second control module 22. The second terminal of the first sub-transistor T1_21 is connected to the first terminal of the second sub-transistor T1_22 of the second control module 22. The second terminal of the second sub-transistor T1_22 is used to receive the second frequency control signal Ctrl2.

[0095] In the shift register provided in this application embodiment, the first transistor T1 is a dual-gate transistor, which can prevent leakage current, reduce the leakage current of the target frequency control signal to the second control unit 220, improve the reliability and stability of the shift register, thereby improving the reliability of the display panel in which the shift register is applied, and thus improving the display effect.

[0096] Please continue reading. Figures 7 to 9 In some embodiments, the first transistor T1 is a P-type transistor. For example, the first transistor T1 is a P-type thin-film transistor (TFT) or a P-type metal-oxide-semiconductor field-effect transistor (MOSFET / MOS). Thus, the effective pulse of the target node signal is a low-level signal, and the invalid pulse is a high-level signal. Based on this, when the target node signal is low, the first transistor T1 is off; when the target node signal is high, the first transistor T1 is on. The on / off state of the path from the target frequency control signal to the second control unit 220 is controlled by controlling the on / off state of the first transistor T1, i.e., the first control unit 210, through the target node signal.

[0097] Please continue reading. Figures 7 to 9 In some embodiments, the second control unit 220 includes a second transistor T2, a third transistor T3, and a fourth transistor T4. The gate of the second transistor T2 is connected to the first control unit 210. The first terminal of the second transistor T2 is connected to the second node N2. The second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the gate of the fourth transistor T4, respectively. The gate of the third transistor T3 is connected to the first node N1. The first terminals of the third transistor T3 and the fourth transistor T4 are used to receive target power signals. The second terminal of the fourth transistor T4 is connected to the first output node SOUT.

[0098] In the first control module 21, the second control unit 221 includes a second transistor T2_1, a third transistor T3_1, and a fourth transistor T4_1. The gate of the second transistor T2_1 is connected to the first control node R1. The first terminal of the second transistor T2_1 is connected to the second node N2. The second terminal of the second transistor T2_1 is connected to the seventh control node R7, which is connected to both the second terminal of the third transistor T3_1 and the gate of the fourth transistor T4_1. The gate of the third transistor T3_1 is connected to the first node N1. The first terminals of the third transistor T3_1 and the fourth transistor T4_1 are used to receive the first power supply signal VGH1. The second terminal of the fourth transistor T4_1 is connected to the first output node SOUT.

[0099] In the second control module 22, the second control unit 222 includes a second transistor T2_2, a third transistor T3_2, and a fourth transistor T4_2. The gate of the second transistor T2_2 is connected to the second control node R2. The first terminal of the second transistor T2_2 is connected to the second node N2. The second terminal of the second transistor T2_2 is connected to the eighth control node R8, which is connected to both the second terminal of the third transistor T3_2 and the gate of the fourth transistor T4_2. The gate of the third transistor T3_2 is connected to the first node N1. The first terminals of the third transistor T3_2 and the fourth transistor T4_2 are used to receive the second power supply signal VGH2. The second terminal of the fourth transistor T4_2 is connected to the first output node SOUT.

[0100] In the shift register provided in this application embodiment, the second control unit 220 effectively controls the gate scan signal OUT output by the first output node SOUT through the second transistor T2, the third transistor T3 and the fourth transistor T4, so as to compensate for the difference in display brightness and achieve the purpose of improving display uniformity.

[0101] Please continue reading. Figure 8 and Figure 9 In some embodiments, the second control unit 220 further includes a second capacitor C2, which is connected to the first terminal and the gate of the fourth transistor T4, respectively. The second capacitor C2 can improve the stability of the gate scan signal OUT output by the first output node SOUT.

[0102] In the first control module 21, the second control unit 221 further includes a second capacitor C2_1, which is connected to the first terminal and the gate of the fourth transistor T4_1, respectively. The second capacitor C2_1 helps improve the stability of the first control module 21 controlling the first output node SOUT to output the first power signal VGH1 as the gate scan signal OUT.

[0103] In the second control module 22, the second control unit 222 further includes a second capacitor C2_2, which is connected to the first terminal and the gate of the fourth transistor T4_2, respectively. The second capacitor C2_2 helps improve the stability of the second control module 22 controlling the first output node SOUT to output the second power signal VGH2 as the gate scan signal OUT.

[0104] Please continue reading. Figures 7 to 9 In some embodiments, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all P-type transistors. For example, the second transistor T2 can be a PTFT or a PMOS, the third transistor T3 can be a PTFT or a PMOS, and the fourth transistor T4 can be a PTFT or a PMOS. Thus, the effective pulses of the first node signal and the first control signal are low-level signals, and the invalid pulses are high-level signals. Based on this, when the first control signal is low, the second transistor T2 is off; when the first control signal is high, the second transistor T2 is on. When the first node signal is low, the third transistor T3 is off; when the first node signal is high, the third transistor T3 is on. Specifically, the first control signal controls the on / off state of the second transistor T2, and the first node signal controls the on / off state of the third transistor T3. Combined with the fourth transistor T4, this effectively controls the gate scan signal OUT output by the first output node SOUT. This allows the first output node SOUT to switch between the first power supply signal VGH1 and the second power supply signal VGH2. Furthermore, the potential difference between the power supply signals compensates for the differences in the drift characteristics of the transistors in the pixel circuit, thereby balancing the display brightness and improving display uniformity.

[0105] Figure 10 This is a schematic diagram of a control module 20 provided in an embodiment of this application. (In conjunction with...) Figure 10 As shown, in some embodiments, both the first control module 21 and the second control module 22 include a third control unit 230 and a fourth control unit 240, that is, the first control module 21 includes a third control unit 230 and a fourth control unit 240, and the second control module 22 includes a third control unit 230 and a fourth control unit 240.

[0106] The third control unit 230 is connected to the second output node NEXT of the drive module 10 and the first output node SOUT of the output module 23, respectively. The third control unit 230 is used to receive the initial scan signal Next, the target frequency control signal and the third power supply signal VGL, and to control the output of the second control signal and the third control signal.

[0107] The fourth control unit 240 is connected to the third control unit 230, the first output node SOUT, and the second output node NEXT. The fourth control unit 240 is used to receive the second control signal, the third control signal, the initial scan signal Next, and the target power signal, and to control the gate scan signal OUT output by the first output node SOUT.

[0108] In the first control module 21, the target frequency control signal is the first frequency control signal Ctrl1, and the target power signal is the first power signal VGH1. Specifically, in the first control module 21, the third control unit 231 is connected to the second output node NEXT and the first output node SOUT, respectively. The third control unit 231 is used to receive the initial scan signal Next, the first frequency control signal Ctrl1, and the third power signal VGL, and to control the second control signal output by the third control node R3 and the third control signal output by the fourth control node R4. The fourth control unit 241 is connected to the third control node R3, the fourth control node R4, the first output node SOUT, and the second output node NEXT, respectively. The fourth control unit 241 is used to receive the second control signal output by the third control node R3, the third control signal output by the fourth control node R4, the initial scan signal Next, and the first power signal VGH1, and to control the gate scan signal OUT output by the first output node SOUT.

[0109] In the second control module 22, the target frequency control signal is the second frequency control signal Ctrl2, and the target power signal is the second power signal VGH2. Specifically, in the second control module 22, the third control unit 232 is connected to the second output node NEXT and the first output node SOUT, respectively. The third control unit 232 is used to receive the initial scan signal Next, the second frequency control signal Ctrl2, and the third power signal VGL, and to control the second control signal output by the fifth control node R5 and the third control signal output by the sixth control node R6. The fourth control unit 242 is connected to the fifth control node R5, the sixth control node R6, the first output node SOUT, and the second output node NEXT, respectively. The fourth control unit 242 is used to receive the second control signal output by the fifth control node R5, the third control signal output by the sixth control node R6, the initial scan signal Next, and the second power signal VGH2, and to control the gate scan signal OUT output by the first output node SOUT.

[0110] In the shift register provided in this application embodiment, the first control module 21, through the third control unit 231 and the fourth control unit 241, effectively controls the gate scan signal OUT output by the first output node SOUT according to the first frequency control signal Ctrl1, and the second control module 22, through the third control unit 232 and the fourth control unit 242, effectively controls the gate scan signal OUT output by the first output node SOUT according to the second frequency control signal Ctrl2. In this way, the gate scan signal OUT can be switched between the first power signal VGH1 and the second power signal VGH2 to compensate for the difference in display brightness, thereby improving display uniformity.

[0111] Please continue reading. Figure 10 In some embodiments, the third control unit 230 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is connected to the second output node NEXT and the gate of the seventh transistor T7, respectively. The first terminal of the fifth transistor T5 is connected to the gate of the sixth transistor T6 and the fourth control unit 240, respectively. The first terminal of the fifth transistor T5 is used to output a third control signal. The second terminal of the fifth transistor T5 is used to receive a target frequency control signal. The first terminal of the sixth transistor T6 is connected to the first terminal of the seventh transistor T7. The second terminal of the sixth transistor T6 is connected to the fourth control unit 240. The second terminal of the sixth transistor T6 is used to output a second control signal. The second terminal of the seventh transistor T7 is used to receive a third power supply signal VGL.

[0112] In the first control module 21, the third control unit 231 includes a fifth transistor T5_1, a sixth transistor T6_1, and a seventh transistor T7_1. The gate of the fifth transistor T5_1 is connected to the second output node NEXT and the gate of the seventh transistor T7_1, respectively. The first terminal of the fifth transistor T5_1 is connected to the gate of the sixth transistor T6_1 and the fourth control node R4, respectively. The first terminal of the fifth transistor T5_1 serves as the fourth control node R4 and is used to output a third control signal. The second terminal of the fifth transistor T5_1 is used to receive a first frequency control signal Ctrl1. The first terminal of the sixth transistor T6_1 is connected to the first terminal of the seventh transistor T7_1. The second terminal of the sixth transistor T6_1 is connected to the fourth control unit 241. The second terminal of the sixth transistor T6_1 serves as the third control node R3 and is used to output a second control signal. The second terminal of the seventh transistor T7_1 is used to receive a third power supply signal VGL.

[0113] In the second control module 22, the third control unit 232 includes a fifth transistor T5_2, a sixth transistor T6_2, and a seventh transistor T7_2. The gate of the fifth transistor T5_2 is connected to the second output node NEXT and the gate of the seventh transistor T7_2, respectively. The first terminal of the fifth transistor T5_2 is connected to the gate of the sixth transistor T6_2 and the sixth control node R6, respectively. The first terminal of the fifth transistor T5_2 serves as the sixth control node R6 and is used to output a third control signal. The second terminal of the fifth transistor T5_2 is used to receive a second frequency control signal Ctrl2. The first terminal of the sixth transistor T6_2 is connected to the first terminal of the seventh transistor T7_2. The second terminal of the sixth transistor T6_2 is connected to the fourth control unit 242. The second terminal of the sixth transistor T6_2 serves as the fifth control node R5 and is used to output a second control signal. The second terminal of the seventh transistor T7_2 is used to receive a third power supply signal VGL.

[0114] In the shift register provided in this application embodiment, the third control unit 230 effectively controls the second and third control signals through the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to compensate for the difference in display brightness and achieve the purpose of improving display uniformity.

[0115] Please continue reading. Figure 10 In some embodiments, the fifth transistor T5 is a P-type transistor, and the sixth transistor T6 and the seventh transistor T7 are both N-type transistors. For example, the fifth transistor T5 can be a PTFT or PMOS, the sixth transistor T6 can be an NTFT or NMOS, and the seventh transistor T7 can be an NTFT or NMOS. Thus, when the initial scan signal Next is high, the fifth transistor T5 is off and the seventh transistor T7 is on. When the initial scan signal Next is low, the fifth transistor T5 is on and the seventh transistor T7 is off; in this case, when the target frequency control signal is low, the sixth transistor T6 is on; when the target frequency control signal is high, the sixth transistor T6 is off. The on / off states of the fifth transistor T5 and the seventh transistor T7 are controlled by the initial scan signal Next, and the on / off state of the sixth transistor T6 is controlled by the target frequency control signal, thereby achieving effective control of the second and third control signals output by the third control unit 230.

[0116] Please continue reading. Figure 10In some embodiments, the fourth control unit 240 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a third capacitor C3; wherein, the gate of the eighth transistor T8 is connected to the second output node NEXT; the first terminal of the eighth transistor T8, the second terminal of the ninth transistor T9, the first terminal of the tenth transistor T10, and the first terminal of the third capacitor C3 are connected, and the first terminal of the eighth transistor T8 is used to receive the target power signal; the second terminal of the eighth transistor T8 is connected to the third control unit 230, the first terminal of the ninth transistor T9, and the gate of the tenth transistor T10, respectively; the gate of the ninth transistor T9 is connected to the second terminal of the third control unit 230 and the third capacitor C3, respectively; and the second terminal of the tenth transistor T10 is connected to the first output node SOUT.

[0117] In the first control module 21, the fourth control unit 241 includes an eighth transistor T8_1, a ninth transistor T9_1, a tenth transistor T10_1, and a third capacitor C3_1. The gate of the eighth transistor T8_1 is connected to the second output node NEXT. The first terminal of the eighth transistor T8_1, the second terminal of the ninth transistor T9_1, the first terminal of the tenth transistor T10_1, and the first terminal of the third capacitor C3_1 are connected. The first terminal of the eighth transistor T8_1 is used to receive the first power supply signal VGH1. The second terminal of the eighth transistor T8_1 is connected to the third control node R3, the first terminal of the ninth transistor T9_1, and the gate of the tenth transistor T10_1, respectively. The gate of the ninth transistor T9_1 is connected to the fourth control node R4 and the second terminal of the third capacitor C3_1, respectively. The second terminal of the tenth transistor T10_1 is connected to the first output node SOUT.

[0118] In the second control module 22, the fourth control unit 242 includes an eighth transistor T8_2, a ninth transistor T9_2, a tenth transistor T10_2, and a third capacitor C3_2. The gate of the eighth transistor T8_2 is connected to the second output node NEXT. The first terminal of the eighth transistor T8_2, the second terminal of the ninth transistor T9_2, the first terminal of the tenth transistor T10_2, and the first terminal of the third capacitor C3_2 are connected. The first terminal of the eighth transistor T8_2 is used to receive the second power supply signal VGH2. The second terminal of the eighth transistor T8_2 is connected to the fifth control node R5, the first terminal of the ninth transistor T9_2, and the gate of the tenth transistor T10_2, respectively. The gate of the ninth transistor T9_2 is connected to the sixth control node R6 and the second terminal of the third capacitor C3_2, respectively. The second terminal of the tenth transistor T10_2 is connected to the first output node SOUT.

[0119] In the shift register provided in this application embodiment, the fourth control unit 240, through the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the third capacitor C3, in conjunction with the third control unit 230, realizes effective control of the gate scan signal OUT output by the first output node SOUT, so as to compensate for the difference in display brightness and achieve the purpose of improving display uniformity.

[0120] Please continue reading. Figure 10 In some embodiments, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all P-type transistors. For example, the eighth transistor T8 can be a PTFT or a PMOS, the ninth transistor T9 can be a PTFT or a PMOS, and the tenth transistor T10 can be a PTFT or a PMOS. When the initial scan signal Next is high, the eighth transistor T8 is off; when the initial scan signal Next is low, the eighth transistor T8 is on. When the second control signal is high, the tenth transistor T10 is off; when the second control signal is low, the tenth transistor T10 is on. When the third control signal is high, the ninth transistor T9 is off; when the third control signal is low, the ninth transistor T9 is on. In this case, the fourth control unit 240 controls the first output node SOUT to output the target power signal. Thus, by using the initial scan signal Next, the second control signal, and the third control signal, the on / off control of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 is achieved, thereby realizing the effective control of the gate scan signal OUT by the fourth control unit 240.

[0121] Please continue reading. Figures 7 to 10 In some embodiments, the output module 23 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is connected to the third node N3 of the driving module 10, the first terminal of the eleventh transistor T11 is connected to the first output node SOUT, and the second terminal of the eleventh transistor T11 is used to receive the third power supply signal VGL. Thus, the output module 23 controls the gate scan signal OUT of the first output node SOUT through the eleventh transistor T11, so that even when the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both invalid, the first output node SOUT can output the third power supply signal VGL, thereby ensuring the normal output of the gate scan signal OUT.

[0122] Please continue reading. Figures 7 to 10In some embodiments, the eleventh transistor T11 is a P-type transistor. The eleventh transistor T11 can be a PTFT or a PMOS. Thus, when the third node signal of the third node N3 is high, the eleventh transistor T11 is off; when the third node signal is low, the eleventh transistor T11 is on. In this case, the output module 23 controls the first output node SOUT to output the third power signal VGL. Therefore, by controlling the on / off state of the eleventh transistor T11 through the third node signal, effective control is achieved over the path of the third power signal VGL to the first output node SOUT, thereby ensuring that the first output node SOUT can effectively output the third power signal VGL.

[0123] Please continue reading. Figures 7 to 10 In some embodiments, the output module 23 further includes a fourth capacitor C4, which is connected to the first terminal and the gate of the eleventh transistor T11. Thus, the stability of the gate scan signal OUT can be improved through the fourth capacitor C4.

[0124] Figure 11 This is a schematic diagram of a drive module 10 provided in an embodiment of this application. (In conjunction with...) Figure 11 As shown, in some embodiments, the drive module 10 includes an input module 11, a first drive module 12, and a second drive module 13. The input module 11 receives a start signal STV and a first clock signal CK, and controls the first node signal of the first node N1 and the fourth node signal of the fourth node N4. The first drive module 12 receives the first node signal, the fourth node signal, the first clock signal CK, the second clock signal XCK, the first power signal VGH1, and the third power signal VGL, and controls the second node signal of the second node N2 and the third node signal of the third node N3. The second drive module 13 receives the second node signal, the third node signal, the first power signal VGH1, and the third power signal VGL, and controls the second output node NEXT to output the initial scan signal Next.

[0125] Figure 12 This is a schematic diagram of the structure of a drive module 10 provided in an embodiment of this application. Figure 13 This is a schematic diagram of another driving module 10 provided in an embodiment of this application. (In conjunction with...) Figure 12 and Figure 13As shown, in some embodiments, the second driving module 13 includes a twelfth transistor T12, a thirteenth transistor T13, and a fifth capacitor C5. The first terminal of the twelfth transistor T12 is used to receive a first power supply signal VGH1, and the first terminal of the twelfth transistor T12 is connected to the first terminal of the fifth capacitor C5. The second terminal of the twelfth transistor T12 is connected to the first terminal of the thirteenth transistor T13, which serves as the second output node NEXT. The gate of the twelfth transistor T12 is connected to the second terminal of the fifth capacitor C5 and the second node N2, respectively. The gate of the thirteenth transistor T13 is connected to the third node N3, and the second terminal of the thirteenth transistor T13 is used to receive a third power supply signal VGL.

[0126] Please continue reading. Figure 12 and Figure 13 In some embodiments, both the twelfth transistor T12 and the thirteenth transistor T13 are P-type transistors. For example, the twelfth transistor T12 can be a PTFT or a PMOS; the thirteenth transistor T13 can be a PTFT or a PMOS. When the second node signal is high, the twelfth transistor T12 is off; when the second node signal is low, the twelfth transistor T12 is on. In this case, the first power supply signal VGH1 is transmitted to the second output node NEXT through the twelfth transistor T12. When the third node signal is high, the thirteenth transistor T13 is off; when the third node signal is low, the thirteenth transistor T13 is on. In this case, the third power supply signal VGL is transmitted to the second output node NEXT through the thirteenth transistor T13.

[0127] In the shift register provided in this application embodiment, the second driving module 13 in the driving module 10 includes a twelfth transistor T12, a thirteenth transistor T13, and a fifth capacitor C5. The on / off control of the twelfth transistor T12 is realized through the second node signal, and the on / off control of the thirteenth transistor T13 is realized through the third node signal, thereby realizing effective control of the gate scan signal OUT output by the first output node SOUT. In addition, the fifth capacitor C5 can improve the stability of the gate scan signal OUT output by the first output node SOUT.

[0128] Please continue reading. Figure 12 and Figure 13In some embodiments, the input module 11 includes a fourteenth transistor T14 and a fifteenth transistor T15. The gates of the fourteenth transistor T14 and the fifteenth transistor T15 are respectively used to receive a first clock signal CK. The first terminal of the fourteenth transistor T14 and the second terminal of the fifteenth transistor T15 are respectively used to receive a start signal STV. The second terminal of the fourteenth transistor T14 is connected to a first node N1, and the first terminal of the fifteenth transistor T15 is connected to a fourth node N4.

[0129] Please continue reading. Figure 12 and Figure 13 In some embodiments, both the fourteenth transistor T14 and the fifteenth transistor T15 are P-type transistors. For example, the fourteenth transistor T14 can be a PTFT or a PMOS; the fifteenth transistor T15 can be a PTFT or a PMOS. When the first clock signal CK is high, both the fourteenth transistor T14 and the fifteenth transistor T15 are off; when the first clock signal CK is low, both the fourteenth transistor T14 and the fifteenth transistor T15 are on. In this case, the start signal STV is transmitted to the first node N1 through the fourteenth transistor T14, and the start signal STV is transmitted to the fourth node through the fifteenth transistor T15.

[0130] In the shift register provided in this application embodiment, the input module 11 in the drive module 10 includes a fourteenth transistor T14 and a fifteenth transistor T15, and the on / off control of the fourteenth transistor T14 and the fifteenth transistor T15 is realized through the first clock signal CK, thereby realizing effective control of the first node N1 outputting the first node signal and the fourth node outputting the fourth node signal respectively.

[0131] Please continue reading. Figure 12 and Figure 13 In some embodiments, the first driving module 12 includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, a sixth capacitor C6, and a seventh capacitor C7.

[0132] The first terminal of the sixteenth transistor T16 is connected to the fifth node N5. The second terminal of the sixteenth transistor T16 is used to receive the third power supply signal VGL, and the gate of the sixteenth transistor T16 is used to receive the first clock signal CK. The first terminal of the seventeenth transistor T17 is connected to the fifth node N5. The second terminal of the seventeenth transistor T17 is used to receive the first clock signal CK, and the gate of the seventeenth transistor T17 is connected to the first node N1. The first terminal of the eighteenth transistor T18 is connected to the sixth node N6. The second terminal of the eighteenth transistor T18 is connected to the fifth node N5, and the gate of the eighteenth transistor T18 is used to receive the third power supply signal VGL.

[0133] The first terminal of the sixth capacitor C6 is connected to the sixth node N6, and the second terminal of the sixth capacitor C6 is connected to the seventh node N7. The first terminal of the nineteenth transistor T19 is connected to the seventh node N7, the second terminal of the nineteenth transistor T19 is used to receive the second clock signal XCK, and the gate of the nineteenth transistor T19 is connected to the sixth node N6. The first terminal of the twentieth transistor T20 is connected to the seventh node N7, the second terminal of the twentieth transistor T20 is connected to the second node N2, and the gate of the twentieth transistor T20 is used to receive the second clock signal XCK. The first terminal of the twenty-first transistor T21 is connected to the second node N2, the second terminal of the twenty-first transistor T21 is used to receive the first power supply signal VGH1, and the gate of the twenty-first transistor T21 is connected to the first node N1.

[0134] The first terminal of transistor T22 is connected to the first node N1, and the second terminal of transistor T22 is connected to the third node N3. The gate of transistor T22 is used to receive the third power supply signal VGL. The first terminal of transistor T23 is connected to the eighth node N8, and the second terminal of transistor T23 is connected to the fourth node N4. The gate of transistor T23 is used to receive the third power supply signal VGL. The first terminal of transistor T24 is connected to the third node N3, and the second terminal and gate of transistor T24 are both connected to the eighth node N8.

[0135] The first terminal of the seventh capacitor C7 is connected to the eighth node N8, and the second terminal of the seventh capacitor C7 is connected to the ninth node N9. The first terminal of the twenty-fifth transistor T25 is used to receive the first power supply signal VGH1, the second terminal of the twenty-fifth transistor T25 is connected to the ninth node N9, and the gate of the twenty-fifth transistor T25 is connected to the fifth node N5. The first terminal of the twenty-sixth transistor T26 is connected to the ninth node N9, the second terminal of the twenty-sixth transistor T26 is used to receive the second clock signal XCK, and the gate of the twenty-sixth transistor T26 is connected to the eighth node N8. The first terminal of the twenty-seventh transistor T27 is connected to the first node N1, the second terminal of the twenty-seventh transistor T27 is used to receive the first power supply signal VGH1, and the gate of the twenty-seventh transistor T27 is used to receive the reset signal RST.

[0136] Please continue reading. Figure 12 and Figure 13 In some embodiments, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the twenty-sixth transistor T26, and the twenty-seventh transistor T27 are all P-type transistors, for example, PTFT or PMOS; based on this, transistors T16 to T27 are turned off in response to a high level and turned on in response to a low level, so as to achieve effective control of the second node signal output by the second node N2 and the third node signal of the third node N3.

[0137] Please continue reading. Figure 13 In some embodiments, the seventeenth transistor T17 can be a dual-gate transistor, for example, including a third sub-transistor and a fourth sub-transistor. The gates of the third and fourth sub-transistors are respectively connected to the first node N1. The first terminal of the third sub-transistor is connected to the fifth node, and the second terminal of the third sub-transistor is connected to the first terminal of the fourth sub-transistor. The second terminal of the fourth sub-transistor is used to receive the first clock signal CK. This prevents leakage current, reduces the leakage of the first clock signal CK to the fifth node, and improves the stability of the initial scan signal Next output by the drive module 10.

[0138] Figure 14 This is a schematic diagram of a shift register provided in an embodiment of this application. Figure 15 This is a timing diagram illustrating multiple signals in a scenario where a shift register outputs a first power signal VGH1, as provided in an embodiment of this application. Figure 16 This is a timing diagram of multiple signals in a scenario where a shift register outputs a third power supply signal VGL, as provided in an embodiment of this application.

[0139] Combination Figures 14 to 16 As shown, in some embodiments, a shift register is provided, which includes a driver module 10 and a control module 20. The driver module 10 can employ the methods described in the foregoing embodiments. Figure 13 The provided 16T3C structure; the control module 20 can adopt the aforementioned embodiments and Figure 9 The provided structure is a 9T5C; where each transistor is a P-type transistor, "T" represents a transistor, and "C" represents a capacitor. Detailed descriptions of the drive module 10 and control module 20 can be found in the preceding text and will not be repeated here.

[0140] In applications, shift registers are used in pixel circuits connected to the display panel. This will be explained using the example of a high-frequency display area corresponding to the pixel circuit.

[0141] like Figure 14 and Figure 15 As shown, during the refresh phase of the display panel, the first frequency control signal Ctrl1 is a valid pulse, i.e., it remains at a low level, and the third transistor T18 is normally open; under this condition, the second frequency control signal Ctrl2 is an invalid pulse, i.e., it is at a high level.

[0142] During the T1 stage of the refresh phase, the drive module 10 writes the start signal STV, and the third node N3 writes a high level. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned off, the potential of the second node N2 is maintained at VGH1, the twelfth transistor T9 and the fourth transistor T20 are turned off, and the initial scan signal Next and the gate scan signal OUT are both maintained at the output low level VGL.

[0143] During the T2 stage of the refresh phase, the second clock signal XCK changes from high level to low level. At this time, the second node N2 and the seventh control node R7 write low level VGL, the twelfth transistor T9 and the fourth transistor T20 are turned on, and the initial scan signal Next and the gate scan signal OUT both output high level VGH1.

[0144] During the T3 stage of the refresh phase, the first clock signal CK is written to STV at a low level. At this time, the third node N3 is at a low level. VGH1 is written to the second node N2 and the seventh control node R7 through the twenty-first transistor T6. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned on, and the twelfth transistor T9 and the fourth transistor T20 are turned off. The initial scan signal Next and the gate scan signal OUT both output the third power supply signal VGL, which is at a low level.

[0145] like Figure 14 and Figure 16As shown, during the maintenance phase of the display panel, both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid pulses, i.e., they remain at a high level, and the third transistor T18 is off. During stage T4 of the maintenance phase, because the third transistor T18 is off, the low level of the second node N2 cannot be transmitted to the seventh control node R7. Therefore, the gate scan signal OUT maintains the third power supply signal VGL at a low level, and the target power supply signal (high level) cannot be output. Under these circumstances, the pixel circuit of the display panel is in a maintenance state.

[0146] Figure 17 This application provides a schematic diagram of the structure of a shift register. Figure 18 This is a timing diagram illustrating multiple signals in a scenario where a shift register outputs a first power signal VGH1, as provided in an embodiment of this application. Figure 19 This is a timing diagram of multiple signals in a shift register outputting a third power supply signal VGHL scenario, provided as an embodiment of this application.

[0147] Combination Figures 17 to 19 As shown, in some embodiments, a shift register is provided, which includes a driver module 10 and a control module 20. The driver module 10 employs the aforementioned embodiments and... Figure 13 The provided 16T3C structure uses P-type transistors for all transistors; the control module 20 adopts the aforementioned embodiment and... Figure 10 The provided 13T3C structure includes N-type transistors (T5 and T6) and P-type transistors for the fifth and sixth transistors, respectively. Detailed descriptions of the drive module 10 and control module 20 can be found in the preceding text and will not be repeated here.

[0148] In applications, shift registers are used in pixel circuits connected to the display panel. This will be explained using the example of a high-frequency display area corresponding to the pixel circuit.

[0149] During the refresh phase of the display panel, the first frequency control signal Ctrl1 is a valid pulse, i.e., it remains at a high level. At this time, the ninth transistor T9 is normally off and the sixth transistor T6 is normally on. Under these circumstances, the second frequency control signal Ctrl2 is an invalid pulse, i.e., it is at a low level.

[0150] like Figure 17 and Figure 18As shown, in the T5 stage of the refresh phase, the drive module 10 writes the start signal STV, and the third node N3 writes a high level. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned off, the second node N2, the seventh control node R7 and the fifth control node R5 are maintained at a high level, the twelfth transistor T9 and the tenth transistor T10 are turned off, and the initial scan signal Next and the gate scan signal OUT both maintain the output of the third power supply signal VGL.

[0151] During the T6 stage of the refresh phase, the second clock signal XCK changes from high level to low level. At this time, the second node N2, the seventh control node R7, and the fifth control node R5 write low level VGL. The twelfth transistor T9 and the tenth transistor T10 are turned on. The initial scan signal Next and the gate scan signal OUT both output high level VGH1, i.e., high level. The eighth transistor T8 is turned off, and the ninth transistor T9 is turned on.

[0152] During the T7 stage of the refresh phase, the first clock signal CK is written low. At this time, the third node N3 is low. The high level is written to the second node N2, the seventh control node R7, and the fifth control node R5 through the first transistor T6. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned on, and the twelfth transistor T9 and the tenth transistor T10 are turned off. Next outputs a low level, the fifth transistor T5 is turned off, the eighth transistor T8 is turned on, and the high level is written to the third control node R3 and the fifth control node R5.

[0153] like Figure 17 and Figure 19 As shown, during the maintenance phase of the display panel, both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid pulses, i.e., they remain at a low level. The ninth transistor T9 is turned on, and the sixth transistor T6 is turned off. During stage T8 of the maintenance phase, since the sixth transistor T6 is turned off, the low level cannot be transmitted to the seventh control node R7 and the fifth control node R5. Therefore, at this time, the first output node SOUT outputs the gate scan signal OUT at a low level and cannot output a high level, and the pixel circuit is in a maintenance state.

[0154] It should be noted that in application, the control logic for outputting the second power supply signal VGH2 from the shift register is similar to that for outputting the first power supply signal VGH1, as detailed above. Figures 14 to 19 And related content, and the control module 20 can select 9T5C structure or 13T3C structure according to actual needs, and set the level type of the effective pulse of each signal accordingly.

[0155] Based on the same concept, embodiments of this application also provide a gate drive circuit, including multiple cascaded shift registers as in any of the previous embodiments.

[0156] Figure 20 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. (In conjunction with...) Figure 20 As shown, in the gate driving circuit 30, the driving module 10 in the first-stage shift register 301 is used to receive the start signal STV. The driving module 10 of the i-th stage shift register 301 is connected to the driving module 10 of the (i-1)-th stage shift register 301. The driving module 10 of the i-th stage shift register 301 is used to receive the initial scan signal Next output by the driving module 10 of the (i-1)-th stage shift register 301. The initial scan signal Next output by the driving module 10 of the i-th stage shift register 301 serves as the start signal STV of the driving module 10 of the (i-1)-th stage shift register 301. The driving module 10 in each stage shift register 301 can also receive the first clock signal CK, the second clock signal XCK, the first power supply signal VGH1, and the third power supply signal VGL, respectively, thereby sequentially outputting the initial scan signal Next. The specific structure of the shift register 301 can be found in the previous description and will not be repeated here.

[0157] The gate driving circuit 30 provided in this application embodiment includes multiple cascaded shift registers 301, which can provide multiple cascaded gate driving signals. The shift registers 301 can select either a first power supply signal VGH1 or a second power supply signal VGH2 as the gate scan signal OUT by controlling a first frequency control signal Ctrl1 and a second frequency control signal Ctrl2. Specifically, by controlling the initial scan signal Next and the first frequency control signal Ctrl1 to be valid while the second frequency control signal Ctrl2 is invalid, the shift register 301 outputs the first power supply signal VGH1 as the gate scan signal OUT, and controls the first frequency control signal Ctrl1 to be invalid while the initial scan signal Next... With both the second frequency control signal Ctrl2 being effective, the shift register 301 outputs the second power supply signal VGH2 as the gate scan signal OUT. Thus, the same shift register 301 can provide different power supply signals as the gate scan signal OUT for different refresh frequencies or different display modes. Furthermore, different shift registers 301 can provide different power supply signals as the gate scan signal OUT. That is, by using gate scan signals OUT with different potentials, the characteristic drift difference of transistors in the segmented frequency display scenario is compensated, thereby compensating for the display brightness difference between different display areas in the segmented frequency scenario, so that the display brightness of different display areas is balanced, thereby achieving the purpose of improving display uniformity.

[0158] Based on the same concept, this application provides a display panel including at least one gate driving circuit and a pixel circuit as in any of the previous embodiments, wherein the gate driving circuit is connected to the pixel circuit.

[0159] In some embodiments, the display panel includes a first display area and a second display area. The refresh rates of the first and second display areas are different. The shift register connected to the pixel circuit of the first display area outputs a first power signal VGH1 as the gate scan signal OUT, and the shift register connected to the pixel circuit of the second display area outputs a second power signal VGH2 as the gate scan signal OUT. For example, if the refresh rate of the first display area is greater than that of the second display area, then the first power signal VGH1 is greater than the second power signal VGH2. Thus, by providing gate scan signals OUT with different potentials to different display areas, the differences in display brightness between the different display areas are compensated, thereby balancing the overall display brightness of the display panel and improving display uniformity.

[0160] In some embodiments, the pixel circuits are arranged in an array, and each shift register in the gate driving circuit is connected to at least one row of pixel circuits. For example, each shift register in the gate driving circuit is connected to one row of pixel circuits, i.e., a one-to-one connection is adopted. Alternatively, each shift register in the gate driving circuit is connected to two rows of pixel circuits, i.e., a one-to-two connection is adopted. It should be noted that this is only an illustrative example; in actual applications, the connection method between the shift registers and the pixel circuits can be set according to requirements, without excessive limitations.

[0161] In some embodiments, each shift register in the gate driving circuit is connected to the gate reset transistor M4 in the pixel circuit to provide a first scan signal S1N to the gate reset transistor M4. In other embodiments, each shift register in the gate driving circuit is connected to the threshold compensation transistor M5 in the pixel circuit to provide a second scan signal S2N to the threshold compensation transistor M5. In yet another embodiment, in the gate driving circuit, at least a portion of the shift registers are connected to the gate reset transistor M4 in the pixel circuit to provide the first scan signal S1N to the gate reset transistor M4; and at least a portion of the shift registers are connected to the threshold compensation transistor M5 in the pixel circuit to provide the second scan signal S2N to the threshold compensation transistor M5. It should be noted that, in applications, the connection relationship between the shift registers and the transistors in the pixel circuit can be configured according to requirements, and no further limitations are imposed here.

[0162] Figure 21 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. Figure 22 This is a schematic diagram of a pixel circuit 40 and a light-emitting element D provided in an embodiment of this application. (Combined with...) Figure 21 and Figure 22As shown, in some embodiments, the display panel includes a first gate driving circuit 31, a second gate driving circuit 32, and a pixel circuit 40, wherein the pixel circuit 40 is arranged in an array.

[0163] In the first gate driving circuit 31, the i-th stage shift register 311 is connected to the gate reset transistors M4 of the pixel circuits in rows 2i-1 and 2i, respectively. The gate scan signal OUT output by the shift register 311 in the first gate driving circuit 31 serves as the first scan signal S1N of the gate reset transistor M4. i is a positive integer. The start signal received by the first stage shift register 311 is STV1.

[0164] In the second gate driving circuit 32, the j-th stage shift register 321 is connected to the threshold compensation transistors M5 of the pixel circuits 40 in rows 2j-1 and 2j, respectively. The gate scan signal OUT output by the shift register 321 in the second gate driving circuit 32 serves as the second scan signal S2N of the gate reset transistor M4. j is a positive integer. The start signal received by the first stage shift register 321 is STV2.

[0165] The first gate driving circuit 31 and the second gate driving circuit 32 can be the gate driving circuits in any of the foregoing embodiments, and the structure of each shift register in the first gate driving circuit 31 and the second gate driving circuit 32 is the shift register in any of the foregoing embodiments. For details, please refer to the above description, which will not be repeated here.

[0166] It should be noted that the above explanation is based on the example of a shift register connecting two rows of pixel circuits 40, i.e., using a one-to-two method. Other driving methods can also be used in applications, such as a shift register connecting one row of pixel circuits 40, i.e., a one-to-one or one-to-three method, etc., which will not be limited here.

[0167] like Figure 22 As shown, in some embodiments, the pixel circuit 40 includes a driving transistor M0, a data writing transistor M1, a first light-emitting control transistor M2, a second light-emitting control transistor M3, a gate reset transistor M4, a threshold compensation transistor M5, an anode reset transistor M6, and a storage capacitor Cst.

[0168] The gate of the driving transistor M0 is connected to the first terminal of the storage capacitor Cst, the second terminal of the gate reset transistor M4, and the first terminal of the threshold compensation transistor M5. The first terminal of the driving transistor M0 is connected to the first terminal of the data writing transistor M1 and the second terminal of the first light-emitting control transistor M2. The second terminal of the driving transistor M0 is connected to the second terminal of the threshold compensation transistor M5 and the first terminal of the second light-emitting control transistor M3. The driving transistor M0 is used to control the driving current.

[0169] The gate of the data writing transistor M1 is used to receive the data writing control signal SP, and the second terminal of the data writing transistor M1 is used to receive the data signal VData. Under the action of the data writing control signal SP, the data writing transistor M1 writes the data signal VData to the gate of the driving transistor M0.

[0170] The gate of the first light-emitting control transistor M2 and the gate of the second light-emitting control transistor M3 are respectively used to receive the light-emitting control signal Emit. The first terminal of the first light-emitting control transistor M2 is used to receive the fourth power supply signal PVDD. The first light-emitting control transistor M2 is used to control the light-emitting element D to emit light. The second terminal of the second light-emitting control transistor M3 is connected to the second terminal of the anode reset transistor M6 and the anode of the light-emitting element D. The second light-emitting control transistor M3 is used to control the light-emitting element D to emit light.

[0171] The gate of gate reset transistor M4 receives the first scan signal S1N, and its first terminal receives the first initialization signal Vref1. Gate reset transistor M4 is used to reset the gate of driving transistor M0. The gate of threshold compensation transistor M5 receives the second scan signal S2N, and its threshold compensation transistor M5 is used to compensate the threshold voltage of driving transistor M0. The gate of anode reset transistor M6 receives the anode reset control signal SP*, and its first terminal receives the second initialization signal Vref2. Anode reset transistor M6 is used to reset the anode of light-emitting element D.

[0172] In some embodiments, the gate reset transistor M4 and the threshold compensation transistor M5 can be N-type transistors, for example, NTFT or NMOS; the driving transistor M0, the data writing transistor M1, the first light-emitting control transistor M2, the second light-emitting control transistor M3, and the anode reset transistor M6 can all be P-type transistors, for example, PTFT or PMOS. In other embodiments, each of the transistors M1 to M6 in the pixel circuit 40 can be a P-type transistor, for example, PTFT or PMOS.

[0173] It should be noted that the above description uses the pixel circuit 40 including 7T1C as an example. In application, the pixel circuit 40 can also adopt other suitable structures, such as 7T2C, 8T1C, 8T2C, 9T1C, etc., without making too many restrictions here.

[0174] Please continue reading. Figure 22In some embodiments, the pixel circuit 40 may further include a bias transistor M7. The gate of the bias transistor M7 is used to receive a bias control signal SP*. The first terminal of the bias transistor M7 is connected to the first terminal of the driving transistor M0, the second terminal of the first light-emitting control transistor M2, and the first terminal of the data writing transistor M1. The second terminal of the bias transistor M7 is used to receive a bias signal DVH. The bias transistor M7 is used to adjust the bias of the driving transistor M0. The bias control signal SP* and the anode reset control signal SP* may be the same or different. That is, the pixel circuit 40 adopts an 8T1C structure, and the bias adjustment of the driving transistor M0 is achieved through the bias transistor M7, which helps to improve the display performance of the display panel. For example, the bias transistor M7 can be a P-type transistor, such as a PMOS or PTFT.

[0175] In various embodiments of this application, the N-type transistor can be an oxide transistor, for example, the oxide can be IGZO (Indium Gallium Zinc Oxide); the P-type transistor can be a low-temperature polycrystalline silicon (LTPS) transistor.

[0176] Figure 23 This is a flowchart illustrating a method for driving a display panel according to an embodiment of this application. Figure 24 This is a schematic diagram of a display panel provided in an embodiment of this application. (In conjunction with...) Figure 23 and Figure 24 As shown, based on the same concept, this application also provides a driving method for a display panel, which can be any of the display panels provided in the foregoing embodiments. The display panel includes a gate driving circuit and a pixel circuit, which are described in detail in the preceding text and will not be repeated here.

[0177] The driving method for the display panel includes the following steps S2302 and S2304.

[0178] S2302: By controlling a portion of the shift register in the gate drive circuit to output the first power signal VGH1, the pixel circuit of the first display area is driven to drive the first display area to display at the first frequency.

[0179] S2304: By controlling the output of the second power signal VGH2 from the remaining shift register in the gate drive circuit, the pixel circuit of the second display area is driven to drive the second display area to display at the second frequency; wherein the first frequency is different from the second frequency, and the first power signal VGH1 is different from the second power signal VGH2.

[0180] It can be understood that the display panel includes a first display area 51 and a second display area 52. The refresh rates of the first display area 51 and the second display area 52 can be different, i.e., displaying scenes with different refresh rates. Alternatively, the refresh rates of the first display area 51 and the second display area 52 can be the same, i.e., displaying scenes with the entire screen at the same refresh rate.

[0181] The pixel circuit of the first display area 51 is connected to a portion of the shift register in the gate driving circuit, and the pixel circuit of the second display area 52 is connected to the remaining portion of the shift register in the gate driving circuit.

[0182] In the application, the first power signal VGH1 can be output by controlling the shift register corresponding to the first display area 51 to drive the first display area 51 to display at the first frequency. The initial scan signal Next and the first frequency control signal Ctrl1 are valid, while the second frequency control signal Ctrl2 is invalid, thereby controlling the shift register to output the first power signal VGH1.

[0183] Furthermore, the second power signal VGH2 can be output from the shift register corresponding to the second display area 52 to drive the second display area 52 to display at the second frequency, thereby achieving segmented frequency display; wherein, the first frequency control signal Ctrl1 is invalid, and the initial scan signal Next and the second frequency control signal Ctrl2 are valid, thereby controlling the shift register to output the second power signal VGH2.

[0184] In addition, the first power signal VGH1 can be output by controlling the shift registers corresponding to the first display area 51 and the second display area 52 to drive the first display area 51 and the second display area 52 to display at the first frequency; or the second power signal VGH2 can be output by controlling the shift registers corresponding to the first display area 51 and the second display area 52 to display at the second frequency, thereby achieving full-screen synchronous display.

[0185] Figure 25 This is a timing diagram of multiple signals provided in an embodiment of this application. Figure 25As shown, the display panel includes a refresh frame and a sustain frame. Taking the second display area 52, i.e., the low-frequency area, as an example, the second display area 52 includes pixel circuits from row 1 to row n, where n is a positive integer. In the refresh frame, by controlling the shift register of the second display area 52, the initial scan signal Next and the second frequency control signal Ctrl2 are both valid, and the first frequency control signal Ctrl1 is invalid. That is, the initial scan signal Next and the first frequency control signal Ctrl1 are at a high level, and the second frequency control signal Ctrl2 is at a low level, causing the shift register of the second display area 52 to output the second power supply signal VGH2. In the sustain frame, by controlling the shift register of the second display area 52, the second frequency control signal Ctrl2 and the first frequency control signal Ctrl1 are both invalid. That is, the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both at a high level, causing the shift register of the second display area 52 to output the third power supply signal VGL.

[0186] It should be noted that the first display area 51 outputs a first power signal VGH1 in the refresh frame and a third power signal VGL in the sustain frame, which is similar to the first display area 51 outputting a second power signal VGH2 and a third power signal VGL as described above, and will not be repeated here.

[0187] The display panel driving method provided in this application embodiment drives the pixel circuit of the first display area 51 by controlling a portion of the shift register in the gate driving circuit to output a first power signal VGH1, thereby driving the first display area 51 to display at a first frequency; and drives the pixel circuit of the second display area 52 by controlling the remaining portion of the shift register in the gate driving circuit to output a second power signal VGH2, thereby driving the second display area 52 to display at a second frequency; wherein the first frequency and the second frequency are different, and the first power signal VGH1 and the second power signal VGH2 are different, thereby driving different display areas with different power signals, compensating for the characteristic drift difference of transistors in the segmented frequency display scenario, and thus compensating for the display brightness difference between different display areas in the segmented frequency scenario, so that the display brightness of different display areas reaches a balance and the display uniformity is improved.

[0188] In some embodiments, the first frequency is greater than the second frequency, and the first power signal VGH1 is greater than the second power signal VGH2. It is understood that, compared to a display area displaying at a higher frequency such as the first frequency, the transistors in the pixel circuit of a display area displaying at a lower frequency such as the second frequency are more prone to characteristic drift, resulting in differences in display brightness between different display areas. To address this, the embodiments of this application provide a larger power signal for the display area displaying at a higher frequency to drive the pixel circuit to provide a larger driving current, thereby compensating for the brightness reduction caused by transistor characteristic drift, and thus balancing the brightness differences between display areas of different frequencies, improving display uniformity.

[0189] In some embodiments, the first frequency is greater than the second frequency; correspondingly, the first power signal VGH1 is less than the second power signal VGH2. This allows a smaller power signal to be provided to the display area displaying at a higher frequency, driving the pixel circuits with a smaller drive current, thereby compensating for the increase in brightness caused by transistor characteristic drift, and thus balancing the brightness differences between display areas of different frequencies, improving display uniformity.

[0190] It should be noted that the magnitude correspondence between the first frequency and the second frequency, as well as between the first power signal VGH1 and the second power signal VGH2, can be determined based on the actual product's display brightness differences.

[0191] In some embodiments, the method further includes: obtaining the cumulative duration for which the first display area 51 displays at a first frequency, and adjusting the first power signal VGH1 according to the cumulative duration. The cumulative duration refers to the total duration for which the first display area 51 displays at the first frequency. In this way, the first power signal VGH1 can be dynamically adjusted based on the brightness difference between the first display area 51 and the second display area 52, thereby achieving dynamic compensation for brightness differences between different display areas and helping to further improve display uniformity.

[0192] For example, such as Figure 26 As shown, the step of adjusting the first power signal VGH1 according to the cumulative duration may include: linearly increasing the first power signal VGH1 according to the cumulative duration. The linear relationship between the voltage value of the first power signal VGH1 and the cumulative duration can be set accordingly based on the brightness difference between the first display area 51 and the second display area 52. This relationship can be obtained through experimentation or simulation in application, and is not further limited here.

[0193] Another example, such as Figure 27As shown, the step of adjusting the first power signal VGH1 according to the accumulated duration may include: increasing the first power signal VGH1 by a preset step size according to the accumulated duration. The preset step size refers to the voltage difference of the first power signal VGH1 before and after adjustment. The preset step size is pre-set and can be obtained through experiments or simulations; it is not limited further here.

[0194] It should be noted that in the application, the first power signal VGH1 can be adjusted linearly or in steps, or other suitable methods can be used to adjust the first power signal VGH1, such as adjusting the first power signal VGH1 according to the cumulative duration and according to a preset mapping table.

[0195] In one embodiment, a driving method for a display panel is provided, wherein the method is applied to Figure 24 Taking the display panel shown as an example, the method may include: controlling a portion of the shift register in the gate driving circuit to output a first power signal VGH1 to drive the pixel circuit of the first display area, so as to drive the first display area to display at a first frequency; controlling the remaining portion of the shift register in the gate driving circuit to output a second power signal VGH2 to drive the pixel circuit of the second display area, so as to drive the second display area to display at a second frequency; obtaining the cumulative duration of the first display area displaying at the first frequency, and linearly increasing the first power signal VGH1 according to the cumulative duration.

[0196] For the low-frequency region, i.e., the second display area, the shift register outputs a second power signal VGH2 to the corresponding pixel circuit of the second display area, thereby driving the second display area to display at the second frequency. For the high-frequency region, i.e., the first display area, the shift register outputs a first power signal VGH1 to the corresponding pixel circuit of the first display area, thereby driving the first display area to display at the first frequency. For example, when the brightness of the high-frequency region is too low, the first power signal VGH1 can be adjusted to be greater than the second power signal VGH2, i.e., VGH1>VGH2, thereby increasing the brightness of the high-frequency region. Conversely, if the brightness of the high-frequency region is too high, the first power signal VGH1 can be adjusted to be less than the second power signal VGH2, i.e., VGH1>VGH2. <VGH2。

[0197] Based on the same concept, this application also provides a display device. Figure 28 This is a schematic diagram of the structure of the display device 70 provided in the embodiments of this application, as shown below. Figure 28 As shown, the display device 70 includes the display panel 60 in any of the above embodiments. Exemplarily, as... Figure 28As shown, the display device 70 includes a display panel 60. Therefore, the display device 70 also has the beneficial effects of the display panel 60 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 60 above, and will not be repeated below.

[0198] The display device 70 provided in this embodiment can be a Figure 28 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0199] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0200] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A shift register, characterized in that, include: The drive module is used to output the initial scan signal; A control module, connected to the drive module, is used to receive at least the initial scan signal, a first power signal, a second power signal, a third power signal, a first frequency control signal, and a second frequency control signal; the first power signal, the second power signal, and the third power signal are all different; the first frequency control signal and the second frequency control signal have different frequencies; the first frequency control signal and the second frequency control signal are respectively used to control the drive frequency of the pixel circuit connected to the shift register. The control module is further configured to output the first power supply signal as a gate scan signal when both the initial scan signal and the first frequency control signal are valid and the second frequency control signal is invalid; or, when the first frequency control signal is invalid and both the initial scan signal and the second frequency control signal are valid, output the second power supply signal as a gate scan signal.

2. The shift register according to claim 1, characterized in that, The control module is also used to output the third power supply signal as a gate scan signal when both the first frequency control signal and the second frequency control signal are invalid.

3. The shift register according to claim 1 or 2, characterized in that, The control module includes a first control module, a second control module, and an output module; The first control module is connected to the drive module and the output module respectively. The first control module is used to receive at least the initial scan signal, the first power signal, the third power signal and the first frequency control signal, and control the gate scan signal output by the first output node of the output module. The second control module is connected to the drive module and the output module respectively. The second control module is used to receive at least the second power signal, the third power signal and the second frequency control signal, and control the gate scan signal output by the first output node. The output module is connected to the drive module. The output module is used to receive at least the third power supply signal and control the gate scan signal output by the first output node.

4. The shift register according to claim 3, characterized in that, Both the first control module and the second control module include a first control unit and a second control unit; wherein, The first control unit is connected to the target node of the drive module. The first control unit is used to receive the target node signal, the target frequency control signal and the third power signal of the target node, and control the output of the first control signal. The second control unit is connected to the first control unit, the first output node, the first node of the drive module, and the second node of the drive module, respectively. The second control unit is used to receive the first control signal, the first node signal of the first node, the second node signal of the second node, and the target power signal, and to control the gate scan signal output by the first output node; wherein, In the first control module, the target node is the second output node of the drive module, the target node signal is the initial scan signal, the target frequency control signal is the first frequency control signal, and the target power signal is the first power signal; In the second control module, the target node is the first node, the target node signal is the first node signal, the target frequency control signal is the second frequency control signal, and the target power signal is the second power signal.

5. The shift register according to claim 4, characterized in that, The first control unit includes a first transistor and a first capacitor; the gate of the first transistor is connected to the target node; the first terminal of the first transistor is connected to the second control unit and the first terminal of the first capacitor respectively, and the first terminal of the first transistor is used to output the first control signal; the second terminal of the first transistor is used to receive the target frequency control signal; and the second terminal of the first capacitor is used to receive the third power supply signal.

6. The shift register according to claim 5, characterized in that, The first transistor includes a dual-gate transistor; the first transistor is a P-type transistor.

7. The shift register according to claim 4, characterized in that, The second control unit includes a second transistor, a third transistor, and a fourth transistor; the gate of the second transistor is connected to the first control unit, the first electrode of the second transistor is connected to the second node, the second electrode of the second transistor is connected to the second electrode of the third transistor and the gate of the fourth transistor, the gate of the third transistor is connected to the first node, the first electrodes of the third transistor and the first electrodes of the fourth transistor are respectively used to receive the target power signal, and the second electrode of the fourth transistor is connected to the first output node.

8. The shift register according to claim 7, characterized in that, The second control unit further includes a second capacitor, which is connected to the first electrode and the gate of the fourth transistor, respectively.

9. The shift register according to claim 8, characterized in that, The second transistor, the third transistor, and the fourth transistor are all P-type transistors.

10. The shift register according to claim 3, characterized in that, Both the first control module and the second control module include a third control unit and a fourth control unit; wherein, The third control unit is connected to the second output node and the first output node of the drive module respectively. The third control unit is used to receive the initial scanning signal, the target frequency control signal and the third power signal, and control the output of the second control signal and the third control signal. The fourth control unit is connected to the third control unit, the first output node, and the second output node, respectively. The fourth control unit receives the second control signal, the third control signal, the initial scan signal, and the target power signal, and controls the gate scan signal output by the first output node. In the first control module, the target frequency control signal is the first frequency control signal, and the target power signal is the first power signal; In the second control module, the target frequency control signal is the second frequency control signal, and the target power signal is the second power signal.

11. The shift register according to claim 10, characterized in that, The third control unit includes a fifth transistor, a sixth transistor, and a seventh transistor; the gate of the fifth transistor is connected to the second output node and the gate of the seventh transistor, respectively; the first terminal of the fifth transistor is connected to the gate of the sixth transistor and the fourth control unit, respectively; the first terminal of the fifth transistor is used to output the third control signal; the second terminal of the fifth transistor is used to receive the target frequency control signal; the first terminal of the sixth transistor is connected to the first terminal of the seventh transistor; the second terminal of the sixth transistor is connected to the fourth control unit; the second terminal of the sixth transistor is used to output the second control signal; and the second terminal of the seventh transistor is used to receive the third power supply signal.

12. The shift register according to claim 11, characterized in that, The fifth transistor is a P-type transistor, while the sixth and seventh transistors are N-type transistors.

13. The shift register according to claim 10, characterized in that, The fourth control unit includes an eighth transistor, a ninth transistor, a tenth transistor, and a third capacitor; wherein, the gate of the eighth transistor is connected to the second output node; the first terminal of the eighth transistor, the second terminal of the ninth transistor, the first terminal of the tenth transistor, and the first terminal of the third capacitor are connected, and the first terminal of the eighth transistor is used to receive the target power signal; the second terminals of the eight transistors are respectively connected to the third control unit, the first terminal of the ninth transistor, and the gate of the tenth transistor; the gate of the ninth transistor is respectively connected to the second terminal of the third control unit and the third capacitor; and the second terminal of the tenth transistor is connected to the first output node.

14. The shift register according to claim 13, characterized in that, The eighth transistor, the ninth transistor, and the tenth transistor are all P-type transistors.

15. The shift register according to claim 3, characterized in that, The output module includes an eleventh transistor, the gate of which is connected to the third node of the driving module, the first terminal of which is connected to the first output node, and the second terminal of which is used to receive the third power signal.

16. The shift register according to claim 15, characterized in that, The output module also includes a fourth capacitor, which is connected to the first electrode and the gate of the eleventh transistor.

17. A gate driving circuit, characterized in that, Includes multiple cascaded shift registers as described in any one of claims 1-16.

18. A display panel, characterized in that, It includes at least one gate driving circuit and a pixel circuit as described in claim 17, wherein the gate driving circuit is connected to the pixel circuit.

19. A driving method for a display panel, characterized in that, Applied to the display panel as described in claim 18, the display panel including a first display area and a second display area, the method includes: By controlling a portion of the shift register in the gate drive circuit to output a first power signal, the pixel circuit of the first display area is driven to drive the first display area to display at a first frequency; By controlling the output of the second power supply signal from the remaining shift register in the gate drive circuit, the pixel circuit of the second display area is driven to drive the second display area to display at a second frequency; wherein the first frequency is different from the second frequency, and the first power supply signal is different from the second power supply signal.

20. The method according to claim 19, characterized in that, The first frequency is greater than the second frequency, and the first power signal is greater than the second power signal.

21. The method according to claim 20, characterized in that, The method further includes: Obtain the cumulative duration for which the first display area is displayed at the first frequency; The first power signal is adjusted according to the cumulative duration.

22. A display device, characterized in that, Includes the display panel as described in claim 18.

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