Gate driver and display device including same
By designing a multi-stage gate driver to process clock signals and gate signals, the problem of high power consumption of clock signals in the prior art is solved, and the effect of reducing power consumption of gate drivers and display devices is achieved.
Patent Information
- Application Number
- CN202411501035.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-26
- Filing Date
- 2024-10-25
- Publication Date
- 2025-04-29
AI Technical Summary
The existing gate drivers consume higher power when processing clock signals, resulting in increased power consumption of the overall display device.
A gate driver including multiple stages is designed to reduce the frequency and power consumption of each clock signal by receiving a clock signal from the first clock line to the Nth clock line and receiving and processing the clock signal and gate signal in each stage.
By increasing the level to receive the clock signal, the frequency of the clock signal is reduced, thereby reducing the power consumption of the gate driver. Furthermore, the number of levels connected to the clock line is reduced, the capacitance of the observed equivalent capacitor is reduced, and power consumption is further reduced.
Smart Images
Figure CN119905069A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the inventive concept relate to a gate driver and a display device including the same. In particular, the inventive concept relates to a gate driver and a display device designed to reduce power consumption. Background Art
[0002] The display device generally includes a display panel and a display panel driver. The display panel includes gate lines, data lines and pixel circuits. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver and the data driver.
[0003] The gate driver may receive a clock signal from a clock line. As the load on the clock signal increases, its power consumption may also increase. Therefore, when the power consumption of the clock signal increases, the power consumption of the gate driver may also increase. Summary of the invention
[0004] Embodiments of the inventive concept provide a gate driver with reduced power consumption.
[0005] Embodiments of the inventive concept provide a display device including a gate driver.
[0006] In an embodiment of the present invention, a gate driver is provided, comprising: a first stage to an Nth stage (where N is a positive integer of 3 or greater) for receiving a first clock signal to an Nth clock signal from a first clock line to an Nth clock line, wherein the first stage comprises a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal, wherein the NKth stage (where K is a positive integer between 1 and N-2) comprises a first clock terminal for receiving an NKth clock signal, a second clock terminal for receiving an N-K+1th clock signal, a carry terminal for receiving an NK-1th gate signal, and an output terminal for outputting an NKth gate signal, and wherein the Nth stage comprises a first clock terminal for receiving an Nth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving an N-1th gate signal, and an output terminal for outputting an Nth gate signal.
[0007] When N is 4, the gate driver includes: a first stage; a second stage, including a first clock terminal for receiving a second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting the second gate signal; a third stage, including a first clock terminal for receiving a third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting the third gate signal; and a fourth stage, including a first clock terminal for receiving a fourth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting the fourth gate signal.
[0008] When N is 6, the gate driver includes: a first stage; a second stage, including a first clock terminal for receiving a second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting the second gate signal; a third stage, including a first clock terminal for receiving a third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting the third gate signal; a fourth stage, including a first clock terminal for receiving a fourth clock signal, a second clock terminal for receiving a fifth clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting the fourth gate signal; a fifth stage, including a first clock terminal for receiving a fifth clock signal, a second clock terminal for receiving a sixth clock signal, a carry terminal for receiving the fourth gate signal, and an output terminal for outputting the fifth gate signal; and a sixth stage, including a first clock terminal for receiving a sixth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the fifth gate signal, and an output terminal for outputting the sixth gate signal.
[0009] The activation period of each of the first to Nth clock signals does not overlap with each other.
[0010] When the length of the activation period of each of the first clock signal to the Nth clock signal is J horizontal times (where J is a positive number), the length of the inactive period of each of the first clock signal to the Nth clock signal is (N-1)×J horizontal times, and the period of each of the first clock signal to the Nth clock signal is N×J horizontal times.
[0011] When N is 4 and J is 1, the length of the activation period of each of the first clock signal to the Nth clock signal is 1 horizontal time, and the length of the inactive period of each of the first clock signal to the Nth clock signal is 3 horizontal times, and the cycle of each of the first clock signal to the Nth clock signal is 4 horizontal times.
[0012] As N increases, the period of each of the first to Nth clock signals increases.
[0013] As N increases, the capacitance of the equivalent capacitor observed from each of the first to Nth clock lines decreases.
[0014] The first stage includes: a first transistor including a gate electrode for receiving a first clock signal, a first electrode for receiving a vertical start signal, and a second electrode connected to a first control node; a second transistor including a second electrode, a gate electrode connected to an inverting control node, and a first electrode for receiving a high gate voltage; a third transistor including a gate electrode for receiving a second clock signal, a first electrode connected to a second electrode of the second transistor, and a second electrode connected to the first control node; a fourth transistor including a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node; a fifth transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node; a sixth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving a high gate voltage, and a second electrode connected to a gate output node configured to output the first gate signal; a seventh transistor including a gate electrode connected to the second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node; a first capacitor including a first electrode for receiving a high gate voltage and a second electrode connected to the inverting control node; and a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output node.
[0015] The first stage also includes an eighth transistor including a gate electrode for receiving a low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.
[0016] In an embodiment of the present invention, a gate driver is provided, comprising: a first stage to a 2Nth stage (where N is a positive integer of 2 or greater), for receiving a first clock signal to a 2Nth clock signal from a first clock line to a 2Nth clock line, wherein the N-K+1th stage (where K is a positive integer greater than 1 and less than N) comprises a first clock terminal for receiving a 2N-2K+1th clock signal and a second clock terminal for receiving a 2N-2K+2th clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting an N-K+1th gate signal, and wherein the 2N-K+1th stage comprises a first clock terminal for receiving a 2N-2K+2th clock signal, a second clock terminal for receiving a 2N-2K+1th clock signal, a carry terminal for receiving a N-K+1th gate signal, and an output terminal for outputting a 2N-K+1th gate signal.
[0017] When N is 2, the gate driver includes: a first stage, including a first clock terminal for receiving a first clock signal, a second clock terminal for receiving a second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal; a second stage, including a first clock terminal for receiving a third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a second gate signal; a third stage, including a first clock terminal for receiving a second clock signal, a second clock terminal for receiving a first clock signal, a carry terminal for receiving a first gate signal, and an output terminal for outputting a third gate signal; and a fourth stage, including a first clock terminal for receiving a fourth clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving a second gate signal, and an output terminal for outputting a fourth gate signal.
[0018] The activation period of each of the first to 2Nth clock signals does not overlap with each other.
[0019] When the length of the activation period of each of the first clock signal to the 2Nth clock signal is J horizontal times (where J is a positive number), the length of the inactive period of each of the first clock signal to the 2Nth clock signal is (2N-1)×J horizontal times, and the period of each of the first clock signal to the 2Nth clock signal is 2N×J horizontal times.
[0020] As N increases, the period of each of the first to 2Nth clock signals increases.
[0021] As N increases, the capacitance of the equivalent capacitor observed from each of the first to 2Nth clock lines decreases.
[0022] The first stage includes: a first transistor including a gate electrode for receiving a first clock signal, a first electrode for receiving a vertical start signal, and a second electrode connected to a first control node; a second transistor including a second electrode, a gate electrode connected to an inverting control node, and a first electrode for receiving a high gate voltage; a third transistor including a gate electrode for receiving a second clock signal, a first electrode connected to a second electrode of the second transistor, and a second electrode connected to the first control node; a fourth transistor including a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node; a fifth transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node; a sixth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving a high gate voltage, and a second electrode connected to a gate output node configured to output the first gate signal; a seventh transistor including a gate electrode connected to the second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node; a first capacitor including a first electrode for receiving a high gate voltage and a second electrode connected to the inverting control node; and a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output node.
[0023] In an embodiment of the present invention, a display device is provided, comprising: a display panel comprising pixels; and a gate driver configured to provide a gate signal to the display panel, wherein the gate driver comprises a first stage to an Nth stage (where N is a positive integer of 3 or greater) for receiving a first clock signal to an Nth clock signal from a first clock line to an Nth clock line, wherein the first stage comprises a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting the first gate signal, wherein the NKth stage (where K is a positive integer between 1 and N-2) comprises a first clock terminal for receiving an NKth clock signal, a second clock terminal for receiving an N-K+1th clock signal, a carry terminal for receiving an NK-1th gate signal, and an output terminal for outputting the NKth gate signal, and wherein the Nth stage comprises a first clock terminal for receiving the Nth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving an N-1th gate signal, and an output terminal for outputting the Nth gate signal.
[0024] When N is 4, the gate driver includes: a first stage, including a first clock terminal for receiving a first clock signal, a second clock terminal for receiving a second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal; a second stage, including a first clock terminal for receiving a second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting the second gate signal; a third stage, including a first clock terminal for receiving a third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting the third gate signal; and a fourth stage, including a first clock terminal for receiving a fourth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting the fourth gate signal.
[0025] The activation period of each of the first to Nth clock signals does not overlap with each other.
[0026] According to the gate driver and the display device including the gate driver, the number of clock signals received by the stage can be increased. Therefore, the frequency of each of the clock signals can be reduced, resulting in reduced power consumption of each clock signal and the gate driver. In addition, reducing the number of stages connected to the clock line providing the clock signal can reduce the capacitance of the equivalent capacitor observed from the clock line. This reduction further reduces the power consumption of each clock signal and the gate driver. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The above and other features of the present inventive concept will become more apparent by describing in detail embodiments of the present inventive concept with reference to the accompanying drawings, in which:
[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept;
[0029] Figure 2A is a block diagram showing a gate driver according to a comparative example;
[0030] Figure 2B It is shown Figure 2A Circuit diagram of the first stage of the gate driver;
[0031] Figure 2C It is shown Figure 2A A timing diagram of the operation of the gate driver;
[0032] Figure 3A is a block diagram showing a gate driver according to an embodiment;
[0033] Figure 3BIt shows that when N is 4 Figure 3A Block diagram of the gate driver;
[0034] Figure 3C It is shown Figure 3A Circuit diagram of the first stage of the gate driver;
[0035] Figure 3D It is shown Figure 3A A timing diagram of a first clock signal to an Nth clock signal of a gate driver;
[0036] Figure 3E is a graph showing that when N is 4 and J is 1 Figure 3A A timing diagram of the operation of the gate driver;
[0037] Figure 3F It shows that when N is 6 Figure 3A Block diagram of the gate driver;
[0038] Figure 4A is a block diagram showing a gate driver according to an embodiment;
[0039] Figure 4B It shows that when N is 2 Figure 4A Block diagram of the gate driver;
[0040] Figure 4C It is shown Figure 4A Circuit diagram of the first stage of the gate driver;
[0041] Figure 4D It is shown Figure 4A A timing diagram of a first clock signal to a 2Nth clock signal of a gate driver;
[0042] Figure 4E is to show that when N is 2 and J is 1 Figure 4A A timing diagram of the operation of the gate driver;
[0043] Figure 4F It shows that when N is 3 Figure 4A Block diagram of the gate driver;
[0044] Figure 5 is a block diagram showing an electronic device; and
[0045] Figure 6 It shows that Figure 5 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION
[0046] Hereinafter, the inventive concept will be described in more detail with reference to the accompanying drawings.
[0047] Figure 1is a block diagram illustrating a display device according to an embodiment of the inventive concept.
[0048] refer to Figure 1 The display device 10 may include a display panel 110 and a display panel driver. The display panel driver may include a driving controller 120, a gate driver 130, a gamma reference voltage generator 140, and a data driver 150.
[0049] For example, the driving controller 120 and the data driver 150 may be integrally formed. Similarly, the driving controller 120, the gamma reference voltage generator 140, and the data driver 150 may be integrally formed. In addition, the driving controller 120, the gate driver 130, the gamma reference voltage generator 140, and the data driver 150 may be integrally formed. A driving module including at least the integrally formed driving controller 120 and the data driver 150 may be referred to as a timing controller embedded data driver (TED).
[0050] The display panel 110 may include a display area for displaying an image and a peripheral area disposed adjacent to the display area.
[0051] For example, the display panel 110 may be an organic light emitting diode display panel including an organic light emitting diode. For example, the display panel 110 may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. For example, the display panel 110 may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter.
[0052] The display panel 110 may include gate lines GL, data lines DL, and pixels P electrically connected to the gate lines GL and the data lines DL, respectively. The gate lines GL may extend in a first direction, and the data lines DL may extend in a second direction crossing the first direction.
[0053] The driving controller 120 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.
[0054] The driving controller 120 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.
[0055] The driving controller 120 may generate a first control signal CONT1 controlling the operation of the gate driver 130 based on the input control signal CONT and output the first control signal CONT1 to the gate driver 130. The first control signal CONT1 may include a vertical start signal and a gate clock signal.
[0056] The driving controller 120 may generate a second control signal CONT2 controlling the operation of the data driver 150 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 150. The second control signal CONT2 may include a horizontal start signal and a load signal.
[0057] The driving controller 120 may generate a data signal DATA based on the input image data IMG. The driving controller 120 may output the data signal DATA to the data driver 150.
[0058] The driving controller 120 may generate a third control signal CONT3 controlling the operation of the gamma reference voltage generator 140 based on the input control signal CONT and output the third control signal CONT3 to the gamma reference voltage generator 140 .
[0059] The gate driver 130 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 120. The gate driver 130 may output the gate signal to the gate line GL.
[0060] In an implementation, the gate driver 130 may be integrated on a peripheral area of the display panel 110 .
[0061] The gamma reference voltage generator 140 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 120. The gamma reference voltage generator 140 may provide the gamma reference voltage VGREF to the data driver 150. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.
[0062] In an implementation, the gamma reference voltage generator 140 may be located within the driving controller 120 or the data driver 150 .
[0063] The data driver 150 may receive the second control signal CONT2 and the data signal DATA from the driving controller 120, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 140. The data driver 150 may convert the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 150 may output the data voltage to the data line DL.
[0064] Figure 2A is a block diagram showing a gate driver according to a comparative example.
[0065] refer to Figure 2A , the gate driver 200 in the comparative example may include a plurality of stages that output a plurality of gate signals. The number of stages may be greater than or equal to the number of pixel rows. Figure 2A , the first stage STAGE[1] to the fourth stage STAGE[4] are shown to explain the operation of the gate driver 200 in the comparative example.
[0066] The gate driver 200 in the comparative example may include first to fourth stages STAGE[ 1 ] to STAGE[ 4 ] that receive first and second clock signals CLK1 and CLK2 from first and second clock lines CL1 and CL2 .
[0067] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1, a second clock terminal for receiving a second clock signal CLK2, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a first gate signal GS[1]. The second stage STAGE[2] may include a first clock terminal for receiving a second clock signal CLK2, a second clock terminal for receiving a first clock signal CLK1, a carry terminal for receiving a first gate signal GS[1] as an input signal, and an output terminal for outputting a second gate signal GS[2]. The third stage STAGE[3] may include a first clock terminal for receiving a first clock signal CLK1, a second clock terminal for receiving a second clock signal CLK2, a carry terminal for receiving a second gate signal GS[2] as an input signal, and an output terminal for outputting a third gate signal GS[3]. The fourth stage STAGE[4] may include a first clock terminal for receiving a second clock signal CLK2, a second clock terminal for receiving a first clock signal CLK1, a carry terminal for receiving a third gate signal GS[3] as an input signal, and an output terminal for outputting a fourth gate signal GS[4].
[0068] Therefore, the first stage STAGE[1] can receive the vertical start signal FLM, and the subsequent stages STAGE[2], STAGE[3], STAGE[4], ... can receive the gate signals GS[1], GS[2], GS[3], GS[4], ... from the respective previous stages as input signals. In addition, the method of applying the first clock signal CLK1 and the second clock signal CLK2 can be repeated every two stages.
[0069] Figure 2B It is shown Figure 2A Circuit diagram of the first stage of the gate driver.
[0070] refer to Figure 2A and Figure 2B , the first stage STAGE[1] may include first to eighth transistors T1 to T8, a first capacitor C1 and a second capacitor C2.
[0071] The first transistor T1 may include a gate electrode for receiving the first clock signal CLK1, a first electrode for receiving the vertical start signal FLM, and a second electrode connected to the first control node NQ1. The second transistor T2 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the third transistor T3. The third transistor T3 may include a gate electrode for receiving the second clock signal CLK2, a first electrode connected to the second electrode of the second transistor T2, and a second electrode connected to the first control node NQ1. The fourth transistor T4 may include a gate electrode connected to the first control node NQ1, a first electrode for receiving the first clock signal CLK1, and a second electrode connected to the inverting control node NQB. The fifth transistor T5 may include a gate electrode for receiving the first clock signal CLK1, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the inverting control node NQB. The sixth transistor T6 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the gate output node NGS for outputting the first gate signal GS[1]. The seventh transistor T7 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS. The eighth transistor T8 may include a gate electrode for receiving the low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2.
[0072] The first capacitor C1 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the inversion control node NQB. The second capacitor C2 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the gate output node NGS.
[0073] Figure 2C It is shown Figure 2A Timing diagram of the operation of the gate driver.
[0074] refer to FIG. 2A to FIG. 2C, each of the first clock signal CLK1 and the second clock signal CLK2 may alternately have an active period and an inactive period, and the active periods of the first clock signal CLK1 and the second clock signal CLK2 do not overlap. The length of both the active period and the inactive period of the first clock signal CLK1 and the second clock signal CLK2 may be 1 horizontal time 1H, thereby generating a cycle of 2 horizontal times 2H for each of the first clock signal CLK1 and the second clock signal CLK2.
[0075] The first stage STAGE[1] may receive the vertical start signal FLM based on the first clock signal CLK1, and output the first gate signal GS[1] based on the second clock signal CLK2. The second stage STAGE[2] may receive the first gate signal GS[1] based on the second clock signal CLK2, and output the second gate signal GS[2] based on the first clock signal CLK1. The third stage STAGE[3] may receive the second gate signal GS[2] based on the first clock signal CLK1, and output the third gate signal GS[3] based on the second clock signal CLK2. The fourth stage STAGE[4] may receive the third gate signal GS[3] based on the second clock signal CLK2, and output the fourth gate signal GS[4] based on the first clock signal CLK1.
[0076] The stages STAGE[1], STAGE[2], STAGE[3], STAGE[4], ... can sequentially output gate signals GS[1], GS[2], GS[3], GS[4], ... within one frame period.
[0077] The power consumption of the clock signal can be calculated using the following equation.
[0078] [Equation]
[0079] Pcl=Ceq×V 2 ×f
[0080] In this equation, Pcl is the power consumption of the clock signal, Ceq is the capacitance of the equivalent capacitor observed from the clock line providing the clock signal, V is the voltage difference between the activation period and the inactivation period of the clock signal, and f is the frequency of the clock signal. The equivalent capacitor observed from the clock line providing the clock signal is proportional to the number of stages connected to the clock line. The period of each of the first clock signal CLK1 and the second clock signal CLK2 is a relatively short 2 horizontal time 2H. Therefore, the frequency of each of the first clock signal CLK1 and the second clock signal CLK2 is high, resulting in significant power consumption. Since the first clock line CL1 and the second clock line CL2 providing the first clock signal CLK1 and the second clock signal CLK2 are connected to all stages, the capacitance of the equivalent capacitor observed from the first clock line CL1 and the second clock line CL2 is large, resulting in high power consumption for each of the first clock signal CLK1 and the second clock signal CLK2.
[0081] Figure 3A is a block diagram showing a gate driver according to an embodiment.
[0082] refer to Figure 3A , the gate driver 300 according to the embodiment may include a plurality of stages that output a plurality of gate signals. The number of stages may be greater than or equal to the number of pixel rows.
[0083] The stages may include first to N stages STAGE[1] to STAGE[N] receiving first to Nth clock signals CLK1 to CLKN from first to Nth clock lines CL1 to CLN. Here, N is a positive integer of 3 or more.
[0084] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1 from a first clock line CL1, a second clock terminal for receiving a second clock signal CLK2 from a second clock line CL2, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a first gate signal GS[1]. The NKth stage STAGE[NK] may include a first clock terminal for receiving an NKth clock signal CLKN-K from an NKth clock line CLN-K, a second clock terminal for receiving an N-K+1th clock signal CLKN-K+1 from an N-K+1th clock line CLN-K+1, a carry terminal for receiving an NK-1th gate signal GS[NK-1] as an input signal, and an output terminal for outputting an NKth gate signal GS[NK]. Here, K is a positive integer between 1 and N-2. The Nth stage STAGE[N] may include a first clock terminal for receiving an Nth clock signal CLKN from an Nth clock line CLN, a second clock terminal for receiving a first clock signal CLK1, a carry terminal for receiving an N-1th gate signal GS[N-1] as an input signal, and an output terminal for outputting an Nth gate signal GS[N].
[0085] Therefore, the first stage STAGE[1] may receive the vertical start signal FLM, and the subsequent stages may receive the gate signal from the previous stage as an input signal. In addition, the method of applying the first clock signal CLK1 to the Nth clock signal CLKN may be repeated in units of N stages.
[0086] Figure 3B It shows that when N is 4 Figure 3A Block diagram of a gate driver.
[0087] refer to Figure 3A and Figure 3B In an embodiment, N may be 4. Figure 3B , the first stage STAGE[1] to the fourth stage STAGE[4] are shown to illustrate the operation of the gate driver 310 when N is 4.
[0088] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1, a second clock terminal for receiving a second clock signal CLK2, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a first gate signal GS[1]. The second stage STAGE[2] may include a first clock terminal for receiving a second clock signal CLK2, a second clock terminal for receiving a third clock signal CLK3 from a third clock line CL3, a carry terminal for receiving the first gate signal GS[1] as an input signal, and an output terminal for outputting a second gate signal GS[2]. The third stage STAGE[3] may include a first clock terminal for receiving a third clock signal CLK3, a second clock terminal for receiving a fourth clock signal CLK4 from a fourth clock line CL4, a carry terminal for receiving the second gate signal GS[2] as an input signal, and an output terminal for outputting a third gate signal GS[3]. The fourth stage STAGE[4] may include a first clock terminal for receiving a fourth clock signal CLK4, a second clock terminal for receiving the first clock signal CLK1, a carry terminal for receiving a third gate signal GS[3], and an output terminal for outputting a fourth gate signal GS[4].
[0089] Therefore, the first stage STAGE[1] can receive the vertical start signal FLM, and the subsequent stages STAGE[2], STAGE[3], STAGE[4], ... can receive the gate signals GS[1], GS[2], GS[3], GS[4], ... from the previous stage as input signals. In addition, the method of applying the first clock signal CLK1 to the fourth clock signal CLK4 can be repeated in units of four stages.
[0090] Figure 3C It is shown Figure 3A Circuit diagram of the first stage of the gate driver.
[0091] refer to FIG. 3A to FIG. 3C , the first stage STAGE[1] may include first to eighth transistors T1 to T8, a first capacitor C1 and a second capacitor C2.
[0092] The first transistor T1 may include a gate electrode for receiving the first clock signal CLK1, a first electrode for receiving the vertical start signal FLM, and a second electrode connected to the first control node NQ1. The second transistor T2 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the third transistor T3. The third transistor T3 may include a gate electrode for receiving the second clock signal CLK2, a first electrode connected to the second electrode of the second transistor T2, and a second electrode connected to the first control node NQ1. The fourth transistor T4 may include a gate electrode connected to the first control node NQ1, a first electrode for receiving the first clock signal CLK1, and a second electrode connected to the inverting control node NQB. The fifth transistor T5 may include a gate electrode for receiving the first clock signal CLK1, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the inverting control node NQB. The sixth transistor T6 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the gate output node NGS for outputting the first gate signal GS[1]. The seventh transistor T7 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS. The eighth transistor T8 may include a gate electrode for receiving the low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2.
[0093] The first capacitor C1 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the inversion control node NQB. The second capacitor C2 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the gate output node NGS.
[0094] Figure 3D It is shown Figure 3A A timing diagram of the first clock signal to the Nth clock signal of the gate driver.
[0095] refer to FIG. 3A to FIG. 3DIn an embodiment, each of the first to Nth clock signals CLK1 to CLKN may alternately have an active period and an inactive period, and the active periods do not overlap. When the length of the active period of each of the first to Nth clock signals CLK1 to CLKN is J horizontal times JH, the length of the inactive period of each of the first to Nth clock signals CLK1 to CLKN is (N-1)×J horizontal times (N-1)×JH, thereby generating a cycle of N×J horizontal times N×JH for each of the first to Nth clock signals CLK1 to CLKN. Here, J is a positive number.
[0096] Figure 3E is a graph showing that when N is 4 and J is 1 Figure 3A Timing diagram of the operation of the gate driver.
[0097] refer to FIG. 3A to FIG. 3E , in an embodiment, N may be 4 and J may be 1. In this case, an activation period of each of the first to Nth clock signals CLK1 to CLKN may be 1 horizontal time 1H, an inactivation period of each of the first to Nth clock signals CLK1 to CLKN may be 3 horizontal times 3H, and a cycle of each of the first to Nth clock signals CLK1 to CLKN may be 4 horizontal times 4H.
[0098] The first stage STAGE[1] may receive the vertical start signal FLM based on the first clock signal CLK1, and output the first gate signal GS[1] based on the second clock signal CLK2. The second stage STAGE[2] may receive the first gate signal GS[1] based on the second clock signal CLK2, and output the second gate signal GS[2] based on the third clock signal CLK3. The third stage STAGE[3] may receive the second gate signal GS[2] based on the third clock signal CLK3, and output the third gate signal GS[3] based on the fourth clock signal CLK4. The fourth stage STAGE[4] may receive the third gate signal GS[3] based on the fourth clock signal CLK4, and output the fourth gate signal GS[4] based on the first clock signal CLK1.
[0099] The stages STAGE[1], STAGE[2], STAGE[3], STAGE[4], ... can sequentially output gate signals GS[1], GS[2], GS[3], GS[4], ... within one frame period.
[0100] The period of each of the first clock signal CLK1 to the fourth clock signal CLK4 can be a relatively large 4 horizontal times 4H. Therefore, the frequency of each of the first clock signal CLK1 to the fourth clock signal CLK4 can be low, resulting in low power consumption. Since the first clock line CL1 to the fourth clock line CL4 providing the first clock signal CLK1 to the fourth clock signal CLK4 are connected to half of the stage, the capacitance of the equivalent capacitor observed from the first clock line CL1 to the fourth clock line CL4 is small, further reducing power consumption.
[0101] Therefore, when N is large, the period of each of the first to N-th clock signals CLK1 to CLKN may be large, resulting in small power consumption for each of the first to N-th clock signals CLK1 to CLKN. In addition, when N is large, the capacitance of the equivalent capacitor observed from each of the first to N-th clock lines CL1 to CLN may be small, and the power consumption of each of the first to N-th clock signals CLK1 to CLKN may be further reduced.
[0102] Figure 3F It shows that when N is 6 Figure 3A Block diagram of a gate driver.
[0103] refer to Figure 3F In an embodiment, N may be 6. Figure 3F , the first stage STAGE[1] to the sixth stage STAGE[6] are shown to illustrate the operation of the gate driver 320 when N is 6.
[0104] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1, a second clock terminal for receiving a second clock signal CLK2, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a first gate signal GS[1]. The second stage STAGE[2] may include a first clock terminal for receiving a second clock signal CLK2, a second clock terminal for receiving a third clock signal CLK3 from a third clock line CL3, a carry terminal for receiving the first gate signal GS[1] as an input signal, and an output terminal for outputting a second gate signal GS[2]. The third stage STAGE[3] may include a first clock terminal for receiving a third clock signal CLK3, a second clock terminal for receiving a fourth clock signal CLK4 from a fourth clock line CL4, a carry terminal for receiving the second gate signal GS[2] as an input signal, and an output terminal for outputting a third gate signal GS[3]. The fourth stage STAGE[4] may include a first clock terminal for receiving a fourth clock signal CLK4, a second clock terminal for receiving a fifth clock signal CLK5 from a fifth clock line CL5, a carry terminal for receiving a third gate signal GS[3] as an input signal, and an output terminal for outputting a fourth gate signal GS[4]. The fifth stage STAGE[5] may include a first clock terminal for receiving a fifth clock signal CLK5, a second clock terminal for receiving a sixth clock signal CLK6 from a sixth clock line CL6, a carry terminal for receiving a fourth gate signal GS[4] as an input signal, and an output terminal for outputting a fifth gate signal GS[5]. The sixth stage STAGE[6] may include a first clock terminal for receiving a sixth clock signal CLK6, a second clock terminal for receiving a first clock signal CLK1, a carry terminal for receiving a fifth gate signal GS[5] as an input signal, and an output terminal for outputting a sixth gate signal GS[6].
[0105] Therefore, the first stage STAGE[1] can receive the vertical start signal FLM, and the subsequent stages STAGE[2], STAGE[3], STAGE[4], STAGE[5], STAGE[6], ... can receive the gate signals GS[1], GS[2], GS[3], GS[4], GS[5], GS[6], ... from the previous stage as input signals. In addition, the method of applying the first clock signal CLK1 to the sixth clock signal CLK6 can be repeated in units of six stages.
[0106] In an embodiment, N may be 6 and J may be 1. In this case, an activation period of each of the first to Nth clock signals CLK1 to CLKN may be 1 horizontal time 1H, an inactive period of each of the first to Nth clock signals CLK1 to CLKN may be 5 horizontal times 5H, and a cycle of each of the first to Nth clock signals CLK1 to CLKN may be 6 horizontal times 6H.
[0107] Since the 6 horizontal times 6H are relatively large, the frequency of each of the first to sixth clock signals CLK1 to CLK6 can be low, resulting in small power consumption. Since the first to sixth clock lines CL1 to CL6 providing the first to sixth clock signals CLK1 to CLK6 are connected to one-third of the stage, the capacitance of the equivalent capacitor observed from the first to sixth clock lines CL1 to CL6 is small, further reducing power consumption.
[0108] Figure 4A is a block diagram showing a gate driver according to an embodiment.
[0109] refer to Figure 4A , the gate driver 400 according to the embodiment may include a plurality of stages outputting a plurality of gate signals. The number of stages may be greater than or equal to the number of pixel rows.
[0110] The stages may include a first stage STAGE[1] to a 2N-K+1 stage STAGE[2N-K+1] that receive a first clock signal CLK1 to a 2N-2K+2 clock signal CLK2N-2K+2 from a first clock line CL1 to a 2N-2K+2 clock line CL2N-2K+2. Here, N is a positive integer of 2 or more.
[0111] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1 from a first clock line CL1, a second clock terminal for receiving a second clock signal CLK2 from a second clock line CL2, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a first gate signal GS[1]. The N-K+1th stage STAGE[N-K+1] may include a first clock terminal for receiving a 2N-2K+1th clock signal CLK2N-2K+1th clock line CL2N-2K+1, a second clock terminal for receiving a 2N-2K+2th clock signal CLK2N-2K+2th clock line CL2N-2K+2, a carry terminal for receiving a vertical start signal FLM, and an output terminal for outputting an N-K+1th gate signal GS[N-K+1]. Here, K is a positive integer between 1 and N or less. The N+1th stage STAGE[N+1] may include a first clock terminal for receiving a second clock signal CLK2, a second clock terminal for receiving a first clock signal CLK1, a carry terminal for receiving a first gate signal GS[1] as an input signal, and an output terminal for outputting an N+1th gate signal GS[N+1]. The 2N-K+1th stage STAGE[2N-K+1] may include a first clock terminal for receiving a 2N-2K+2th clock signal CLK2N-2K+2, a second clock terminal for receiving a 2N-2K+1th clock signal CLK2N-2K+1, a carry terminal for receiving an N-K+1th gate signal GS[N-K+1], and an output terminal for outputting a 2N-K+1th gate signal GS[2N-K+1].
[0112] Therefore, the first stage STAGE[1] to the N-K+1th stage STAGE[N-K+1] can receive the vertical start signal FLM, and the subsequent stages can receive the gate signals of the respective previous stages as input signals. In addition, the method of applying the first clock signal CLK1 to the sixth clock signal CLK6 can be repeated in units of six stages.
[0113] Figure 4B It shows that when N is 2 Figure 4A Block diagram of a gate driver.
[0114] refer to Figure 4A and Figure 4B In an embodiment, N may be 2. Figure 4B , the first stage STAGE[1] to the fourth stage STAGE[4] are shown to illustrate the operation of the gate driver 410 when N is 2.
[0115] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1, a second clock terminal for receiving a second clock signal CLK2, a carry terminal for receiving a vertical start signal FLM, and an output terminal for outputting a first gate signal GS[1]. The second stage STAGE[2] may include a first clock terminal for receiving a third clock signal CLK3 from a third clock line CL3, a second clock terminal for receiving a fourth clock signal CLK4 from a fourth clock line CL4, a carry terminal for receiving a vertical start signal FLM, and an output terminal for outputting a second gate signal GS[2]. The third stage STAGE[3] may include a first clock terminal for receiving a second clock signal CLK2, a second clock terminal for receiving a first clock signal CLK1, a carry terminal for receiving the first gate signal GS[1] as an input signal, and an output terminal for outputting a third gate signal GS[3]. The fourth stage STAGE[4] may include a first clock terminal for receiving a fourth clock signal CLK4, a second clock terminal for receiving a third clock signal CLK3, a carry terminal for receiving the second gate signal GS[2] as an input signal, and an output terminal for outputting a fourth gate signal GS[4].
[0116] Therefore, the first stage STAGE[1] and the second stage STAGE[2] can receive the vertical start signal FLM, and the subsequent stages STAGE[3], STAGE[4], ... can receive the gate signals GS[1], GS[2], GS[3], GS[4], ... of the respective previous stages as input signals. In addition, the method of applying the first clock signal CLK1 to the fourth clock signal CLK4 can be repeated in units of four stages.
[0117] Figure 4C It is shown Figure 4A Circuit diagram of the first stage of the gate driver.
[0118] refer to FIG. 4A to FIG. 4C , the first stage STAGE[1] may include first to eighth transistors T1 to T8, a first capacitor C1 and a second capacitor C2.
[0119] The first transistor T1 may include a gate electrode for receiving the first clock signal CLK1, a first electrode for receiving the vertical start signal FLM, and a second electrode connected to the first control node NQ1. The second transistor T2 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the third transistor T3. The third transistor T3 may include a gate electrode for receiving the second clock signal CLK2, a first electrode connected to the second electrode of the second transistor T2, and a second electrode connected to the first control node NQ1. The fourth transistor T4 may include a gate electrode connected to the first control node NQ1, a first electrode for receiving the first clock signal CLK1, and a second electrode connected to the inverting control node NQB. The fifth transistor T5 may include a gate electrode for receiving the first clock signal CLK1, a first electrode for receiving the low gate voltage VGL, and a second electrode connected to the inverting control node NQB. The sixth transistor T6 may include a gate electrode connected to the inverting control node NQB, a first electrode for receiving the high gate voltage VGH, and a second electrode connected to the gate output node NGS for outputting the first gate signal GS[1]. The seventh transistor T7 may include a gate electrode connected to the second control node NQ2, a first electrode for receiving the second clock signal CLK2, and a second electrode connected to the gate output node NGS. The eighth transistor T8 may include a gate electrode for receiving the low gate voltage VGL, a first electrode connected to the first control node NQ1, and a second electrode connected to the second control node NQ2.
[0120] The first capacitor C1 may include a first electrode for receiving the high gate voltage VGH and a second electrode connected to the inversion control node NQB. The second capacitor C2 may include a first electrode connected to the second control node NQ2 and a second electrode connected to the gate output node NGS.
[0121] Figure 4D It is shown Figure 4A A timing diagram of the first clock signal to the 2Nth clock signal of the gate driver.
[0122] refer to 4A to 4DIn an embodiment, each of the first to 2N-th clock signals CLK1 to CLK2N may alternately have an active period and an inactive period, and the active periods do not overlap. In an embodiment, when the length of the active period of each of the first to 2N-th clock signals CLK1 to CLK2N is J horizontal times JH, the length of the inactive period of each of the first to 2N-th clock signals CLK1 to CLK2N is (2N-1)×J horizontal times (2N-1)×JH, thereby generating a cycle of 2N×J horizontal times 2N×JH for each of the first to 2N-th clock signals CLK2N. Here, J is a positive number.
[0123] Figure 4E is to show that when N is 2 and J is 1 Figure 4A Timing diagram of the operation of the gate driver.
[0124] refer to FIG. 4A to FIG. 4E , in an embodiment, N may be 2 and J may be 1. In this case, the length of the active period of each of the first to 2N-th clock signals CLK1 to CLK2N may be 1 horizontal time 1H, the length of the inactive period of each of the first to 2N-th clock signals CLK1 to CLK2N may be 3 horizontal times 3H, and the cycle of each of the first to 2N-th clock signals CLK1 to CLK2N may be 4 horizontal times 4H.
[0125] The first stage STAGE[1] may receive the vertical start signal FLM based on the first clock signal CLK1, and output the first gate signal GS[1] based on the second clock signal CLK2. The second stage STAGE[2] may receive the vertical start signal FLM based on the third clock signal CLK3, and output the second gate signal GS[2] based on the fourth clock signal CLK4. The third stage STAGE[3] may receive the first gate signal GS[1] based on the second clock signal CLK2, and output the third gate signal GS[3] based on the first clock signal CLK1. The fourth stage STAGE[4] may receive the second gate signal GS[2] based on the fourth clock signal CLK4, and output the fourth gate signal GS[4] based on the third clock signal CLK3.
[0126] The stages STAGE[1], STAGE[2], STAGE[3], STAGE[4], ... can sequentially output gate signals GS[1], GS[2], GS[3], GS[4], ... within one frame period.
[0127] The period of each of the first clock signal CLK1 to the fourth clock signal CLK4 can be a relatively long 4 horizontal times 4H. Therefore, the frequency of each of the first clock signal CLK1 to the fourth clock signal CLK4 is low, resulting in low power consumption. Since the first clock line CL1 to the fourth clock line CL4 providing the first clock signal CLK1 to the fourth clock signal CLK4 are connected to half of the stage, the capacitance of the equivalent capacitor observed from the first clock line CL1 to the fourth clock line CL4 is small, further reducing power consumption.
[0128] Therefore, when N is large, the period of each of the first to 2N clock signals CLK1 to CLK2N can be long, resulting in low power consumption. In addition, when N is large, the capacitance of the equivalent capacitor observed from each of the first to 2N clock lines CL1 to CL2N can be small, further reducing power consumption.
[0129] Figure 4F It shows that when N is 3 Figure 4A Block diagram of a gate driver.
[0130] refer to Figure 4F In an embodiment, N may be 3. Figure 4F , the first stage STAGE[1] to the sixth stage STAGE[6] are shown to illustrate the operation of the gate driver 430 when N is 3.
[0131] The first stage STAGE[1] may include a first clock terminal for receiving a first clock signal CLK1, a second clock terminal for receiving a second clock signal CLK2, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a first gate signal GS[1]. The second stage STAGE[2] may include a first clock terminal for receiving a third clock signal CLK3, a second clock terminal for receiving a fourth clock signal CLK4, a carry terminal for receiving a vertical start signal FLM as an input signal, and an output terminal for outputting a second gate signal GS[2]. The third stage STAGE[3] may include a first clock terminal for receiving a fifth clock signal CLK5 from a fifth clock line CL5, a second clock terminal for receiving a sixth clock signal CLK6 from a sixth clock line CL6, a carry terminal for receiving a vertical start signal FLM, and an output terminal for outputting a third gate signal GS[3]. The fourth stage STAGE[4] may include a first clock terminal for receiving the second clock signal CLK2, a second clock terminal for receiving the first clock signal CLK1, a carry terminal for receiving the first gate signal GS[1] as an input signal, and an output terminal for outputting a fourth gate signal GS[4]. The fifth stage STAGE[5] may include a first clock terminal for receiving the fourth clock signal CLK4, a second clock terminal for receiving the third clock signal CLK3, a carry terminal for receiving the second gate signal GS[2] as an input signal, and an output terminal for outputting a fifth gate signal GS[5]. The sixth stage STAGE[6] may include a first clock terminal for receiving the sixth clock signal CLK6, a second clock terminal for receiving the fifth clock signal CLK5, a carry terminal for receiving the third gate signal GS[3], and an output terminal for outputting the sixth gate signal GS[6].
[0132] Therefore, the first stage STAGE[1] to the third stage STAGE[3] may receive the vertical start signal FLM, and the subsequent stages STAGE[4], STAGE[5], STAGE[6], ... may receive the gate signals GS[1], GS[2], GS[3], GS[4], GS[5], GS[6], ... of the respective previous stages. In addition, the method of applying the first clock signal CLK1 to the sixth clock signal CLK6 may be repeated in units of six stages.
[0133] In an embodiment, N may be 3 and J may be 1. In this case, the length of the active period of each of the first to 2N-th clock signals CLK1 to CLK2N may be 1 horizontal time 1H, and the length of the inactive period of each of the first to 2N-th clock signals CLK1 to CLK2N may be 5 horizontal times 5H. Therefore, the cycle of each of the first to 2N-th clock signals CLK1 to CLK2N may be 6 horizontal times 6H.
[0134] The 6 horizontal times 6H are relatively long. Therefore, the frequency of each of the first clock signal CLK1 to the sixth clock signal CLK6 can be low, resulting in small power consumption. Since the first clock line CL1 to the sixth clock line CL6 providing the first clock signal CLK1 to the sixth clock signal CLK6 are connected to one-third of the stage, the capacitance of the equivalent capacitor observed from the first clock line CL1 to the sixth clock line CL6 is small, further reducing power consumption.
[0135] Figure 5 is a block diagram illustrating an electronic device. Figure 6 It shows that Figure 5 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a smart phone.
[0136] refer to Figure 5 and Figure 6 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The display device 10. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a graphics card, a sound card, a memory card, a universal serial bus (USB) device, another electronic device, and the like.
[0137] In an embodiment, if Figure 5 As shown in , the electronic device 1000 may be implemented as a smart watch. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, a video phone, a smart board, a smart watch, a tablet PC, a car navigation system, a computer monitor, a laptop computer, a head mounted display (HMD) device, etc.
[0138] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.
[0139] The memory device 1020 may store data for operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.
[0140] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, or the like.
[0141] I / O devices 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc. and output devices such as a printer, a speaker, etc. In some embodiments, I / O devices 1040 may include a display device 1060 .
[0142] The power supply 1050 may provide power for the operation of the electronic device 1000 .
[0143] Display device 1060 may be connected to other components via a bus or other communication links.
[0144] The inventive concept disclosed herein can be applied to any display device and any electronic device including a touch panel. For example, the inventive concept can be applied to mobile phones, smart phones, tablet computers, digital televisions (TVs), 3D TVs, personal computers (PCs), household appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.
[0145] The foregoing is an example of the inventive concept and should not be construed as limiting thereof. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible without substantially departing from the scope of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as set forth in the claims.
Claims
1. A gate driver, comprising: The first stage to the Nth stage are used to receive the first clock signal to the Nth clock signal from the first clock line to the Nth clock line, wherein N is a positive integer of 3 or more, The first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal. wherein the NKth stage comprises a first clock terminal for receiving an NKth clock signal, a second clock terminal for receiving an N-K+1th clock signal, a carry terminal for receiving an NK-1th gate signal, and an output terminal for outputting an NKth gate signal, wherein K is a positive integer between 1 and N-2, and The Nth stage includes a first clock terminal for receiving the Nth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the N-1th gate signal, and an output terminal for outputting the Nth gate signal.
2. The gate driver according to claim 1, wherein: When N is 4, the gate driver includes: said first level; a second stage, comprising a first clock terminal for receiving the second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a second gate signal; a third stage, comprising a first clock terminal for receiving the third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a third gate signal; and The fourth stage includes a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting a fourth gate signal.
3. The gate driver according to claim 1, when N is 6, the gate driver comprises: said first level; a second stage, comprising a first clock terminal for receiving the second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a second gate signal; a third stage, comprising a first clock terminal for receiving the third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a third gate signal; a fourth stage, comprising a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving the fifth clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting a fourth gate signal; a fifth stage, comprising a first clock terminal for receiving the fifth clock signal, a second clock terminal for receiving the sixth clock signal, a carry terminal for receiving the fourth gate signal, and an output terminal for outputting the fifth gate signal; as well as The sixth stage includes a first clock terminal for receiving the sixth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the fifth gate signal, and an output terminal for outputting the sixth gate signal.
4. The gate driver according to claim 1, wherein: An activation period of each of the first to Nth clock signals does not overlap with each other.
5. The gate driver according to claim 4, wherein: When the length of the activation period of each of the first clock signal to the Nth clock signal is J horizontal times, the length of the inactive period of each of the first clock signal to the Nth clock signal is (N-1)×J horizontal times, and the period of each of the first clock signal to the Nth clock signal is N×J horizontal times, where J is a positive number.
6. The gate driver according to claim 5, wherein: When N is 4 and J is 1, the length of the activation period of each of the first clock signal to the Nth clock signal is 1 horizontal time, and the length of the inactive period of each of the first clock signal to the Nth clock signal is 3 horizontal times, and the period of each of the first clock signal to the Nth clock signal is 4 horizontal times.
7. The gate driver according to claim 5, wherein: As N increases, the period of each of the first to Nth clock signals increases.
8. The gate driver according to claim 5, wherein: As N increases, the capacitance of the equivalent capacitor observed from each of the first clock line to the Nth clock line decreases.
9. The gate driver according to claim 1, wherein: The first level includes: a first transistor comprising a gate electrode for receiving the first clock signal, a first electrode for receiving the vertical start signal, and a second electrode connected to a first control node; a second transistor including a second electrode, a gate electrode connected to the inverting control node, and a first electrode for receiving a high gate voltage; a third transistor comprising a gate electrode for receiving the second clock signal, a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first control node; a fourth transistor comprising a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node; a fifth transistor comprising a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node; a sixth transistor comprising a gate electrode connected to the inverting control node, a first electrode for receiving the high gate voltage, and a second electrode connected to a gate output node configured to output the first gate signal; a seventh transistor comprising a gate electrode connected to the second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node; a first capacitor including a first electrode for receiving the high gate voltage and a second electrode connected to the inverting control node; and A second capacitor includes a first electrode connected to the second control node and a second electrode connected to the gate output node.
10. The gate driver according to claim 9, wherein: The first level also includes: An eighth transistor includes a gate electrode for receiving the low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.
11. A gate driver comprising: The first stage to the 2N stage are used to receive the first clock signal to the 2N clock signal from the first clock line to the 2N clock line, wherein N is a positive integer of 2 or more, The N-K+1th stage includes a first clock terminal for receiving a 2N-2K+1th clock signal and a second clock terminal for receiving a 2N-2K+2th clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting an N-K+1th gate signal, wherein K is a positive integer greater than 1 and less than N, and Among them, the 2N-K+1th level includes a first clock terminal for receiving the 2N-2K+2th clock signal, a second clock terminal for receiving the 2N-2K+1th clock signal, a carry terminal for receiving the N-K+1th gate signal, and an output terminal for outputting the 2N-K+1th gate signal.
12. The gate driver according to claim 11, wherein: When N is 2, the gate driver includes: The first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, a carry terminal for receiving the vertical start signal, and an output terminal for outputting a first gate signal; The second stage includes a first clock terminal for receiving a third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the vertical start signal, and an output terminal for outputting a second gate signal; a third stage, comprising a first clock terminal for receiving the second clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a third gate signal; and The fourth stage includes a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving the third clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a fourth gate signal.
13. The gate driver according to claim 11, wherein: An activation period of each of the first to 2Nth clock signals does not overlap with each other.
14. The gate driver according to claim 13, wherein: When the length of the activation period of each of the first clock signal to the 2Nth clock signals is J horizontal times, the length of the inactive period of each of the first clock signal to the 2Nth clock signals is (2N-1)×J horizontal times, and the period of each of the first clock signal to the 2Nth clock signals is 2N×J horizontal times, where J is a positive number.
15. The gate driver according to claim 14, wherein: As N increases, the period of each of the first to 2Nth clock signals increases.
16. The gate driver according to claim 14, wherein: As N increases, the capacitance of the equivalent capacitor observed from each of the first to the 2Nth clock lines decreases.
17. The gate driver according to claim 11, wherein: The first level includes: a first transistor comprising a gate electrode for receiving the first clock signal, a first electrode for receiving the vertical start signal, and a second electrode connected to a first control node; a second transistor including a second electrode, a gate electrode connected to the inverting control node, and a first electrode for receiving a high gate voltage; a third transistor comprising a gate electrode for receiving the second clock signal, a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first control node; a fourth transistor comprising a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node; a fifth transistor comprising a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node; a sixth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving the high gate voltage, and a second electrode connected to a gate output node configured to output a first gate signal; a seventh transistor comprising a gate electrode connected to the second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node; a first capacitor including a first electrode for receiving the high gate voltage and a second electrode connected to the inverting control node; and A second capacitor includes a first electrode connected to the second control node and a second electrode connected to the gate output node.
18. A display device comprising: A display panel, including pixels; as well as a gate driver configured to provide a gate signal to the display panel, wherein the gate driver comprises a first stage to an Nth stage for receiving a first clock signal to an Nth clock signal from a first clock line to an Nth clock line, wherein N is a positive integer of 3 or more, The first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal. wherein the NKth stage comprises a first clock terminal for receiving an NKth clock signal, a second clock terminal for receiving an N-K+1th clock signal, a carry terminal for receiving an NK-1th gate signal, and an output terminal for outputting an NKth gate signal, wherein K is a positive integer between 1 and N-2, and The Nth stage includes a first clock terminal for receiving the Nth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the N-1th gate signal, and an output terminal for outputting the Nth gate signal.
19. The display device according to claim 18, wherein: When N is 4, the gate driver includes: The first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, a carry terminal for receiving the vertical start signal, and an output terminal for outputting a first gate signal; a second stage, comprising a first clock terminal for receiving the second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a second gate signal; a third stage, comprising a first clock terminal for receiving the third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a third gate signal; and The fourth stage includes a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting a fourth gate signal.
20. The display device according to claim 18, wherein: An activation period of each of the first to Nth clock signals does not overlap with each other.