Read reference circuit, compensation method thereof and read reference circuit device

Abstract

The invention provides a read reference circuit, a compensation method thereof and a read reference circuit device. The read reference circuit comprises a sensitive amplification module, a first circuit module and a second circuit module, wherein the sensitive amplification module is provided with a first input end and a second input end; the first circuit module comprises a first reference module, the first reference module comprises a first magnetic tunnel junction unit and a first switching device, the first reference module is electrically connected with a first input end of the sensitive amplification module, and the first magnetic tunnel junction unit is in an anti-parallel state; the second circuit module comprises a first data module, the first data module comprises a second magnetic tunnel junction unit and a second switching device, and the first data module is electrically connected with the second input end of the sensitive amplification module; the number of the first branches connected in parallel with the first reference module is consistent with the number of the second branches connected in parallel with the first data module, and the reading reference circuit improves the reading circuit yield and increases the reading window of the circuit under the condition of temperature change.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit design, and in particular, to a read reference circuit, a compensation method thereof, and a read reference circuit device. Background Art

[0002] Since the MRAM device has a temperature characteristic in the antiparallel state (AP state), that is, the resistance in the AP state changes with temperature, the existing technology uses a separate Poly reference resistor with a small temperature coefficient and cannot be adaptively adjusted with temperature, resulting in a large change in the relative resistance value of the reference resistor and the data resistor due to temperature reasons, which reduces the read yield when reading the data circuit and reduces the read window at high temperatures. Summary of the invention

[0003] The main purpose of the present application is to provide a read reference circuit, a compensation method thereof and a read reference circuit device, so as to at least solve the problem in the prior art that the read yield of reading the resistance of the data circuit of an MRAM device under temperature changes is reduced and the read window becomes smaller at high temperatures.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a read reference circuit is provided, including: a sensitive amplifier module, having a first input terminal and a second input terminal; a first circuit module, including a first reference module, wherein the first reference module includes a plurality of first branches connected in parallel, each first branch includes a first magnetic tunnel junction unit, a first switching device and a first reference word line, wherein the first reference word line is electrically connected to the first switching device in a one-to-one correspondence, the first reference module is electrically connected to the first input terminal of the sensitive amplifier module, and the first magnetic tunnel junction unit is in an anti-parallel state; a second circuit module, including a first data module, wherein the first data module includes a plurality of second branches connected in parallel, each second branch includes a second magnetic tunnel junction unit, a second switching device and a first data word line, wherein the first data word line is electrically connected to the second switching device in a one-to-one correspondence, and the first data module is electrically connected to the second input terminal of the sensitive amplifier module; the number of first branches connected in parallel in the first reference module is consistent with the number of second branches connected in parallel in the first data module.

[0005] Optionally, the first reference module also includes a resistance module and a compensation resistor, and the resistance module and the compensation resistor are both arranged in series with multiple parallel first branches, wherein the resistance module is an adjustable resistor, the compensation resistor is a fixed resistor, and the resistance value of the compensation resistor is 1 / 2 of the resistance value when the second magnetic tunnel junction unit is in a parallel state.

[0006] Optionally, the first reference module further includes: a first reference bit line electrically connected to one end of the plurality of parallel first branches located on the same side; and a first reference source line electrically connected to one end of the plurality of parallel first branches located on the other side.

[0007] Optionally, the first data module further includes: a first data bit line electrically connected to the same side of the plurality of parallel second branches; and a first data source line electrically connected to the same side of the plurality of parallel second branches.

[0008] Optionally, a clamping tube is connected between the first circuit module and the first input end, and between the second circuit module and the second input end.

[0009] Optionally, the first reference module also includes a first transmission gate, which is arranged in series with multiple parallel first branches, compensation resistors and resistance modules on the first reference bit line; the first data module also includes a second transmission gate, which is arranged in series with multiple parallel second branches on the first data bit line.

[0010] Optionally, the first circuit module further includes a second reference module, the second reference module having a second reference source line, a second reference bit line, a third transmission gate and a plurality of third branches connected in parallel, the third transmission gate and the plurality of third branches connected in parallel are arranged in series on the second reference bit line, each third branch includes a third magnetic tunnel junction unit, a third switch device and a second reference word line, the second reference word line is electrically connected to the third switch device in a one-to-one correspondence, the first reference module has one end of the first transmission gate and the second reference module has one end of the third transmission gate electrically connected to the resistor module, the compensation resistor and the first input terminal, and the other end of the second reference module is electrically connected to the second reference The source line is electrically connected; the second circuit module also includes a second data module, the second data module has a second data source line, a second data bit line, a fourth transmission gate and a plurality of parallel fourth branches, the fourth transmission gate and the plurality of parallel fourth branches are arranged in series on the second data bit line, each fourth branch includes a fourth magnetic tunnel junction unit, a fourth switching device and a second data word line, the second data word line and the fourth switching device are electrically connected in a one-to-one correspondence, the first data module has one end of the second transmission gate and the second data module has one end of the fourth transmission gate are electrically connected to the second input terminal, and the other end of the second data module is electrically connected to the second data source line.

[0011] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a compensation method for a read reference circuit is provided, wherein the first reference module in the read reference circuit includes a resistance module and a compensation resistor, and the compensation method includes: when the first magnetic tunnel junction unit in the first branch of the first reference module in the first circuit module in the read reference circuit is adjusted to an anti-parallel state, controlling a second switch unit of the first data module in the second circuit module in the read reference circuit to be opened so as to turn on one of the multiple second branches in the first data module; controlling two first switch units of the first reference module in the first circuit module so as to turn on two of the multiple first branches in the first reference module; and calculating the reference resistance of the first reference module according to the resistance of the turned-on first branch, the resistance of the resistance module and the resistance of the compensation resistor.

[0012] Optionally, the first data module in the read reference circuit includes a first data bit line. After the step of turning on a second branch among the multiple second branches, the compensation method also includes: obtaining position information of the turned-on second branch, and deriving a parasitic resistance value of the position information, wherein the first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit, the turned-on second branch is connected to the first node of the first data bit line, and the position information is used to indicate the length between the first end and the first node on the first data bit line; determining a parasitic resistance value corresponding to the position information based on the position information and a preset resistance value of the first data bit line; and sending an adjustment signal to the resistance module based on the parasitic resistance value corresponding to the position information, so that the resistance module adjusts the resistance value to be consistent with the parasitic resistance value.

[0013] According to another aspect of the present application, a read reference circuit device is provided, wherein a first reference module in the read reference circuit includes a resistance module and a compensation resistor, and the circuit device includes: a first control module, used to control a second switch unit of a first data module in a second circuit module in the read reference circuit to open when a first magnetic tunnel junction unit in a first branch of the first reference module in a first circuit module in the read reference circuit is adjusted to an antiparallel state, so as to turn on a second branch among multiple second branches in the first data module; a second control module, used to control two first switch units of the first reference module in the first circuit module, so as to turn on two branches among multiple first branches in the first reference module; and a calculation module, used to calculate a reference resistance value of the first reference module according to the resistance value of the turned-on first branch, the resistance value of the resistance module and the resistance value of the compensation resistor.

[0014] Optionally, the first data module in the read reference circuit includes a first data bit line, and the first control module in the read reference circuit device also includes: an acquisition module, used to acquire the position information of the second branch that is turned on, and derive the parasitic resistance value of the position information, wherein the first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit, the second branch that is turned on is connected to the first node of the first data bit line, and the position information is used to indicate the length between the first end and the first node on the first data bit line; a first processing module, used to determine the parasitic resistance value corresponding to the position information based on the position information and the preset resistance value of the first data bit line; and a second processing module, used to send an adjustment signal to the resistance module based on the parasitic resistance value corresponding to the position information, so that the resistance module adjusts the resistance value to be consistent with the parasitic resistance value.

[0015] By applying the technical solution of the present application, the sensitive amplifier module has a first input terminal and a second input terminal, the first data module in the second circuit module includes a plurality of second branches connected in parallel, each of the second branches includes a first data word line, and a second magnetic tunnel junction unit and a second switch device electrically connected to the first data word line, the first data module is electrically connected to the second input terminal of the sensitive amplifier module, the first reference module in the first circuit module includes a plurality of first branches connected in parallel, each of the first branches includes a first reference word line, and a first magnetic tunnel junction unit and a first switch device electrically connected to the first reference word line, the first reference module is electrically connected to the first input terminal of the sensitive amplifier module, and the first magnetic The tunnel junction unit is in an antiparallel state. When the second magnetic tunnel junction unit in the first data module is in an antiparallel state, if the temperature changes, its resistance will change accordingly. The resistance of the first magnetic tunnel junction unit in the antiparallel state in the first reference module will also change with the temperature, which can offset the impact of the temperature change on the resistance of the second magnetic tunnel junction unit in the first data module. Since the number of first branches connected in parallel in the first reference module is consistent with the number of second branches connected in parallel in the first data module, the first branch can also compensate for the leakage current generated by the second branch. The above technical solution improves the yield of the read circuit and increases the read window of the circuit under temperature changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic structural diagram of a read reference circuit provided in an embodiment of the present application is shown;

[0018] Figure 2 A schematic diagram of the structure of another read reference circuit provided according to an embodiment of the present application is shown;

[0019] Figure 3 A flowchart of a compensation method for a read reference circuit provided according to an embodiment of the present application is shown;

[0020] Figure 4 A flowchart of another compensation method for a read reference circuit provided according to an embodiment of the present application is shown;

[0021] Figure 5 A schematic structural block diagram of a read reference circuit device provided according to an embodiment of the present application is shown;

[0022] Figure 6 A schematic structural block diagram of another read reference circuit device provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] As introduced in the background technology, in the prior art, MRAM devices have temperature characteristics in the antiparallel state (AP state), that is, the AP state resistance will change with temperature. In the prior art, a separate Poly reference resistor is used, which has a small temperature coefficient and cannot be adaptively adjusted with temperature, resulting in a large change in the relative resistance value of the reference resistor and the data resistor due to temperature reasons, which leads to a decrease in the read yield when reading the data circuit and a smaller read window at high temperatures. In order to solve the problem of a decrease in the read yield of the data circuit resistance in the MRAM device under temperature changes and a smaller read window at high temperatures, the embodiments of the present application provide a read reference circuit and a compensation method thereof, and a read reference circuit device.

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0028] According to one embodiment of the present application, Figure 1As shown, the read reference circuit includes: a sensitive amplifier module SA, a first circuit module and a second circuit module, wherein the sensitive amplifier module SA has a first input terminal IREF and a second input terminal IREAD; the first circuit module includes a first reference module, the first reference module includes a plurality of first branches connected in parallel, each first branch includes a first reference word line WL_REF_U (WL_REF_U0 to WL_REF_U1023), a first magnetic tunnel junction unit R_REF (R_REF0 to R_REF1023) and a first switch device S (S0 to S1023), wherein the first reference word line WL_REF_U is electrically connected to the first switch device S in a one-to-one correspondence, and the first reference module is electrically connected to the sensitive amplifier module SA. The first input terminal IREF of the module SA is electrically connected, and the first magnetic tunnel junction unit R_REF is in an anti-parallel state; the second circuit module includes a first data module, the first data module includes multiple parallel second branches, each second branch includes a first data word line WL_D (WL_D0~WL_D1023), a second magnetic tunnel junction unit R (R0~R1023) and a second switch device SS (SS0~SS1023), wherein the first data word line WL_D is electrically connected to the second switch device SS in a one-to-one correspondence, and the first data module is electrically connected to the second input terminal IREAD of the sensitive amplifier module SA; the number of first branches in parallel of the first reference module is consistent with the number of second branches in parallel of the first data module.

[0029] In the above optional implementation, if Figure 1As shown, the sensitive amplifier SA has a first input terminal IREF and a second input terminal IREAD, wherein the first input terminal IREF is electrically connected to the first circuit module, and the second input terminal IREAD is electrically connected to the second circuit module; the first reference module in the first circuit module is used to generate a reference resistance and calibrate the accuracy of the resistance of the second circuit module, and the first reference module includes a plurality of first branches connected in parallel, each of which includes a first magnetic tunnel junction unit R_REF (R_REF0~R_REF1023), a first switch device S (S0~S1023) and a first The reference word line WL_REF_U, wherein the first reference word line WL_REF_U is electrically connected to the second switch device SS in a one-to-one correspondence, the first magnetic tunnel junction unit R_REF is in an anti-parallel state, and the first reference word line WL_REF_U of each first branch is shared; the second circuit module includes a first data module, the first data module includes a plurality of parallel second branches, each second branch includes a second magnetic tunnel junction unit R (R0-R1023), a second switch device SS (SS0-SS1023) and a first data word line WL_D, wherein the first A data word line WL_D is electrically connected to the second switch device SS in a one-to-one correspondence, and the first data word line WL_D of each second branch is shared. The first data module is used to read the resistance value of the second magnetic tunnel junction unit R; the number of first branches connected in parallel to the first reference module is consistent with the number of second branches connected in parallel to the first data module, that is, the first reference module and the first data module have the same structure, so that when the temperature changes, the influence of the temperature change on the resistance value of the second magnetic tunnel junction unit R in the first data module can be offset. When the second magnetic tunnel junction unit R in the first data module is in a parallel state, if the temperature changes, its resistance value will change accordingly, and the resistance value of the first magnetic tunnel junction unit R_REF in the anti-parallel state in the first reference module will also change with the temperature change, thereby offsetting the influence of the temperature change on the resistance value of the second magnetic tunnel junction unit R in the first data module. Since the number of first branches connected in parallel to the first reference module is consistent with the number of second branches connected in parallel to the first data module, the first branch can also compensate for the leakage current generated by the second branch. The above technical solution improves the yield of the read circuit and increases the read window of the circuit under temperature changes.

[0030] The above-mentioned switching device can be a switching transistor, in which case the base of the switching transistor is electrically connected to the reference circuit, the collector is electrically connected to the magnetic tunnel junction unit, and the emitter is electrically connected to the reference source line or the data source line; or the base of the switching transistor is electrically connected to the reference circuit, the emitter is electrically connected to the magnetic tunnel junction unit, and the collector is electrically connected to the reference source line or the data source line. This application does not specifically limit the type of switching device.

[0031] The magnetic tunnel junction unit may have various forms depending on the application, including but not limited to in-plane MTJ, vertical MTJ, top pinned MTJ, bottom pinned MTJ, double-layer MgO MTJ, single-layer MgO MTJ and polymorphic MTJ, which are not specifically limited in this field.

[0032] In some optional embodiments, such as Figure 1 As shown, the first reference module also includes a resistance module R1 and a compensation resistor R2. The resistance module R1 is an adjustable resistor, and both the resistance module R1 and the compensation resistor R2 are arranged in series with multiple parallel first branches. The compensation resistor R2 is a fixed resistor, and the resistance value of the compensation resistor R2 is 1 / 2 of the resistance value when the second magnetic tunnel junction unit R is in a parallel state.

[0033] In the above optional implementation, if Figure 1 As shown, the first reference module may also include two resistance parts for better compensating the resistance value of the first data circuit when the temperature changes, namely, resistance module R1 and compensation resistor R2, wherein the resistance module R1 is set to an adjustable resistor, and the resistance value of the compensation resistor R2 is set to 1 / 2 of the resistance value when the second magnetic tunnel junction unit R is in a parallel state. In order to make the first reference module in a relatively ideal reference state when reading the circuit, it is necessary to set the resistance value of the first reference module to the middle value of the resistance value of the first data module. The first data module has two forms, parallel state and anti-parallel state, and the resistance value in the parallel state is fixed. Here, the resistance value of the compensation resistor R2 is set to 1 / 2 of the resistance value when the second magnetic tunnel junction unit R is in the parallel state, just to make the parallel state resistance in the first reference module at the middle value of the parallel state resistance of the first data module, and then the resistance value of the anti-parallel state can be set. The first reference module is in a relatively ideal reference state, which can enhance the accuracy of the reading circuit reference.

[0034] In the above optional implementation manner, the resistance module R1 can be a digital resistor or an analog resistor, which is not specifically limited in the present application.

[0035] In some optional embodiments, such as Figure 1 As shown, the first reference module also includes: a first reference bit line BL_REF_U and a first reference source line SL_REF_U, wherein the first reference bit line BL_REF_U is electrically connected to one end of multiple parallel first branches located on the same side, and the first reference source line SL_REF_U is electrically connected to one end of multiple parallel first branches located on the other side.

[0036] In the above optional implementation, if Figure 1As shown, the multiple parallel first branches have a first reference word line WL_REF_U, a first magnetic tunnel junction unit R_REF and a first switch device S, so that one end of the multiple parallel first branches located on the same side is electrically connected to the first reference bit line BL_REF_U, and one end of the multiple parallel first branches located on the other side is electrically connected to the first reference source line SL_REF_U, the first reference bit line BL_REF_U is connected to one end of each first branch close to the first magnetic tunnel junction unit R_REF, and the first reference source line SL_REF_U is connected to one end of each first branch close to the first switch device S. Figure 1 In the circuit structure shown in FIG. 1 , the first reference bit line BL_REF_U can also be connected to one end of each first branch close to the first switching device S, and the first reference source line SL_REF_U is connected to one end of each first branch close to the first magnetic tunnel junction unit R_REF, so that the entire first reference module forms an array structure.

[0037] In some optional embodiments, such as Figure 1 As shown, the first data module also includes: a first data bit line BL_D and a first data source line SL_D, wherein the first data bit line BL_D is electrically connected to the same side of multiple parallel second branches; the first data source line SL_D is electrically connected to the same side of multiple parallel second branches.

[0038] In the above optional implementation, if Figure 1 As shown, the plurality of parallel second branches have a first data bit line BL_D, a second magnetic tunnel junction unit R and a second switch device SS, so that one end of the plurality of parallel second branches located on the same side is electrically connected to the first data bit line BL_D, one end of the plurality of parallel second branches located on the other side is electrically connected to the first data source line SL_D, the first data bit line BL_D is connected to one end of each second branch close to the second magnetic tunnel junction unit R, and the first data bit line BL_D is connected to one end of each second branch close to the second switch device SS. Figure 1 In the circuit structure shown in, the first data bit line BL_D can also be connected to one end of each second branch close to the second switching device SS, and the first data bit line BL_D is connected to one end of each second branch close to the second magnetic tunnel junction unit R, so that the entire first data module forms an array structure.

[0039] In some optional embodiments, such as Figure 1 As shown, a clamping tube is connected between the first circuit module and the first input terminal IREF and between the second circuit module and the second input terminal IREAD.

[0040] In the above optional implementation, if Figure 1As shown, two clamping tubes are provided, namely the first clamping tube Q1 and the second clamping tube Q2, wherein the first circuit module is electrically connected to the first input terminal IREF of the sense amplifier SA through the first clamping tube Q1, and the second circuit module is electrically connected to the second input terminal IREAD of the sense amplifier SA through the second clamping tube Q2. When the voltage exceeds the forward voltage of the clamping tube, the clamping tube starts to conduct and guides the current in the circuit to the ground. The provision of the clamping tube can prevent overvoltage and overcurrent from occurring and protect other electronic components in the integrated circuit from damage; the above-mentioned clamping tube can be a diode.

[0041] In some optional embodiments, such as Figure 2 As shown, the first reference module also includes a first transmission gate TG1, which is connected in series with multiple parallel first branches, compensation resistor R2 and resistance module R1 and is arranged on the first reference bit line BL_REF_U; the first data module also includes a second transmission gate TG2, which is connected in series with multiple parallel second branches and is arranged on the first data bit line BL_D.

[0042] In the above optional implementation, if Figure 2 As shown, multiple parallel first branches in the first reference module, the compensation resistor R2, the resistor module R1 and the first transmission gate TG1 are arranged in series on the first reference bit line BL_REF_U, and multiple parallel second branches in the first data module and the second transmission gate TG2 are arranged in series on the first data bit line BL_D. By setting a transmission gate in each module, the read reference circuit can read more than one data module, and can read multiple data modules alternately. For example, the first data module can be read first, using the first reference module as a reference, and then the second data module can be read, using the second reference module as a reference. There is no need to replace a new circuit, which is more convenient.

[0043] In some optional embodiments, such as Figure 2As shown, the first circuit module also includes a second reference module, having a second reference source line SL_REF_D, a second reference bit line BL_REF_D, a third transmission gate TG3 and a plurality of third branches connected in parallel, the third transmission gate TG3 and the plurality of third branches connected in parallel are arranged in series on the second reference bit line BL_REF_D, each third branch includes a third magnetic tunnel junction unit R1_REF (R1_REF0~R1_REF1023), a third switch device S1 (S1_0~S1_1023) and a second reference word line WL_REF_D (WL_REF_D0~WL_REF_D1023), wherein the second reference word line WL_REF_D is electrically connected to the third switch device in a one-to-one correspondence, the first reference module has one end of the first transmission gate TG1, and the second reference module has one end of the third transmission gate TG3 electrically connected to the resistor module R1, the compensation resistor R2 and the first input terminal IREF, and the second The other end of the reference module is electrically connected to the second reference source line SL_REF_D; the second circuit module also includes a second data module, having a second data source line SL_U, a second data bit line BL_U, a fourth transmission gate TG4 and a plurality of parallel fourth branches, the fourth transmission gate TG4 and the plurality of parallel fourth branches are arranged in series on the second data bit line BL_U, each fourth branch includes a fourth magnetic tunnel junction unit R1 (R1_0~R1_1023), a fourth switching device SS1 (SS1_0~SS1_1023) and a second data word line WL_U (WL_U0~WL_U1023), wherein the second data word line WL_U is electrically connected to the fourth switching device in a one-to-one correspondence, one end of the first data module having the second transmission gate TG2 and one end of the second data module having the fourth transmission gate TG4 are electrically connected to the second input terminal IREAD, and the other end of the second data module is electrically connected to the second data source line SL_U.

[0044] In the above optional implementation, if Figure 2As shown, the first circuit module can have two reference modules at the same time, and the second circuit module can also have two data modules at the same time. Specifically, the first circuit module also includes a second reference module, and the second reference module includes a second reference source line SL_REF_D, a second reference bit line BL_REF_D, a third transmission gate TG3 and a plurality of third branches connected in parallel, each of which includes a third magnetic tunnel junction unit R1_REF (R1_REF0~R1_REF1023), a third switch device S1 (S1_0~S1_1023) and a second reference word line WL_REF_ D (WL_REF_D0 ~ WL_REF_D1023), wherein the second reference word line WL_REF_D is electrically connected to the third switch device in a one-to-one correspondence, the first reference module has one end of the first transmission gate TG1 and the second reference module has one end of the third transmission gate TG3 is electrically connected to the resistor module R1, the compensation resistor R2 and the first input terminal IREF, and the other end of the second reference module is electrically connected to the second reference source line SL_REF_D; the second circuit module also includes a second data module, the second data module includes a second data source line SL_U, a second data bit line B L_U, a fourth transmission gate TG4 and a plurality of fourth branches connected in parallel, each of the fourth branches comprising a fourth magnetic tunnel junction unit R1 (R1_0 to R1_1023), a fourth switch device SS1 (SS1_0 to SS1_1023) and a second data word line WL_U (WL_U0 to WL_U1023), wherein the second data word line WL_U is electrically connected to the fourth switch device in a one-to-one correspondence, the first data module has an end of the second transmission gate TG2 and the second data module has an end of the fourth transmission gate TG4 electrically connected to the second input terminal IREAD, and the second data module The other end is electrically connected to the second data source line SL_U, wherein the transmission gate is used to select reading the first data module, with the first reference module serving as a reference for the first data module, or reading the second data module, with the second reference module serving as a reference for the second data module. When the control signal of the transmission gate is at a high level, the input signal can pass through the transmission gate and be transmitted to the output end, i.e., the module is selected to be turned on. When the control signal is at a low level, the transmission gate will be disconnected, and the input signal cannot pass through, i.e., the module is not selected. By setting a transmission gate in each module, the read reference circuit can read multiple circuits, which is more convenient.

[0045] Exemplarily, the read reference circuit includes a sense amplifier SA, a first circuit module and a second circuit module, wherein the sense amplifier SA has a first input terminal IREF and a second input terminal IREAD, wherein the first input terminal IREF is electrically connected to the first circuit module, and the second input terminal IREAD is electrically connected to the second circuit module; the first circuit module includes a first reference module for generating a reference resistance and calibrating the accuracy of the resistance of the second circuit module, the first reference module includes a plurality of first branches connected in parallel, each of the first branches includes a first magnetic tunnel junction unit R_REF (R_REF0 to R_REF1023), a first switch device S (S0 to S1023) and a first reference word line WL_REF_U, wherein the first reference word line WL_REF_U is electrically connected to the second switch device SS in a one-to-one correspondence, The first magnetic tunnel junction unit R_REF is in an anti-parallel state, and the first reference word line WL_REF_U of each first branch is shared; the second circuit module includes a first data module, the first data module includes a plurality of second branches connected in parallel, each second branch includes a second magnetic tunnel junction unit R (R0-R1023), a second switch device SS (SS0-SS1023) and a first data word line WL_D, wherein the first data word line WL_D is electrically connected to the second switch device SS in a one-to-one correspondence, the first data word line WL_D of each second branch is shared, and the first data module is used to read the resistance value of the second magnetic tunnel junction unit R; the number of first branches connected in parallel in the first reference module is consistent with the number of second branches connected in parallel in the first data module, that is, the structure of the first reference module and the first data module is the same;

[0046] The first reference module also includes two resistance parts, which are used to better compensate the resistance value of the first data circuit when the temperature changes, namely the resistance module R1 and the compensation resistor R2, wherein the resistance module R1 is set to an adjustable resistor, and the resistance value of the compensation resistor R2 is set to 1 / 2 of the resistance value when the second magnetic tunnel junction unit R is in a parallel state. Since the first reference module is to be in a relatively ideal reference state when reading the circuit, it is necessary to set the resistance value of the first reference module to the middle value of the resistance value of the first data module. The first data module has two forms, a parallel state and an anti-parallel state, and the resistance value in the parallel state is fixed. Here, the resistance value of the compensation resistor R2 is set to 1 / 2 of the resistance value when the second magnetic tunnel junction unit R is in a parallel state, just to make the parallel state resistance in the first reference module at the middle value of the parallel state resistance of the first data module;

[0047] A plurality of parallel first branches have a first reference word line WL_REF_U, a first magnetic tunnel junction unit R_REF and a first switch device S, so that one end of the plurality of parallel first branches located on the same side is electrically connected to the first reference bit line BL_REF_U, one end of the plurality of parallel first branches located on the other side is electrically connected to the first reference source line SL_REF_U, the first reference bit line BL_REF_U is connected to one end of each first branch close to the first magnetic tunnel junction unit R_REF, a plurality of parallel second branches have a first data bit line BL_D, a second magnetic tunnel junction unit R and a second switch device SS, so that one end of the plurality of parallel second branches located on the same side is electrically connected to the first data bit line BL_D, and one end of the plurality of parallel second branches located on the other side is electrically connected to the first data source line SL_D;

[0048] Two clamping tubes are provided, namely, a first clamping tube Q1 and a second clamping tube Q2, wherein the first circuit module is electrically connected to the first input terminal IREF of the sense amplifier SA through the first clamping tube Q1, and the second circuit module is electrically connected to the second input terminal IREAD of the sense amplifier SA through the second clamping tube Q2, a plurality of parallel first branches in the first reference module, a compensation resistor R2, a resistor module R1 and a first transmission gate TG1 are arranged in series on a reference bit line BL_REF_U, and a plurality of parallel second branches in the first data module and a second transmission gate TG2 are arranged in series on a data bit line BL_D;

[0049] The first circuit module may have two reference modules at the same time, and the second circuit module may also have two data modules at the same time. Specifically, the first circuit module also includes a second reference module, and the second reference module includes a second reference source line SL_REF_D, a second reference bit line BL_REF_D, a third transmission gate TG3, and a plurality of third branches connected in parallel, each of which includes a third magnetic tunnel junction unit R1_REF (R1_REF0 to R1_REF1023), a third switch device S1 (S1_0 to S1_1023), and a second reference word line WL_REF_D (WL_REF_D 0~WL_REF_D1023), wherein the second reference word line WL_REF_D is electrically connected to the third switch device in a one-to-one correspondence, the first reference module has one end of the first transmission gate TG1 and the second reference module has one end of the third transmission gate TG3 electrically connected to the resistor module R1, the compensation resistor R2 and the first input terminal IREF, and the other end of the second reference module is electrically connected to the second reference source line SL_REF_D; the second circuit module also includes a second data module, the second data module includes a second data source line SL_U, a second data bit line BL_U, a fourth transmission gate TG4 and a plurality of parallel first transmission gates TG5 and TG6. Four branches, each fourth branch includes a fourth magnetic tunnel junction unit R1 (R1_0 ~ R1_1023), a fourth switch device SS1 (SS1_0 ~ SS1_1023) and a second data word line WL_U (WL_U0 ~ WL_U1023), wherein the second data word line WL_U is electrically connected to the fourth switch device in a one-to-one correspondence, the first data module has an end of the second transmission gate TG2 and the second data module has an end of the fourth transmission gate TG4 is electrically connected to the second input terminal IREAD, and the other end of the second data module is electrically connected to the second data source line SL_U, by in each module Setting a transmission gate can make the read reference circuit read multiple circuits, which is more convenient. Through the above technical solution, if the temperature changes, the resistance of the magnetic tunnel junction unit in the data module will change accordingly, and the resistance of the magnetic tunnel junction unit in the anti-parallel state in the reference module will also change with the temperature, which can offset the impact of temperature changes on the resistance of the magnetic tunnel junction unit in the data module. Since the number of branches connected in parallel in the reference module is consistent with the number of branches connected in parallel in the data module, the leakage current generated by the branches in the data module can also be compensated, thereby improving the read circuit yield and increasing the read window of the circuit under temperature changes.

[0050] According to another embodiment of the present application, a compensation method for a read reference circuit is also provided. The first reference module in the read reference circuit includes a resistor module and a compensation resistor. The compensation method includes the following steps: Figure 3 As shown:

[0051] Step S101: when a first magnetic tunnel junction unit in a first branch of a first reference module in a first circuit module in a read reference circuit is adjusted to an antiparallel state, a second switch unit in a first data module in a second circuit module in the read reference circuit is controlled to be turned on, so that one second branch among a plurality of second branches in the first data module is turned on;

[0052] Specifically, the first magnetic tunnel junction unit is adjusted to an antiparallel state before reading the circuit. When reading circuit information, only the state of one branch can be read first, and a second switch unit of the first data module is controlled to be turned on to conduct a second branch.

[0053] Step S102: controlling two first switch units of a first reference module in a first circuit module to conduct two of the plurality of first branches in the first reference module;

[0054] Specifically, when making a reference to a second branch that is turned on, two parallel reference branches are required to control the two first switch units to turn on the two first branches. Since the first reference module is to be in a relatively ideal reference state when reading the circuit, the resistance value of the first reference module needs to be set to the middle value of the resistance value of the first data module. The two first branches are connected in parallel to make the anti-parallel resistance in the first reference module be at the middle value of the anti-parallel resistance of the first data module. Putting the first reference module in a relatively ideal reference state can enhance the accuracy of the reading circuit reference.

[0055] Step S103: Calculate the reference resistance of the first reference module according to the resistance of the first branch that is turned on, the resistance of the resistance module and the resistance of the compensation resistor.

[0056] Specifically, according to the resistance of the two first branches that are turned on, the resistance of the resistance module and the resistance of the compensation resistor can obtain the intermediate value of the resistance in the parallel state and the anti-parallel state of the first data module, so that the first reference module is in a more ideal reference state to enhance the accuracy of the read circuit reference.

[0057] By adjusting the first magnetic tunnel junction unit in the first branch of the first reference module in the first circuit module in the read reference circuit to an antiparallel state, first controlling a second switch unit in the first data module in the second circuit module in the read reference circuit to be turned on, so that one of the multiple second branches in the first data module is turned on, and then controlling the two first switch units of the first reference module in the first circuit module to turn on two of the multiple first branches in the first reference module, and finally calculating the reference resistance of the first reference module according to the resistance of the turned-on first branch, the resistance of the resistance module and the resistance of the compensation resistor. In order to make the first reference module in a relatively ideal reference state when reading the circuit, it is necessary The resistance value of the first reference module is set to the middle value of the resistance value of the first data module, and a second branch is turned on. The two first branches are connected in parallel so that the antiparallel resistance in the first reference module is at the middle value of the antiparallel resistance of the first data module, so that the first reference module is in a relatively ideal reference state. If the temperature changes, its resistance value will change accordingly. The resistance value of the first magnetic tunnel junction unit in the antiparallel state in the first reference module will also change with the temperature change, which can offset the influence of the temperature change on the resistance value of the second magnetic tunnel junction unit in the first data module, and can enhance the accuracy of the reading circuit reference. The above technical solution improves the yield of the reading circuit and increases the reading window of the circuit under temperature changes.

[0058] In some optional embodiments, such as Figure 4 As shown, the first data module in the read reference circuit includes a data bit line. After step S101, the compensation method further includes:

[0059] Step S1011: acquiring position information of the turned-on second branch and obtaining a parasitic resistance value of the position information, wherein the first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit, the turned-on second branch is connected to the first node of the first data bit line, and the position information is used to indicate the length between the first end and the first node on the first data bit line;

[0060] Specifically, the second branch that is turned on is electrically connected to the first data bit line, and has a first node at the connection point. The first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit. The length between the first node on the first data bit line and the second input end is the position of the second branch that is turned on, so as to subsequently obtain the resistance information of the second branch that is turned on.

[0061] Step S1012: determining a parasitic resistance value corresponding to the position information according to the position information and a preset resistance value of the first data bit line;

[0062] Specifically, according to the position information obtained in step S1011, the length between the first node and the second input terminal on the first data bit line can be known. The first data bit line has a preset resistance value, which can be set to the overall resistance value of the first data bit line. According to the ratio of the length between the first node and the second input terminal to the overall length of the first data bit line, the parasitic resistance value corresponding to the above length can be calculated, that is, the parasitic resistance value of the second branch that is conductive at this position is obtained.

[0063] Step S1013: sending an adjustment signal to the resistance module according to the parasitic resistance value corresponding to the position information, so that the resistance module adjusts the resistance value to be consistent with the parasitic resistance value.

[0064] Specifically, according to the parasitic resistance value of the conductive second branch obtained in step S1012, the resistance value of the resistance module in the first reference module is adjusted to the parasitic resistance value to compensate for the parasitic resistance of the conductive second branch in the first data module.

[0065] Exemplarily, before reading the circuit, the first magnetic tunnel junction unit is adjusted to an antiparallel state. When reading the circuit information, only the state of one branch can be read first. A second switch unit of the first data module is controlled to be turned on to turn on a second branch. The turned-on second branch is electrically connected to the first data bit line, and has a first node at the connection point. The first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit. The length between the first node and the second input end on the first data bit line is the position of the turned-on second branch. According to the obtained position information, the length between the first node and the second input end on the first data bit line can be known. The first data bit line has a preset resistance value, which can be set to the overall resistance value of the first data bit line. According to the ratio of the length between the first node and the second input end to the overall length of the first data bit line, the parasitic resistance value corresponding to the above length can be calculated, that is, the turned-on first data bit line at this position is obtained. The parasitic resistance of the second branch is adjusted according to the parasitic resistance, so as to compensate for the parasitic resistance of the second branch that is turned on in the first data module. When making a reference to the turned-on second branch, two parallel reference branches are required, so the two first switch units are controlled to turn on the two first branches. Finally, according to the resistance of the two turned-on first branches, the resistance of the resistance module and the resistance of the compensation resistor can obtain the middle value of the resistance in the parallel state and the anti-parallel state of the first data module. Since the first reference module is to be in a relatively ideal reference state when reading the circuit, the resistance value of the first reference module needs to be set to the middle value of the resistance value of the first data module. The two first branches are connected in parallel to make the anti-parallel resistance in the first reference module at the middle value of the anti-parallel resistance of the first data module. Putting the first reference module in a relatively ideal reference state can enhance the accuracy of the reading circuit reference.

[0066] The embodiment of the present application also provides a read reference circuit device. It should be noted that the read reference circuit device of the embodiment of the present application can be used to execute the method for reading reference circuit provided by the embodiment of the present application. The device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0067] The following is an introduction to the read reference circuit device provided in the embodiment of the present application.

[0068] Figure 5 is a schematic diagram of a read reference circuit device according to an embodiment of the present application. Figure 5As shown, the first reference module in the read reference circuit includes a resistance module and a compensation resistor, and the device includes: a first control module 10, a second control module 20, and a calculation module 30, wherein the first control module 10 is used to control a second switch unit of the first data module in the second circuit module in the read reference circuit to open when the first magnetic tunnel junction unit in the first branch of the first reference module in the first circuit module in the read reference circuit is adjusted to an anti-parallel state, so as to turn on a second branch among multiple second branches in the first data module; the second control module 20 is used to control two first switch units of the first reference module in the first circuit module, so as to turn on two branches among multiple first branches in the first reference module; the calculation module 30 is used to calculate the reference resistance of the first reference module according to the resistance of the turned-on first branch, the resistance of the resistance module and the resistance of the compensation resistor.

[0069] In the case where the first magnetic tunnel junction unit in the first branch of the first reference module in the first circuit module in the read reference circuit is adjusted to an antiparallel state, the first control module 10 first controls a second switch unit in the first data module in the second circuit module in the read reference circuit to be turned on, so that one of the multiple second branches in the first data module is turned on, and the second control module 20 then controls two first switch units in the first reference module in the first circuit module, so that two of the multiple first branches in the first reference module are turned on, and the calculation module 30 finally calculates the reference resistance of the first reference module according to the resistance of the turned-on first branch, the resistance of the resistance module and the resistance of the compensation resistor. Since it is desired to make the first reference module in a relative position when reading the circuit, For a more ideal reference state, it is necessary to set the resistance value of the first reference module to the middle value of the resistance value of the first data module, and turn on a second branch. The two first branches are connected in parallel to make the antiparallel resistance in the first reference module at the middle value of the antiparallel resistance of the first data module, so that the first reference module is in a more ideal reference state. If the temperature changes, its resistance value will change accordingly. The resistance value of the first magnetic tunnel junction unit in the antiparallel state in the first reference module will also change with the temperature, which can offset the influence of the temperature change on the resistance value of the second magnetic tunnel junction unit in the first data module, and can enhance the accuracy of the read circuit reference. The above technical solution improves the read circuit yield and increases the read window of the circuit under temperature changes.

[0070] In some optional embodiments, such as Figure 6As shown, the first data module in the read reference circuit includes a first data bit line, and the first control module in the read reference circuit device also includes: an acquisition module 110 is used to obtain the position information of the second branch that is turned on, and obtain the parasitic resistance value of the position information, wherein the first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit, the turned-on second branch is connected to the first node of the first data bit line, and the position information is used to indicate the length between the first end and the first node on the first data bit line; the first processing module 120 is used to determine the parasitic resistance value corresponding to the position information according to the position information and the preset resistance value of the first data bit line; the second processing module 130 is used to send an adjustment signal to the resistance module according to the parasitic resistance value corresponding to the position information, so that the resistance module adjusts the resistance value to be consistent with the parasitic resistance value.

[0071] In the above optional implementation, if Figure 6 As shown, the acquisition module 110 acquires that the second branch that is turned on is electrically connected to the first data bit line, and has a first node at the connection point. The first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit. The length between the first node and the second input end on the first data bit line is the position of the second branch that is turned on. According to the above position information, the length between the first node and the second input end on the first data bit line can be known. The first data bit line has a preset resistance value, and the preset resistance value can be set to the overall resistance value of the first data bit line. According to the ratio of the length between the first node and the second input end to the overall length of the first data bit line, the parasitic resistance value corresponding to the above length can be calculated, that is, the parasitic resistance value of the second branch that is turned on at this position is obtained. According to the above parasitic resistance value, the resistance value of the resistance module in the first reference module is adjusted to the parasitic resistance value to compensate for the parasitic resistance of the second branch that is turned on in the first data module, which can enhance the accuracy of the read circuit reference.

[0072] The read reference circuit device comprises a processor and a memory. The first control module, the second control module, the calculation module, the acquisition module, the first processing module and the second processing module are all stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions. The modules are all located in the same processor; or, the modules are located in different processors in any combination.

[0073] The processor includes a core, which retrieves the corresponding program unit from the memory. One or more cores can be set to improve the read yield of the resistance of the MRAM device data circuit under temperature changes by adjusting the core parameters, and increase the read window at high temperature.

[0074] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0075] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the compensation method for the read reference circuit.

[0076] Specifically, the compensation methods include:

[0077] Step S101: when a first magnetic tunnel junction unit in a first branch of a first reference module in a first circuit module in a read reference circuit is adjusted to an antiparallel state, a second switch unit in a first data module in a second circuit module in the read reference circuit is controlled to be turned on, so that one second branch among a plurality of second branches in the first data module is turned on;

[0078] Specifically, the first magnetic tunnel junction unit is adjusted to an antiparallel state before reading the circuit. When reading circuit information, only the state of one branch can be read first, and a second switch unit of the first data module is controlled to be turned on to conduct a second branch.

[0079] Step S102: controlling two first switch units of a first reference module in a first circuit module to conduct two of the plurality of first branches in the first reference module;

[0080] Specifically, when making a reference to a second branch that is turned on, two parallel reference branches are required to control the two first switch units to turn on the two first branches. Since the first reference module is to be in a relatively ideal reference state when reading the circuit, the resistance value of the first reference module needs to be set to the middle value of the resistance value of the first data module. The two first branches are connected in parallel to make the anti-parallel resistance in the first reference module be at the middle value of the anti-parallel resistance of the first data module. Putting the first reference module in a relatively ideal reference state can enhance the accuracy of the reading circuit reference.

[0081] Step S103: Calculate the reference resistance of the first reference module according to the resistance of the first branch that is turned on, the resistance of the resistance module and the resistance of the compensation resistor.

[0082] Specifically, according to the resistance of the two first branches that are turned on, the resistance of the resistance module and the resistance of the compensation resistor can obtain the intermediate value of the resistance in the parallel state and the anti-parallel state of the first data module, so that the first reference module is in a more ideal reference state to enhance the accuracy of the read circuit reference.

[0083] An embodiment of the present invention provides an electronic device, the device includes a processor, a memory, and a program stored in the memory and executable on the processor, and the processor implements at least the following steps when executing the program: when the first reference module in the read reference circuit includes a resistance module and a compensation resistor, when the first magnetic tunnel junction unit in the first branch of the first reference module in the first circuit module in the read reference circuit is adjusted to an antiparallel state, a second switch unit of the first data module in the second circuit module in the read reference circuit is controlled to be turned on, so that one of the multiple second branches in the first data module is turned on; two first switch units of the first reference module in the first circuit module are controlled to turn on two of the multiple first branches in the first reference module; and the reference resistance of the first reference module is calculated based on the resistance of the turned-on first branch, the resistance of the resistance module, and the resistance of the compensation resistor. The electronic device in this article can be a server, a PC, a PAD, a mobile phone, etc.

[0084] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program that is initialized with at least the following method steps: when a first reference module in a read reference circuit includes a resistance module and a compensation resistor, when a first magnetic tunnel junction unit in a first branch of the first reference module in a first circuit module in the read reference circuit is adjusted to an antiparallel state, a second switch unit of a first data module in a second circuit module in the read reference circuit is controlled to be turned on so that one of the multiple second branches in the first data module is turned on; two first switch units of a first reference module in the first circuit module are controlled to turn on two of the multiple first branches in the first reference module; and a reference resistance value of the first reference module is calculated based on the resistance value of the turned-on first branch, the resistance value of the resistance module and the resistance value of the compensation resistor.

[0085] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0086] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0087] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0088] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0089] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0090] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0091] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0092] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0093] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0094] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0095] 1) By adopting the read reference circuit of the embodiment of the present application, when the second magnetic tunnel junction unit in the first data module is in a parallel state, if the temperature changes, its resistance value will change accordingly, and the resistance value of the first magnetic tunnel junction unit in the antiparallel state in the first reference module will also change with the temperature change, which can offset the influence of the temperature change on the resistance value of the second magnetic tunnel junction unit in the first data module. The above technical solution improves the yield of the read circuit and increases the read window of the circuit under temperature changes;

[0096] 2) In the present application, the number of first branches connected in parallel with the first reference module is consistent with the number of second branches connected in parallel with the first data module. The first branch can also compensate for the leakage current generated by the second branch, thereby enhancing the accuracy of the reading circuit.

[0097] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A read reference circuit, characterized in that: include: A sensitive amplifier module having a first input terminal and a second input terminal; A first circuit module, comprising a first reference module, wherein the first reference module comprises a plurality of first branches connected in parallel, each of the first branches comprises a first magnetic tunnel junction unit, a first switch device and a first reference word line, wherein the first reference word line is electrically connected to the first switch device in a one-to-one correspondence, the first reference module is electrically connected to the first input end of the sensitive amplifier module, and the first magnetic tunnel junction unit is in an anti-parallel state; A second circuit module includes a first data module, wherein the first data module includes a plurality of second branches connected in parallel, each of the second branches includes a second magnetic tunnel junction unit, a second switch device and a first data word line, wherein the first data word line is electrically connected to the second switch device in a one-to-one correspondence, and the first data module is electrically connected to the second input end of the sensitive amplifier module; The number of first branches connected in parallel to the first reference modules is consistent with the number of second branches connected in parallel to the first data modules.

2. The read reference circuit according to claim 1, characterized in that: The first reference module also includes a resistance module and a compensation resistor, and the compensation resistor is arranged in series with the multiple parallel first branches, wherein the resistance module is an adjustable resistor, the compensation resistor is a fixed resistor, and the resistance value of the compensation resistor is 1 / 2 of the resistance value when the second magnetic tunnel junction unit is in a parallel state.

3. The read reference circuit according to claim 2, characterized in that: The first reference module also includes: A first reference bit line is electrically connected to one end of the plurality of parallel first branches located on the same side; The first reference source line is electrically connected to one end of the plurality of parallel first branches located on the other side.

4. The read reference circuit according to any one of claims 1 to 3, characterized in that: The first data module also includes: a first data bit line electrically connected to a same side of the plurality of parallel second branches; The first data source electrode line is electrically connected to the same side of the plurality of parallel second branches.

5. The read reference circuit according to claim 1, characterized in that: A clamping tube is connected between the first circuit module and the first input end, and between the second circuit module and the second input end.

6. The read reference circuit according to claim 3, characterized in that: The first reference module further comprises a first transmission gate, which is arranged in series with the plurality of parallel first branches, the compensation resistor and the resistor module on the first reference bit line; The first data module further includes a second transmission gate which is connected in series with the plurality of parallel second branches and is arranged on the first data bit line.

7. The read reference circuit according to any one of claim 6, characterized in that: The first circuit module also includes a second reference module, the second reference module has a second reference source line, a second reference bit line, a third transmission gate and a plurality of third branches connected in parallel, the third transmission gate and the plurality of third branches connected in parallel are arranged in series on the second reference bit line, each of the third branches includes a third magnetic tunnel junction unit, a third switch device and a second reference word line, the second reference word line is electrically connected to the third switch device in a one-to-one correspondence, the first reference module has one end of the first transmission gate and the second reference module has one end of the third transmission gate and the resistance module, the compensation resistor is electrically connected to the first input terminal, and the other end of the second reference module is electrically connected to the second reference source line; The second circuit module also includes a second data module, the second data module has a second data source polar line, a second data bit line, a fourth transmission gate and a plurality of fourth branches in parallel, the fourth transmission gate and the plurality of fourth branches in parallel are arranged in series on the second data bit line, each of the fourth branches includes a fourth magnetic tunnel junction unit, a fourth switching device and a second data word line, the second data word line is electrically connected to the fourth switching device in a one-to-one correspondence, the first data module has one end of the second transmission gate and the second data module has one end of the fourth transmission gate electrically connected to the second input end, and the other end of the second data module is electrically connected to the second data source polar line.

8. A compensation method for a read reference circuit according to any one of claims 1 to 7, characterized in that: The first reference module in the read reference circuit includes a resistance module and a compensation resistor, and the compensation method includes: When the first magnetic tunnel junction unit in the first branch of the first reference module in the first circuit module in the read reference circuit is adjusted to an antiparallel state, controlling a second switch unit in the first data module in the second circuit module in the read reference circuit to be turned on, so as to turn on one of the multiple second branches in the first data module; Controlling two first switch units of a first reference module in a first circuit module to conduct two of the plurality of first branches in the first reference module; The reference resistance of the first reference module is calculated according to the resistance of the first branch that is turned on, the resistance of the resistance module and the resistance of the compensation resistor.

9. The compensation method according to claim 8, characterized in that: The first data module in the read reference circuit includes a first data bit line. After the step of conducting a second branch among the plurality of second branches, the compensation method further includes: Acquire the position information of the second branch that is turned on, and obtain the parasitic resistance value of the position information, wherein the first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit, the second branch that is turned on is connected to the first node of the first data bit line, and the position information is used to indicate the length between the first end and the first node on the first data bit line; Determining a parasitic resistance value corresponding to the position information according to the position information and a preset resistance value of the first data bit line; According to the parasitic resistance value corresponding to the position information, an adjustment signal is sent to the resistance module, so that the resistance module adjusts the resistance value to be consistent with the parasitic resistance value.

10. A read reference circuit device, characterized in that: The first reference module in the read reference circuit includes a resistance module and a compensation resistor, and the circuit device includes: A first control module is used to control a second switch unit of a first data module in a second circuit module in the read reference circuit to be turned on, so as to turn on one of the multiple second branches in the first data module, when a first magnetic tunnel junction unit in a first branch of a first reference module in a first circuit module in the read reference circuit is adjusted to an antiparallel state; A second control module, used for controlling two first switch units of a first reference module in the first circuit module, so as to make two branches of the plurality of first branches in the first reference module conductive; The calculation module is used to calculate the reference resistance of the first reference module according to the resistance of the first branch that is turned on, the resistance of the resistance module and the resistance of the compensation resistor.

11. The read reference circuit device according to claim 10, characterized in that: The first data module in the read reference circuit includes a first data bit line, and the first control module further includes: an acquisition module, configured to acquire position information of the second branch that is turned on, and obtain a parasitic resistance value of the position information, wherein the first end of the first data bit line is electrically connected to the second input end of the sensitive amplifier module in the read reference circuit, the second branch that is turned on is connected to the first node of the first data bit line, and the position information is used to indicate the length between the first end and the first node on the first data bit line; A first processing module, configured to determine a parasitic resistance value corresponding to the position information according to the position information and a preset resistance value of the first data bit line; The second processing module is used to send an adjustment signal to the resistance module according to the parasitic resistance value corresponding to the position information, so that the resistance module adjusts the resistance value to be consistent with the parasitic resistance value.

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