Memory device and reading method thereof

Abstract

The invention provides a memory device and a reading method thereof. The memory device comprises a four-transistor (4T-SRAM) unit and a sensing circuit. The 4T-SRAM cell comprises two P-type MOSFET devices used for data bit storage and two N-type MOSFET devices used for access switches, and the 4T-SRAM cell has the advantages that the number of the MOSFET devices is small, and smaller cell size and low leakage current can be achieved. The sensing circuit comprises a switching device, a sensing latch and a discharging device. The switching device coupled between the sense latch and a ground voltage rail is designed to reduce read disturbances of the sense circuit to the 4T SRM cell by cutting off a channel leakage current path from an NMOSFET transistor in the sense latch to the ground voltage rail. A differential voltage signal for reading digital data stored in a 4T SRAM cell is enhanced by increasing sensing time. The read margin of the 4T SRAM is then greatly improved, thereby achieving an excellent and reliable read.

Description

Technical Field

[0001] The present invention relates to a sensing circuit and a timing scheme for reading a bit of information stored in a four-transistor static random access memory (4T SRAM) cell. In particular, the sensing circuit and the sensing method of the present invention can reduce the sensing circuit read disturbance of a small differential bit line voltage signal (generated by a storage node in a 4T SRAM cell in a memory array). The sensing circuit and the timing scheme of the present invention can also significantly improve the read margin of the 4T SRAM, resulting in excellent read reliability. Background Art

[0002] Semiconductor memory has been widely used in electronic systems. Electronic systems need semiconductor memory to store instructions and data, which are derived from the basic functions of controlling complex computing processes. Semiconductor memory can be divided into volatile memory and non-volatile memory. Volatile memory includes static random access memory (SRAM) and dynamic random access memory (DRAM), and its stored data will disappear after the memory power is turned off, while non-volatile memory, such as read-only memory (ROM), electronically erasable programmable read-only memory (EEPROM) and flash memory (Flash), its stored data will still be saved after the memory power is turned off.

[0003] Because computer processors operate at very high frequency clock speeds (tens of MH to tens of GHz), the access time to read and change data in memory must match the computing speed of the computer processor. Due to the fast random access time during read / write operations, volatile SRAM and DRAM have become the memory options for computer processors. A DRAM cell includes a MOSFET device and a capacitor, where the MOSFET device acts as an access switch and the capacitor acts as a one-bit data storage, and the DRAM cell can be manufactured to extremely high density at extremely low manufacturing costs using DRAM process technology. However, DRAM needs to be refreshed all the time, resulting in high power consumption, while SRAM consumes much less power than DRAM because it does not require data refresh. Furthermore, SRAM is manufactured using complementary metal oxide semiconductor (CMOS) process technology, which is the same process technology used to manufacture digital processor integrated circuits (ICs). Therefore, SRAM is usually embedded in ICs with digital processors as memory needs. However, because a conventional SRAM cell used as a bit of storage contains six MOSFET devices, it occupies a relatively large area compared to a DRAM cell (a MOSFET device and a capacitor), so the storage cost per bit of SRAM is much higher than that of DRAM. Therefore, the industry urgently needs to reduce the cell size of SRAM by using fewer MOSFET devices, thereby improving memory density and reducing the per-bit storage cost in digital processor IC chips. Please refer to Figure 1 , the conventional SRAM cell 100 includes six MOSFET devices: two N-type MOSFET devices 13 and 14, which are used as data access switches, and a pair of cross-coupled inverter latches: a P-type MOSFET device 11 and an N-type MOSFET device 15, and a PMOSFET device 12 and an NMOSFET device 16, which are used as one-bit data storage, wherein the pair of cross-coupled inverter latches form two storage nodes n1 and n2 respectively. Please refer to Figure 2 , the 4T SRAM cell 200 includes four MOSFET devices: two N-type MOSFET devices 23 and 24, which are used as data access switches, and two mutually coupled P-type MOSFET devices 22 and 21, which are used as one-bit data storage, wherein the drain electrodes of the mutually coupled P-type MOSFET devices 21 and 22 form two storage nodes n3 and n4 respectively. In order to reduce the storage cost per bit of SRAM, the size of the 4T SRAM cell 200 is generally smaller than that of the 4T SRAM cell 200. Figure 1 The 6T SRAM cell 100 (made using the same CMOS process node) is about 25% to 35% smaller. Although the 4T SRAM cell 200 uses fewer MOSFET devices to save per-bit storage cost, how to reliably read the stored data from the 4T SRAM cell is still an important issue for whether 4T SRAM can be widely used in IC chips.

[0004] By setting asymmetric voltage potentials on the two storage nodes n3 and n4 of the 4T SRAM cell 200, one bit of data is stored. For example, V DD (digital supply / high voltage) and V SS (ground voltage) to store data 1, and set the two storage nodes n3 and n4 to V SS With V DD To store data 0. Afterwards, the stored data in the 4TSRAM cell 200 is read back by sensing the asymmetric voltage potentials on the two storage nodes n3 and n4. Figure 1 In the 6T SRAM cell 100, the pair of mutually coupled reverse latches (reverse devices 11 and 15 and reverse devices 12 and 16) have one storage node connected to V after data is stored in the 6T SRAM cell 100. DD , while the other storage node is always connected to V SS Therefore, data can be directly read from the conventional 6T SRAM cell 100 using conventional SRAM sensing circuits and methods or updated read-assist sensing circuits. Figure 2 When the 4T SRAM cell 200 is firstly configured, the storage nodes n3 and n4 are set to V by using the write circuit disclosed in the application document of Taiwan Patent No. 113103434. DD With V SS Represents storing data 1 and setting storage nodes n3 and n4 to V SS With V DD represents storage data 0. However, during the data retention period after data is written into the 4T SRAM cell 200 (access transistors 23 and 24 are turned off), unlike the 6T SRAM cell 100, Figure 2 One of the storage nodes of the 4T SRAM cell 200 is always floating and is not connected to the ground voltage V SSAs disclosed in Taiwan Patent Application No. 113117394, depending on the leakage current balance between the PMOSFET channel diffusion current and the access NMOSFET diode leakage current in the 4T SRAM cell 200, the potential of the floating node will rise from the ground voltage to a stable voltage potential, and the voltage potential is lower than the digital supply / high voltage V DD .

[0005] In order to minimize the read error of the floating storage node in the 4T SRAM cell 200, the patent application No. 113103434 in Taiwan, China is disclosed. Figure 3 The sensing circuit 350 detects the rising floating voltage potential on a storage node n3 / n4 of the 4T SRAM cell 200 and the V DD Reading data: (1) Before accessing a 4TSRAM cell 200, the connected bit line BL 321 and the complementary bit line BL 322 are connected by two NMOSFET devices 311. 322 to discharge the residual charge to avoid unnecessary read disturbance; (2) sensing the connected bit line BL 321 and the complementary bit line 322 (transmitted from the two storage nodes n3 and n4); and (3) during the cell data reading period / process, simultaneously refreshing the original data voltage potential V on the two storage nodes DD With V SS When the word line 334 (gates of the cell access MOSFETs 24 and 23) of the selected 4T SRAM cell 200 is activated for the cell data read process, initially, the differential voltage between the bit line 321 and the complementary bit line 322 (connected to the read sensing circuit 350) transmitted from the cell storage nodes n3 and n4 will be further reduced to a smaller differential voltage signal, such as , due to the initial inter-capacitance charge sharing effect between the small gate capacitance of the cell PMOSFET device and the large capacitance of the bit line. Figure 4 For example, in one embodiment, regarding the bit line capacitance of 256 memory cells connected in a 4T SRAM memory array, when the word line voltage potential (such as Figure 4 When the first row in FIG. 1 is turned on, initially, the voltage potential of the high voltage storage node n3 representing the storage data “1” (eg Figure 4The second row of the bit line (connected to the gate of the PMOSFET device 22) will drop from 1.2V to 175.6 millivolts (mV). At the same time, during the bit line voltage drop, the voltage on the storage node n4 (connected to the gate of the PMOSFET device 22) will also drop to compensate for the complementary capacitor sharing effect, and the voltage potential of the storage node n4 changes from the initial 17.4mV to 131.6mV. When the gate voltage of the two PMOSFET devices 21 and 22, which are initially in the "on" state, is lower than (V DD When the cell PMOSFET threshold voltage (about 0.42V) is reached, the capacitor 341 of the bit line 321 and the capacitor 342 of the complementary bit line 322 will be charged to increase the storage node voltage potential and the bit line and complementary bit line voltage potentials, respectively. Figure 4 As shown in the second and third rows of FIG. Meanwhile, regarding the case of reading a 4T SRAM cell having stored data "1", since the gate voltage potential (initial value is 175.6 mV) of the PMOSFET 21 connected to the storage node n3 is higher than the gate voltage potential (initial value is 131.6 mV) of the PMOSFET 22 connected to the storage node n4, the PMOSFET device 22 will charge the bit line 321 to the first voltage potential at a faster speed, while the PMOSFET device 21 will charge the complementary bit line 322 to the second voltage potential at a slower speed, and the first voltage potential should be higher than the second voltage potential. However, as Figure 4 As shown in FIG. 1 , due to the erroneous reading of the 4TSRAM cell storing data “1”, the differential voltage potential ΔV between the bit line and the complementary bit line may evolve to a cross over voltage in some way, i.e., the voltage potentials of the bit line and the complementary bit line are equal (i.e., ΔV=0V), or even develop to a state with a sign opposite to that of the original differential voltage, causing the sensing circuit 350 to read an erroneous bit and change the cell bit, as shown in FIG. Figure 4 As shown in the second and third rows of FIG. 1 , the above-mentioned erroneous reading events may be increased due to the inaccurate sensing timing generated by the margin design and timing circuit of the sensing circuit 350 caused by the variation of the MOSFET devices in the process and different operating temperature environments. It has been found that the channel leakage current of the NMOSFET devices 313 and 314 in the sensing circuit 350 is the cause of the erroneous reading events. Summary of the invention

[0006] In order to solve the problems existing in the prior art, the present invention provides a memory device and a reading method thereof.

[0007] In one aspect, the present invention provides a memory device, comprising:

[0008] A static random access memory cell comprising:

[0009] a pair of mutually coupled PMOSFET transistors coupled to a digital voltage rail and two storage nodes; and

[0010] two access transistors, responsive to a word line and coupled to the storage node and a pair of bit lines; and

[0011] A sensing circuit comprising:

[0012] a sensing latch coupled between a first connection node and a second connection node and having two output nodes respectively coupled to the pair of bit lines;

[0013] a discharge device, responsive to a first control signal and coupled to the output node, the bit line pair and a ground voltage rail; and

[0014] A switch device is used to selectively connect the second connection node to the ground voltage rail in response to a second control signal.

[0015] On the other hand, the present invention provides a read method for reading a data bit from a static random access memory cell of a memory device, wherein the memory device comprises a sensing circuit, and the SRAM cell comprises a pair of mutually coupled PMOSFET transistors and two access transistors, wherein the pair of mutually coupled PMOSFET transistors are coupled to a digital voltage rail and two storage nodes, wherein the two access transistors are used to respond to form a word line and are coupled to the two storage nodes and the pair of bit lines, wherein the sensing circuit comprises a switch device, a sensing latch and a discharge device, wherein the sensing latch is coupled between a first connection node and a second connection node and has two output nodes respectively coupled to the pair of bit lines, wherein the discharge device is coupled to the two output nodes, the pair of bit lines and the ground voltage rail, and the switch device is coupled between the second connection node and the ground voltage rail, and the method comprises the following steps:

[0016] (1) discharging the pair of bit lines to a ground voltage by activating the discharge device;

[0017] (2) closing the switch device;

[0018] (3) after steps (1) and (2), activating the word line, causing the voltages at the two storage nodes to drop to near the ground voltage, and then causing the pair of bit lines to be charged; and

[0019] (4) After step (3), during a sensing period, the switch device and the sensing latch are activated to pull the differential voltage between the pair of bit lines to a supply voltage carried by the digital voltage rail.

[0020] The 4T-SRAM cell of the memory device includes two P-type MOSFET devices for data bit storage and two N-type MOSFET devices for access switch. The advantage of the 4T-SRAM cell is that it has a smaller number of MOSFET devices, which can achieve a smaller cell size and low leakage current. The sensing circuit of the memory device includes a switch device, a sensing latch and a discharge device. The switch device coupled between the sensing latch and the ground voltage rail is designed to reduce the read interference of the sensing circuit to the 4TSRM cell by cutting off the channel leakage current path from the NMOSFET transistor in the sensing latch to the ground voltage rail. By increasing the sensing time, the differential voltage signal used to read the digital data stored in the 4T SRAM cell is enhanced. Then, the read margin of the 4T SRAM is greatly improved, thereby achieving excellent and reliable reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to better understand the present invention and to illustrate how to implement the present invention, reference will now be made to the following drawings which show preferred embodiments of the present invention, in which:

[0022] Figure 1 A schematic diagram of a conventional 6T-SRAM cell is shown.

[0023] Figure 2 A schematic diagram of a conventional 4T-SRAM cell is shown.

[0024] Figure 3 FIG. 1 is a schematic diagram of a sensing circuit 350 of a 4T SRAM cell disclosed in Taiwan Patent Application No. 113103434.

[0025] Figure 4 Shows the use Figure 3 When the sensing circuit 350 in FIG. 4 reads the 4T SRAM cell, an erroneous reading occurs.

[0026] Figure 5 A schematic diagram of a sensing circuit 550 of a 4T SRAM cell is shown in accordance with the present invention.

[0027] Figure 6 According to the present invention, display Figure 5 Voltage potential waveform diagram of the reading timing of the sensing circuit in FIG.

[0028] Figure 7A circuit simulation waveform diagram for reading a 4T SRAM cell with extracted parasitic resistance and capacitance parameters of a bit line and a complementary bit line is shown for a memory array layout topology using a 40 nm CMOS process technology provided by a wafer foundry according to an embodiment of the present invention.

[0029] [Refer to Figure Number]

[0030] 100:6T SRAM cell

[0031] 200:4T SRAM cell

[0032] 13, 14, 15, 16, 23, 24, 311, 313, 314, 516: NMOSFET devices

[0033] 11, 12, 21, 22, 312: PMOSFET device

[0034] 350, 550: Sensing circuit

[0035] BL 321: Bit Line:

[0036] 322: Complementary bit line

[0037] n1, n2, n3, n4: storage nodes

[0038] C BL 341, C BL 342: Load capacitance:

[0039] 315: Tri-state buffer

[0040] BLrst: voltage pulse signal

[0041] 35, 36, 37, 55, 56, 57, 331-333, 534: nodes

[0042] WL 334: Character Line

[0043] Sn: voltage signal

[0044] Dt: Time

[0045] 605: Steady-state floating storage node voltage potential V of 4T-SRAM cell floating curve

[0046] 5a, 5b: Inverter DETAILED DESCRIPTION

[0047] In view of the problems existing in the prior art, in the present invention, we redesign a new sensing circuit 550 to cut off the channel leakage current path of NMOSFET 313 and 314 to prevent the sensing circuit from causing read disturbance to the 4T SRAM cell. Through the new sensing circuit and timing sensing method, the read margin of the 4T SRAM can be enhanced to cope with the variation of MOSFET devices caused by different process and operating temperatures of integrated circuit chips.

[0048] Unlike the conventional 6T-SRAM cell which always biases one of the storage nodes to the ground voltage, the 4T-SRAM cell 200 does not have a low voltage node VSS connected to the ground voltage, so during the cell data reading process / period, a floating storage node n4 / n3 of the 4T-SRAM cell 200 needs to be restored to the ground voltage to retain the original stored data. The design of the sensing circuit 550 of the present invention can restore the floating storage node of the selected 4T-SRAM cell to the ground voltage during the cell data reading process / period.

[0049] For the 4T-SRAM cell 200, during the cell data retention period, the voltage potential of the floating storage node is lower than the high voltage potential V of another storage node. DD Therefore, the sensing circuit 550 is designed to detect the asymmetric voltage difference (V DD -V floating ) in order to obtain a complete digital voltage signal during the cell data reading process / period, that is, a high voltage V DD and ground voltage V SS , as the output signal, where V floating represents the voltage potential of the floating storage node of the 4T-SRAM cell 200 during data retention. Figure 6 As shown. The floating storage node voltage potential V floating is lower than the supply voltage V DD The floating connection is due to the diffusion current (V DD To a stable V floating ) and reverse P-drain / N-well junction leakage current (V DD To a stable V floating ) and access NMOSFET devices 23 / 24 (stable V floating The detailed balanced leakage current between the reverse N-drain / P-substrate junction leakage current to the substrate can be obtained as the voltage potential V of the steady-state floating storage node of the 4T SRAM cell 200. floating (like Figure 6Generally speaking, the greater the reverse N-drain / P-substrate junction leakage current of the access NMOSFET device 23 / 24, the lower the stable floating storage node voltage potential toward the ground voltage.

[0050] Figure 5 According to the present invention, a schematic diagram of a sensing circuit 550 for reading a 4T SRAM cell 200 is shown. The sensing circuit 550 of the present invention includes two bit line reset NMOSFET devices 311, a transmission enable PMOSFET device 312, two sensing interconnect inverters 5a and 5b, a tri-state buffer 315, and an NMOSFET device 516. The two bit line reset NMOSFET devices 311 are used to reset the bit line BL 321 (with a load capacitor C BL 341) and complementary bit lines 322 (with load capacitance C BL The residual charge on the NMOSFET device 516 is discharged, and the NMOSFET device 516 is used to cut off the leakage current path of the sensing circuit to the ground potential. The gate electrode of the NMOSFET device 516 is connected to the sensing voltage signal "S n ”, and NMOSFET device 516 is coupled between the source electrodes (node ​​57) of NMOSFET devices 313 and 314 and the ground voltage potential, as shown Figure 5 NMOSFET device 516 is used to cut off the channel leakage current path of NMOSFET 313 and 314 to prevent the sensing circuit from reading disturbing the 4T SRAM cell.

[0051] The read timing of the 4T SRAM cell 200 is as follows: at the beginning, a voltage pulse signal BLrstV is applied to the node 331. DD and last for a period of time τ to connect the bit line BL 321 and the complementary bit line 322 reset to ground potential, such as Figure 6 As shown in the first row. After the bit line 321 and the complementary bit line 322 are discharged for the time τ, a voltage signal V is applied to the node 534 in the 4T SRAM memory array. DD To turn on the selected word line ( Figure 6 (3rd row). When the selected word line is turned on, due to the charge sharing of the bit line capacitance and the complementary bit line capacitance with the cell PMOSFET gate capacitance at the storage nodes n3 and n4, the voltage potentials at the storage nodes n3 and n4 of the selected 4T SRAM cell 200 initially drop to a voltage potential close to the ground voltage. For the stored cell data "1", it can be roughly expressed as follows mathematically: and like Figure 6 As shown in the fourth row, for the stored cell data "0", vice versa, where V b and V cb They represent the stable bit line voltage potential and complementary bit line voltage potential after achieving balanced capacitor charge sharing; C pg represents the gate capacitance of the PMOSFET (21 / 22) of the selected 4T SRAM, and C bL Represents the bit line / complementary bit line capacitance. Since the voltage potential at the storage node (n3 and n4) after the capacitor charge sharing is lower than the voltage (V DD - the threshold voltage of the cell PMOSFET 21 / 22), so both the cell PMOSFET devices 21 and 22 are initially turned on to charge the bit line and the complementary bit line to a higher voltage potential. In the case of the sensing circuit 550 without the interference of the leakage current from the NMOSFET devices 314 and 313 (these leakage currents are cut off by the NMOSFET device 516), for the 4T SRAM cell storing data "1", the cell PMOSFET 22 with a slightly lower voltage potential at the gate or storage node n4 is turned on more than the cell PMOSFET 21 with a slightly higher voltage potential at the gate or storage node n3 (i.e., V n3 >V n4 ), so that the charging speed of the bit line 321 is faster than that of the complementary bit line 321, and vice versa for the 4T SRAM cell with stored data "0". Therefore, for the 4T SRAM cell with stored data "1" and stored data "0", the differential voltage potential between the bit line and the complementary bit line at the sensing nodes 56 and 55 increases over time, respectively. Figure 6 After time "Dt", when the differential voltage potential between the bit line and the complementary bit line increases to a significant differential voltage margin ΔV, a voltage potential V DD The voltage signal Sn is used to turn on the sensing circuit 550 to initiate a sensing process to increase the differential voltage between the bit line and the complementary bit line from ΔV to the maximum differential voltage V DD ,like Figure 6 The fifth and sixth rows of FIG. 1 respectively show voltage curves of a bit line and a complementary bit line of a 4T SRAM cell storing data “1” and data “0”.

[0052] The voltage potential V is applied to the node 332. DD The “Sn” signal of the cell also turns on the tri-state buffer 315 to convert the data voltage signal V stored in the cell into DD(Data “1”) from the sense voltage signal V at the complementary sense node 55 SS Output to the data output bus line. At the same time, the voltage V DD The Sn signal also turns on the PMOSFET device 312 to accelerate the sensing process, thereby charging the bit line BL 321 to V DD The maximum voltage potential V DD It should be noted that during the sensing process, the cell node n4 is refreshed to the ground potential from the previous floating storage node during the data retention period using the ground voltage, so that the cell node n4 can be refreshed to the ground potential from the previous floating storage node during the data retention period using the ground voltage at the gate and the digital supply voltage V at the base (body). DD The total charge on the gate of the PMOSFET device 22 is fully restored to fully charge the gate and body (N-well) capacitances. Therefore, the data originally stored in the selected 4T SRAM cell is completely and correctly refreshed.

[0053] The following detailed description is for illustrative purposes only and is not intended to be limiting. It should be understood that other embodiments and various MOSFET devices, such as FinFET devices and Gate All Around (GAA) devices, may be used, all of which should fall within the scope of the claims of the present invention. Furthermore, it should be understood that the grammar and terminology used in this specification are for illustrative purposes only and should not be considered limiting. Those skilled in the art should understand that the embodiments of the methods and schematic diagrams in this specification are for illustrative purposes only and are not intended to be limiting. Those skilled in the art who understand the spirit of the present invention as a result of the disclosure of this specification may use other embodiments, all of which should fall within the scope of the claims of the present invention.

[0054] In one embodiment, the sensing circuit 550 of the 4T SRAM memory array is implemented in a 1Mb 4T SRAM wafer manufactured using a 40nm CMOS logic process technology of a wafer foundry. In addition, parasitic resistance and capacitance parameters are extracted from the topological layout of the above 4T SRAM memory array. At the same time, the MOSFET SPICE model in the process design kit (PDK) of the wafer foundry is used to simulate the 4T SRAM write / read operation. The complete wafer simulation has been performed for different process deviation corner values ​​and different temperature environments. Figure 7 A typical analog read waveform is shown to illustrate the working principle of the sensing circuit 550 and the sensing method of the 4TSRAM memory array of the present invention. Figure 7 The second row shows that when the voltage potential V DDWhen the word line is turned on, the voltage potential of the storage nodes n3 and n4 of the selected 4T SRAM cell initially drops to a low voltage potential due to the capacitive charge sharing between the cell PMOSFET gate capacitance and the bit line capacitance to turn on the two cell PMOSFET devices 21 and 22. Then, the two turned-on cell PMOSFET devices 22 and 21 charge the bit line and the complementary bit line to a higher voltage potential. In the case of reading the data "1" stored in the 4T SRAM cell, after the word line is turned on, the differential voltage potential between the storage nodes n3 and n4 increases from 30 millivolts (mV) at 0.58 nanoseconds (ns), 41 mV at 0.89 nanoseconds, to 72 mV at 1.29 nanoseconds. At the same time, after the word line is turned on, the differential voltage potential between the bit line at the sensing node 56 and the complementary bit line at the sensing node 55 will also increase accordingly, from 9.92 mV at 0.58 ns, 14.3 mV at 0.89 ns to 18.3 mV at 1.29 ns. Figure 7 It can be seen that as the sensing time Dt increases, the sensing circuit 550 with the sequential sensing method is used to pull the larger differential voltage between the sensing nodes 55 and 56 to the maximum differential voltage V DD In post-simulation of the complete wafer, the wafer was tested across all process deviation margins and different temperature environments.

[0055] The preferred embodiments provided above are only used to illustrate the present invention, and are not intended to limit the present invention to a specific type or exemplary embodiment. Therefore, this specification should be regarded as illustrative rather than restrictive. The preferred embodiments provided above are intended to effectively illustrate the gist of the present invention and its best mode for implementation, so that those skilled in the art can understand the various embodiments and various changes of the present invention to adapt to specific uses or implementation purposes. The scope of the present invention is defined by the appended claims and their equivalents, in which all terms are intended to have the broadest reasonable meaning unless otherwise specifically indicated. Therefore, "the present invention" and similar terms do not limit the scope of the claims to a specific embodiment, and any reference to a specific preferred embodiment of the present invention does not mean to limit the present invention, and no such limitation will be inferred. The present invention is defined only by the scope and spirit of the appended claims. The abstract of the present invention is provided in accordance with the requirements of the law so that searchers can quickly confirm the subject matter of this technical disclosure from any patent approved by this specification, and is not used to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that various modifications or changes can be made by the industry, all of which should fall within the scope of the invention defined by the claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether the elements and components are listed in the claims.

Claims

1. A memory device, characterized in that: Include: A static random access memory cell comprising: a pair of mutually coupled PMOSFET transistors coupled to a digital voltage rail and two storage nodes; and two access transistors, responsive to a word line and coupled to the storage node and a pair of bit lines; as well as A sensing circuit comprising: a sensing latch coupled between a first connection node and a second connection node and having two output nodes respectively coupled to the pair of bit lines; a discharge device, responsive to a first control signal and coupled to the output node, the bit line pair and a ground voltage rail; as well as A switch device is used to selectively connect the second connection node to the ground voltage rail in response to a second control signal.

2. The memory device according to claim 1, wherein: The first control signal is activated before the word line is activated, and wherein the word line is activated before the second control signal is activated.

3. The memory device according to claim 2, wherein: The discharge device comprises: a first reset transistor and a second reset transistor for responding to the first control signal, wherein the first reset transistor is coupled to one of the output nodes, one of the pair of bit lines, and the ground voltage rail, and wherein the second reset transistor is coupled to the other of the output nodes, the other of the pair of bit lines, and the ground voltage rail.

4. The memory device according to claim 2, wherein: When the word line is activated, the voltage at the storage node drops below (V DD -V thp ), causing the pair of mutually coupled PMOSFET transistors to be turned on to charge the pair of bit lines, so that the differential voltage between the pair of bit lines increases over time, where V thp represents the threshold voltage of the pair of mutually coupled PMOSFET transistors, and the digital voltage rail carries a supply voltage V DD .

5. The memory device according to claim 2, wherein: Before the second control signal is activated, the switch device is turned off to cut off a channel leakage current path of a plurality of NMOSFET transistors in the sense latch to the ground voltage rail.

6. The memory device according to claim 2, wherein: The sensing circuit further comprises: A speed-up transistor, responsive to the second control signal, is configured to selectively couple the digital voltage rail to the first connection node.

7. The memory device according to claim 6, wherein: When the second control signal is activated, the switch device, the acceleration transistor and the sensing latch are turned on, so that the differential voltage between the pair of bit lines is pulled up to a supply voltage carried by the digital voltage rail.

8. The memory device according to claim 1, wherein: The sensing circuit further comprises: A tri-state buffer has a data input node coupled to one of the output nodes, and is used to respond to the second control signal and selectively output a data bit based on a voltage at one of the output nodes.

9. The memory device according to claim 1, wherein: The switch device is an NMOSFET transistor, and a gate electrode of the NMOSFET transistor receives the second control signal.

10. A method for reading a data bit from a static random access memory cell of a memory device, characterized in that: The memory device includes a sensing circuit, and the static random access memory cell includes a pair of mutually coupled PMOSFET transistors and two access transistors, wherein the pair of mutually coupled PMOSFET transistors are coupled to a digital voltage rail and two storage nodes, wherein the two access transistors are used to respond to form a word line and are coupled to the two storage nodes and a pair of bit lines, wherein the sensing circuit includes a switch device, a sensing latch and a discharge device, wherein the sensing latch is coupled between a first connection node and a second connection node and has two output nodes respectively coupled to the pair of bit lines, wherein the discharge device is coupled to the two output nodes, the pair of bit lines and the ground voltage rail, and the switch device is coupled between the second connection node and the ground voltage rail, and the method includes the following steps: (1) discharging the pair of bit lines to a ground voltage by activating the discharge device; (2) closing the switch device; (3) after steps (1) and (2), activating the word line, causing the voltages at the two storage nodes to drop to close to the ground voltage, and then causing the pair of bit lines to be charged; as well as (4) After step (3), during a sensing period, the switch device and the sensing latch are activated to increase the differential voltage between the pair of bit lines to a supply voltage V carried by the digital voltage rail. DD .

11. The method according to claim 10, characterized in that Step (3) comprises: activating the word line, causing the voltages at the two storage nodes to drop to near the ground voltage due to charge sharing between the gate capacitances of the pair of mutually coupled PMOSFET transistors and the capacitances of the pair of bit lines at the two storage nodes; as well as When the voltage at the two storage nodes drops below (V DD -V thp ), the pair of mutually coupled PMOSFET transistors are turned on to charge the pair of bit lines, so that the differential voltage between the pair of bit lines increases over time, where V thp represents the threshold voltage of the pair of mutually coupled PMOSFET transistors.

12. The method according to claim 10, characterized in that Also includes: After step (3), during the sensing period, a tri-state buffer is activated to output the data bit based on the voltage of one of the two output nodes; The sensing circuit further includes the tri-state buffer having a data input node coupled to one of the two output nodes.

13. The method according to claim 10, characterized in that Step (4) comprises: After step (3), during the sensing period, an acceleration transistor is activated to couple the digital voltage rail to the first connection node to charge one of the pair of bit lines to the supply voltage V DD ; The acceleration transistor is coupled between the digital voltage rail and the first connection node.

14. The method according to claim 10, characterized in that The switching device is an NMOSFET transistor.

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