Memory device and semiconductor device having cell-on-periphery structure

Abstract

An example memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, and a first test pad. The second semiconductor layer is disposed in a vertical direction with respect to the first semiconductor layer, and includes a peripheral circuit, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit. The test circuit checks a connection state of the first bonding pad and the second bonding pad. The test circuit receives a first test signal through the first test pad and the second test pad, generates a first test result signal representing a first misalignment between the first bonding pad and the second bonding pad based on the first test signal, and compensates operation of the peripheral circuit based on the first test result signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0145459 filed on October 27, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Background Art

[0003] Semiconductor memory devices can be divided into two categories depending on whether they retain stored data when disconnected from power. These categories include volatile memory devices that lose stored data when disconnected from power, and non-volatile memory devices that retain stored data when disconnected from power. Although volatile memory devices can perform read and write operations at high speed, the content stored therein may be lost when power is off. Since non-volatile memory devices retain the content stored therein even when power is off, they can be used to store data that needs to be retained.

[0004] Various structures are being adopted to increase the integration of memory devices and reduce the size of memory devices. However, since the memory device should also include a peripheral circuit for driving a memory cell array and a wiring structure for electrically connecting the memory cell array to the peripheral circuit, the reduction in size of the memory device is limited. Recently, a method is used in which elements included in the memory device are manufactured on separate wafers, rather than being manufactured on a single wafer and then bonded to each other. Summary of the invention

[0005] The present disclosure relates to a memory device capable of efficiently reducing size, easily detecting defects, and preventing performance degradation, and a semiconductor device capable of efficiently reducing size, easily detecting defects, and preventing performance degradation.

[0006] In general, according to some aspects, a memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, and a first test pad. The memory cell array is connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a peripheral circuit, a second bonding pad, a second test pad, and a test circuit. The peripheral circuit controls the memory cell array. The second bonding pad is connected to the first bonding pad. The second test pad is connected to the first test pad. The test circuit checks the connection state of the first bonding pad and the second bonding pad. The test circuit receives a first test signal through the first test pad and the second test pad, generates a first test result signal based on the first test signal, and compensates for the operation of the peripheral circuit based on the first test result signal. The first test result signal indicates a first misalignment between the first bonding pad and the second bonding pad.

[0007] In general, according to some aspects, a memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, a second bonding pad, a first test pad, and a second test pad. The memory cell array is connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a peripheral circuit, a third bonding pad, a fourth bonding pad, a third test pad, a fourth test pad, and a test circuit. The peripheral circuit controls the memory cell array. The third bonding pad and the fourth bonding pad are connected to the first bonding pad and the second bonding pad, respectively. The third test pad and the fourth test pad are connected to the first test pad and the second test pad, respectively. The test circuit checks the connection state of the first bonding pad and the second bonding pad and the connection state of the third bonding pad and the fourth bonding pad. The first bonding pad and the third bonding pad and the first test pad and the third test pad are arranged to correspond to the first region of the memory cell array. The second bonding pad and the fourth bonding pad and the second test pad and the fourth test pad are set to correspond to a second area of ​​the memory cell array that is different from the first area. When it is determined based on the first test signal provided through the first test pad and the third test pad that the misalignment between the first bonding pad and the third bonding pad has occurred at a first level that is a compensable level, the test circuit controls the operation of the peripheral circuit so that at least one of the sensing time of the first area of ​​the memory cell array and the first operating voltage supplied to the first area of ​​the memory cell array is adjusted. When it is determined based on the second test signal provided through the second test pad and the fourth test pad that the misalignment between the second bonding pad and the fourth bonding pad has occurred at a second level that is an uncompensable level, the test circuit shields the use of the second area of ​​the memory cell array, or repairs the second area of ​​the memory cell array to another area of ​​the memory cell array.

[0008] In general, according to some aspects, a semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a first circuit, a first bonding pad, and a first test pad. The second semiconductor layer is arranged in a vertical direction relative to the first semiconductor layer, and includes a second circuit, a second bonding pad, a second test pad, and a test circuit. The second circuit is interoperable with the first circuit. The second bonding pad is connected to the first bonding pad. The second test pad is connected to the first test pad. The test circuit checks the connection state of the first bonding pad and the second bonding pad. The test circuit receives a first test signal through the first test pad and the second test pad, generates a first test result signal based on the first test signal, and compensates for the operation of the second circuit based on the first test result signal. The first test result signal indicates a misalignment between the first bonding pad and the second bonding pad.

[0009] In some implementations, the memory device may have or adopt a structure in which a peripheral circuit and a memory cell array are stacked, for example, a cell over periphery (COP) structure in which the peripheral circuit is formed below and the memory cell array is stacked on the peripheral circuit. Therefore, the memory device may have a relatively small size.

[0010] In some implementations, the memory device and the semiconductor device may further include a test pad that is separated, independent and / or formed separately from the bonding pad, and may further include a test circuit connected to the test pad. The test pad and the test circuit may be used to determine whether misalignment occurs between the bonding pads, and appropriate feedback operations such as screening, repairing, and adjusting operating conditions may be performed depending on the degree of misalignment. Therefore, defects in the memory device may be detected relatively easily, and performance degradation of the memory device may be effectively prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Illustrative, non-limiting example implementations will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a perspective view of an example of a memory device.

[0013] Figure 2 is a cross-sectional view of an example of a memory device.

[0014] Figure 3A , Figure 3B and Figure 3C is a diagram for describing an example of a memory device.

[0015] Figure 4 is a block diagram illustrating an example of a memory device.

[0016] Figure 5A , Figure 5B and Figure 5C It is shown Figure 4 FIG. 1 is a diagram of an example of a memory cell array included in a memory device of FIG.

[0017] Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C is a diagram showing an example of bonding pads, test pads, and test circuits included in a memory device.

[0018] Figure 8 is a block diagram illustrating an example of a test circuit included in a memory device.

[0019] Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B It is shown Figure 8 FIG. 1 is a diagram of an example of multiple sense amplifiers included in a test circuit.

[0020] Fig.11A , Fig. 11B and Fig. 11C It is used to describe the use of memory devices Figure 8 FIG. 1 is a diagram of an example of the operation of the test circuit.

[0021] Fig.12 It is shown Figure 8 A block diagram of an example of a memory cell included in a test circuit.

[0022] Fig.13A and Fig. 13B is a block diagram illustrating an example of a test circuit included in a memory device.

[0023] Fig.14 It is shown Fig.13A and Fig. 13B A block diagram of an example of a memory cell included in a test circuit.

[0024] Fig.15A , Fig. 15B and Fig. 15C is a diagram for describing an example of a memory device.

[0025] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a diagram for describing an example of the operation of a memory device.

[0026] Fig.17A and Fig. 17B is a diagram for describing an example of a memory device.

[0027] Fig.18A , Fig.18B and Fig. 18C are exemplary perspective views of a memory device and a semiconductor device.

[0028] Fig.19A and Fig.19B is a cross-sectional view of an example of a memory package.

[0029] Fig. 20 is a block diagram illustrating an example of a memory system.

[0030] Fig.21 is a flow chart illustrating an example of a method of operating a memory device. DETAILED DESCRIPTION

[0031] Various example implementations will be described more fully with reference to the accompanying drawings, in which implementations are shown. However, the present disclosure may be implemented in a variety of different forms and should not be construed as being limited to the implementations set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0032] Figure 1 is a perspective view of an example of a memory device.

[0033] exist Figure 1 In the figure, two directions that are each parallel to or substantially parallel to the first surface (e.g., top surface) of the substrate and intersect each other are referred to as the first direction D1 (e.g., X-axis direction) and the second direction D2 (e.g., Y-axis direction). In addition, the direction perpendicular to or substantially perpendicular to the first surface of the substrate is referred to as the third direction D3 (e.g., Z-axis direction). For example, the first direction D1 and the second direction D2 may be perpendicular or substantially perpendicular to each other. In addition, the third direction D3 may be perpendicular or substantially perpendicular to both the first direction D1 and the second direction D2. In addition, the direction indicated by the arrows in the figure and the opposite direction thereof are considered to be the same direction. The definitions of the first direction D1, the second direction D2, and the third direction D3 are the same in the subsequent figures.

[0034] refer to Figure 1 , the memory device 10 includes a first semiconductor layer L1 and a second semiconductor layer L2.

[0035] The first semiconductor layer L1 and the second semiconductor layer L2 are arranged or stacked in the third direction D3. For example, the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the third direction D3, and the second semiconductor layer L2 may be arranged below the first semiconductor layer L1 in the third direction D3 (for example, directly below the first semiconductor layer L1 or indirectly below the first semiconductor layer L1). However, implementations are not limited thereto. For example, the memory device 10 may be flipped during the manufacturing process, and thus the second semiconductor layer L2 may be stacked on the first semiconductor layer L1 in the third direction D3. In some implementations, as will be referred to in Fig.18A and Fig.18B As described, three or more semiconductor layers may be stacked in the third direction D3.

[0036] The first semiconductor layer L1 includes a plurality of word lines WL, a plurality of bit lines BL, and a memory cell array MCA. Therefore, the first semiconductor layer L1 may be referred to as a memory cell region (MCR).

[0037] For example, if you refer to Figure 2As described, the first semiconductor layer L1 may include a first substrate. A plurality of word lines WL, a plurality of bit lines BL, and a memory cell array MCA may be disposed and / or formed on the first substrate. For example, each of the plurality of word lines WL may extend in a first direction D1, and the plurality of word lines WL may be arranged along a second direction D2. For example, each of the plurality of bit lines BL may extend in a second direction D2, and the plurality of bit lines BL may be arranged along the first direction D1. For example, the memory cell array MCA may be connected to the plurality of word lines WL and the plurality of bit lines BL.

[0038] The second semiconductor layer L2 includes a peripheral circuit PCKT for controlling the memory cell array MCA. Therefore, the second semiconductor layer L2 may be referred to as a peripheral circuit region (PCR).

[0039] For example, if you refer to Figure 2 As described above, the second semiconductor layer L2 may include a second substrate. The peripheral circuit PCKT may be disposed and / or formed on the second substrate. For example, as will be described with reference to Figure 4 As described, the peripheral circuit PCKT may include a control logic circuit, a sense amplifier unit, and the like.

[0040] The first semiconductor layer L1 includes a first bonding pad PD_L1, and the second semiconductor layer L2 includes a second bonding pad PD_L2. The second bonding pad PD_L2 is connected to the first bonding pad PD_L1. The memory cell array MCA (e.g., word lines WL and bit lines BL) of the first semiconductor layer L1 can be electrically connected to the peripheral circuit PCKT of the second semiconductor layer L2 through the first bonding pad PD_L1 and the second bonding pad PD_L2.

[0041] In some implementations, the first semiconductor layer L1 and the second semiconductor layer L2 may be manufactured separately, and then the first semiconductor layer L1 and the second semiconductor layer L2 may be connected to each other by a bonding scheme (or method). For example, the bonding scheme may represent a method of electrically or physically connecting a bonding metal pattern (e.g., a first bonding pad PD_L1) formed in the first semiconductor layer L1 to a bonding metal pattern (e.g., a second bonding pad PD_L2) formed in the second semiconductor layer L2. For example, the bonding pads PD_L1 and PD_L2 may be formed of copper (Cu), and the bonding scheme may be a Cu-Cu bonding scheme. Alternatively, the bonding pads PD_L1 and PD_L2 may be formed of aluminum (Al) or tungsten (W).

[0042] The first semiconductor layer L1 includes a first test pad TPD_L1, and the second semiconductor layer L2 includes a second test pad TPD_L2 and a test circuit TCKT. The second test pad TPD_L2 is connected to the first test pad TPD_L1. For example, the first test pad TPD_L1 and the second test pad TPD_L2 may be formed by the same material and the same process as the first bonding pad PD_L1 and the second bonding pad PD_L2. The test circuit TCKT checks the connection state (or condition) of the first bonding pad PD_L1 and the second bonding pad PD_L2. For example, the test circuit TCKT may determine whether the connection state of the first bonding pad PD_L1 and the second bonding pad PD_L2 is normal or abnormal by checking the connection state of the first test pad TPD_L1 and the second test pad TPD_L2.

[0043] Figure 2 is a cross-sectional view of an example of a memory device.

[0044] refer to Figure 1 and Figure 2 , the first semiconductor layer L1 may include a first substrate SUB1, a memory cell array MCA, a first bonding pad PD_L1, a first test pad TPD_L1, a first contact CT_L1, and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, a peripheral circuit PCKT, a second bonding pad PD_L2, a second test pad TPD_L2, a test circuit TCKT, a second contact CT_L2, and a second insulating layer IL2.

[0045] The first substrate SUB1 may be a supporting layer supporting components (or elements) of the first semiconductor layer L1, and the second substrate SUB2 may be a supporting layer supporting components of the second semiconductor layer L2. For example, each of the first substrate SUB1 and the second substrate SUB2 may be a silicon substrate and may be referred to as a base substrate. The first insulating layer IL1 may cover the components of the first semiconductor layer L1, and the second insulating layer IL2 may cover the components of the second semiconductor layer L2.

[0046] The memory cell array MCA may include a plurality of memory cells MC, and the peripheral circuit PCKT may include a plurality of transistors TR. Figure 4 , Figure 5A , Figure 5B and Figure 5C As described, at least some of the plurality of memory cells MC may be grouped into mats, blocks, banks, etc., and various types of circuits may be implemented by the plurality of transistors TR.

[0047] The memory cell MC and the transistor TR may be electrically connected to each other through the first contact CT_L1 and the second contact CT_L2 and the first bonding pad PD_L1 and the second bonding pad PD_L2. For example, the memory cell MC may be electrically connected to the first contact CT_L1 and the first bonding pad PD_L1, the transistor TR may be electrically connected to the second contact CT_L2 and the second bonding pad PD_L2, and the memory cell MC and the transistor TR may be electrically connected to each other by electrically connecting the first bonding pad PD_L1 to the second bonding pad PD_L2. Although not shown in detail, at least one conductive line and / or contact may be further formed to connect the memory cell MC to the first bonding pad PD_L1, and at least one conductive line and / or contact may be further formed to connect the transistor TR to the second bonding pad PD_L2.

[0048] The first test pad TPD_L1 and the second test pad TPD_L2 may be electrically connected to each other and may be electrically connected to the test circuit TCKT. When the test voltage VFC is applied to the first test pad TPD_L1, the test circuit TCKT may receive the test signal TS through the first test pad TPD_L1 and the second test pad TPD_L2, may generate a test result signal TRS based on the test signal TS, and may compensate the operation of the peripheral circuit PCKT based on the test result signal TRS. The test result signal TRS may represent or indicate a misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 (for example, may represent or indicate a misalignment between the first test pad TPD_L1 and the second test pad TPD_L2, or may represent or indicate whether a misalignment occurs between the first test pad TPD_L1 and the second test pad TPD_L2).

[0049] Reference Figures 8 to 14 The detailed configuration and operation of the test circuit TCKT are described.

[0050] In some implementations, the first semiconductor layer L1 may be manufactured by forming a memory cell array MCA, a first bonding pad PD_L1, a first test pad TPD_L1, a first contact CT_L1, and a first insulating layer IL1 in and / or on a first substrate SUB1, the second semiconductor layer L2 may be manufactured by forming a peripheral circuit PCKT, a second bonding pad PD_L2, a second test pad TPD_L2, a test circuit TCKT, a second contact CT_L2, and a second insulating layer IL2 in and / or on a second substrate SUB2, the first semiconductor layer L1 may be flipped, and the bonding pads PD_L1 and PD_L2 and the test pads TPD_L1 and TPD_L2 may be connected using a bonding scheme. Therefore, the first semiconductor layer L1 and the second semiconductor layer L2 may be electrically connected in a third direction D3.

[0051] although Figure 1 and Figure 2 An example is shown in which the semiconductor layers L1 and L2 include a pair of bonding pads PD_L1 and PD_L2 and a pair of test pads TPD_L1 and TPD_L2, but the implementation is not limited thereto, and the number of bonding pads and the number of test pads included in the semiconductor layers L1 and L2 may be determined in various ways.

[0052] The memory device 10 may have or adopt a structure in which a peripheral circuit PCKT and a memory cell array MCA are stacked, for example, a cell-on-periphery (COP) structure in which the peripheral circuit PCKT is formed below and the memory cell array MCA is stacked on the peripheral circuit PCKT. Therefore, the memory device 10 may have a relatively small size.

[0053] In addition, the memory device 10 may further include test pads TPD_L1 and TPD_L2 that are separated, independent and / or formed separately from the bonding pads PD_L1 and PD_L2, and may further include a test circuit TCKT connected to the test pads TPD_L1 and TPD_L2. The test pads TPD_L1 and TPD_L2 and the test circuit TCKT may be used to determine whether misalignment occurs between the bonding pads PD_L1 and PD_L2, and appropriate feedback operations such as shielding, repairing, and adjusting operating conditions may be performed depending on the degree of misalignment. Therefore, defects in the memory device 10 may be detected relatively easily, and performance degradation of the memory device 10 may be effectively prevented.

[0054] However, the implementation is not limited thereto, and the memory device 10 may have or adopt a bonding vertical NAND (BVNAND) structure in which the memory cell array MCA includes vertical flash memory cells (e.g., vertical NAND cells) and the peripheral circuit PCKT and the memory cell array MCA are set or arranged in a third direction D3.

[0055] Figure 3A , Figure 3B and Figure 3C is a diagram for describing an example of a memory device.

[0056] refer to Figure 3A , Figure 3B and Figure 3C , showing various situations that may occur when the first semiconductor layer L1 and the second semiconductor layer L2 are connected through a bonding scheme.

[0057] Figure 3A An example in which misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 does not occur is shown.

[0058] For example, the bonding pads PD_L1 and PD_L2 may have the same shape and the same size, and in a plane or in a plan view, the area (or length) of the bonding pads PD_L1 and PD_L2 overlap may be greater than the first area (or first length). For example, the resistance between the bonding pads PD_L1 and PD_L2 may be less than the first resistance value. For example, the test signal TS may have a relatively high voltage level. For example, Figure 3A As shown, when the bonding pads PD_L1 and PD_L2 completely overlap, the resistance between the bonding pads PD_L1 and PD_L2 may be about 0Ω, and the test signal TS may have substantially the same voltage level as that of the test voltage VFC.

[0059] For example, the test pads TPD_L1 and TPD_L2 may also have the same shape and the same size as the bonding pads PD_L1 and PD_L2, and the distance between the first bonding pad PD_L1 and the first test pad TPD_L1 may be substantially equal to the distance between the second bonding pad PD_L2 and the second test pad TPD_L2. In this case, if the misalignment between the bonding pads PD_L1 and PD_L2 does not occur, the misalignment between the test pads TPD_L1 and TPD_L2 may not occur.

[0060] Figure 3B An example is shown in which the misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 has occurred at a first level as a compensable level. Figure 3A Duplicate description.

[0061] For example, on a plane or in a plan view, the overlapping area (or length) of the bonding pads PD_L1 and PD_L2 may be less than or equal to the first area (or first length) and greater than the second area (or second length). For example, the resistance between the bonding pads PD_L1 and PD_L2 may be greater than or equal to the first resistance value and less than the second resistance value. For example, as the degree of misalignment between the bonding pads PD_L1 and PD_L2 increases, for example, as the overlapping area (or length) of the bonding pads PD_L1 and PD_L2 decreases, the resistance between the bonding pads PD_L1 and PD_L2 may increase. In other words, the more severe the misalignment between the bonding pads PD_L1 and PD_L2, for example, the smaller the overlapping area (or length) of the bonding pads PD_L1 and PD_L2, the greater the resistance between the bonding pads PD_L1 and PD_L2 may be. For example, with Figure 3ACompared with the example of , the test signal TS may have a lower voltage level, and as the resistance between the bonding pads PD_L1 and PD_L2 increases, the voltage level of the test signal TS may become lower.

[0062] For example, like the bonding pads PD_L1 and PD_L2 , the misalignment between the first test pad TPD_L1 and the second test pad TPD_L2 has occurred at the first level which is a compensable level.

[0063] In some implementations, when misalignment between the bonding pads PD_L1 and PD_L2 has occurred at a first level, a compensation operation may be performed by adjusting a sensing time and / or an operating voltage when a specific memory cell (or a specific memory region) connected to the bonding pads PD_L1 and PD_L2 operates, referring to Fig. 11B and Fig. 11C Describe this.

[0064] Figure 3C An example is shown in which the misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 has occurred at the second level which is an uncompensable level. Figure 3A and Figure 3B Duplicate description.

[0065] For example, on a plane or in a plan view, the area (or length) of the bonding pads PD_L1 and PD_L2 overlapping may be less than or equal to the second area (or second length). For example, the resistance between the bonding pads PD_L1 and PD_L2 may be greater than or equal to the second resistance value. Figure 3B Compared with the example of , the test signal TS may have a lower voltage level. Figure 3C As shown, when the bonding pads PD_L1 and PD_L2 do not overlap at all, the resistance between the bonding pads PD_L1 and PD_L2 may be approximately ∞Ω, and the test signal TS may have a voltage level of approximately 0V.

[0066] For example, like the bonding pads PD_L1 and PD_L2 , the misalignment between the first test pad TPD_L1 and the second test pad TPD_L2 has occurred at the second level which is a compensable level.

[0067] In some implementations, when the misalignment between the bonding pads PD_L1 and PD_L2 has occurred at the second level, the use of a specific memory cell (or a specific memory region) connected to the bonding pads PD_L1 and PD_L2 can be shielded or prevented, and / or the specific memory cell (or a specific memory region) can be repaired to other memory cells (or another memory region) or replaced with other memory cells (or another memory region), referring to Fig.16A , Fig. 16B , Fig. 16C and Fig.16D Describe this.

[0068] Figure 4 is a block diagram illustrating an example of a memory device.

[0069] refer to Figure 4 , the memory device 200 may include a peripheral circuit 201, a memory cell array 300, and a test circuit 400. The peripheral circuit 201 may include a control logic circuit 210, an address register 220, a bank control logic circuit 230, a row address multiplexer 240, a refresh counter 245, a column address latch 250, a row decoder 260, a column decoder 270, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, and a data I / O buffer 295. For example, the memory device 200 may be one of various volatile memory devices, such as a dynamic random access memory (DRAM).

[0070] The memory cell array 300 may include a first memory bank array 310 to an eighth memory bank array 380 (e.g., a first memory bank array to an eighth memory bank array 310, 320, 330, 340, 350, 360, 370, and 380). The row decoder 260 may include a first memory bank row decoder 260a to an eighth memory bank row decoder 260h connected to the first memory bank array 310 to the eighth memory bank array 380, respectively. The column decoder 270 may include a first memory bank column decoder 270a to an eighth memory bank column decoder 270h connected to the first memory bank array 310 to the eighth memory bank array 380, respectively. The sense amplifier unit 285 may include a first memory bank sense amplifier 285a to an eighth memory bank sense amplifier 285h connected to the first memory bank array 310 to the eighth memory bank array 380, respectively.

[0071] The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form the first to eighth banks. Each of the first to eighth bank arrays 310 to 380 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC located at intersections of the word lines WL and the bit lines BL.

[0072] although Figure 4The memory device 200 is shown as including eight memory banks (and eight memory bank arrays, eight row decoders, etc.), but the memory device 200 may include any number of memory banks; for example, one, two, four, eight, sixteen, or thirty-two memory banks, or any number between one and thirty-two.

[0073] The address register 220 can be obtained from a memory controller (e.g., Fig. 20 The memory controller 1200 in the embodiment receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic circuit 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0074] The bank control logic circuit 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, one bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 260a to the eighth bank row decoder 260h may be activated, and in response to the bank control signal, one bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 270a to the eighth bank column decoder 270h may be activated.

[0075] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and may receive a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h.

[0076] One of the first to eighth bank row decoders 260a to 260h that is activated may decode the row address RA output from the row address multiplexer 240, and may activate a word line WL corresponding to the row address RA in the corresponding bank array. For example, the activated bank row decoder may generate a word line driving voltage, and may apply the word line driving voltage to the word line WL corresponding to the row address RA.

[0077] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some implementations, in the burst mode, the column address latch 250 may generate a column address incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 270a to 270h.

[0078] An activated one of the first to eighth bank column decoders 270 a to 270 h may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0079] The I / O gating circuit 290 may include a circuit configured to gate input / output data. The I / O gating circuit 290 may also include a read data latch configured to store data output from the first memory array 310 to the eighth memory array 380, and may also include a write control device for writing data into the first memory array 310 to the eighth memory array 380.

[0080] The data DAT read from one of the first memory array 310 to the eighth memory array 380 may be sensed by a sense amplifier connected to the one memory array from which the data DAT is to be read, and may be stored in a read data latch. The data DAT stored in the read data latch may be provided to a memory controller via a data I / O buffer 295. The data DAT to be written into one of the first memory array 310 to the eighth memory array 380 may be provided from the memory controller to the I / O gating circuit 290 via the data I / O buffer 295, and the I / O gating circuit 290 may write the data DAT into one memory array through a write driver.

[0081] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal for the memory device 200 to perform a write operation and / or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from a memory controller and a mode register 212 that sets an operation mode of the memory device 200. In some implementations, the operations described herein as being performed by the control logic circuit 210 may be performed by a processing circuit. For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0082] The test circuit 400 may receive a test signal TS through a first test pad TPD_L1 in a first semiconductor layer L1 including the memory cell array 300 and a second test pad TPD_L2 in a second semiconductor layer L2 including the peripheral circuit 201, may generate a test result signal TRS indicating a misalignment between a first bonding pad PD_L1 in the first semiconductor layer L1 and a second bonding pad PD_L2 in the second semiconductor layer L2 based on the test signal TS, and may compensate for an operation of the peripheral circuit 201 based on the test result signal TRS. For example, at least one of a sensing time of the memory cell array 300 by the sense amplifier unit 285 and an operating voltage supplied to the memory cell array 300 may be adjusted based on the test result signal TRS.

[0083] Figure 5A , Figure 5B and Figure 5C It is shown Figure 4 FIG. 1 is a diagram of an example of a memory cell array included in a memory device of FIG.

[0084] refer to Figure 4 and Figure 5A , the first memory array 310 included in the memory cell array 300 may include a plurality of word lines WL1, WL2, ..., WLm-1, WLm (where m is a positive integer greater than or equal to 2), a plurality of bit lines BL1, BL2, ..., BLn-1, BLn (where n is a positive integer greater than or equal to 2, which may be the same as or different from m), and a plurality of memory cells MC arranged at or near the intersections between the word lines WL1 to WLm and the bit lines BL1 to BLn. For example, each of the plurality of memory cells MC may include a DRAM cell structure. The plurality of word lines WL1 to WLm connected to the plurality of memory cells MC may be referred to as rows of the first memory array 310, and the plurality of bit lines BL1 to BLn connected to the plurality of memory cells MC may be referred to as columns of the first memory array 310.

[0085] refer to Figure 5B , the i-th (where i is a positive integer) memory bank array BANKi included in the memory cell array 300 may include first to x-th (where x is a positive integer greater than or equal to 2) blocks BLK1, BLK2, ..., BLKx. Although not shown in detail, each of the blocks BLK1 to BLKx may also include a plurality of memory cells. For convenience, the memory bank array may be referred to as a memory bank.

[0086] refer to Figure 5C, the j-th (where j is a positive integer) block BLKj included in the memory cell array 300 may include first to y-th (where y is a positive integer greater than or equal to 2) mats MAT1, MAT2, ..., MATy. Although not shown in detail, each of the mats MAT1 to MATy may include a plurality of memory cells. The mat may be referred to as a sub-array.

[0087] Although the memory device is described based on DRAM, the memory device can be any volatile memory device and / or any non-volatile memory device, such as static random access memory (SRAM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0088] Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C is a diagram showing an example of bonding pads, test pads, and test circuits included in a memory device.

[0089] refer to Fig. 6A , Figure 6B and Figure 6C , shows the configuration of bonding pads and test pads included in one pad and the operation of a test circuit using the bonding pads and the test pads. For ease of explanation, components not related to the pads and the test circuit are omitted.

[0090] Fig. 6A An example is shown where one of the pads includes a pair of test pads.

[0091] For example, the first mat MAT1 may include a bonding pad PD_L1_MAT1 formed in the first semiconductor layer L1 and a bonding pad PD_L2_MAT1 formed in the second semiconductor layer L2 and connected to the bonding pad PD_L1_MAT1. For example, the first mat MAT1 may include a test pad TPD_L1_MAT1 formed in the first semiconductor layer L1 and a test pad TPD_L2_MAT1 formed in the second semiconductor layer L2 and connected to the test pad TPD_L1_MAT1.

[0092] The test circuit 400 may receive a test signal TS_MAT1 through the test pads TPD_L1_MAT1 and TPD_L2_MAT1 included in the first pad MAT1. Based on the test signal TS_MAT1, the test circuit 400 may generate and store a test result signal TRS_MAT1 indicating misalignment between the bonding pads PD_L1_MAT1 and PD_L2_MAT1 of the first pad MAT1. Based on the test result signal TRS_MAT1, the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the first pad MAT1.

[0093] Figure 6B An example is shown in which one pad includes several pairs of test pads and the test pads are connected in parallel. Fig. 6A Duplicate description.

[0094] exist Figure 6B In an example, the first mat MAT1 may include test pads TPD1_L1_MAT1 and TPD2_L1_MAT1 formed in the first semiconductor layer L1, and test pads TPD1_L2_MAT1 and TPD2_L2_MAT1 formed in the second semiconductor layer L2 and connected to the test pads TPD1_L1_MAT1 and TPD2_L1_MAT1, respectively. The test pads TPD1_L1_MAT1 and TPD1_L2_MAT1 may be connected to the test circuit 400 independently, individually, or separately from the test pads TPD2_L1_MAT1 and TPD2_L2_MAT1.

[0095] The test circuit 400 may receive a test signal TS1_MAT1 through the test pads TPD1_L1_MAT1 and TPD1_L2_MAT1 of the first pad MAT1, and receive a test signal TS2_MAT1 through the test pads TPD2_L1_MAT1 and TPD2_L2_MAT1 of the first pad MAT1. Based on the test signals TS1_MAT1 and TS2_MAT1, the test circuit 400 may generate and store test result signals TRS1_MAT1 and TRS2_MAT1, which indicate whether misalignment has occurred between the bonding pads PD_L1_MAT1 and PD_L2_MAT1 of the first pad MAT1. Based on the test result signals TRS1_MAT1 and TRS2_MAT1, the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the first pad MAT1.

[0096] Figure 6C An example is shown in which one pad includes several pairs of test pads and the test pads are connected in series. Fig. 6A and Figure 6BDuplicate description.

[0097] exist Figure 6C In the example of FIG. 4 , the test pads TPD1_L1_MAT1 and TPD1_L2_MAT1 may be connected to the test circuit 400 together with the test pads TPD2_L1_MAT1 and TPD2_L2_MAT1 .

[0098] The test circuit 400 may receive two test signals through the test pads TPD1_L1_MAT1, TPD1_L2_MAT1 of the first pad MAT1 and the test pads TPD2_L1_MAT1, TPD2_L2_MAT1 of the first pad MAT1. Since the test pads TPD1_L1_MAT1, TPD1_L2_MAT1, TPD2_L1_MAT1, and TPD2_L2_MAT1 are connected to the test circuit 400 in common, the two test signals may be provided as an integrated test signal TS_MAT1'. Based on the test signal TS_MAT1', the test circuit 400 may generate and store a test result signal TRS_MAT1' indicating whether misalignment has occurred between the bonding pads PD_L1_MAT1 and PD_L2_MAT1 of the first pad MAT1. Based on the test result signal TRS_MAT1', the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the first pad MAT1.

[0099] although Figure 6B and Figure 6C An example is shown in which one pad includes two pairs of test pads, but the implementation is not limited thereto. For example, one pad may include any number of test pads.

[0100] Fig. 7A An example is shown in which each of the different pads includes a pair of test pads. Fig. 6A Duplicate description.

[0101] For example, the second mat MAT2 may include bonding pads PD_L1_MAT2 and PD_L2_MAT2 formed in the first and second semiconductor layers L1 and L2 and connected to each other. For example, the second mat MAT2 may include test pads TPD_L1_MAT2 and TPD_L2_MAT2 formed in the first and second semiconductor layers L1 and L2 and connected to each other.

[0102] The test circuit 400 may receive a test signal TS_MAT2 through the test pads TPD_L1_MAT2 and TPD_L2_MAT2 of the second pad MAT2. Based on the test signal TS_MAT2, the test circuit 400 may generate and store a test result signal TRS_MAT2 indicating misalignment between the bonding pads PD_L1_MAT2 and PD_L2_MAT2 of the second pad MAT2. Based on the test result signal TRS_MAT2, the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the second pad MAT2.

[0103] Figure 7B An example is shown in which each of the different blocks includes a pair of test pads.

[0104] For example, the first block BLK1 may include bonding pads PD_L1_BLK1 and PD_L2_BLK1 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other, and test pads TPD_L1_BLK1 and TPD_L2_BLK1 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other. For example, the second block BLK2 may include bonding pads PD_L1_BLK2 and PD_L2_BLK2 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other, and test pads TPD_L1_BLK2 and TPD_L2_BLK2 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other.

[0105] The test circuit 400 may receive a test signal TS_BLK1 through the test pads TPD_L1_BLK1 and TPD_L2_BLK1 of the first block BLK1. Based on the test signal TS_BLK1, the test circuit 400 may generate and store a test result signal TRS_BLK1 indicating a misalignment between the bonding pads PD_L1_BLK1 and PD_L2_BLK1 of the first block BLK1. Based on the test result signal TRS_BLK1, the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the first block BLK1. In addition, the test circuit 400 may receive a test signal TS_BLK2 through the test pads TPD_L1_BLK2 and TPD_L2_BLK2 of the second block BLK2. Based on the test signal TS_BLK2, the test circuit 400 may generate and store a test result signal TRS_BLK2 indicating a misalignment between the bonding pads PD_L1_BLK2 and PD_L2_BLK2 of the second block BLK2. Based on the test result signal TRS_BLK2 , the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the second block BLK2 .

[0106] Figure 7CAn example is shown in which each of the different memory banks includes a pair of test pads.

[0107] For example, the first memory bank BANK1 may include bonding pads PD_L1_BANK1 and PD_L2_BANK1 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other, and test pads TPD_L1_BANK1 and TPD_L2_BANK1 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other. For example, the second memory bank BANK2 may include bonding pads PD_L1_BANK2 and PD_L2_BANK2 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other, and test pads TPD_L1_BANK2 and TPD_L2_BANK2 formed in the first semiconductor layer L1 and the second semiconductor layer L2 and connected to each other.

[0108] The test circuit 400 may receive a test signal TS_BANK1 through the test pads TPD_L1_BANK1 and TPD_L2_BANK1 of the first memory bank BANK1. Based on the test signal TS_BANK1, the test circuit 400 may generate and store a test result signal TRS_BANK1 indicating a misalignment between the bonding pads PD_L1_BANK1 and PD_L2_BANK1 of the first memory bank BANK1. Based on the test result signal TRS_BANK1, the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the first memory bank BANK1. In addition, the test circuit 400 may receive a test signal TS_BANK2 through the test pads TPD_L1_BANK2 and TPD_L2_BANK2 of the second memory bank BANK2. Based on the test signal TS_BANK2, the test circuit 400 may generate and store a test result signal TRS_BANK2 indicating a misalignment between the bonding pads PD_L1_BANK2 and PD_L2_BANK2 of the second memory bank BANK2. Based on the test result signal TRS_BANK2 , the test circuit 400 may compensate for the operation of the peripheral circuit PCKT when operating the second memory bank BANK2 .

[0109] although Fig. 7A , Figure 7B and Figure 7C An example is shown in which one pad, one block, and one storage body include a pair of test pads, but the implementation is not limited thereto. Figure 6B and Figure 6C As described, several pairs of test pads connected in parallel or in series may be included in one pad, one block, and one bank.

[0110] In the memory device, a pair of test pads or a plurality of pairs of test pads may be provided for each pad, for each block, and / or for each memory bank. Based on the test pads, bonding defects (e.g., misalignment) may be detected for each pad, for each block, and / or for each memory bank, and when defects are detected, feedback operations (e.g., shielding, repair, and operating condition adjustment, etc.) may be performed for each pad, for each block, and / or for each memory bank.

[0111] Figure 8 is a block diagram illustrating an example of a test circuit included in a memory device.

[0112] refer to Figure 8 , the test circuit 400 a may include a plurality of sense amplifiers 410 and a storage unit 420 .

[0113] The plurality of sense amplifiers 410 may generate a test result signal TRS based on the test signal TS. The storage unit 420 may store and output the test result signal TRS.

[0114] For example, each of the plurality of sense amplifiers 410 may compare the test signal TS with a reference voltage within a predetermined sensing time, and may generate a portion or part of the test result signal TRS as a result of the comparison. For example, the storage unit 420 may include components each of which stores a portion of the test result signal TRS. For example, the test signal TS may be a reference voltage. Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C One of the test signals TS_MAT1, TS1_MAT1, TS2_MAT1, TS_MAT1', TS_MAT2, TS_BLK1, TS_BLK2, TS_BANK1, and TS_BANK2 described above, and the test result signal TRS may be a reference. Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C One of the test result signals TRS_MAT1, TRS1_MAT1, TRS2_MAT1, TRS_MAT1', TRS_MAT2, TRS_BLK1, TRS_BLK2, TRS_BANK1 and TRS_BANK2 is described.

[0115] Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B It is shown Figure 8FIG. 1 is a diagram of an example of multiple sense amplifiers included in a test circuit.

[0116] refer to Fig.9A and Fig. 9B , the plurality of sense amplifiers 410 a may include a first sense amplifier 411 a , a second sense amplifier 413 a , and a third sense amplifier 415 a .

[0117] The plurality of sense amplifiers 410 a may operate based on different reference voltages VSREF1 , VSREF2 , and VSREF3 and based on the same sensing time tSA.

[0118] For example, the first sense amplifier 411a may generate a first bit BIT1 of the test result signal TRS based on the test signal TS, a first reference voltage VSREF1 having a first voltage level SREF1, and a sensing time tSA. The second sense amplifier 413a may generate a second bit BIT2 of the test result signal TRS based on the test signal TS, a second reference voltage VSREF2 having a second voltage level SREF2 higher than the first voltage level SREF1, and a sensing time tSA. The third sense amplifier 415a may generate a third bit BIT3 of the test result signal TRS based on the test signal TS, a third reference voltage VSREF3 having a third voltage level SREF3 higher than the second voltage level SREF2, and a sensing time tSA. For example, the first bit BIT1, the second bit BIT2, and the third bit BIT3 may be the least significant bit (LSB), the center significant bit (CSB), and the most significant bit (MSB) of the test result signal TRS, respectively.

[0119] exist Fig. 9B In the example of , at the sensing time tSA, the voltage level of the test signal TS may be higher than the first voltage level SREF1 of the first reference voltage VSREF1, may be higher than the second voltage level SREF2 of the second reference voltage VSREF2, and may be lower than the third voltage level SREF3 of the third reference voltage VSREF3. Therefore, the first sense amplifier 411a may generate a first bit BIT1 having a first logic level (e.g., “1”) by comparing the first reference voltage VSREF1 with the test signal TS, the second sense amplifier 413a may generate a second bit BIT2 having a first logic level (e.g., “1”) by comparing the second reference voltage VSREF2 with the test signal TS, and the third sense amplifier 415a may generate a third bit BIT3 having a second logic level (e.g., “0”) by comparing the third reference voltage VSREF3 with the test signal TS. For example, a test result signal TRS having a value of “011” may be generated. In addition, as shown in reference Figure 3A , Figure 3B and Figure 3CAs described, the voltage level of the test signal TS may vary depending on the degree of misalignment between the bonding pads PD_L1 and PD_L2. For example, as the degree of misalignment between the bonding pads PD_L1 and PD_L2 increases, the voltage level of the test signal TS may decrease (e.g., the more severe the misalignment between the bonding pads PD_L1 and PD_L2, the lower the voltage level of the test signal TS may be).

[0120] refer to Fig. 10A and Fig. 10B , the plurality of sense amplifiers 410 b may include a first sense amplifier 411 b , a second sense amplifier 413 b , and a third sense amplifier 415 b .

[0121] The plurality of sense amplifiers 410 b may operate based on different sensing times tSA1 , tSA2 , and tSA3 and based on the same reference voltage VSREF.

[0122] For example, the first sense amplifier 411b may generate a first bit BIT1 of the test result signal TRS based on the reference voltage VSREF having a voltage level SREF, the test signal TS, and the first sensing time tSA1. The second sense amplifier 413b may generate a second bit BIT2 of the test result signal TRS based on the reference voltage VSREF, the test signal TS, and the second sensing time tSA2 longer than the first sensing time tSA1. The third sense amplifier 415b may generate a third bit BIT3 of the test result signal TRS based on the reference voltage VSREF, the test signal TS, and the third sensing time tSA3 longer than the second sensing time tSA2.

[0123] exist Fig. 10B In the example of , the voltage level of the test signal TS may be lower than the voltage level SREF of the reference voltage VSREF at the first sensing time tSA1, the voltage level of the test signal TS may be lower than the voltage level SREF of the reference voltage VSREF at the second sensing time tSA2, and the voltage level of the test signal TS may be higher than the voltage level SREF of the reference voltage VSREF at the third sensing time tSA3. Therefore, the first sense amplifier 411b may generate a first bit BIT1 having a first logic level (e.g., “1”) by comparing the reference voltage VSREF with the test signal TS, the second sense amplifier 413b may generate a second bit BIT2 having a first logic level (e.g., “1”) by comparing the reference voltage VSREF with the test signal TS, and the third sense amplifier 415b may generate a third bit BIT3 having a second logic level (e.g., “0”) by comparing the reference voltage VSREF with the test signal TS. For example, a test result signal TRS having a value of “011” may be generated. In addition, as shown in the reference Figure 3A , Figure 3B and Figure 3C As described, the voltage level of the test signal TS may vary depending on the degree of misalignment between the bonding pads PD_L1 and PD_L2. For example, as the degree of misalignment between the bonding pads PD_L1 and PD_L2 increases, the voltage level of the test signal TS may decrease.

[0124] Fig.11A , Fig. 11B and Fig. 11C It is used to describe the use of memory devices Figure 8 FIG. 1 is a diagram of an example of the operation of the test circuit.

[0125] refer to Figure 4 and Fig.11A , shows an example in which the voltage level of the bit line depends on the change of the operation (eg, sensing operation) of the bit line sense amplifier included in the sense amplifier unit 285 of the memory device 200. For example, Fig.11A It is shown that the voltage level of the bit line changes depending on the resistances Rbond1, Rbond2, Rbond3, Rbond4, Rbond5, Rbond6, Rbond7, Rbond8 and Rbond9 between the bonding pads.

[0126] For example, offset cancellation may be performed during a first time tOC, charge sharing between a memory cell and a bit line may be performed during a second time tCS, and data stored in the memory cell may be actually sensed during a third time tSEN. The total time tOC, tCS, and tSEN during which the sensing operation is performed may be defined as a sensing time.

[0127] Regarding the resistances Rbond1 to Rbond9 between the bonding pads, the resistance Rbond1 may have a minimum value, the resistances Rbond2 to Rbond8 may have gradually increasing values, and the resistance Rbond9 may have a maximum value. As the resistance between the bonding pads increases, for example, as the degree of misalignment between the bonding pads becomes more severe, the performance of the sensing operation may be degraded or deteriorated.

[0128] refer to Figure 3A , Figure 3B , Figure 3C , Fig. 11B and Fig. 11C , shows an example in which the degree of misalignment between bonding pads is determined depending on the value of the test result signal TRS obtained based on the voltage level of the test signal TS.

[0129] For example, when the test signal TS has a relatively high voltage level (e.g., a voltage level substantially the same as the test voltage VFC) and the value of the test result signal TRS is obtained as “111”, it can be determined that the misalignment between the bonding pads PD_L1 and PD_L2 does not occur, as shown in FIG. Figure 3A In this case, the pad, block and / or memory bank including the bonding pads PD_L1 and PD_L2 may operate normally without an additional feedback operation.

[0130] For example, when the test signal TS has Figure 3A When the voltage level is lower than that of the example and the value of the test result signal TRS is obtained as one of “110”, “101”, “100”, “011”, and “010”, it can be determined that the misalignment between the bonding pads PD_L1 and PD_L2 has occurred at the first level as the compensable level, such as Figure 3B In this case, when operating a pad, a block, and / or a memory bank including the bonding pads PD_L1 and PD_L2 or when operating a pad, a block, and / or a memory bank including the bonding pads PD_L1 and PD_L2, the operation of the peripheral circuit PCKT may be controlled so that Fig. 11B Adjust the sensing time as shown or as Fig. 11C For example, the operation of adjusting the sensing time may represent increasing the voltage used to perform the reference Fig.11A The operation of the first time tOC of offset cancellation is described. For example, the operation of adjusting the operating voltage may represent an operation of increasing a high level of a voltage supplied to a word line (eg, an enable level of a VPP voltage).

[0131] For example, when the test signal TS has Figure 3B When the voltage level is lower than that of the example and the value of the test result signal TRS is obtained as one of "001" and "000", it can be determined that the misalignment between the bonding pads PD_L1 and PD_L2 has occurred at the second level which is an uncompensable level. In this case, as will be referred to Fig.16A , Fig. 16B , Fig. 16C and Fig.16D As described, the operation of the peripheral circuit PCKT may be controlled so that the use of a pad, a block, and / or a storage body including the bonding pads PD_L1 and PD_L2 is shielded, or the pad, a block, and / or a storage body including the bonding pads PD_L1 and PD_L2 is repaired.

[0132] In some implementations, when it is determined that the misalignment between the bonding pads PD_L1 and PD_L2 has occurred at a first level that is a compensable level, it can be determined that there is almost no misalignment when the voltage level of the test signal TS is high and the value of the test result signal TRS is large, and it can be determined that the misalignment is more severe when the voltage level of the test signal TS is low and the value of the test result signal TRS is small. For example, when the value of the test result signal TRS is "110", it can be determined that a weak misalignment has occurred. For example, when the value of the test result signal TRS is "010", it can be determined that a strong or severe misalignment has occurred.

[0133] In some implementations, when it is determined that the misalignment between the bonding pads PD_L1 and PD_L2 has occurred at a first level that is a compensable level, and when Fig. 11B When adjusting the sensing time (e.g., the first time tOC) as shown, the sensing time may increase as the degree of misalignment between the bonding pads increases (e.g., the more severe the misalignment, the longer the sensing time may be). For example, when the value of the test result signal TRS is "110", "101", "100", "011", and "010", the sensing time (e.g., the first time tOC) may increase by Δt5, Δt4, Δt3, Δt2, and Δt1, respectively. For example, when the value of the test result signal TRS is "010", the increment Δt1 of the sensing time may be the maximum value. For example, when the value of the test result signal TRS is "110", the increment Δt5 of the sensing time may be the minimum value. For example, Δt1>Δt2>Δt3>Δt4>Δt5.

[0134] In some implementations, when it is determined that the misalignment between the bonding pads PD_L1 and PD_L2 has occurred at a first level that is a compensable level, and when Fig. 11C When adjusting the voltage level of the operating voltage (e.g., the enable level of the VPP voltage) as shown, the voltage level of the operating voltage may increase as the degree of misalignment between the bonding pads increases (e.g., the more severe the misalignment, the higher the voltage level of the operating voltage may be). For example, when the value of the test result signal TRS is "110", "101", "100", "011", and "010", the voltage level of the operating voltage (e.g., the enable level of the VPP voltage) may increase by ΔV5, ΔV4, ΔV3, ΔV2, and ΔV1, respectively. For example, when the value of the test result signal TRS is "010", the level increment ΔV1 of the operating voltage may be the maximum value. For example, when the value of the test result signal TRS is "110", the level increment ΔV5 of the operating voltage may be the minimum value. For example, ΔV1>ΔV2>ΔV3>ΔV4>ΔV5.

[0135] In some implementations, the Fig. 11B and Fig. 11C compensation operation.

[0136] Fig.12 It is shown Figure 8 A block diagram of an example of a memory cell included in a test circuit.

[0137] refer to Fig.12 , the memory cell 420 a may include a first antifuse 421 , a second antifuse 423 , and a third antifuse 425 .

[0138] The first antifuse 421 can store and output the first bit BIT1 of the test result signal TRS. The second antifuse 423 can store and output the second bit BIT2 of the test result signal TRS. The third antifuse 425 can store and output the third bit BIT3 of the test result signal TRS. For example, the antifuse can be implemented in a structure in which a dielectric material is inserted between two conductive electrodes, and the antifuse can be programmed (e.g., electrically short-circuited) by applying a programming voltage (e.g., a relatively high voltage) through the two conductive electrodes of the antifuse (e.g., the two ends of the antifuse) for a sufficient time, so that the dielectric material between the two conductive electrodes is damaged, destroyed or broken. For example, when each bit of the test result signal TRS has a first logic level (e.g., "1"), the corresponding antifuse can be programmed.

[0139] However, the implementation is not limited thereto, and the storage unit may include at least one of various components for storing bits of the test result signal TRS.

[0140] although Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 11B , Fig. 11C and Fig.12 An example of generating and storing the test result signal TRS as a 3-bit digital code using three sense amplifiers and three antifuses is shown, but the implementation is not limited thereto.

[0141] Fig.13A and Fig. 13B is a block diagram illustrating an example of a test circuit included in a memory device.

[0142] refer to Fig.13A , the test circuit 400 b may include a plurality of sense amplifiers 410 , a storage unit 420 , and a multiplexer 430 .

[0143] The test circuit 400b can be used with Figure 8The test circuit 400a is substantially the same as the test circuit 400b, except that the test circuit 400b further includes a multiplexer 430.

[0144] The multiplexer 430 may select and output one of a plurality of test signals TS1, TS2, ..., TSK (where k is a positive integer greater than or equal to 2) based on the selection signal SEL. The plurality of sense amplifiers 410 may generate a plurality of test result signals TRS1, TRS2, ..., TRSk based on the plurality of test signals TS1 to TSK. The storage unit 420 may store and output the plurality of test result signals TRS1 to TRSk. For example, each of the plurality of test signals TS1 to TSK may be a reference signal. Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C One of the test signals TS_MAT1, TS1_MAT1, TS2_MAT1, TS_MAT1′, TS_MAT2, TS_BLK1, TS_BLK2, TS_BANK1, and TS_BANK2 described above, and each of the plurality of test result signals TRS1 to TRSk may be a reference signal. Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C One of the test result signals TRS_MAT1, TRS1_MAT1, TRS2_MAT1, TRS_MAT1', TRS_MAT2, TRS_BLK1, TRS_BLK2, TRS_BANK1, and TRS_BANK2 described. For example, the selection signal SEL may be a test mode register set (TMRS) signal, and a test operation may be performed for each pad, block, and bank using the TMRS signal.

[0145] refer to Fig. 13B , the test circuit 400 c may include a plurality of sense amplifiers 410 , a storage unit 420 , and a multiplexer 430 .

[0146] The test circuit 400c can be used with Figure 8 The test circuit 400 is substantially the same as the test circuit 400 , except that the test circuit 400 c further includes a multiplexer 430 .

[0147] The multiplexer 430 can select and output one of the plurality of test signals TS1, TS2, ..., TSK and the test voltage VFC based on the selection signal SEL. The plurality of sense amplifiers 410 can generate a plurality of test result signals TRS1, TRS2, ..., TRSk and a reference test signal TREF based on the plurality of test signals TS1 to TSK and the test voltage VFC. The test voltage VFC and the reference test signal (TREF) can be used as reference signals.

[0148] Fig.14 It is shown Fig.13A and Fig. 13B A block diagram of an example of a memory cell included in a test circuit.

[0149] refer to Fig.14 , the memory cell 420 b may include a first antifuse set 422 , a second antifuse set 424 , and a kth antifuse set 426 .

[0150] The first antifuse set 422, the second antifuse set 424, and the kth antifuse set 426 may store the first test result signal TRS1, the second test result signal TRS2, and the kth test result signal TRSk, respectively. For example, each of the antifuse sets 422, 424, and 426 may include a first test result signal TRS1, a second test result signal TRS2, and a kth test result signal TRSk. Fig.12 Description of the antifuse.

[0151] Fig.15A , Fig. 15B and Fig. 15C is a diagram for describing an example of a memory device.

[0152] refer to Fig.15A , Fig. 15B and Fig. 15C , showing various situations that may occur when the first semiconductor layer L1 and the second semiconductor layer L2 are connected through a bonding scheme.

[0153] Fig.15A FIG. 2 shows an example of a first region REG1 of a memory cell array. In the first region REG1, the first semiconductor layer L1 and the second semiconductor layer L2 are perfectly connected (eg, bonded) without errors. Figure 3A Like the example of FIG. 1 , in the entire first region REG1 , misalignment between the first bonding pad PD_L1 of the first semiconductor layer L1 and the second bonding pad PD_L2 of the second semiconductor layer L2 may not occur.

[0154] Fig. 15B FIG. 2 shows an example of a second region REG2 of the memory cell array. In the second region REG2, the first semiconductor layer L1 may be moved to the right and connected (eg, bonded) to the second semiconductor layer L2. Figure 3CAs in the example of FIG. 2 , in the entire second region REG2 , a misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 may occur at a second level that is an uncompensable level.

[0155] Fig. 15C An example of a third region REG3 of a memory cell array is shown. In the third region REG3, the first semiconductor layer L1 may be rotated counterclockwise and connected (e.g., bonded) to the second semiconductor layer L2. For example, in the first sub-region SREG1 of the third region REG3, a misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 may occur at a first level as a compensable level. For example, in the second sub-region SREG2 of the third region REG3, a misalignment between the first bonding pad PD_L1 and the second bonding pad PD_L2 may occur at a second level as an uncompensable level.

[0156] like Fig. 15B As shown, if the degree of misalignment of the bonding pad is uniform in the entire specific region REG2, the operation of detecting defects and the feedback operation can be performed for the entire specific region REG2 by testing only some sub-regions of the specific region REG2. Fig. 15C As shown, if the degree of misalignment of the bonding pads is non-uniform in the specific region REG3, each sub-region included in the specific region REG3 may be tested, and an operation of detecting a defect and a feedback operation may be performed for each sub-region.

[0157] In some implementations, Fig.15A , Fig. 15B and Fig. 15C The relationship or correspondence between the regions REG1, REG2 and REG3 and the sub-regions SREG1 and SREG2 in the reference may be similar to that in the reference Figure 5A , Figure 5B and Figure 5C The relationship or correspondence between the described storage bodies, blocks, and pads. For example, when regions REG1, REG2, and REG3 correspond to storage bodies, sub-regions SREG1 and SREG2 may correspond to blocks or pads. For example, when regions REG1, REG2, and REG3 correspond to blocks, sub-regions SREG1 and SREG2 may correspond to pads.

[0158] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a diagram for describing an example of the operation of a memory device.

[0159] refer to Fig.16A and Fig. 16B, shows an example in which the use of a sub-region or area including bonding pads is shielded or blocked when misalignment between bonding pads has occurred at a second level that is an uncompensable level.

[0160] For example, when misalignment between bonding pads included in the first pad MAT1-1 among the plurality of pads MAT1-1, MAT1-2, . . . , MAT1-y included in the first block BLK11 has occurred at the second level which is an uncompensable level, it may be possible as shown in FIG. Fig.16A Shielding or preventing the use of the first pad MAT1-1 as shown, and / or Fig. 16B The use of the first block BLK11 including the first pad MAT1 - 1 is shown to be shielded or blocked.

[0161] refer to Fig. 16C and Fig.16D , shows an example in which, when misalignment between bonding pads has occurred at a second level that is an uncompensable level, a sub-region or a region including bonding pads is repaired to or replaced with another sub-region or another region.

[0162] For example, when misalignment between bonding pads included in a first pad MAT1-1 among a plurality of pads MAT1-1, MAT1-2, . . . , MAT1-y included in the first block BLK11 or BLK12 has occurred at the second level that is an uncompensable level, the first pad MAT1-1 may be repaired to or replaced with a redundant pad RPMAT1 included in the first block BLK12, as shown in FIG. Fig. 16C As shown, and / or the first block BLK11 including the first pad MAT1-1 may be repaired to or replaced with a redundant block RPBLK11 including redundant pads RPMAT1-1, RPMAT1-2, ..., RPMAT1-y, as shown. Fig.16D shown.

[0163] Fig.17A and Fig. 17B is a diagram for describing an example of a memory device.

[0164] refer to Fig.17A In some implementations, the test pad TPD_L1 may be arranged to correspond to the center (or central area) of the first semiconductor layer L1. Although not shown in detail, like the test pad TPD_L1, the test pad TPD_L2 included in the second semiconductor layer L2 may also be arranged to correspond to the center of the second semiconductor layer L2.

[0165] refer to Fig. 17BIn some implementations, the test pad TPD_L1 may be arranged to correspond to at least one edge of the first semiconductor layer L1. Although not shown in detail, like the test pad TPD_L1, the test pad TPD_L2 included in the second semiconductor layer L2 may also be arranged to correspond to at least one edge of the second semiconductor layer L2.

[0166] In some implementations, test operations (e.g., determining or detecting misalignment) using the test pads and the test circuits may be performed during the manufacturing process of the memory device. In some implementations, feedback operations (e.g., shielding, repairing, adjusting operating conditions, etc.) using the test circuits may be performed during actual operation of the memory device.

[0167] Fig.18A , Fig.18B and Fig. 18C is an example of a perspective view of a memory device and a semiconductor device. Figure 1 Duplicate description.

[0168] refer to Fig.18A , the memory device 12 includes a first semiconductor layer L1, a second semiconductor layer L2 and a third semiconductor layer L3. In addition to the memory device 12 also including the third semiconductor layer L3, Fig.18A The example can be compared with Figure 1 The examples are basically the same.

[0169] The first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 are arranged or stacked in the third direction D3. Fig.18A An example is shown in which the first semiconductor layer L1 and the third semiconductor layer L3 are respectively disposed above and below the second semiconductor layer L2, but the implementation is not limited thereto. For example, both the first semiconductor layer L1 and the third semiconductor layer L3 may be disposed above or below the second semiconductor layer L2.

[0170] Like the first semiconductor layer L1, the third semiconductor layer L3 may include a memory cell array MCA and may be referred to as a memory cell region. For example, the memory cell array MCA included in the first semiconductor layer L1 may be referred to as a first memory cell array, and the memory cell array MCA included in the third semiconductor layer L3 may be referred to as a second memory cell array.

[0171] The first bonding pad PD_L1 and the first test pad TPD_L1 of the first semiconductor layer L1 may be connected to the second bonding pad PD1_L2 and the second test pad TPD1_L2 of the second semiconductor layer L2, respectively.

[0172] The third semiconductor layer L3 may further include a third bonding pad PD_L3 and a third test pad TPD_L3. The second semiconductor layer L2 may further include a fourth bonding pad PD2_L2 connected to the third bonding pad PD_L3 and a fourth test pad TPD2_L2 connected to the third test pad TPD_L3. The test circuit TCKT may further receive a second test signal through the third test pad TPD_L3 and the fourth test pad TPD2_L2. Based on the second test signal, the test circuit TCKT may further generate and store a second test result signal indicating a misalignment between the third bonding pad PD_L3 and the fourth bonding pad PD2_L2. Based on the second test result signal, the test circuit TCKT may compensate for the operation of the peripheral circuit PCKT.

[0173] refer to Fig.18B , the memory device 14 includes a first semiconductor layer L1, a second semiconductor layer L2 and a fourth semiconductor layer L4. In addition to the memory device 14 also including the fourth semiconductor layer L4, Fig.18B The example can be compared with Figure 1 The examples are basically the same.

[0174] The first semiconductor layer L1, the second semiconductor layer L2, and the fourth semiconductor layer L4 are arranged or stacked in the third direction D3. Fig.18B An example is shown in which the fourth semiconductor layer L4 and the second semiconductor layer L2 are respectively disposed above and below the first semiconductor layer L1, but the implementation is not limited thereto. For example, both the second semiconductor layer L2 and the fourth semiconductor layer L4 may be disposed above or below the first semiconductor layer L1.

[0175] Like the second semiconductor layer L2, the fourth semiconductor layer L4 may include a peripheral circuit PCKT and may be referred to as a peripheral circuit region. For example, the peripheral circuit PCKT included in the second semiconductor layer L2 may be referred to as a first peripheral circuit, and the peripheral circuit PCKT included in the fourth semiconductor layer L4 may be referred to as a second peripheral circuit.

[0176] The first bonding pad PD1_L1 and the first test pad TPD1_L1 of the first semiconductor layer L1 may be connected to the second bonding pad PD_L2 and the second test pad TPD_L2 of the second semiconductor layer L2, respectively.

[0177] The first semiconductor layer L1 may further include a fifth bonding pad PD2_L1 and a fifth test pad TPD2_L1. The fourth semiconductor layer L4 may further include a sixth bonding pad PD_L4 connected to the fifth bonding pad PD2_L1, a sixth test pad TPD_L4 connected to the fifth test pad TPD2_L1, and a test circuit TCKT. The test circuit TCKT of the fourth semiconductor layer L4 may receive a third test signal through the fifth test pad TPD2_L1 and the sixth test pad TPD_L4. Based on the third test signal, the test circuit TCKT of the fourth semiconductor layer L4 may generate and store a third test result signal indicating a misalignment between the fifth bonding pad PD2_L1 and the sixth bonding pad PD_L4. Based on the third test result signal, the test circuit TCKT of the fourth semiconductor layer L4 may compensate for the operation of the peripheral circuit PCKT of the fourth semiconductor layer L4.

[0178] Although not shown in detail, the memory device may also include four or more semiconductor layers stacked.

[0179] refer to Fig. 18C , the semiconductor device 16 includes a first semiconductor layer LA and a second semiconductor layer LB.

[0180] The first semiconductor layer LA and the second semiconductor layer LB are arranged or stacked in the third direction D3. The first semiconductor layer LA includes a first circuit CKTA, a first bonding pad PD_L1, and a first test pad TPD_L1. The second semiconductor layer LB includes a second circuit CKTB, a second bonding pad PD_L2, a second test pad TPD_L2, and a test circuit TCKT. The first circuit CKTA and the second circuit CKTB can be electrically connected to each other and can interoperate with each other. The first bonding pad PD_L1, the first test pad TPD_L1, the second bonding pad PD_L2, the second test pad TPD_L2, and the test circuit TCKT can be connected to the reference Figure 1 Those described are essentially the same.

[0181] In some implementations, the semiconductor device may include a Fig.18A and Fig.18B The stacked three semiconductor layers are described, but may include stacked four or more semiconductor layers.

[0182] As described above, the structure or configuration for detecting and compensating misalignment between semiconductor layers using a test pad and a test circuit can be applied or adopted not only to a memory device having a COP structure but also to any semiconductor device in which different wafers are connected by a bonding scheme.

[0183] Fig.19A and Fig.19Bis a cross-sectional view of an example of a memory package.

[0184] refer to Fig.19A , the memory package 700 includes a substrate 710 and a plurality of memory chips CHP1 , CHP2 , and CHP3 stacked on the substrate 710 .

[0185] Each of the memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of I / O pads IOPAD. The memory cell layer CLY and the peripheral circuit layer PLY may correspond to reference 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54 Figure 1 The first semiconductor layer L1 and the second semiconductor layer L2 described herein may further include the elements described herein, which are included in the first semiconductor layer L1 and the second semiconductor layer L2, respectively, according to any implementation described herein. Each of the memory chips CHP1 to CHP3 may include a memory device.

[0186] In some implementations, the memory chips CHP1 to CHP3 can be stacked on the substrate 710 so that the surface on which a plurality of I / O pads IOPAD are formed faces upward. In some implementations, relative to each of the memory chips CHP1 to CHP3, a plurality of I / O pads IOPAD can be arranged near one side of the semiconductor substrate. In this way, the memory chips CHP1 to CHP3 can be stacked stepwise, that is, stacked in a stepped shape so that a plurality of I / O pads IOPAD of each memory chip can be exposed. In this stacked state, the memory chips CHP1 to CHP3 can be electrically connected to the substrate 710 by a plurality of bonding wires BW.

[0187] The stacked memory chips CHP1 to CHP3 and the plurality of bonding wires BW may be fixed by a sealing member 740, and an adhesive member 730 may be interposed between the substrate 710 and the memory chips CHP1 to CHP3. Conductive bumps 720 may be formed on the bottom surface of the substrate 710 for electrical connection with external devices.

[0188] refer to Fig.19B , the memory package 800 includes a substrate 810 and a plurality of memory chips CHP1 to CHP3 stacked on the substrate 810. Fig.19A Duplicate description.

[0189] Each of the memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of through silicon vias (TSVs) 830 .

[0190] In some implementations, with respect to each of the memory chips CHP1 to CHP3, a plurality of TSVs 830 may be arranged at the same position in each memory chip. Thus, the memory chips CHP1 to CHP3 may be stacked so that the plurality of TSVs 830 of each memory chip may completely overlap (e.g., the arrangement of the plurality of TSVs 830 may perfectly match in the memory chips CHP1 to CHP3). In this stacked state, the memory chips CHP1 to CHP3 may be electrically connected to each other and to the substrate 810 through the plurality of TSVs 830 and the conductive material 840.

[0191] The conductive bump 820 and the sealing member 850 may be Fig.19A The conductive bumps 720 and the sealing member 740 in FIG. 7 are substantially the same.

[0192] Fig. 20 is a block diagram illustrating an example of a memory system.

[0193] refer to Fig. 20 , the memory system 1000 includes a memory controller 1200 and a memory device 1400. The memory system 1000 may further include a plurality of signal lines 1300 electrically connecting the memory controller 1200 and the memory device 1400.

[0194] The memory device 1400 is controlled by the memory controller 1200. For example, based on a request from a host, the memory controller 1200 may store (e.g., write or program) data into the memory device 1400, or may retrieve (e.g., read or sense) data from the memory device 1400. The memory device 1400 may be a memory device, and may include a test pad TPD and a test circuit TCKT for detecting and compensating for misalignment of two or more semiconductor layers connected by a bonding scheme.

[0195] The plurality of signal lines 1300 may include a control line, a command line, an address line, a data input / output (I / O) line, and a power line. The memory controller 1200 may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device 1400 via the command line, the address line, and the control line, may exchange a data signal DS with the memory device 1400 via the data I / O line, and may transmit a power supply voltage PWR to the memory device 1400 via the power line. Although not shown in detail, the plurality of signal lines 1300 may further include a DQS line for transmitting a data strobe (DQS) signal.

[0196] Although the implementation is described based on the memory packages 700 and 800 including the memory chips CHP1 to CHP3 and the memory system 1000 including the memory device 1400, the implementation is not limited thereto. For example, the implementation may include reference Fig. 18C The described semiconductor devices are implemented in the form of semiconductor packages and semiconductor systems.

[0197] Fig.21 is a flow chart illustrating an example of a method of operating a memory device.

[0198] refer to Fig.21 In a method of operating a memory device, a test signal is received through test pads included in different semiconductor layers and connected to each other (operation S100), a test result signal indicating misalignment between pads included in different semiconductor layers and connected to each other is generated based on the test signal (operation S200), and an operation of a peripheral circuit included in the memory device is compensated based on the test result signal (operation S300). The memory device may be a reference Figures 1 to 18C In some implementations, Fig.21 The method can be described as operating on reference Fig. 18C A method for a semiconductor device is described.

[0199] The implementation can be applied to various electronic devices and systems including memory devices and semiconductor devices. For example, the implementation can be applied to personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0200] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of a sub-combination.

[0201] The foregoing is an illustration of implementations and should not be construed as limiting the implementations. Although some implementations have been described, it will be readily appreciated by those skilled in the art that a variety of modifications may be made in the implementations without substantially departing from the novel teachings and advantages of the implementations. Therefore, all such modifications are intended to be included within the scope of the implementations defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various implementations and should not be construed as being limited to the disclosed implementations, and modifications to the disclosed implementations and other implementations are intended to be included within the scope of the appended claims.

Claims

1. A memory device, comprising: The first semiconductor layer comprises: A memory cell array connected to a plurality of word lines and a plurality of bit lines, the plurality of word lines extending in a first direction, the plurality of bit lines extending in a second direction, the second direction intersecting the first direction, a first bonding pad, and a first test pad; and A second semiconductor layer is arranged in a third direction relative to the first semiconductor layer, the third direction being perpendicular to both the first direction and the second direction, the second semiconductor layer comprising: a peripheral circuit configured to control the memory cell array, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit configured to check a connection state of the first bonding pad and the second bonding pad, Wherein, the test circuit is configured as follows: receiving a first test signal through the first test pad and the second test pad, generating a first test result signal based on the first test signal, and compensating the operation of the peripheral circuit based on the first test result signal, and The first test result signal indicates a first misalignment between the first bonding pad and the second bonding pad.

2. The memory device according to claim 1, in, The first semiconductor layer comprises: a third bonding pad; and The third test pad, Wherein, the second semiconductor layer comprises: a fourth bonding pad connected to the third bonding pad; and a fourth test pad connected to the third test pad, and The test circuit is configured to receive a second test signal through the third test pad and the fourth test pad.

3. The memory device according to claim 2, in, The third test pad and the fourth test pad are connected to the test circuit together with the first test pad and the second test pad, The test circuit is configured to generate the first test result signal based on the first test signal and the second test signal, and The first test result signal further indicates a second misalignment between the third bonding pad and the fourth bonding pad.

4. The memory device according to claim 2, in, The third test pad and the fourth test pad are connected to the test circuit independently of the first test pad and the second test pad, Wherein, the test circuit is configured as follows: generating a second test result signal based on the second test signal, and compensating an operation of the memory cell array or an operation of the peripheral circuit based on the first test result signal and the second test result signal, and The second test result signal indicates a third misalignment between the third bonding pad and the fourth bonding pad.

5. The memory device according to claim 2, in, The memory cell array includes a plurality of memory banks, wherein the first bonding pad, the second bonding pad, the first test pad, and the second test pad are included in a first memory bank among the plurality of memory banks, and The third bonding pad, the fourth bonding pad, the third test pad, and the fourth test pad are included in a second memory bank different from the first memory bank among the plurality of memory banks.

6. The memory device according to claim 2, in, The memory cell array includes a plurality of memory banks, Each of the plurality of storage bodies includes a plurality of blocks. wherein the first bonding pad, the second bonding pad, the first test pad, and the second test pad are included in a first block among the plurality of blocks, and The third bonding pad, the fourth bonding pad, the third test pad, and the fourth test pad are included in a second block different from the first block among the plurality of blocks.

7. The memory device according to claim 2, in, The memory cell array includes a plurality of memory banks, Each of the plurality of storage bodies includes a plurality of blocks. wherein each of the plurality of blocks comprises a plurality of pads, wherein the first bonding pad, the second bonding pad, the first test pad, and the second test pad are included in a first pad among the plurality of pads, and The third bonding pad, the fourth bonding pad, the third test pad, and the fourth test pad are included in a second pad different from the first pad among the plurality of pads.

8. The memory device according to claim 1, wherein: The test circuit comprises: a plurality of sense amplifiers configured to generate the first test result signal based on the first test signal; and The storage circuit is configured to store the first test result signal.

9. The memory device according to claim 8, wherein: Each of the plurality of sense amplifiers is configured to operate based on a corresponding reference voltage of a plurality of reference voltages, and the plurality of reference voltages are different from one another.

10. The memory device according to claim 9, wherein: The plurality of sense amplifiers include: a first sense amplifier configured to generate a first bit of the first test result signal based on a first reference voltage and the first test signal; a second sense amplifier configured to generate a second bit of the first test result signal based on a second reference voltage having a higher voltage level than the first reference voltage and the first test signal; and A third sense amplifier is configured to generate a third bit of the first test result signal based on a third reference voltage and the first test signal, wherein a voltage level of the third reference voltage is higher than the voltage level of the second reference voltage.

11. The memory device according to claim 8, wherein: Each of the plurality of sense amplifiers is configured to operate at a corresponding sense time of a plurality of sense times, and the plurality of sense times are different from one another.

12. The memory device according to claim 11, wherein: The plurality of sense amplifiers include: a first sense amplifier configured to generate a first bit of the first test result signal based on a first reference voltage and the first test signal during a first sensing time; a second sense amplifier configured to generate a second bit of the first test result signal based on the first reference voltage and the first test signal during a second sensing time, the second sensing time being longer than the first sensing time; and A third sense amplifier is configured to generate a third bit of the first test result signal based on the first reference voltage and the first test signal during a third sensing time, the third sensing time being longer than the second sensing time.

13. The memory device according to claim 8, in, The first semiconductor layer comprises: a third bonding pad; and The third test pad, Wherein, the second semiconductor layer comprises: a fourth bonding pad connected to the third bonding pad; and a fourth test pad connected to the third test pad, Wherein, the test circuit comprises: a multiplexer configured to select one of the first test signal and a second test signal, the second test signal being received through the third test pad and the fourth test pad, wherein the plurality of sense amplifiers are configured to generate a second test result signal based on the second test signal, and Wherein, the storage circuit is configured to store the second test result signal.

14. The memory device according to claim 1, in, Based on the first test result signal having a first value, the memory device is configured to determine that the first misalignment between the first bonding pad and the second bonding pad does not occur, wherein, based on the first test result signal having a second value different from the first value, the memory device is configured to determine that the first misalignment between the first bonding pad and the second bonding pad has occurred at a first level, the first level being a compensable level, and Wherein, based on the first test result signal having a third value different from the first value and the second value, the memory device is configured to determine that the first misalignment between the first bonding pad and the second bonding pad has occurred at a second level, and the second level is an uncompensable level.

15. The memory device according to claim 14, wherein: Based on determining that the first misalignment between the first bonding pad and the second bonding pad has occurred at the first level, the test circuit is configured to control operation of the peripheral circuit so that at least one of a sensing time of the memory cell array or an operating voltage supplied to the memory cell array is adjusted.

16. The memory device according to claim 15, in, based on the sensing time of the memory cell array being adjusted, the sensing time of the memory cell array increasing as the degree of the first misalignment between the first bonding pad and the second bonding pad increases, and Wherein, based on the operation voltage supplied to the memory cell array being adjusted, a voltage level of the operation voltage supplied to the memory cell array increases as the degree of the first misalignment between the first bonding pad and the second bonding pad increases.

17. The memory device according to claim 14, in, The memory cell array includes a plurality of sub-regions, and Wherein, based on determining that the first misalignment between the first bonding pad and the second bonding pad has occurred at the second level, use of a first sub-region among the multiple sub-regions including the first bonding pad and the second bonding pad is shielded, or the first sub-region is replaced with a second sub-region among the multiple sub-regions that is different from the first sub-region.

18. The memory device according to claim 14, The memory cell array includes a plurality of regions, in, Each of the plurality of regions includes a plurality of sub-regions, and Wherein, based on determining that the first misalignment between the first bonding pad and the second bonding pad has occurred at the second level, use of a first area among the multiple areas including a first sub-area is shielded, or the first area is replaced with a second area among the multiple areas that is different from the first area, and the first sub-area includes the first bonding pad and the second bonding pad.

19. A memory device comprising: The first semiconductor layer comprises: A memory cell array connected to a plurality of word lines and a plurality of bit lines, the plurality of word lines extending in a first direction, the plurality of bit lines extending in a second direction, the second direction intersecting the first direction, a first bonding pad and a second bonding pad, and a first test pad and a second test pad; and A second semiconductor layer is arranged in a third direction relative to the first semiconductor layer, the third direction being perpendicular to both the first direction and the second direction, the second semiconductor layer comprising: a peripheral circuit configured to control the memory cell array, a third bonding pad and a fourth bonding pad, connected to the first bonding pad and the second bonding pad, respectively, a third test pad and a fourth test pad, connected to the first test pad and the second test pad, respectively; and a test circuit configured to check a connection state between the first bonding pad and the second bonding pad and a connection state between the third bonding pad and the fourth bonding pad, wherein the first bonding pad, the third bonding pad, the first test pad, and the third test pad correspond to a first region of the memory cell array, wherein the second bonding pad, the fourth bonding pad, the second test pad and the fourth test pad correspond to a second region of the memory cell array that is different from the first region, wherein the test circuit is configured to determine that misalignment between the first bonding pad and the third bonding pad has occurred at a first level based on a first test signal provided through the first test pad and the third test pad, the first level being a compensable level, and wherein the test circuit is configured to control the operation of the peripheral circuit so that at least one of a sensing time of the first region of the memory cell array or a first operating voltage supplied to the first region of the memory cell array is adjusted, and wherein the test circuit is configured to determine, based on a second test signal provided through the second test pad and the fourth test pad, that misalignment between the second bonding pad and the fourth bonding pad has occurred at a second level, the second level being an uncompensable level, and wherein the test circuit is configured to mask the use of the second area of ​​the memory cell array, or to replace the second area of ​​the memory cell array with another area of ​​the memory cell array.

20. A semiconductor device comprising: The first semiconductor layer comprises: First circuit, a first bonding pad, and a first test pad; and A second semiconductor layer is disposed in a vertical direction relative to the first semiconductor layer, and the second semiconductor layer includes: a second circuit, interoperable with the first circuit, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit configured to check a connection state of the first bonding pad and the second bonding pad, Wherein, the test circuit is configured as follows: receiving a first test signal through the first test pad and the second test pad, generating a first test result signal based on the first test signal, and compensating operation of the second circuit based on the first test result signal, and The first test result signal indicates a misalignment between the first bonding pad and the second bonding pad.

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