Self-Testing Method of Storage Device, Self-Testing Circuit, Storage Device and System

Abstract

An embodiment of the present invention provides a self-detection method, a self-detection circuit, a storage device and a system for a storage device, relating to the technical field of storage detection. The self-detection method for a storage device includes: after entering the self-detection mode of the storage device, sending a self-detection enable signal to a clock generation module and sending self-detection command data to each distributed detection unit; the clock generation module generating a self-detection clock signal and sending it to the self-detection module and each distributed detection unit; based on the self-detection command data, obtaining test-related data for testing a corresponding target storage module, and performing a fault test on the target storage module based on the test-related data to obtain fault information of the target storage module. The present invention reduces the power consumption of self-detection and improves the self-detection efficiency of the storage module.

Description

Technical Field

[0001] The present invention relates to the technical field of storage detection, and particularly relates to a self-detection method, a self-detection circuit, a storage device and a system for a storage device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in a computer. DRAM is composed of multiple sub-storage modules (Banks), and each Bank is composed of multiple storage cells (Cells) arranged in a row and column array form. The circuit structure of DRAM is complex and has a high integration level. With the advancement of the process technology, problems such as poor contact of the DRAM circuit structure or unqualified storage cells may occur during the manufacturing process, resulting in some storage cells in the DRAM being unable to work properly, and causing data errors when the DRAM performs read and write operations on the failed storage cells.

[0003] In order to avoid the above data errors and improve the yield of DRAM, it is necessary to use fault detection technology to find and mark the faulty storage cells in the DRAM, avoid performing read and write operations on the faulty storage cells in the DRAM, and also facilitate subsequent redundant repair operations. However, the commonly used fault detection schemes for DRAM have problems such as narrow applicability, long detection time, and large detection power consumption overhead. Summary of the Invention

[0004] The purpose of the present invention is to provide a self-detection method, a self-detection circuit, a storage device and a system for a storage device. After the self-detection of the self-detection circuit is completed, the clock generation module no longer generates a self-test clock signal, reducing the power consumption of the self-detection; thus, the internal clock of the storage device will be in the off mode during the normal working state, avoiding increasing the power consumption overhead of the normal read and write of the storage device; realizing the distributed self-detection of multiple storage modules in the storage device in parallel, shortening the self-detection time of the storage device, and improving the self-detection efficiency of the storage module.

[0005] To achieve the above object, the present invention provides a self-detection method for a storage device, which is applied to a self-detection circuit of the storage device. The self-detection circuit includes: a clock generation module, a self-detection module, and a plurality of distributed detection units; the plurality of distributed detection units correspond to a plurality of storage modules in the storage device one by one; the method includes: after entering the self-detection mode of the storage device, the self-detection module sends a self-detection enable signal to the clock generation module, and sends self-detection command data to each of the distributed detection units; after receiving the self-detection enable signal, the clock generation module generates a self-detection clock signal and sends it to the self-detection module and each of the distributed detection units; the distributed detection unit obtains test-related data for testing the corresponding target storage module based on the self-detection command data, and performs a fault test on the target storage module based on the test-related data to obtain the fault information of the target storage module, and sends the fault information to the self-detection module; wherein the test-related data includes test data for writing to the corresponding storage module and the test unit address corresponding to the test data; after the self-detection of all the storage modules is completed, the self-detection module sends a self-detection end signal to the clock generation module to turn off the clock generation module.

[0006] The present invention also provides a self-detection circuit for a storage device. The storage device includes a plurality of storage modules. The self-detection circuit includes: a clock generation module, a self-detection module, and a plurality of distributed detection units; the plurality of distributed detection units correspond to the plurality of storage modules one by one; the self-detection module is configured to send a self-detection enable signal to the clock generation module and send self-detection command data to each of the distributed detection units after entering the self-detection mode of the storage device; the clock generation module is configured to generate a self-detection clock signal and send it to the self-detection module and each of the distributed detection units after receiving the self-detection enable signal; the distributed detection unit is configured to: obtain test-related data for testing the corresponding target storage module based on the self-detection command data, where the test-related data includes test data for writing to the corresponding storage module and the test unit address corresponding to the test data; perform a fault test on the target storage module based on the test-related data to obtain the fault information of the target storage module, and send the fault information to the self-detection module; the self-detection module is further configured to send a self-detection end signal to the clock generation module to turn off the clock generation module after the self-detection of all the storage modules is completed.

[0007] The present invention also provides a storage device, including: a plurality of storage modules and the above self-detection circuit.

[0008] The present invention also provides a storage system, including: a controller and the above-mentioned storage device.

[0009] In one embodiment, the method further includes: the self-detection module sends the fault information of each of the received storage modules to an external controller for the external controller to store the fault information of each of the storage modules; before entering the self-detection mode of the storage device, it further includes: after the storage device is powered on, when the self-detection module does not receive the fault information of the storage modules in the storage device sent by the external controller, enter the self-detection mode; after the storage device is powered on, when the self-detection module receives the fault information of the storage modules sent by the external controller, store the fault information of the storage modules and skip the self-detection.

[0010] In one embodiment, the distributed detection unit obtains test-related data for testing a corresponding target storage module based on the self-test command data, including:

[0011] The distributed detection unit selects a target test item from a plurality of pre-stored test items based on the self-test command data, and the target test item includes test data for writing into the target storage module and the test unit address corresponding to the test data.

[0012] In one embodiment, the self-detection module is further configured to send the fault information of each of the storage modules to an external controller for the external controller to store the fault information of each of the storage modules;

[0013] The self-detection module is configured to, after the storage device is powered on: enter the self-detection mode if it receives a self-detection start signal sent by the external controller;

[0014] If it receives a control instruction indicating external writing of fault information sent by the external controller, skip the self-detection, and obtain and store the fault information of the storage module from the external controller.

[0015] In one embodiment, the distributed detection unit includes: a test command circuit and a comparison circuit;

[0016] The test command circuit is configured to:

[0017] Based on the self-test command data, select a target test item from a plurality of pre-stored test items, and the target test item includes test data for writing into the corresponding target storage module and the test unit address corresponding to the test data;

[0018] Write the test data into the corresponding test unit address in the target storage module, and send the test data to the comparison circuit;

[0019] The comparison circuit is used to read the detection data from the target storage module, compare the detection data with the data corresponding to the same storage unit address in the test data, and record the addresses and fault types of the storage units that malfunction in the storage module; the fault information of the storage module includes: the addresses and fault types of the storage units that malfunction in the storage module.

[0020] In one embodiment, each of the storage modules includes a storage unit array formed by a plurality of storage units; the comparison circuit is used to compare the detection data with the test data row by row according to the storage unit array in the storage module. For each row of the storage unit array, if the data in some of the storage units in all the storage units included in the row of the detection data is inconsistent with the test data, the addresses of the storage units where the data inconsistency occurs and the fault type of single-bit fault are respectively recorded; if the data in all the storage units included in the row of the detection data is inconsistent with the test data, the address of the row and the fault type of word line fault are recorded.

[0021] In one embodiment, the self-detection module includes: a detection status control unit and an address storage unit;

[0022] The detection status control unit is used to send a self-test enable signal to the clock generation module after entering the self-detection mode of the storage device; and send the self-test command data to each of the distributed detection units;

[0023] The distributed detection unit is used to send the fault information to the address storage unit for storage.

[0024] In one embodiment, the clock generation module includes: an enable status register, an oscillation circuit and a frequency multiplier;

[0025] The enable status register is used to activate the oscillation circuit and the frequency multiplier to start working after receiving the self-test enable signal;

[0026] The oscillation circuit is used to generate a clock signal with a preset reference clock frequency and send the clock signal with the reference clock frequency to the frequency multiplier;

[0027] The frequency multiplier is used to amplify the reference clock frequency of the clock signal to obtain the self-test clock signal.

[0028] In one embodiment, the clock generation module further includes: a temperature compensation circuit;

[0029] The enable status register is further configured to activate the temperature compensation circuit to start working after receiving the self-test enable signal;

[0030] The temperature compensation circuit is configured to perform temperature compensation on the oscillation circuit so that the oscillation circuit outputs a clock signal with a stable reference clock frequency.

[0031] In one embodiment, the self-detection circuit further includes: a first multiplexer, a second multiplexer, and a third multiplexer. One input terminal of the first multiplexer is connected to an external clock signal, and the other input terminal is connected to the clock generation module. One input terminal of the second multiplexer is connected to an external command signal, and the other input terminal is connected to the self-detection module. One input terminal of the third multiplexer is connected to an external data signal bus, and the other input terminal is connected to the self-detection module;

[0032] The self-detection module is configured to send self-test enable signals to the first multiplexer, the second multiplexer, and the third multiplexer respectively after entering the self-detection mode of the storage device;

[0033] The clock generation module is configured to send the self-test clock signal to the first multiplexer, and the first multiplexer is configured to select to transmit the self-test clock signal to each of the distributed detection units under the enable of the self-test enable signal;

[0034] The self-detection module is configured to send self-test command data to the second multiplexer, and the second multiplexer is configured to select to send the self-test command data to each of the distributed detection units under the enable of the self-test enable signal;

[0035] The distributed detection unit is configured to send the fault information of the target storage module to the third multiplexer, and the third multiplexer is configured to select to send the fault information of the target storage module to the self-detection module under the enable of the self-test enable signal;

[0036] The first multiplexer is further configured to select to switch the external clock signal to the internal clock source of the storage device when the self-test enable signal is not received. Description of the Drawings

[0037] Figure 1 is a specific flowchart of the self-detection method of the storage device according to the first embodiment of the present invention;

[0038] Figure 2 is a schematic structural diagram of the self-detection circuit for the storage device according to the second embodiment of the present invention;

[0039] Figure 3 It is a schematic structural diagram of the address storage table of the self-detection module in the second embodiment of the present invention;

[0040] Figure 4 It is a schematic diagram of the connection between the storage device and the external controller according to the second embodiment of the present invention;

[0041] Figure 5 It is a schematic structural diagram of the distributed detection unit in the self-detection circuit according to the second embodiment of the present invention;

[0042] Figure 6 It is a schematic structural diagram of the clock generation module in the self-detection circuit according to the second embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of the storage device applied in the self-detection circuit according to the second embodiment of the present invention;

[0044] Figure 8 It is a schematic structural diagram of a stacked memory according to the third embodiment of the present invention. Detailed implementation manners

[0045] The following will describe each embodiment of the present invention in detail with reference to the accompanying drawings to more clearly understand the purpose, features and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not limitations on the scope of the present invention, but only to illustrate the essential spirit of the technical solution of the present invention.

[0046] In the following description, certain specific details are set forth for the purpose of explaining various disclosed embodiments to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other instances, well-known devices, structures and techniques associated with the present application may not be shown or described in detail so as not to unnecessarily obscure the description of the embodiments.

[0047] Unless the context requires otherwise, throughout the specification and claims, the words "comprise" and its variations, such as "comprising" and "having" should be understood in an open, inclusive sense, i.e., should be interpreted as "including, but not limited to".

[0048] References to "one embodiment" or "an embodiment" in the course of the specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0049] As used in this specification and the appended claims, the singular forms "a" and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally used in its inclusive sense of "and / or" unless the context clearly dictates otherwise.

[0050] In the following description, in order to clearly show the structure and working mode of the present invention, many directional terms will be used for description. However, terms such as "front", "rear", "left", "right", "outer", "inner", "outward", "inward", "up", "down", etc. should be understood as convenient terms and should not be understood as restrictive terms.

[0051] The first embodiment of the present invention relates to a self-detection method for a storage device, which is applied to a self-detection circuit of the storage device. The self-detection circuit includes: a clock generation module, a self-detection module, and a plurality of distributed detection units; the plurality of distributed detection units correspond one-to-one with a plurality of storage modules in the storage device.

[0052] The specific process of the self-detection method of the storage device in this embodiment is as Figure 1 shown.

[0053] Step 101, after entering the self-detection mode of the storage device, the self-detection module sends a self-detection enable signal to the clock generation module and sends self-detection command data to each distributed detection unit.

[0054] Step 102, after receiving the self-detection enable signal, the clock generation module generates a self-detection clock signal and sends it to the self-detection module and each distributed detection unit.

[0055] Step 103, the distributed detection unit obtains test-related data for testing the corresponding target storage module based on the self-detection command data, and performs a fault test on the target storage module based on the test-related data to obtain the fault information of the target storage module, and sends the fault information to the self-detection module; wherein the test-related data includes test data for writing to the corresponding storage module and the test unit address corresponding to the test data.

[0056] Step 104, after the self-detection of all storage modules is completed, the self-detection module sends a self-detection end signal to the clock generation module to turn off the clock generation module.

[0057] Furthermore, the self-detection method further includes: the self-detection module sends the fault information of each received storage module to an external controller for the external controller to store the fault information of each storage module.

[0058] Before entering the self - test mode of the storage device, it further includes: after the storage device is powered on, when the self - test module does not receive the fault information of the storage module in the storage device sent by the external controller, enter the self - test mode; after the storage device is powered on, when the self - test module receives the fault information of the storage module sent by the external controller, store the fault information of the storage module and skip the self - test.

[0059] The distributed detection unit obtains test - related data for testing the corresponding target storage module based on the self - test command data, including: the distributed detection unit selects a target test item from multiple test items based on the self - test command data, and the target test item includes test data for writing to the corresponding storage module and the test unit address corresponding to the test data.

[0060] In this embodiment, a self - test circuit is configured in the storage device. After the storage device enters the self - test mode, the self - test module sends a self - test enable signal to the clock generation module. When the clock generation module receives the self - test enable signal, it can generate a self - test clock signal. The self - test clock signal is sent to the self - test module and the distributed detection unit as an internal clock, so that precise delay can be provided for the self - test. And after the self - test is completed, the clock generation module no longer generates the self - test clock signal, reducing the power consumption of the self - test; thus, when the storage device is in the normal working state, the internal clock will be in the off mode, avoiding increasing the power consumption overhead of the normal read and write of the storage device.

[0061] The self - test circuit includes distributed detection units corresponding one - to - one with multiple storage modules in the storage device. During the self - test process, each distributed detection unit can respectively perform fault tests on the corresponding storage module, record the fault information of each storage module and send it to the self - test module; that is to say, an independent distributed detection unit is equipped for each storage module. Thus, the self - test module only needs to send the self - test command data to each distributed detection unit respectively, and each distributed detection unit independently completes the distributed self - test, realizing the distributed self - test of multiple storage modules in parallel, shortening the self - test time of the storage device and improving the self - test efficiency of the storage module.

[0062] Moreover, during the self - test process, signals such as clock, control, and test are all sourced from within the storage device. Thus, even after the storage device has left the factory, the user can perform the self - test of the storage device.

[0063] The second embodiment of the present invention relates to a self - test circuit for a storage device. Please refer to Figure 2, the storage device includes multiple memory modules (BANKs). In the figure, the number of memory modules is P (P is an integer greater than 1), that is, BANK1 to BANKP; each memory module includes a memory cell array formed by multiple memory cells (Cells), such as an array with m rows and n columns, as well as a row decoder and a column decoder. The row decoder is connected to all rows of the memory cells, and the column decoder is connected to all columns of the memory cell array. Each memory cell (Cell) includes a capacitor and a transistor. The applicable scenarios of the storage device are, for example, assembled on a test computer before leaving the factory, or assembled on a personal computer by a personal user.

[0064] The storage device is, for example, a dynamic random access memory DRAM. Its basic working method is as follows: The opening or closing of the transistor is controlled by a voltage signal input to the word line (a row of the memory cell array) of the memory cell array, and then the data information stored in the capacitor of the memory cell is read through the bit line (a column of the memory cell array), or the data information is written into the capacitor of the memory cell through the bit line for storage; each memory cell represents a binary bit (bit) as 1 or 0 by the amount of charge stored in the capacitor.

[0065] The self-detection circuit includes: a clock generation module 1, a self-detection module 2, and multiple distributed detection units 3; the multiple distributed detection units 3 correspond one-to-one with the multiple memory modules, that is, the number of distributed detection units 3 is also P. The P distributed detection units 3 correspond one-to-one and are communicatively connected with the P memory modules (BANK1 to BANKP). The self-detection module (MBIST module) 2 is communicatively connected to each distributed detection unit 3 and the clock generation module 1 respectively. Among them, two signal transmission lines are formed between the self-detection module 2 and the multiple distributed detection units 3. One is an instruction transmission line and the other is a data transmission line. For example, the multiple distributed detection units 3 are respectively connected to the instruction transmission bus CMD_BUS and the data transmission bus DATA _BUS. The self-detection module 2 can be directly or indirectly connected to the instruction transmission bus CMD_BUS and the data transmission bus DATA _BUS respectively.

[0066] The following details the self-detection process after the storage device is powered on, as follows:

[0067] After the self - detection module 2 enters the self - detection mode of the storage device, it sends a self - test enable signal MBIST_EN to the clock generation module 1 and sends self - test command data to each distributed detection unit 3. Among them, the self - test command data includes: a self - test trigger signal MBIST_TRIG and a self - test command set CMDSET. After the self - detection module 2 enters the self - detection mode, it first sends the self - test trigger signal MBIST_TRIG to the instruction transmission bus CMD_BUS, and then sends the self - test command set CMDSET to the instruction transmission bus CMD_BUS. Thus, the self - test trigger signal MBIST_TRIG and the self - test command set CMDSET can be broadcast to each distributed detection unit 3.

[0068] After the clock generation module 1 receives the self - test enable signal MBIST_EN, it generates a self - test clock signal MBIST_CLK and sends it to the self - detection module 2 and each distributed detection unit 3. Thus, during the self - detection process, the self - detection module 2 and the distributed detection unit 3 use this self - test clock signal MBIST_CLK as the internal clock for self - detection, providing the precise delay required for reading / writing / data refreshing during the subsequent self - detection process, and also providing the working clock for the self - detection module.

[0069] For each distributed detection unit 3 corresponding to each storage module, based on the self - test command data, test - related data for testing the corresponding target storage module is obtained. The test - related data includes test data for writing to the corresponding target storage module and the test unit address corresponding to the test data; based on the test - related data, a fault test is performed on the target storage module to obtain the fault information of the target storage module, and the fault information is sent to the self - detection module. Among them, the fault information of the target storage module includes the address and fault type of the storage unit that has a fault in the target storage module; for each distributed detection unit 3, if the corresponding target storage module has no fault, there is no need to send fault information to the self - detection module 2.

[0070] The self - detection module 2 is also used to send a self - test end signal to the clock generation module 1 after the self - detection of all storage modules is completed, so as to turn off the clock generation module 1. That is to say, after the self - detection of all storage modules in the storage device is completed, the self - detection module 2 can receive the fault information sent by any distributed detection unit 3 for storage, and send a self - test end signal to the clock generation module 1 to turn off the clock generation module 1. The turned - off clock generation module 1 stops outputting the self - test clock signal. At this time, the storage device can use the external clock signal as the clock source to perform normal reading and writing of the storage device.

[0071] After completing the above process, the self - detection module 2 exits the self - detection mode.

[0072] In one example, the self-detection module 2 includes a detection status control unit 21 and an address storage unit 22. The detection status control unit 21 is communicatively connected to each distributed detection unit 3 respectively, and the address storage unit 22 is communicatively connected to each distributed detection unit 3.

[0073] The detection status control unit 21 is configured to send a self-test enable signal to the clock generation module 1 after entering the self-detection mode of the storage device; and send self-test command data to each distributed detection unit 3.

[0074] The distributed detection unit 3 is configured to send fault information to the address storage unit 22 for storage. The address storage unit 22 is an address storage table (AST). Each distributed detection unit 3 sends the fault information of the corresponding target storage module to the address storage table (AST) for storage through the data transmission bus DATA _BUS.

[0075] The structure of the address storage table is as Figure 3 shown. The address storage table includes multiple storage table entries. Each storage table entry contains 2 fault information identification bits and 2 fault addresses. The 2-bit fault information identification bit represents the fault type. When the fault information identification bit is 01, it indicates a single storage unit fault. At this time, the row address (Row_ADDR) and bit address (Col_ADDR) of the faulty unit are stored in the fault address respectively; when the fault information identification bit is 00, it indicates a word line fault of the storage cell array. At this time, the row start address (Row_ADDR) and row end address (Row_ADDR) of the faulty word line are stored in the fault address respectively; when the fault information identification bit is 00, it indicates a bit line fault of the storage cell array. At this time, the column start address (Col_ADDR) and column end address (Col_ADDR) of the faulty word line are stored in the fault address respectively; to save storage space, each storage table entry can also store two different word line faults and / or bit line faults at the same time, and the address of one of the storage units in the row where the word line is located or the column where the bit line is located can be used for identification.

[0076] In one example, the storage device is also connected to an external controller. The external controller can be a processor of a detection computer dedicated to detecting the storage device, or a processor of a user's personal computer.

[0077] The self-detection module 2 is also configured to send the fault information of each storage module to the external controller for the external controller to store the fault information of each storage module.

[0078] The self-detection module 2 is used after the storage device is powered on: when receiving a self-detection start signal sent by an external controller, it enters the self-detection mode; when receiving a control instruction indicating external writing of fault information sent by the external controller, it skips the self-detection and obtains and stores the fault information of the storage module from the external controller.

[0079] Specifically, please refer to Figure 4 , the external controller may include: a fault detection control unit, a memory controller (MC), and a fault external storage table that are communicatively connected in sequence. The fault detection control unit is communicatively connected to the fault external storage table; the memory controller is communicatively connected to the detection status control unit 21 in the self-detection module 2 through an external instruction transmission bus CMD1, and the memory controller is communicatively connected to the address storage unit 22 through an external data transmission bus DQ1.

[0080] When the self-detection module 2 finishes self-detection each time, it sends the received fault information of each storage module to the memory controller through the external data transmission bus, so that the memory controller stores the fault information of each storage module in the fault external storage table. The specific structure of the fault external storage table is similar to the aforementioned address storage table and will not be elaborated here.

[0081] After the storage device is powered on and started each time, the fault detection control unit in the external controller queries whether the fault external storage table stores the fault information of the storage module in the storage device;

[0082] If the fault detection control unit determines through query that the fault external storage table does not store the fault information of the storage module in the storage device, the fault detection control unit uses the external instruction transmission bus CMD1 through the memory controller to send a self-detection start signal to the detection status control unit 21, triggering the detection status control unit 21 to enter the self-detection mode.

[0083] If the fault detection control unit determines through query that the fault external storage table already stores the fault information of the storage module in the storage device, the fault detection control unit uses the external instruction transmission bus CMD1 through the memory controller to send a control instruction indicating external writing of fault information to the detection status control unit 21. After receiving the control instruction, the detection status control unit 21 skips the self-detection link and reads the fault information of the storage device from the fault external storage table through the external data transmission bus DQ1 and stores it in the address storage unit 22.

[0084] Among them, the detection status control unit 21 can perform timing after the storage device is powered on. If it receives a self-detection start signal sent by the memory controller before the timing reaches the preset duration, it triggers to enter the self-detection mode; or if it still does not receive a self-detection start signal sent by the memory controller when the timing reaches the preset duration, it triggers to enter the self-detection mode.

[0085] As described above, the present invention proposes an external recording mechanism for the failure information of a storage device, which can transmit and store the failure information of the storage device obtained by detection in an external controller after the storage device completes self-detection, so that the failure information of the storage device can be directly read from the external controller when the storage device is powered on next time, avoiding repeated self-detection of the storage device every time it is powered on.

[0086] In one example, please refer to Figure 5 , the distributed detection unit 3 includes: a test command circuit 31 and a comparison circuit 32 connected to each other; the test command circuit 31 is connected to the instruction transmission bus CMD_BUS, the comparison circuit 32 is connected to the data transmission bus DATA _BUS, the test command circuit 31 is connected to the row decoder and column decoder of the corresponding target storage module, and the comparison circuit 32 is connected to the column decoder of the corresponding target storage module.

[0087] For each distributed detection unit 3, the test command circuit 31 of the distributed detection unit 3 selects a target test item from a plurality of pre-stored test items based on the self-test command data. The target test item includes test data for writing to the corresponding target storage module and the test unit address corresponding to the test data; subsequently, the test data is written to the corresponding test unit address in the target storage module, and the test data is sent to the comparison circuit. The comparison circuit is used to read the detection data from the target storage module, compare the detection data with the data at the same address in the test data, and store the addresses and failure types of the storage units that fail in the storage module; the failure information of the storage module includes: the addresses and failure types of the storage units that fail in the storage module.

[0088] Specifically, the test command circuit 31 can be a state machine, and a plurality of test item files required for testing are pre-stored in the state machine register. Each test item file includes: the test data used for testing and the test unit address of the storage cell array corresponding to the test data.

[0089] After receiving the self - test trigger signal MBIST_TRIG on the instruction transfer bus CMD_BUS, the test command circuit 31 triggers the test of the target storage module; the self - test command set CMDSET received on the instruction transfer bus CMD_BUS includes test instructions (such as start detection instruction, stop detection instruction) and the selected test items for the test. The test command circuit 31 selects the target test item from multiple pre - stored test items, obtains the test data to be written into the target storage module and the test unit addresses of the storage unit array corresponding to the test data. The test unit addresses corresponding to the test data include the word line address and the bit line address of the storage unit array, so that the data to be written into each storage unit in the storage unit array can be located, and then the test data can be sequentially written into the corresponding storage units in the storage module.

[0090] Among them, the test data can be selected from multiple pre - set test item data in the test command circuit 31. In one example, the test data included in the test item data is, for example, a test pattern. The test pattern can include various test patterns for detecting specific faults and structural defects and has a high fault coverage rate; the test patterns can include random test patterns, pseudo - random test patterns (similar to random test patterns except that their test vector sequences are repeated), or test patterns for parallel bit test (PBT) including the same data (for example, "0" or "1").

[0091] The corresponding test command circuit 31 also sends the test data written into each storage unit to the comparison circuit 32. After a specific time interval, the comparison circuit 32 reads data from each storage unit in the storage module to obtain the detection data; the specific time interval is related to the type of storage device. For example, if the storage device is DRAM, the specific time interval is usually set to just reach the refresh time interval specified by the DRAM standard.

[0092] Subsequently, the comparison circuit 32 uses the test data sent by the test command circuit 31 as the reference data, compares the test data with the detection data read from the storage unit array, compares the data with the same storage unit address in the detection data and the test data, and records the addresses and fault types of the storage units with faults in the storage module; the fault information of the storage module includes: the addresses and fault types of each storage unit with faults in the storage module.

[0093] For each memory cell, if the test data written to the memory cell is consistent with the detection data read from the memory cell, it indicates that the memory cell has no fault; if the test data written to the memory cell is inconsistent with the detection data read from the memory cell, it indicates that the memory cell has a fault. Specifically: The detection data and the test data are compared row by row according to the memory cell array in the memory module. For each row of the memory cell array, if the detection data and the test data are inconsistent in the data of some memory cells among all the memory cells included in this row, the addresses of the memory cells where the data inconsistency occurs and the fault type of single-bit fault are respectively recorded. The address of the memory cell where the data inconsistency occurs includes the row address of the row where the memory cell is located and the column address of the column where the memory cell is located; if the detection data and the test data are inconsistent in the data of all the memory cells included in this row, the address of this row and the fault type of word-line fault are recorded; if the detection data and the test data are consistent in the data of all the memory cells included in this row, it indicates that the memory cells in this row have no fault. In an example, if the detection data and the test data are inconsistent in the data of all the memory cells included in a certain column of the memory cell array, the address of this column and the fault type of bit-line fault are recorded.

[0094] In an example, the comparison circuit 32 is, for example, an exclusive OR (XOR) logic circuit or an exclusive NOR (XNOR) logic circuit; for each memory cell in the memory module, if the logical states of the detection data and the test data are consistent, the comparison circuit 32 can output a comparison signal, such as a logical low level, to indicate that the memory cell has no fault; on the contrary, if the logical states of the detection data and the test data are inconsistent, the comparison circuit 32 can output a comparison signal, such as a logical high level, indicating that the memory cell has a fault.

[0095] In addition, the area overhead of the distributed detection unit separately configured for each memory module in this embodiment is relatively small compared to a single memory module and will not increase the area overhead of the memory module.

[0096] In one embodiment, please refer to Figure 6 , the clock generation module 1 includes: an enable status register 11, an oscillation circuit 12 and a frequency multiplier 13; further, the clock generation module 1 further includes a temperature compensation circuit 14. Among them, the enable status register 11 is electrically connected to the oscillation circuit 12, the frequency multiplier 13 and the temperature compensation circuit 14 respectively, the oscillation circuit 12 is electrically connected to the frequency multiplier 13, and the temperature compensation circuit 14 is electrically connected to the oscillation circuit 12.

[0097] The enable status register 11 is used to activate the oscillation circuit 12, the frequency multiplier 13, and the temperature compensation circuit 14 to start working after receiving the self-test enable signal. Specifically, the enable status register 11 is connected to the self-detection module 2, and the self-detection module 2 sends a high-level self-test enable signal to the enable status register 11, and the enable status register 11 activates the oscillation circuit 12, the frequency multiplier 13, and the temperature compensation circuit 14 to start working.

[0098] The oscillation circuit 12 is used to generate a clock signal with a preset reference clock frequency and send the clock signal with the reference clock frequency to the frequency multiplier 13. Among them, the oscillation circuit 12 can be composed of an inverter chain and can generate a clock signal with a preset reference clock frequency.

[0099] The frequency multiplier 13 is used to amplify the reference clock frequency of the clock signal to obtain a self-test clock signal. Among them, the reference clock frequency of the clock signal sent by the oscillation circuit 12 is less than the operating frequency of the core device of the storage device (DRAM). Therefore, in order to provide the high-frequency clock frequency required by the core device of the storage device (for example, when the storage device is DRAM, the highest for DDR / DDR2 / DDR3 / DDR4 is 200M, and the highest for DDR5 / LPDDR5 is 400M), the frequency multiplier 13 can amplify the reference clock frequency of the clock signal sent by the oscillation circuit 12 to obtain a self-test clock signal that can meet the high-frequency clock frequency required by the core device of the storage device. The frequency multiplier 13 outputs the self-test clock signal to the self-detection module 2 and each distributed detection unit 3.

[0100] The temperature compensation circuit 14 is used to perform temperature compensation on the oscillation circuit 12 so that the oscillation circuit 12 outputs a clock signal with a stable reference clock frequency, thereby avoiding the influence of temperature on the read and write timing of the storage device.

[0101] After the self-detection is completed, the self-detection module 2 sends a low-level self-test end signal to the enable status register 11, and the oscillation circuit 12, the frequency multiplier 13, and the temperature compensation circuit 14 stop working, and the clock generation module 1 no longer outputs the self-test clock signal, reducing the power consumption overhead.

[0102] In this embodiment, please refer to Figure 7 , the self-detection circuit further includes: a first multiplexer MUX1, a second multiplexer MUX2, a third multiplexer MUX3, and a fourth multiplexer MUX4.

[0103] One input terminal of the first multiplexer MUX1 is connected to the external clock signal CLK, and the other input terminal is connected to the clock generation module 1. The output terminal of the first multiplexer MUX1 is respectively connected to the self-detection module 2 and each distributed detection unit 3;

[0104] One input terminal of the second multiplexer MUX2 is connected to an external command signal source CMD / ADDR through an external command bus, and another input terminal is connected to the self-detection module 2. The output terminal of the second multiplexer MUX2 is connected to the test command circuit 31 of the distributed detection unit 3 through an instruction transmission bus CMD_BUS;

[0105] One input terminal of the third multiplexer MUX3 is connected to an external data signal source DQ through an external data signal bus, and another input terminal is connected to the self-detection module 2. The output terminal of the third multiplexer MUX3 is connected to the comparison circuit 32 of the distributed detection unit 3. Specifically, one input terminal of the third multiplexer MUX3 is connected to the fourth multiplexer MUX4, another input terminal of the fourth multiplexer MUX4 is connected to the self-detection module 2, and the output terminal of the fourth multiplexer MUX4 is connected to the external data signal source DQ through an external data signal bus.

[0106] The self-detection module 2 is also respectively connected to the control terminals of the first multiplexer MUX1, the second multiplexer MUX2, the third multiplexer MUX3, and the fourth multiplexer MUX4;

[0107] The self-detection module 2 is used to send a self-test enable signal MBIST_EN to the control terminals of the first multiplexer MUX1, the second multiplexer MUX2, the third multiplexer MUX3, and the fourth multiplexer MUX4 respectively after entering the self-detection mode of the storage device.

[0108] The clock generation module 1 is used to send a self-test clock signal MBIST_CLK to the first multiplexer MUX1. The first multiplexer switches the clock source to the internal self-test clock signal under the enable of the self-test enable signal MBIST_EN, and selects to transmit the self-test clock signal MBIST_CLK to each distributed detection unit 3; the clock generation module 1 also directly sends the self-test clock signal MBIST_CLK to the self-detection module 2.

[0109] The self-detection module 2 is also used to send self-test command data to the second multiplexer MUX2; the second multiplexer MUX2 switches the command signal source to the self-test command data under the enable of the self-test enable signal MBIST_EN, and selects to send the self-test command data to the test command circuit 31 of each distributed detection unit 3 through the instruction transmission bus CMD_BUS.

[0110] The distributed detection unit 3 is used to send the fault information of the target storage module to the third multiplexer MUX3. Under the enablement of the self-test enable signal MBIST_EN, the third multiplexer MUX3 selects to send the fault information of the target storage module to the address storage unit 22 of the self-detection module 2 for storage.

[0111] Further, the data signal source of the third multiplexer MUX3 is switched to the self-test data input by the self-detection module 2. That is, the self-detection module 2 sends the self-test data to the distributed detection unit 3 through the third multiplexer MUX3. Thus, the distributed detection unit 3 can use the latest test data (self-test data) to test the target storage module.

[0112] The self-detection module 2 sends the fault information of each storage module in the storage device to the fourth multiplexer MUX4. Under the enablement of the self-test enable signal MBIST_EN, the fourth multiplexer MUX4 switches the signal output to the external data signal source DQ to the fault information of the storage module input by the self-detection module 2, that is, selects to send the fault information of each storage module to the external controller for storage.

[0113] Thus, by adding four multiplexers in the storage device, the switching of the internal clock signal and the external clock signal, the internal instruction signal and the external instruction signal, and the internal data signal source and the external data signal source is realized.

[0114] The third embodiment of the present invention relates to a storage device, including: a plurality of storage modules and the self-detection circuit in the second embodiment.

[0115] Wherein, the storage device can be any one of volatile storage devices: synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics double data rate SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, wide input / output (I / O) DRAM, high bandwidth memory (HBM), and hybrid memory cube (HMC). The storage modules in the storage device can be implemented by unbuffered dual in-line memory modules (UDIMM), registered DIMM (RDIMM), low load DIMM (LRDIMM), fully buffered DIMM (FBDIMM), small outline DIMM (SODIMM), etc. In addition, the storage device can also be any one of non-volatile storage devices such as: flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0116] In other embodiments, please refer to Figure 8 , the storage device in this embodiment may further include a first group of dies and a second group of dies. The first group of dies includes at least one buffer die, and the second group of dies includes K memory dies, where K is an integer greater than 1; the second group of dies is stacked on top of the first group of dies, and each memory die in the second die exchanges control signals and / or data with the first group of dies through a plurality of through-silicon via (TSV) lines. For example, the TSV lines are respectively electrically connected to the micro-bumps MCB formed between the K memory dies, and each memory die includes at least one memory module, and the memory module includes a memory cell array, and each memory cell includes an access transistor and a memory capacitor.

[0117] The buffer die can be configured with a clock generation module and a self-detection module in the self-detection circuit. The clock generation module generates an internal high-speed clock (i.e., a self-test clock signal) required for self-detection. The self-detection module may include a detection status control unit and an address storage table (AST). A plurality of distributed detection units corresponding one-to-one to the memory modules are provided on each memory die; among them, the address storage table is used to record fault information (fault type and fault address), or is used to store fault information read in from an external controller.

[0118] The detection status control unit sends a self-detection test command and guides the distributed detection units in the K memory dies to perform fault tests.

[0119] Among them, the specific functions of the self-detection module, the clock generation module, and the distributed detection units are similar to those in the first embodiment. For details, please refer to the first embodiment and will not be elaborated here.

[0120] Since the first, second, and this embodiment correspond to each other, this embodiment can be implemented in cooperation with the first and second embodiments. The relevant technical details mentioned in the first and second embodiments are still valid in this embodiment, and the technical effects achievable in the first and second embodiments can also be achieved in this embodiment. To avoid repetition, they will not be elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the first and second embodiments.

[0121] The fourth embodiment of the present invention relates to a storage system, including: a controller and the storage device of the third embodiment. The controller therein is the external controller connected to the storage device.

[0122] The preferred embodiments of the present invention have been described in detail above. However, it should be understood that if necessary, aspects of the embodiments can be modified to adopt aspects, features, and concepts of various patents, applications, and publications to provide additional embodiments.

[0123] In view of the foregoing detailed description, these and other variations can be made to the embodiments. In general, in the claims, the terms used should not be construed as limited to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments together with the full scope of equivalents to which these claims are entitled.

Claims

1. A self-detection method for a storage device, characterized in that, Applied to the self - detection circuit included in a storage device, the self - detection circuit includes: a clock generation module, a self - detection module, and multiple distributed detection units; the multiple distributed detection units correspond one - to - one with multiple storage modules in the storage device; the method includes: After the storage device is powered on: If a self - detection start signal sent by an external controller is received, enter the self - detection mode; if a control instruction indicating external writing of fault information sent by the external controller is received, skip self - detection, and obtain and store the fault information of the storage module from the external controller; After entering the self - detection mode of the storage device, the self - detection module sends a self - detection enable signal to the clock generation module, and sends self - detection command data to each of the distributed detection units; After receiving the self - detection enable signal, the clock generation module generates a self - detection clock signal and sends it to the self - detection module and each of the distributed detection units; The distributed detection unit obtains test - related data for testing the corresponding target storage module based on the self - detection command data, and performs a fault test on the target storage module based on the test - related data to obtain the fault information of the target storage module, and sends the fault information to the self - detection module; wherein the test - related data includes test data for writing to the corresponding storage module and the test unit address corresponding to the test data; After self - detection of all the storage modules is completed, the self - detection module sends a self - detection end signal to the clock generation module to turn off the clock generation module; The self - detection module sends the fault information of each storage module to the external controller for the external controller to store the fault information of each storage module; Use an external clock signal as the clock source for data reading and writing of the storage device.

2. A self-detection circuit for a storage device, characterized in that, The storage device includes multiple storage modules, and the self - detection circuit includes: a clock generation module, a self - detection module, and multiple distributed detection units; the multiple distributed detection units correspond one - to - one with the multiple storage modules; The self - detection module is used for: after the storage device is powered on: if a self - detection start signal sent by an external controller is received, enter the self - detection mode; if a control instruction indicating external writing of fault information sent by the external controller is received, skip self - detection, and obtain and store the fault information of the storage module from the external controller; The self - detection module is used for, after entering the self - detection mode of the storage device, sending a self - detection enable signal to the clock generation module, and sending self - detection command data to each of the distributed detection units; The clock generation module is used for, after receiving the self - detection enable signal, generating a self - detection clock signal and sending it to the self - detection module and each of the distributed detection units; The distributed detection unit is used for: Based on the self-check command data, obtain test-related data for testing the corresponding target storage module, where the test-related data includes test data for writing to the corresponding storage module and the test unit address corresponding to the test data; Perform a fault test on the target storage module based on the test-related data, obtain the fault information of the target storage module, and send the fault information to the self-detection module; The self-detection module is further configured to send a self-check end signal to the clock generation module to turn off the clock generation module after the self-check of all the storage modules is completed; The self-detection module is further configured to send the fault information of each storage module to the external controller for the external controller to store the fault information of each storage module; After turning off the clock generation module, use the external clock signal as the clock source to perform data reading and writing of the storage device.

3. The self-test circuit for a storage device according to claim 2, wherein, The distributed detection unit includes: a test command circuit and a comparison circuit; The test command circuit is configured to: Based on the self-check command data, select a target test item from a plurality of pre-stored test items, where the target test item includes test data for writing to the corresponding target storage module and the test unit address corresponding to the test data; Write the test data to the corresponding test unit address in the target storage module and send the test data to the comparison circuit; The comparison circuit is configured to read the detection data from the target storage module, compare the detection data with the data of the same storage unit address in the test data, and record the address and fault type of the storage unit that fails in the storage module; the fault information of the storage module includes: the address and fault type of each storage unit that fails in the storage module.

4. The self-detection circuit for a storage device according to claim 3, wherein, Each storage module includes a storage unit array formed by a plurality of storage units; The comparison circuit is configured to compare the detection data with the test data row by row according to the storage unit array in the storage module. For each row of the storage unit array, if the data in some of the storage units included in the row of the detection data and the test data is inconsistent, record the addresses of the storage units where the data is inconsistent and the fault type as a single-bit fault respectively; if the data in all the storage units included in the row of the detection data and the test data is inconsistent, record the address of the row and the fault type as a word line fault.

5. The self-test circuit for a storage device according to claim 2, characterized in that, The self-detection module includes: a detection status control unit and an address storage unit; The detection status control unit is configured to send a self-check enable signal to the clock generation module after entering the self-check mode of the storage device; and send the self-check command data to each distributed detection unit; The distributed detection unit is configured to send the fault information to the address storage unit for storage.

6. The self-detection circuit for a storage device according to claim 2, wherein The clock generation module includes: an enable status register, an oscillation circuit, and a frequency multiplier; The enable status register is used to activate the oscillation circuit and the frequency multiplier to start working after receiving the self-test enable signal; The oscillation circuit is used to generate a clock signal with a preset reference clock frequency and send the clock signal with the reference clock frequency to the frequency multiplier; The frequency multiplier is used to amplify the reference clock frequency of the clock signal to obtain the self-test clock signal.

7. The self-detection circuit for a storage device according to claim 2, wherein The self-detection circuit further includes: a first multiplexer, a second multiplexer, and a third multiplexer. One input terminal of the first multiplexer is connected to an external clock signal, and the other input terminal is connected to the clock generation module. One input terminal of the second multiplexer is connected to an external command signal, and the other input terminal is connected to the self-detection module. One input terminal of the third multiplexer is connected to an external data signal bus, and the other input terminal is connected to the self-detection module; The self-detection module is used to send self-test enable signals to the first multiplexer, the second multiplexer, and the third multiplexer respectively after entering the self-detection mode of the storage device; The clock generation module is used to send the self-test clock signal to the first multiplexer, and the first multiplexer, under the enable of the self-test enable signal, selects to transmit the self-test clock signal to each of the distributed detection units; The self-detection module is used to send self-test command data to the second multiplexer, and the second multiplexer, under the enable of the self-test enable signal, selects to send the self-test command data to each of the distributed detection units; The distributed detection unit is used to send the fault information of the target storage module to the third multiplexer, and the third multiplexer, under the enable of the self-test enable signal, selects to send the fault information of the target storage module to the self-detection module; The first multiplexer is further used to select to switch the external clock signal to the internal clock source of the storage device when the self-test enable signal is not received.

8. A storage device, characterized in that, Comprising: A plurality of storage modules and the self-detection circuit according to any one of claims 2 to 7.

9. A storage system, characterized in that, Comprising: A controller and the storage device according to claim 8.

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