Storage chip testing method and device, computer equipment and storage medium

Abstract

The invention provides a memory chip testing method and device, computer equipment and a storage medium, and relates to the technical field of semiconductors. The method comprises the steps that M times of collapse loop tests are executed on a storage chip, M is a positive integer larger than 0, and each collapse loop test comprises the following steps that N times of write operation are executed on the storage chip, and N is a positive integer larger than 1; under the condition that the N times of write operations are executed, verifying the storage chip to obtain a verification result; and obtaining a collapse test result based on the M verification results of the memory chip after the collapse loop test. According to the method and the device, the collapse test result is obtained based on the M verification results after M collapse loop tests are executed, so that the probability that the memory chip is misjudged as a failure product due to slight poor contact can be reduced. Besides, after N write operations are executed, the storage chip is verified, so that the verification frequency in the collapse test process is reduced, the collapse test duration is shortened, and the test cost is reduced.

Description

Background Art

[0002] In the field of semiconductor technology, semiconductor products such as memory chips need to go through multiple processing procedures. In order to ensure the quality of semiconductor products, semiconductor products are tested after they are manufactured to detect whether they are damaged during the manufacturing process, and then detect failed products. This is the so-called burn-in test. Most burn-in tests place the products to be tested in a relatively high temperature environment to perform the test operations, and use more stringent test conditions to pre-detect products that are on the verge of damage or poor quality, and hope that the products will pass the preliminary tests early and enter the stable period, so that stable product characteristics can be obtained when consumers use them.

[0003] The existing stress test is time-consuming, costly, and has a high rate of false positives.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a memory chip testing method, device, equipment and medium, which at least to a certain extent overcome the problems of long time consumption, high testing cost and high misjudgment rate of failed products in breakdown stress testing.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a memory chip testing method is provided, the method comprising:

[0008] Performing M collapse stress cycle tests on the memory chip, where M is a positive integer greater than 0, wherein each collapse stress cycle test comprises the following steps:

[0009] Performing N write operations on the memory chip, where N is a positive integer greater than 1;

[0010] After executing N write operations, verifying the storage chip to obtain a verification result;

[0011] Based on the M verification results of the memory chip after the collapse stress cycle test, a collapse stress test result is obtained.

[0012] In one embodiment of the present disclosure, the memory chip includes a function configuration storage area, the function configuration storage area includes at least one frequency selection bit, and the frequency selection bit stores an N value.

[0013] In one embodiment of the present disclosure, N write operations are performed on the memory chip, and each write operation includes at least one of the following: performing an erase operation on the memory chip; performing a program operation on the memory chip.

[0014] In one embodiment of the present disclosure, after executing N write operations, verifying the memory chip to obtain a verification result includes: after executing N write operations, performing a programming operation on the memory chip, and after the programming operation is completed, verifying the memory chip to obtain a first verification result; and / or, after executing N write operations, performing an erasing operation on the memory chip, and after the erasing operation is completed, verifying the memory chip to obtain a second verification result; obtaining a verification result based on the first verification result and / or the second verification result.

[0015] In one embodiment of the present disclosure, a collapse stress test result is obtained based on M verification results of the memory chip after the collapse stress cycle test, including: when the i-th verification result among the M verification results of the memory chip after the collapse stress cycle test and the verification results after the i-th verification result are all verified as passed, the collapse stress test result is passed, wherein i is a positive integer less than or equal to M.

[0016] In one embodiment of the present disclosure, the memory chip includes a programmable storage area, and the programmable storage area is used to store the verification result corresponding to each crash stress cycle test.

[0017] In one embodiment of the present disclosure, each collapse stress cycle test also includes: obtaining the number of write operations Q performed in the current collapse stress cycle test, wherein Q is a positive integer less than or equal to N; if Q is less than N, starting the write operation circuit, wherein the write operation circuit is used to perform a write operation on the memory chip; if Q is equal to N, starting the verification circuit, and storing the verification result in the programmable storage area, wherein the started verification circuit is used to verify the memory chip.

[0018] In one embodiment of the present disclosure, before obtaining the collapse stress test result based on the M verification results of the storage chip after the collapse stress cycle test, the method further includes: when the verification result corresponding to the Mth collapse stress cycle test is obtained from the programmable storage area, ending the collapse stress cycle test.

[0019] According to another aspect of the present disclosure, a memory chip testing device is provided, the device comprising:

[0020] The collapse stress cycle test module is used to perform M collapse stress cycle tests on the memory chip, where M is a positive integer greater than 0, wherein each collapse stress cycle test includes the following steps:

[0021] Performing N write operations on the memory chip, where N is a positive integer greater than 1;

[0022] After executing N write operations, verifying the storage chip to obtain a verification result;

[0023] The test result calculation module is used to obtain a collapse stress test result based on the M verification results of the memory chip after the collapse stress cycle test.

[0024] According to another aspect of the present disclosure, there is provided a computer device, comprising one or more processors; and a memory configured to store one or more programs, so that when the one or more programs are executed by the one or more processors, the computer device implements the memory chip testing method in any embodiment of the present disclosure.

[0025] According to another aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, wherein the computer program is suitable for being loaded and executed by a processor so that a computer device having the processor executes the memory chip testing method in any embodiment of the present disclosure.

[0026] According to another aspect of the present disclosure, a computer program product is provided, the computer program product comprising a computer program or computer instructions, the computer program or the computer instructions being loaded and executed by a processor so that a computer implements any of the above-mentioned memory chip testing methods.

[0027] The memory chip testing method, device, equipment and medium provided by the embodiments of the present disclosure perform M times of collapse stress cycle tests on the memory chip, perform N write operations on the memory chip during each collapse stress cycle test, and verify the memory chip after performing N write operations to obtain a verification result. In other words, M collapse stress cycle tests are performed on the memory chip to obtain M verification results, and after the M collapse stress cycle tests are performed, the collapse stress test result is obtained based on the M verification results. The present disclosure obtains the collapse stress test result based on the M verification results only after performing M times of collapse stress cycle tests, thereby reducing the probability of misjudging the memory chip as a failed product due to slight poor contact. In addition, after performing N write operations, the memory chip is verified, thereby reducing the number of verifications during the collapse stress test, thereby reducing the duration of the collapse stress test and reducing the testing cost.

[0028] Furthermore, the present disclosure stores the N value in the functional configuration area of ​​the memory chip, so that the N value cannot be changed at will, thereby ensuring the security of the N value and the reliability of the crash test.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0031] Figure 1 A schematic diagram showing a memory chip testing system architecture in an embodiment of the present disclosure.

[0032] Figure 2 A flow chart of a memory chip testing method in an embodiment of the present disclosure is shown.

[0033] Figure 3 A schematic diagram showing the distribution of storage areas of a storage chip in an embodiment of the present disclosure is shown.

[0034] Figure 4 A schematic diagram of a memory chip testing device in an embodiment of the present disclosure is shown.

[0035] Figure 5 A schematic diagram of the structure of a computer device in an embodiment of the present disclosure is shown.

[0036] Figure 6 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0039] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0040] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0041] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0042] For ease of understanding, several terms involved in the present disclosure are explained below:

[0043] The function configuration storage area is used to store the function configuration information of the storage chip. For example, the function configuration information may be data stored on the trim bit, and the frequency selection bit may be one of the trim bits. The value of the frequency selection bit is burned in the factory.

[0044] A programmable storage area is used to store various status flag information inside the memory chip. For example, the programmable storage area may be a fuse array of the memory chip, and the programmable storage area includes a plurality of storage bits, which may store the verification result corresponding to each crash cycle test.

[0045] In the field of semiconductor technology, in order to evaluate the performance of memory chips under extreme working conditions, semiconductor chips need to be subjected to breakdown stress testing.

[0046] In the related art, multiple erase and programming operations are performed on the memory chip, and after each erase and programming operation, a full chip read verification is performed to determine whether the erase and programming are successful. Once the erase and programming verification fails, the crash response is stopped and the chip is judged as a failed product. The related art requires a full chip read verification after each erase and programming operation, which is time-consuming, high in testing cost, and has a high misjudgment rate for failed products.

[0047] The inventor has found that in the crash test, due to the existing large-scale testing needs, the crash test cycle is long, but often due to non-product reasons (such as poor contact of the test board) there are midway errors, resulting in early termination of the test, resulting in a high misjudgment rate of failed products. It should be noted that the poor contact of the test board can be a poor contact between the memory chip and the socket on the test board, or other poor contact. Therefore, a memory chip testing method is provided, which can shorten the test time of the crash test, reduce the test cost, and reduce the misjudgment rate of failed products.

[0048] The present exemplary implementation is described in detail below with reference to the accompanying drawings and embodiments.

[0049] In order to facilitate an overall understanding of the technical solution provided by the embodiment of the present disclosure, the memory testing system provided by the embodiment of the present disclosure is first described below.

[0050] Figure 1 FIG. 1 is a schematic diagram showing a memory chip test system architecture in an embodiment of the present disclosure. Figure 1 As shown, the memory chip testing system 10 may include a control device 11 and a testing board 12 .

[0051] The control device 11 may be a host computer with a control function (such as a test machine), which can control the memory chip test work on one or more test boards 12. The control device 11 may send various instructions to the test board 12, such as a crash test command, a data read instruction, etc. In some embodiments, the control device 11 may also receive an operator's selection operation for the memory chip to be tested, so as to flexibly select the object of the memory chip test required from the memory chip 13 connected to the test board 12 according to the demand, thereby improving the flexibility of the memory chip test.

[0052] The test board 12 may be connected to one or more memory chips 13, wherein the memory chip 13 may be a single memory chip (die) or multiple memory chips. The test board 12 may be used to perform at least one stress cycle test on the memory chip 13, and may also obtain stress test results based on multiple verification results of the memory chip 13 after the stress cycle test after performing all stress cycle tests. The test board 12 may be an automated test equipment (ATE), but the present disclosure is not limited thereto, and any device that can achieve the above functions may be used.

[0053] Exemplarily, several memory chips 13 (for example, the number of memory chips is 10K (thousand)) are configured on the same test board 12. The test board 12 receives a crash test command, performs parallel testing on the memory chips 13, performs multiple crash cycle tests on the memory chips 13 in parallel, and after the test, obtains the crash test results corresponding to the memory chips 13 based on the test results of the multiple crash cycle tests (hereinafter referred to as verification results).

[0054] The test board 12 connection can respond to the crash test command sent by the control device 11, locate the memory chip to be tested in the connected memory chip 13, and then test it. It should be noted that the memory chip 13 may include at least one physical memory body 131, the physical memory body 131 includes a plurality of particles (die) 132, the particles 132 may include a plurality of memory blocks (bank), the memory block may include a plurality of memory arrays (array), and each memory array includes a plurality of memory cells (cell).

[0055] In terms of connection mode, in some exemplary embodiments, the control device 11 and the test board 12 can communicate by wire. Exemplarily, in order to save communication costs, the control device 11 and the test board 12 can communicate by serial port. It should be noted that the control device 11 and the test board 12 can also select parallel communication or wireless communication and other communication modes according to the actual application scenario and specific application requirements, and there is no specific limitation on this.

[0056] In an exemplary embodiment of the present disclosure, a memory chip is placed on a test board 12, and the test board 12 is connected to a test machine, which is controlled by a computer system. After the staff writes the test program, the test machine will send corresponding instructions to each pin of the memory chip on the test board (crash test board) at different test time nodes according to the program settings to perform operations such as erase / program / verify. The test machine can output a log (a text file for recording events, states, and error information generated during the operation of a system or application) file in a txt (a text format) notepad format, which is used to record relevant information during each crash cycle test, and can be saved in a computer system with the test machine. A complete memory chip test can output one or more log files, and the present disclosure is not limited thereto. The log file records a lot of information during the entire test process, which may include information such as the test machine number, time, temperature, memory chip number, and crash test results. In addition, the results of operations such as erase / program / verify during the test process will be recorded in different letters or symbols in the log file.

[0057] In the embodiments of the present disclosure, a memory chip testing method is provided, which can be performed by any electronic device with computing processing capabilities. For example, the method can be performed by semiconductor manufacturing equipment such as automated testing equipment, or by other processing equipment that is communicatively connected to the semiconductor manufacturing equipment, without specific limitation.

[0058] Figure 2 A flow chart of a memory chip testing method according to an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the memory chip testing method provided in the embodiment of the present disclosure may include performing M collapse stress cycle tests on the memory chip, where M is a positive integer greater than 0, wherein each collapse stress cycle test may include the following S201 and S202.

[0059] S201, performing N write operations on a storage chip, where N is a positive integer greater than 1.

[0060] In an embodiment of the present disclosure, N write operations are performed on a memory chip, and each write operation may include at least one of the following: performing an erase operation on the memory chip; performing a program operation on the memory chip. For example, N write operations are performed on a memory chip, and each write operation may include: first performing an erase operation on the memory chip, and then performing a program operation on the memory chip. For another example, N write operations are performed on a memory chip, and each write operation may include: first performing a program operation on the memory chip, and then performing an erase operation on the memory chip, but the embodiment of the present disclosure is not limited thereto.

[0061] The present disclosure does not limit the value of N. For example, the value range of N can be 2-50, and the value of N can be any value of 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 14, 15, 18, 20, 26, 28, 30, 32, 34, 36, 40, 42, 44, 48, and 50.

[0062] Exemplarily, when a write operation is performed on a memory chip, the write operation may be performed on the entire memory array of the memory chip, or the write operation may be performed sequentially after partitioning the memory array of the memory chip.

[0063] It should be noted that the storage chip in the embodiment of the present disclosure may be NOR FLASH (NOR flash memory). For a NORFLASH storage unit, whether the information recorded in the storage unit is 0 or 1 depends on whether a large amount of charge is stored in the gate oxide layer. The programming process is to send the charge into the gate oxide layer, and the erasing process is to remove the charge from the gate oxide layer.

[0064] The disclosed embodiment can detect memory chips that are on the verge of damage or poor quality (failed products) during the test phase by performing multiple write operations on the memory chips. Exposing failed products in advance can improve the reliability of the memory chips.

[0065] S202, after executing N write operations, verify the storage chip to obtain a verification result.

[0066] In an embodiment of the present disclosure, after executing N write operations, verifying the memory chip to obtain a verification result may include: after executing N write operations, performing a programming operation on the memory chip, and after the programming operation is completed, verifying the memory chip to obtain a first verification result; and / or, after executing N write operations, performing an erase operation on the memory chip, and after the erase operation is completed, verifying the memory chip to obtain a second verification result; obtaining a verification result based on the first verification result and / or the second verification result.

[0067] In an exemplary embodiment, after executing N write operations, a programming operation is performed on the memory chip, and after the programming operation is completed, the memory chip is verified to obtain a first verification result, and a verification result is obtained based on the first verification result. For example, after executing N write operations, a programming operation is performed on the memory chip, that is, "1" is written into the memory chip. Then a read operation is performed on the memory chip for verification. If the result read is "1", it means that the verification result is passed. If the result read is "0", it is different from the data "1" written by programming, so the verification result is failed.

[0068] In the embodiment of the present disclosure, after executing N write operations, the memory chip is programmed and verified, thereby reducing the total number of verifications, thereby shortening the test time and reducing the test cost.

[0069] In another exemplary embodiment, after N write operations are performed, an erase operation is performed on the memory chip, and after the erase operation is completed, the memory chip is verified to obtain a second verification result; based on the second verification result, a verification result is obtained. For example, after N write operations are performed, an erase operation is performed on the memory chip, that is, "0" is written into the memory chip. Then a read operation is performed on the memory chip to verify, and if the result read is "0", it means that the verification result is passed. If the result read is "1", it is different from the data "0" written in the program, so the verification result is failed.

[0070] In the embodiment of the present disclosure, after executing N write operations, the storage chip is erased and verified, thereby reducing the total number of verifications, thereby shortening the test time and reducing the test cost.

[0071] In another exemplary embodiment, after performing N write operations, a programming operation is performed on the memory chip, and after the programming operation is completed, the memory chip is verified to obtain a first verification result; then an erasure operation is performed on the memory chip, and after the erasure operation is completed, the memory chip is verified to obtain a second verification result; based on the first verification result and the second verification result, a verification result is obtained. For example, after performing N write operations, a programming operation is performed on the memory chip, that is, "1" is written to the memory chip. Then a read operation is performed on the memory chip for verification. If the result read is "1", it means that the first verification result is passed. Then an erase operation is performed on the memory chip, that is, "0" is written to the memory chip. Then a read operation is performed on the memory chip for verification. If the result read is "0", it means that the second verification result is passed. When both the first verification result and the second verification result are passed, the verification result is passed.

[0072] It should be noted that the information in the storage chip after the programming operation and the erasing operation is different. Therefore, verification is performed after each of the programming operation and the erasing operation, and the verified information is different. Verification after each of the programming operation and the erasing operation is beneficial to improving the reliability of the verification results and improving the accuracy of identifying failed products.

[0073] In the disclosed embodiment, after executing N write operations, a verification result is obtained based on the first verification result and the second verification result, and the reliability of the verification result is higher, thereby improving the accuracy of distinguishing failed products.

[0074] Based on M verification results of the memory chip after the collapse stress cycle test, the collapse stress test result is obtained.

[0075] The present disclosure does not limit the value of M, and the value of M can be set according to the actual application scenario and specific application requirements. For example, the value range of M can be 2-100, and the value of M can be any value of 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 16, 18, 20, 24, 26, 28, 30, 32, 34, 36, 40, 42, 44, 48, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100.

[0076] In an exemplary embodiment, a collapse stress test result is obtained based on M verification results of the memory chip after the collapse stress cycle test, which may include: when the i-th verification result and the verification results after the i-th verification result among the M verification results of the memory chip after the collapse stress cycle test are all verified as passed, the collapse stress test result is passed, where i is a positive integer less than or equal to M.

[0077] Regarding the value of i, the embodiments of the present disclosure do not limit this. The value of i can be set according to the actual application scenario and specific application requirements. For example, the value range of i is 2-80, and the value of M can be any value of 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 16, 18, 20, 26, 28, 30, 32, 34, 36, 40, 42, 44, 48, 50, 55, 60, 65, 70, 75, 80.

[0078] For example, if the third verification result and the verification results after the third verification result of the 20 verification results of the memory chip after the collapse stress cycle test are all verified to pass, the collapse stress test result is passed. Exemplarily, when the third to 20th verification results are all passed, the collapse stress test result is passed. The 20 verification results are shown in Table 1 below.

[0079] Table 1 Verification results

[0080] 1st time 2nd 3rd 4th … 19th 20th Not passed Not passed pass pass pass pass pass

[0081] For another example, if the fifth verification result and the verification results after the fifth verification result of the memory chip in the 20 verification results after the collapse stress cycle test are all verified to pass, the collapse stress test result is passed. Exemplarily, when the fifth to 20th verification results are consecutively passed, the collapse stress test result is passed. The 20 verification results are shown in Table 2 below.

[0082] Table 2 Verification results

[0083] 1st time 2nd 3rd 4th 5th … 20th Not passed Not passed pass Not passed pass pass pass

[0084] It should be noted that, when the i-th verification result among the M verification results of the memory chip after the burn-in test and the verification results after the i-th verification result are continuously verified to pass, the burn-in test result is passed. The disclosed embodiment will not stop the test of the memory chip due to the failure of the burn-in test during the test process, thereby reducing the probability of misjudging a normal memory chip as a failed memory chip due to slight poor contact. It should be noted that in the related art, the memory chip may be considered a failed (FAIL) product during the BI (Burn-In) process due to sporadic and intermittent errors in the burn-in process caused by slight poor contact.

[0085] The disclosed embodiment can reduce the total number of judgments / verifications without reducing the number of executions of programming and erasing operations, and can reduce the probability of misjudging a memory chip as a failed product due to slight poor contact while ensuring the measurement quality, thereby reducing the misjudgment rate of failed products. In addition, after executing N write operations, the memory chip is verified, thereby reducing the number of verifications / judgments during the crash test, thereby reducing the crash test duration and reducing the test cost.

[0086] The storage area of ​​the memory chip is described below.

[0087] like Figure 3 As shown, the storage area of ​​the memory chip includes a main storage area 31, which is a storage cell array of the memory chip. The main storage area 31 is used to store user data, and the storage cell array other than the main storage area 23 is called a fixed area. That is to say, the memory cell array may include multiple storage areas, and the storage area for storing user data in the storage area is the main storage area 31, and the other storage areas are storage areas outside the main storage area 31 (also called fixed areas). The main storage area 31 may include a main storage array (main array) 311, a specific area 312, and a function configuration storage area 313. Among them, the main storage array 311 is a storage area for storing user data, and the specific area 312 may be a fuse array in a mini array. Various information of registers (such as SR (Set-Reset, SR) registers) is also stored in the fuse array, and the fuse array can be understood as a register area. The function configuration storage area 313 is used to store the function configuration information of the memory chip.

[0088] In an exemplary embodiment, the memory chip may include a function configuration storage area, and the function configuration storage area may include at least one frequency selection bit, and the N value is stored in the frequency selection bit.

[0089] In the disclosed embodiment, the function configuration storage area is used to store the function configuration information of the storage chip. For example, the function configuration information may be data stored on the trim bit, and the frequency selection bit may be one of the trim bits. The value of the frequency selection bit is burned in the factory, that is, the value on the frequency selection bit is not easy to change and has good stability.

[0090] In the memory chip test process, the present invention first performs N programming-erasing operations, then performs programming-verification-erase-verification operations, and repeats the above operations M times in a cycle; a corresponding gear switch (frequency selection bit) is designed inside the memory chip to adjust the number of programming-erasing operations performed in a single collapse cycle test, that is, to adjust the frequency of inserting read verification operations after erasing and programming operations of the memory chip; the present invention can select different gears for memory chips of different qualities.

[0091] In the disclosed embodiment, the value burned into the frequency selection bit is used to determine the value of N. That is to say, the adjustment of different gears is achieved by configuring different values ​​of the frequency selection bit. Corresponding frequency selection bits are reserved inside the memory chip to adjust the frequency of the verification operation. For example, 2 frequency selection bits are reserved, and the 2 frequency selection bits can have 4 values, namely 00 / 01 / 10 / 11. 00 / 01 / 10 / 11 can configure 4 frequencies. "00" corresponds to 4 erase operations-program operations followed by one erase operation-verification-program operation-verification and a cycle, that is, the value of N is 4; "01" corresponds to 8 erase operations-program operations followed by one erase operation-verification-program operation-verification and a cycle, that is, the value of N is 8; "10" corresponds to 12 erase operations-program operations followed by one erase operation-verification-program operation-verification and a cycle, that is, the value of N is 12; "11" corresponds to 16 erase operations-program operations followed by one erase operation-verification-program operation-verification and a cycle, that is, the value of N is 16. For another example, 3 frequency selection bits can combine to form 8 frequencies. The number of frequency selection bits can be set according to the actual application scenario and application needs, and the present disclosure is not limited thereto.

[0092] The disclosed embodiment can configure different values ​​on the frequency selection bit according to the quality of the memory chip, so as to perform different numbers of write operations on the memory chip in each crash cycle test. While meeting the test requirements, the test time can be saved and the test cost can be reduced. In addition, the disclosed embodiment can configure different values ​​on the frequency selection bit, thereby improving the flexibility of the test.

[0093] In the related art, the log file output by the crash test is stored in the test machine, and contains much redundant information, which is not conducive to timely viewing and analyzing the required content (such as the verification results of programming and erasing operations).

[0094] In another exemplary embodiment, the memory chip may include a programmable memory area, and the programmable memory area is used to store the verification result corresponding to each crash stress cycle test.

[0095] In the disclosed embodiment, the information in the programmable storage area can be rewritten by instructions, and the manufacturer / designer can choose whether to open the rewriting function of this information to the customer.

[0096] The programmable storage area may include multiple storage bits, and the storage bits may be used to store the verification results corresponding to each crash stress cycle test, and may also be used to store the number of crash stress cycle tests M, but the present disclosure is not limited thereto. The present disclosure does not limit the number of storage bits. For example, the number of storage bits in the programmable storage area is greater than or equal to M. It should be noted that the present disclosure needs to ensure that there are enough storage bits in the programmable storage area to record complete information when the maximum number of crash stress cycle tests is performed.

[0097] Exemplarily, the number of storage bits in the programmable storage area is M, and each storage bit stores a verification result. For example, the fifth storage bit is used to store the verification result corresponding to the fifth stress cycle test. If the data on the fifth storage bit is 1, it means that the verification result corresponding to the fifth stress cycle test is passed. If the data on the fifth storage bit is 0, it means that the verification result corresponding to the fifth stress cycle test is not passed.

[0098] It should be noted that, in the embodiment of the present disclosure, even if the verification result fails in the middle, the test will continue until the set M times are reached, and the result of each test will be recorded. If there are a few failures in the middle and then continuous passes later, it can be considered that the contact is poor in the middle, and the storage chip will not be considered a failed product.

[0099] The disclosed embodiment stores the verification result through the storage bits of the programmable storage area. When the verification result fails during the test, the test will not be stopped. The erasing operation and programming operation in the next crash cycle test will still proceed normally and record information, thereby preventing verification failure caused by contact problems and reducing the probability of misjudging the storage chip as a failed product.

[0100] In addition, the embodiment of the present disclosure does not need to view and analyze the crash test results from a lot of redundant information through log files. The embodiment of the present disclosure only uses the storage verification results stored in the storage bits of the programmable storage area to view and analyze the verification results in a timely manner, thereby obtaining the crash test results, thereby shortening the crash test time.

[0101] The termination conditions of the crash cycle test and the termination conditions of the memory chip test are described below.

[0102] In an exemplary embodiment, each breakdown stress cycle test may also include: obtaining the number of times Q of write operations performed in the current breakdown stress cycle test, where Q is a positive integer less than or equal to N; if Q is less than N, starting the write operation circuit, and the write operation circuit is used to perform a write operation on the memory chip; if Q is equal to N, starting the verification circuit, and storing the verification result in the programmable storage area, wherein the started verification circuit is used to verify the memory chip.

[0103] In the disclosed embodiment, obtaining Q is helpful to determine whether N write operations are completed in the crash cycle test. If Q is equal to N, it means that N write operations are completed, and then the memory chip is verified. If Q is less than N, it means that N write operations are not completed, and the memory chip needs to continue to be written.

[0104] In the disclosed embodiment, the write operation circuit is used to perform a write operation on the memory chip, and the verification circuit can perform an erase operation and then verify the memory chip, and / or perform a program operation and then verify the memory chip.

[0105] It should be noted that the value (gear) configured on the frequency selection bit corresponds to the working circuit to achieve the above functions. Each gear certainly requires different circuit logic and digital signal support. The specific frequency can also be adjusted during the circuit design process according to different projects.

[0106] For example, assuming that the verification frequency is 4 times and verification once, and the cycle is 5 times, then the process of memory chip testing is "erase operation-program operation-erase operation-program operation-erase operation-program operation-erase operation-verification-program operation-verification" repeated 5 times, and the total number of collapses is 40 times. The purpose of multiple cycles is to achieve the expected number of collapses, which is used to quickly pass the early high-incidence failure stage in the bathtub curve.

[0107] In the embodiment of the present disclosure, for N write operations (programming operation-erase operation) in each collapse cycle test and the erase operation-verification-programming operation-verification operation inserted after the N write operations are performed, there can be two circuit implementation forms:

[0108] One method is to implement it through the internal logic of the circuit. Before the number of programming and erasing reaches N value, the verification circuit is not enabled. After the number of programming and erasing reaches N value, the verification circuit is enabled, and after the collapse cycle test is completed, this part of the circuit is turned off until the next write operation number reaches N value.

[0109] The other method is to control through digital signals, which can be implemented with two digital signals. Digital signal A controls the circuit for programming operation-erasing operation (write operation circuit), and digital signal B controls the circuit for programming operation-verification-erasing operation-verification (verification circuit). Before the number of programming operation-erasing operations reaches N value, signal A is valid. After the number of programming operation-erasing operations reaches N, signal B is valid, and the cycle continues.

[0110] It should be noted that the frequency of performing read verification after a write operation during the crash cycle test is adjustable, that is, the value of N is adjustable.

[0111] The disclosed embodiment determines whether N write operations are completed by obtaining the total number of times from the first write operation to the current write operation, thereby realizing the test of the memory chip. The disclosed embodiment can save test time and cost, has high flexibility and wide applicability, and can flexibly select different read verification frequencies for memory chips of different qualities, thereby reducing the number of judgments, reducing the probability of misjudgment, and improving product yield.

[0112] In another exemplary embodiment, before obtaining the collapse stress test result based on M verification results of the storage chip after the collapse stress cycle test, the method may further include: when the verification result corresponding to the Mth collapse stress cycle test is obtained from the programmable storage area, ending the collapse stress cycle test.

[0113] Exemplarily, if the programmable storage area stores the verification result corresponding to the Mth crash stress cycle test, the crash stress cycle test is terminated, and the crash stress test result is obtained based on the M verification results of the storage chip after the crash stress cycle test.

[0114] The embodiments of the present disclosure can cover the requirements of dozens to hundreds of collapse tests through different combinations of verification frequencies (N) and number of cycles (M), and have high flexibility. It should be noted that, through different combinations of verification frequencies and number of cycles, the present disclosure can also be used for collapse tests exceeding hundreds of times or more, and the present disclosure does not limit this.

[0115] Based on the same inventive concept, the present disclosure also provides a memory chip testing device in the following embodiments. Since the principle of solving the problem in the device embodiment is similar to that in the above method embodiment, the implementation of the device embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0116] Figure 4 A schematic diagram of a memory chip testing device according to an embodiment of the present disclosure is shown. Figure 4 As shown, the memory chip testing device may include a stress cycle testing module 41 and a test result calculation module 42 .

[0117] The stress cycle test module 41 may be used to perform M stress cycle tests on the memory chip, where M is a positive integer greater than 0, wherein each stress cycle test includes the following steps:

[0118] Performing N write operations on the memory chip, where N is a positive integer greater than 1;

[0119] After executing N write operations, verify the storage chip and obtain a verification result;

[0120] The test result calculation module 42 may be used to obtain a collapse stress test result based on the M verification results of the memory chip after the collapse stress cycle test.

[0121] In one embodiment, the memory chip includes a function configuration storage area, the function configuration storage area includes at least one frequency selection bit, and the N value is stored in the frequency selection bit.

[0122] In one embodiment, the crash cycle test module 41 may also be used to perform N write operations on the memory chip, where each write operation includes at least one of the following:

[0123] Perform an erase operation on the memory chip;

[0124] Perform programming operations on memory chips.

[0125] In one embodiment, the crash cycle test module 41 may also be used to perform a programming operation on the memory chip after performing N write operations, and after the programming operation is completed, verify the memory chip to obtain a first verification result; and / or,

[0126] When N write operations are performed, an erasing operation is performed on the storage chip, and after the erasing operation is completed, the storage chip is verified to obtain a second verification result;

[0127] Based on the first verification result and / or the second verification result, a verification result is obtained.

[0128] In one embodiment, the test result calculation module 42 can also be used to determine that the collapse test result is passed when the i-th verification result and the verification results after the i-th verification result among the M verification results of the storage chip after the collapse cycle test are all verified to be passed, where i is a positive integer less than or equal to M.

[0129] In one embodiment, the memory chip includes a programmable storage area, and the programmable storage area is used to store the verification result corresponding to each crash cycle test.

[0130] In one embodiment, the breakdown stress cycle test module 41 can also be used to obtain the number of times Q of write operations performed in the current breakdown stress cycle test, where Q is a positive integer less than or equal to N; if Q is less than N, the write operation circuit is started, and the write operation circuit is used to perform a write operation on the memory chip; if Q is equal to N, the verification circuit is started, and the verification result is stored in the programmable storage area, where the started verification circuit is used to verify the memory chip.

[0131] In one embodiment, before obtaining the collapse stress test result based on M verification results of the storage chip after the collapse stress cycle test, the collapse stress cycle test module 41 can also be used to end the collapse stress cycle test when the verification result corresponding to the Mth collapse stress cycle test is obtained from the programmable storage area.

[0132] In the disclosed embodiment, the memory chip test device performs M times of the crash test cycle before obtaining the crash test result based on M verification results, thereby reducing the probability of misjudging the memory chip as a failed product due to slight poor contact. In addition, after performing N write operations, the memory chip is verified, thereby reducing the number of verifications during the crash test, thereby reducing the crash test time and reducing the test cost.

[0133] Furthermore, the memory chip testing device in the embodiment of the present disclosure stores the N value in the function configuration area of ​​the memory chip, so that the N value cannot be changed at will, thereby ensuring the reliability of the crash test while ensuring the security of the N value.

[0134] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as "circuits", "modules" or "systems".

[0135] See below Figure 5 , Figure 5 Schematic diagram of a computer device provided by an embodiment of the present disclosure. Figure 5 As shown, the computer device in the embodiment of the present disclosure may include: one or more processors 501, a memory 502, and an input-output interface 503. The processor 501, the memory 502, and the input-output interface 503 are connected via a bus 504. The memory 502 is used to store a computer program, which includes program instructions. The input-output interface 503 is used to receive data and output data, such as for data interaction between a host machine and a computer device, or for data interaction between virtual machines in a host machine; the processor 501 is used to execute the program instructions stored in the memory 502.

[0136] Among them, the processor 501 can perform the following operations: perform M times of collapse stress cycle test on the memory chip, M is a positive integer greater than 0, wherein each collapse stress cycle test includes the following steps: perform N times of write operation on the memory chip, wherein N is a positive integer greater than 1; after performing N times of write operation, verify the memory chip to obtain a verification result; based on the M verification results of the memory chip after the collapse stress cycle test, obtain the collapse stress test result.

[0137] The memory 502 may include a read-only memory and a random access memory, and provide instructions and data to the processor 501 and the input / output interface 503. A portion of the memory 502 may also include a non-volatile random access memory. In implementation, the computer device may execute the implementation methods provided by the various steps in any of the above method embodiments through its built-in functional modules, and the implementation methods provided by the various steps in the figures shown in the above method embodiments may be referred to, and will not be repeated here.

[0138] The embodiments of the present disclosure provide a computer device, including a processor, an input / output interface, and a memory. The processor obtains a computer program in the memory to execute each step of the method shown in any of the above embodiments.

[0139] The present disclosure also provides a computer-readable storage medium storing a computer program. Figure 6 A schematic diagram of a computer-readable storage medium in an embodiment of the present disclosure is shown. Figure 6 As shown, a program product capable of implementing the above method of the present disclosure is stored on the computer-readable storage medium 600. The computer program is suitable for being loaded by the processor and executing the memory chip testing method provided in each step of any of the above embodiments.

[0140] In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of various exemplary implementations of the present disclosure described in the above "Specific Implementation Methods" section of this specification.

[0141] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0142] In the present disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein a readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A readable signal medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0143] Alternatively, the program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0144] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet).

[0145] The embodiment of the present disclosure provides a computer program product or a computer program, which includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the memory chip testing method provided in various optional ways in any embodiment of the present disclosure.

[0146] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0147] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0148] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0149] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope of the present disclosure is indicated by the appended claims.

Claims

1. A memory chip testing method, characterized in that: include: Performing M collapse stress cycle tests on the memory chip, where M is a positive integer greater than 0, wherein each collapse stress cycle test comprises the following steps: Performing N write operations on the memory chip, where N is a positive integer greater than 1; After executing N write operations, verifying the storage chip to obtain a verification result; Based on the M verification results of the memory chip after the collapse stress cycle test, a collapse stress test result is obtained.

2. The memory chip testing method according to claim 1, characterized in that: The memory chip includes a function configuration storage area, the function configuration storage area includes at least one frequency selection bit, and the frequency selection bit stores an N value.

3. The memory chip testing method according to claim 1, characterized in that: Performing N write operations on the memory chip, each write operation including at least one of the following: Performing an erase operation on the storage chip; A programming operation is performed on the memory chip.

4. The memory chip testing method according to claim 1, characterized in that: After executing N write operations, verifying the storage chip to obtain a verification result includes: After executing N write operations, performing a programming operation on the memory chip, and after the programming operation is completed, verifying the memory chip to obtain a first verification result; and / or, When N write operations are performed, an erasing operation is performed on the storage chip, and after the erasing operation is completed, the storage chip is verified to obtain a second verification result; A verification result is obtained based on the first verification result and / or the second verification result.

5. The memory chip testing method according to claim 1, characterized in that: Based on the M verification results of the memory chip after the collapse stress cycle test, a collapse stress test result is obtained, including: When the i-th verification result and the verification results after the i-th verification result among the M verification results of the memory chip after the collapse stress cycle test are all verified to pass, the collapse stress test result is passed, where i is a positive integer less than or equal to M.

6. The memory chip testing method according to claim 1, characterized in that: The memory chip comprises a programmable storage area, and the programmable storage area is used to store the verification result corresponding to each crash cycle test.

7. The memory chip testing method according to claim 6, characterized in that: Each stress cycle test also includes: Obtain the number of write operations Q executed in the current crash cycle test, where Q is a positive integer less than or equal to N; If Q is less than N, a write operation circuit is started, wherein the write operation circuit is used to perform a write operation on the memory chip; If Q is equal to N, the verification circuit is started and the verification result is stored in the programmable storage area, wherein the started verification circuit is used to verify the storage chip.

8. The memory chip testing method according to claim 6 or 7, characterized in that: Before obtaining the collapse stress test result based on the M verification results of the memory chip after the collapse stress cycle test, the method further includes: When the verification result corresponding to the Mth crash stress cycle test is obtained from the programmable storage area, the crash stress cycle test is terminated.

9. A memory chip testing device, characterized in that: The device comprises: The collapse stress cycle test module is used to perform M collapse stress cycle tests on the memory chip, where M is a positive integer greater than 0, wherein each collapse stress cycle test includes the following steps: Performing N write operations on the memory chip, where N is a positive integer greater than 1; After executing N write operations, verifying the storage chip to obtain a verification result; The test result calculation module is used to obtain a collapse stress test result based on the M verification results of the memory chip after the collapse stress cycle test.

10. A computer device, characterized in that: include: one or more processors; The memory is configured to store one or more programs, and when the one or more programs are executed by the one or more processors, the computer device implements the method according to any one of claims 1 to 8.

11. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 8.

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