Staggered pin connector

Abstract

The invention relates to a staggered pin connector. A substrate includes a first edge and a second edge opposite the first edge. A plurality of first edge pins are located proximate the first edge, where first edge pins of a first subset are located at a first distance from the first edge, and first edge pins of a second subset are located at a second distance from the first edge that is different from the first distance. A plurality of second edge pins are located proximate the second edge, where the second edge pins of a first subset are located at a first distance from the second edge, and the second edge pins of a second subset are located at a second distance from the second edge different from the first distance, a connector having a staggered pin arrangement is thus provided.

Description

Technical Field

[0001] The present disclosure relates to connectors, and more particularly, to staggered pin connectors. Background Art

[0002] Magnetic jacks, modular jacks (modjacks), and similar connectors include one or more ports capable of receiving an Ethernet connection, such as using an RJ11 or RJ45 connector. Magnetic jacks, modular jacks, and similar connectors include various circuit boards, printed circuit boards (PCBs), integrated circuits (ICs), or similar substrates located in close proximity to each other, employing magnetic components and circuitry for handling signals and / or power (e.g., Power over Ethernet or PoE) transmitted through a connector. The proximity of multiple conductive substrates in the connector causes alien near-end crosstalk (NEXT) and other potential types of signal interference. At 1GbE and lower data speeds, alien near-end crosstalk generally has minimal impact on data transmission. However, as data speeds increase (e.g., 2.5GbE, 5GbE, 10GbE, and higher), alien near-end crosstalk can hinder data signal integrity and impair the performance of an Ethernet-enabled device. Summary of the invention

[0003] Various embodiments are disclosed for a connector having a staggered pin arrangement for improved performance. In a first aspect, a connector is described as comprising: a plurality of substrates located proximate to each other, wherein at least one of the plurality of substrates comprises: a first edge and a second edge opposite the first edge; a plurality of first edge pins located proximate to the first edge, wherein a first subset of first edge pins are located at a first distance from the first edge, and a second subset of first edge pins are located at a second distance from the first edge that is different from the first distance; and a plurality of second edge pins located proximate to the second edge, wherein a first subset of second edge pins are located at a first distance from the second edge, and a second subset of second edge pins are located at a second distance from the second edge that is different from the first distance.

[0004] At least one of the plurality of substrates is a printed circuit board (PCB). Each of the first edge pins of the first subset has a diameter that is smaller than the diameter of each of the first edge pins of the second subset. Each of the second edge pins of the first subset has a diameter that is larger than the diameter of each of the second edge pins of the second subset. Each of the first edge pins and the second edge pins is located within a through hole.

[0005] The connector may also include: a plurality of first through holes, located close to the first edge, having a first diameter, wherein the first edge pins of the first subset are located within the plurality of first through holes; and a plurality of second through holes, located close to the first edge, having a second diameter different from the first diameter, wherein the first edge pins of the second subset are located within the plurality of second through holes.

[0006] In another aspect, the connector may also include: a plurality of first through holes located near the second edge and having a first diameter, wherein the second edge pins of the first subset are located within the plurality of first through holes; and a plurality of second through holes located near the second edge and having a second diameter different from the first diameter, wherein the second edge pins of the second subset are located within the plurality of second through holes.

[0007] The connector can also include: a plurality of port terminals connected to the substrate, configured to engage with a housing of an external connector. Each of the plurality of substrates can include a conductive trace connected to one of the plurality of port terminals, wherein the first edge pin and the second edge pin connect the conductive trace to a downstream magnetic element. The plurality of port terminals can be four, six, or eight in number, and the external connector can be an RJ45 connector.

[0008] Each pin in the first edge pins of the first subgroup can have a first predetermined offset relative to each pin in the first edge pins of the second subgroup, wherein the first predetermined offset is a predetermined distance selected for optimal performance, and each pin in the second edge pins of the first subgroup can have a second predetermined offset relative to each pin in the second edge pins of the second subgroup, wherein the second predetermined offset is a predetermined distance selected for optimal performance.

[0009] In a second aspect, a connector is described as comprising: a plurality of substrates located close to each other, wherein at least one of the plurality of substrates comprises: a first edge and a second edge opposite to the first edge; and a plurality of first edge pins located close to the first edge, wherein a first subset of first edge pins are located at a first distance from the first edge, and a second subset of first edge pins are located at a second distance from the first edge that is different from the first distance.

[0010] The connector may further include: a plurality of second edge pins located proximate the second edge, wherein a first subset of second edge pins are located at a first distance from the second edge; and a second subset of second edge pins are located at a second distance from the second edge that is different from the first distance. At least one of the plurality of substrates may be a printed circuit board (PCB).

[0011] Each pin in the first subset of first edge pins can have a diameter that is smaller than a diameter of each pin in the second subset of first edge pins. Each pin in the first subset of second edge pins can have a diameter that is larger than a diameter of each pin in the second subset of second edge pins. Each pin in the first edge pin and the second edge pin can be located in a through hole.

[0012] The connector may also include: a plurality of first through holes, located close to the first edge, having a first diameter, wherein the first edge pins of the first subset are located within the plurality of first through holes; and a plurality of second through holes, located close to the first edge, having a second diameter different from the first diameter, wherein the first edge pins of the second subset are located within the plurality of second through holes.

[0013] In some aspects, the connector may also include: a plurality of first through holes located near the second edge and having a first diameter, wherein the second edge pins of the first subset are located within the plurality of first through holes; and a plurality of second through holes located near the second edge and having a second diameter different from the first diameter, wherein the second edge pins of the second subset are located within the plurality of second through holes.

[0014] The connector can also include: a plurality of port terminals connected to the substrate and configured to engage with a housing of an external connector. Each of the plurality of substrates can include a conductive trace connected to one of the plurality of port terminals, wherein the first edge pin and the second edge pin connect the conductive trace to a downstream magnetic element. The plurality of port terminals can be four, six, or eight in number, and the external connector can be an RJ45 connector. Each of the first edge pins of the first subset can have a first predetermined offset relative to each of the first edge pins of the second subset, wherein the first predetermined offset is a predetermined distance selected for optimal performance, and each of the second edge pins of the first subset can have a second predetermined offset relative to each of the second edge pins of the second subset, wherein the second predetermined offset is a predetermined distance selected for optimal performance.

[0015] In a third aspect, a connector is described as comprising a substrate, comprising: a plurality of first edge pins located proximate a first edge in a staggered arrangement, wherein a first subset of first edge pins are located at a first distance from the first edge, and a second subset of first edge pins are located at a second distance from the first edge that is different from the first distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Many aspects of the present disclosure may be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, but emphasis is placed on clearly illustrating the principles of the present disclosure. In addition, in the drawings, similar reference numerals throughout the several views represent corresponding parts.

[0017] Figure 1 is a top perspective view of a connector according to various embodiments of the present disclosure.

[0018] Figure 2 According to various embodiments of the present disclosure Figure 1 A bottom perspective view of a connector.

[0019] Figure 3 According to various embodiments of the present disclosure Figure 1 A front view of a connector.

[0020] Figure 4 According to various embodiments of the present disclosure Figure 1 A rear view of the connector.

[0021] Figure 5 According to various embodiments of the present disclosure Figure 1 A top perspective view of a connector, wherein the housing of the connector is omitted.

[0022] Figure 6 According to various embodiments of the present disclosure Figure 1 A bottom perspective view of a connector, wherein the housing of the connector is omitted.

[0023] Figure 7 According to various embodiments of the present disclosure Figure 1 A top view of a substrate of a connector.

[0024] Figure 8 The present invention is a pin diagram of a substrate in the related art.

[0025] Fig. 9 According to various embodiments of the present disclosure Figure 1 A pin diagram of a substrate of a connector. DETAILED DESCRIPTION

[0026] As will be explained, the present disclosure relates to a connector having a staggered pin arrangement for improved performance. A Jack-45 connector, also commonly referred to as an RJ45 connector, is a wired connector that interfaces with network-enabled devices on a local area network (LAN), including but not limited to Ethernet. An RJ45 connector generally includes a male plug that is inserted or otherwise positioned in a female port. The RJ45 connector includes a housing having an array of parallel conductive contacts for docking with a port having correspondingly aligned conductive contacts. A spring or tab located on the housing is used to couple the RJ45 connector to a corresponding plug in a biased and interference manner.

[0027] As described above, in a connector having a large number of plugs, including but not limited to an Ethernet jack or plug, the proximity of multiple PCBs or other substrates can cause alien near-end crosstalk (NEXT). The alien near-end crosstalk can cause undesirable interference on data communication signals. Although alien near-end crosstalk often does not interfere with data speeds, power or data transmission at lower speeds, due to the increase in data speeds in recent years (e.g., 2.5GbE, 5GbE, 10GbE and higher), alien near-end crosstalk can hinder signal integrity and degrade the performance of signals or power of a device using the connector, especially in high data speed applications.

[0028] A common approach to addressing external near-end crosstalk in a connector includes positioning a metallic, conductive shield between adjacent terminal box assemblies (TBAs). Each TBA includes two ports, an upper port and a lower port. The PCB in each assembly leads to magnetic components for the upper and lower ports. The positioned metallic, conductive shield is typically placed between the assemblies, spanning most if not all of the height of the TBA, to reduce external near-end crosstalk from the entire TBA, including the magnetic components of the device and pins within the substrate. Although such a shield can improve signal performance, it increases the required materials and manufacturing difficulty, thereby increasing the overall cost for the connector.

[0029] Thus, various embodiments are described herein for a connector having a staggered pin arrangement for improved signal and power performance. The connector can include an Ethernet or modular jack connector having a plurality of substrates (substrates) located proximate to each other, such as in a horizontal side-by-side arrangement. One or more of the plurality of substrates includes a first edge and a second edge opposite the first edge, a plurality of first edge pins located along the first edge, and a plurality of second edge pins located along the second edge.

[0030] Additionally, in various embodiments, a single continuous substrate can be used to horizontally arrange TBAs side by side. In this case, the distance between the plurality of first edge pins and the plurality of second edge pins from one TBA to an adjacent TBA is of great concern because there is no substrate edge between the two TBAs.

[0031] A first subset of first edge pins can be located at a first distance from the first edge. Likewise, a second subset of first edge pins can be located at a second distance from the first edge that is different from the first distance, thereby providing a staggered arrangement along the first edge. Likewise, a plurality of second edge pins can be located proximate the second edge, wherein a first subset of second edge pins can be located at a first distance from the second edge, and a second subset of second edge pins can be located at a second distance from the second edge that is different from the first distance. Thus, a staggered arrangement along the second edge is provided.

[0032] One or more of the plurality of substrates in the connector can include a circuit board, a printed circuit board (PCB), an integrated circuit (IC), or a similar substrate. In some embodiments, each pin in the first subset of first edge pins can have a diameter that is larger than the diameter of each pin in the second subset of first edge pins. Similarly, in some embodiments, each pin in the first subset of second edge pins can have a diameter that is larger than the diameter of each pin in the second subset of second edge pins.

[0033] The substrate can also include a plurality of first through holes, each of which has a first diameter. The first edge pins of the first subset can be located within the plurality of first through holes. The substrate can also include a plurality of second through holes, each of which has a second diameter different from the first diameter. The first edge pins of the second subset can be located within the plurality of second through holes. By staggering the plurality of pins along the two edges of the substrate, the distance between the pins on adjacent substrates is increased, reducing external near-end crosstalk and improving performance, especially at high data speeds.

[0034] Turning now to the accompanying drawings, which are, Figure 1 FIG. 1 shows a top perspective view of a connector 100 according to various embodiments of the present disclosure. Figure 2 FIG. 1 shows a bottom perspective view of a connector 100 according to various embodiments of the present disclosure. Figure 3 A front view of the connector 100 according to various embodiments of the present disclosure is shown, and Figure 4 A rear view of connector 100 is shown according to various embodiments of the present disclosure. As can be appreciated, connector 100 can be coupled to or positioned with an electronic device to make the device a network-enabled device. Thus, connector 100 can be referred to as a network connector, an Ethernet connector, or the like. Connector 100 can also include a magnetic jack, modular jack, or the like. In some embodiments, connector 100 is 802.3 Ethernet 10 / 100 / 1000 compatible, 802.3at (PoE+) compliant and / or 802.3af (PoE Ethernet) compliant.

[0035] Refer to Figures 1 to 4, the connector 100 can include a housing 103 and a housing shield 106 that together define a plurality of ports 109 located on a front face 112 of the connector 100. The ports 109 can receive a suitable connector, such as an RJ45 connector, but other types of connectors are intended to be within the scope of the present disclosure. Although two rows and six columns of ports 109 are shown, it is understood that in various embodiments, the connector 100 can include one or more ports 109.

[0036] The housing 103 can be formed of a non-conductive material, such as plastic, but other materials can be used. Likewise, the housing shield 106 can be formed of a metallic conductive material, such as aluminum, but other materials can be used to provide a shielding effect. The housing shield 106 can be formed with a plurality of resilient fingers 107 and / or a plurality of other tabs for engaging and holding various components together when the connector 100 is placed into a larger housing (not shown) such as a housing of an electronic device.

[0037] Each port 109 of the connector 100 can include a port terminal 115 configured to electrically contact a corresponding contact on a mating plug (e.g., an RJ45 connector) when a mating plug is inserted into the port terminal 115. The number of port terminals 115 in each port 109 can vary depending on the type of connector. Some example configurations include four, six, or eight port pins for Ethernet connectors and RJ45 connectors. Figures 1 to 4 In the particular embodiment shown, eight port terminals 115 are shown, but other numbers of port terminals 115 can be implemented.

[0038] The connector 100 can convert a serially transmitted data signal into an Ethernet signal. By positioning the connector 100 on a surface mount device (not shown) and soldering or otherwise attaching the connector 100 to a desired substrate via corresponding through holes, the Ethernet signal can be transmitted to a downstream circuit (e.g., a motherboard, PCB or other device) through the board mounting terminal 118. In some embodiments, the board mounting terminal 118 can extend from the housing 103 or through the housing 103 in a downward direction, such as Figure 2 However, it is understood that other arrangements can be employed.

[0039] According to various embodiments, the connector 100 can include a plurality of support posts 121 that can hold the housing 103 at a predetermined distance from the surface mount device. The plurality of support posts 121 can be formed of a non-conductive material, such as a polymer material. In some embodiments, the plurality of support posts 121 can be located in corresponding through-holes on the surface mount device.

[0040] continue, Figure 5 and Figure 6 A top perspective view and a bottom perspective view of the connector 100 are shown, respectively, wherein the housing 103 and the housing shield 106 are omitted for purposes of explanation. Within the housing 103, the connector 100 can include a port terminal 115 that can be attached to a plurality of substrates 124a...124n (collectively referred to as "substrates 124"). As can be appreciated, as in Figure 5 As best seen in the top perspective view of , the substrate 124 can also include conductive traces 127, through holes 130, pins 133, and other components. Other components that can be formed on the substrate 124 or otherwise included on the substrate 124 can include active or passive components, such as inductors and capacitors, light emitting diodes (LEDs), and other components. On each substrate 124, the port terminals 115 are connected to the conductive traces 127, wherein the pins 133 connect the conductive traces 127 to magnetics 136 of the connector 100 or other downstream electronic devices. For example, the magnetics 136 provide signal isolation, impedance matching, signal transformation, surge protection, and other functions, thereby providing a signal through the board mounted terminals 118.

[0041] Next, refer to Figure 7 , Figure 7 A top view of a representative substrate 124 of the connector 100 is shown, wherein the housing 103 and the housing shield 106 are again omitted for purposes of explanation. Figure 5 As shown, the substrate 124 can be located close to other substrates 124. For example, the plurality of substrates 124 can be arranged horizontally, wherein the substrates 124 in a particular row are located side by side along the same plane. Figure 7 , the substrate 124 can include a first edge 139 and a second edge 142 opposite to the first edge 139. For example, the first edge 139 and the second edge 142 are located on opposite sides of the substrate 124.

[0042] The plurality of first edge pins 133a are located along or near the first edge 139. For example, the plurality of first edge pins 133a are closer to the first edge 139 than the second edge 142. A first subset of the first edge pins 133a are located at a first distance D1 from the first edge 139, and a second subset of the first edge pins 133a are located at a second distance D2 from the first edge 139. In various embodiments, the second distance D2 is different from the first distance D1, thereby providing a staggered arrangement of the plurality of first edge pins 133a, such as Figure 7 As shown. Note that Figure 7As shown, the paired first edge pins 133a have a longer distance (D1) from the first edge 139 relative to the isolated first edge pins 133a located closer to the first edge 139 (D2), (although other staggered arrangements are possible).

[0043] A plurality of second edge pins 133b are located along or near the second edge 142. Figure 7 It is observed that a plurality of second edge pins 133b are located closer to the second edge 142 relative to the first edge 139. As with the first edge pins 133a described above, a first subset of second edge pins 133b are located at a first distance D3 from the second edge 142, and a second subset of second edge pins 133b are located at a second distance D4 from the second edge 142, wherein the second distance D4 is different from the first distance D3.

[0044] This shows a staggered arrangement of the plurality of second edge pins 133b along the second edge 142. For example, Figure 7 As shown, the pairs of second edge pins 133b have a longer distance from the second edge 142 relative to the isolated second edge pins 133b located closer to the second edge 142. However, it is understood that in alternative staggered arrangements, the isolated second edge pins 133b of the plurality of second edge pins 133b can be located farther from the second edge 142 relative to the pairs of second edge pins 133b. Note that not all of the first edge pins 133a are aligned along a common axis that is located parallel to the first edge 139, and / or not all of the second edge pins 133b are aligned along a common axis that is located parallel to the second edge 142.

[0045] Additionally, in some embodiments, each pin 133 in the first subset of first edge pins 133a can have a diameter that is smaller than the diameter of each pin 133 in the second subset of first edge pins 133a. For example, first edge pins 133a arranged in pairs along a horizontal direction of substrate 124 have a diameter that is smaller than the diameter of isolated first edge pins 133a in the plurality of first edge pins 133a that are located closer to first edge 139. In some embodiments, the two diameters are not different from each other. Because the plurality of pins 133 are offset, the pad on the larger pin can be a standard size rather than a unique oval shape that may not connect to through-hole 130 on all sides.

[0046] Likewise, in some embodiments, each pin 133 in the first subset of second edge pins 133b can have a diameter smaller than each pin 133 in the second subset of second edge pins 133b. For example, second edge pins 133b arranged in pairs along a horizontal direction of the substrate 124 have a diameter smaller than the diameter of isolated second edge pins 133b located closer to the second edge 142 among the plurality of second edge pins 133b. A ground pin 145 can be located at a rear end of the substrate 124 relative to the port terminal 115.

[0047] Each pin 133 of the plurality of first edge pins 133a and / or the plurality of second edge pins 133b can be positioned within a through hole 130 to allow the pin 133 to couple a conductive trace 127 to a magnetic element 136 or other downstream portion of the connector 100. In some embodiments, a first team of through holes 130 has a first diameter, wherein a first subset of first edge pins 133a are positioned within the first team of through holes 130, and a second team of through holes 130 has a second diameter different from the first diameter. A second subset of first edge pins 133a can be positioned within a second team of through holes 130.

[0048] Next turn Figure 8 , Figure 8 A pin schematic diagram of an example substrate 124 of the related art is shown. As can be seen, all of the pins along a first side of the substrate are aligned along a common axis a1 located parallel to the first side. All of the pins along a second side of the substrate are aligned along a common axis a2 located parallel to the second side. In addition, each of the multiple pins on either the first side or the second side is of a uniform size and is located in a through hole that is also of a uniform size. It is understood that when multiple substrates 124 of the related art are located adjacent to each other or even stacked on each other in a vertical arrangement, the proximity of the pins between adjacent substrates 124 causes external near-end crosstalk, which impairs the ability to transmit at high data speeds (particularly for 2.5GbE and above). In the related art, moving the position of the pins is difficult and undesirable because such movement of the pins interferes with the trace routing and there will be other difficulties.

[0049] In contrast, Fig. 9A schematic diagram of a pin arrangement of a first substrate 124a adjacent to a second substrate 124b is shown according to various embodiments described herein. Generally, pairs of pins 133 along the first edge 139 or the second edge 142 of the substrate 124a are located further away from the edge to provide increased spacing between the pins 133 on the second substrate 124b. Isolated pins 133 of the plurality of pins 133 have an increased center-tap plating through-hole size and / or an increased pin diameter. Pins 133 located in pairs (e.g., first edge pins 133a of the first subset) have an offset o1 relative to isolated pins 133 of the plurality of pins 133 (e.g., first edge pins 133a of the second subset). In some embodiments, the offset o1 is 0.5 mm, 1 mm, 1.5 mm, 2 mm, or other dimensions that maintain increased performance.

[0050] The above-mentioned features, structures or characteristics may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in the various embodiments may be interchangeable. In the following description, many specific details are provided to fully understand the multiple embodiments of the present disclosure. However, it will be appreciated by those skilled in the art that the technical solutions of the present disclosure may be practiced without one or more of the many specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid confusion in many aspects of the present disclosure.

[0051] Although relative terms such as "on", "below", "upper" and "lower" are used in the specification to explain the relative relationship of one component to another component, these terms are used in the specification only for convenience, for example as directions in the examples shown in the drawings. It should be understood that if the device is turned upside down, the above-mentioned "upper" component will become a "lower" component. When a structure is "on" another structure, it may be that the structure is integrally formed on the other structure, or the structure is "directly" provided on the other structure, or the structure is "indirectly" provided on the other structure through other structures.

[0052] In this specification, terms such as "a", "an", "the", and "said" are used to indicate the presence of one or more elements and components. The terms "comprise", "include", "have", "contain" and variations thereof are used to be open ended and mean that additional elements, components, etc. are included in addition to the listed elements, components, etc., unless otherwise specified in the accompanying claims.

[0053] The terms "first", "second", etc. are used only as labels and are not limitations on a number of objects. It is understood that if a plurality of components are given, these components may be referred to as "first" components, "second" components, etc., within the applicable scope.

[0054] The above-mentioned embodiments of the present disclosure are merely possible examples of the embodiments set forth for a clear understanding of the principles of the present disclosure. In the case of not departing from the spirit and principles of the present disclosure in essence, many variations and modifications may be made to the above-mentioned embodiments. All such modifications and variations are included herein within the scope of the present disclosure and are protected by the following claims.

Claims

1. A connector, comprising: A plurality of substrates located in proximity to each other, wherein at least one of the plurality of substrates comprises: a first edge and a second edge opposite to the first edge; a plurality of first edge pins located proximate the first edge, wherein a first subset of the first edge pins are located at a first distance from the first edge, and a second subset of the first edge pins are located at a second distance from the first edge that is different than the first distance; and A plurality of second edge pins are located proximate to the second edge, wherein a first subset of second edge pins are located at a first distance from the second edge, and a second subset of second edge pins are located at a second distance from the second edge that is different from the first distance.

2. The connector according to claim 1, wherein: At least one of the plurality of substrates is a printed circuit board (PCB).

3. The connector according to claim 1, wherein: Each pin in the first subset of first edge pins has a diameter that is smaller than a diameter of each pin in the second subset of first edge pins.

4. The connector according to claim 1 or 3, wherein: Each pin in the first subset of second edge pins has a diameter that is greater than a diameter of each pin in the second subset of second edge pins.

5. The connector according to claim 1, wherein: Each of the first edge pins and the second edge pins is located in a through hole.

6. The connector according to claim 1, further comprising: a plurality of first through holes located proximate the first edge and having a first diameter, wherein the first edge pins of the first subset are located within the plurality of first through holes; and A plurality of second through holes are located proximate to the first edge and have a second diameter different from the first diameter, wherein the first edge pins of the second subset are located within the plurality of second through holes.

7. The connector according to claim 1 or 6, further comprising: a plurality of first through holes located proximate the second edge and having a first diameter, wherein the second edge pins of the first subset are located within the plurality of first through holes; and A plurality of second through holes are located proximate to the second edge and have a second diameter different from the first diameter, wherein the second edge pins of the second subset are located within the plurality of second through holes.

8. The connector according to claim 1, further comprising: A plurality of port terminals are connected to the substrate and configured to engage with a housing of an external connector.

9. The connector according to claim 8, wherein: Each of the plurality of substrates includes a conductive trace coupled to one of the plurality of port terminals, wherein the first edge pin and the second edge pin couple the conductive trace to a downstream magnetic element.

10. The connector according to claim 1, wherein: The number of the plurality of port terminals is four, six or eight, and The external connector is an RJ45 connector.

11. The connector according to claim 1, wherein: Each pin in the first subset of first edge pins has a first predetermined offset relative to each pin in the second subset of first edge pins, wherein the first predetermined offset is a predetermined distance selected for optimal performance; and Each pin in the first subset of second edge pins has a second predetermined offset relative to each pin in the second subset of second edge pins, wherein the second predetermined offset is a predetermined distance selected for optimal performance.

12. A connector, comprising: A plurality of substrates located in proximity to each other, wherein at least one of the plurality of substrates comprises: a first edge and a second edge opposite to the first edge; and A plurality of first edge pins are located proximate to the first edge, wherein a first subset of first edge pins are located at a first distance from the first edge, and a second subset of first edge pins are located at a second distance from the first edge that is different from the first distance.

13. The connector according to claim 12, further comprising: A plurality of second edge pins are located proximate to the second edge, wherein a first subset of second edge pins are located at a first distance from the second edge, and a second subset of second edge pins are located at a second distance from the second edge that is different from the first distance.

14. The connector according to claim 12 or 13, wherein: At least one of the plurality of substrates is a printed circuit board (PCB).

15. The connector according to claim 12 or 13, wherein: Each pin in the first subset of first edge pins has a diameter that is smaller than a diameter of each pin in the second subset of first edge pins.

16. The connector according to claim 15, wherein: Each pin in the first subset of second edge pins has a diameter that is greater than a diameter of each pin in the second subset of second edge pins.

17. The connector according to claim 13, wherein: Each of the first edge pins and the second edge pins is located in a through hole.

18. The connector according to claim 13, further comprising: a plurality of first through holes located proximate the first edge and having a first diameter, wherein the first edge pins of the first subset are located within the plurality of first through holes; and A plurality of second through holes are located proximate to the first edge and have a second diameter different from the first diameter, wherein the first edge pins of the second subset are located within the plurality of second through holes.

19. The connector according to claim 18, further comprising: a plurality of first through holes located proximate the second edge and having a first diameter, wherein the second edge pins of the first subset are located within the plurality of first through holes; and A plurality of second through holes are located proximate to the second edge and have a second diameter different from the first diameter, wherein the second edge pins of the second subset are located within the plurality of second through holes.

20. The connector according to claim 12, further comprising: A plurality of port terminals are connected to the substrate and configured to engage with a housing of an external connector.

21. The connector according to claim 20, wherein: Each of the plurality of substrates includes a conductive trace coupled to one of the plurality of port terminals, wherein the first edge pin and the second edge pin couple the conductive trace to a downstream magnetic element.

22. The connector according to claim 21, wherein The number of the plurality of port terminals is four, six or eight, and The external connector is an RJ45 connector.

23. The connector of claim 13, wherein: Each pin in the first subset of first edge pins has a first predetermined offset relative to each pin in the second subset of first edge pins, wherein the first predetermined offset is a predetermined distance selected for optimal performance; and Each pin in the first subset of second edge pins has a second predetermined offset relative to each pin in the second subset of second edge pins, wherein the second predetermined offset is a predetermined distance selected for optimal performance.

24. A connector, comprising a substrate, the substrate comprising: A plurality of first edge pins are located near a first edge in a staggered arrangement, wherein a first subset of first edge pins are located at a first distance from the first edge, and a second subset of first edge pins are located at a second distance from the first edge that is different from the first distance.

Images