SiC MOSFET dual protection circuit based on di / dt detection

Abstract

The invention discloses a SiC MOSFET dual protection circuit based on di / dt detection, and the circuit comprises a current sampling module, the input end of the current sampling module is connected with the two ends of a parasitic inductor LSs, the auxiliary source electrode of a SiC MOSFET is grounded, the output end of the current sampling module is connected with the input end of a short-circuit fault judgment module and the input end of an overload fault judgment module, and the output end of the short-circuit fault judgment module is connected with the input end of the overload fault judgment module. The output end of the short circuit fault judgment module and the output end of the overload fault judgment module are connected with the input end of the fault signal latch module, the output end of the fault signal latch module is connected with the input end of the output stage and soft turn-off module, and the output end of the output stage and soft turn-off module is connected with the grid electrode of the SiC MOSFET. According to the SiC MOSFET dual protection circuit based on di / dt detection, reliable protection of hard switching faults, load short-circuit faults and overload faults of devices can be realized by using a single detection circuit, and the drive protection circuit has a soft turn-off function, so that the drive protection circuit is more comprehensive and effective, the service life of power devices is prolonged, and the reliability of a system is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of short circuit protection and relates to a method for i SiC MOSFET dual protection circuit with / dt detection. Background Art

[0002] Wide-bandgap power semiconductors such as silicon carbide (SiC) devices have larger bandgap widths and higher critical field strengths compared to traditional silicon-based metal-oxide semiconductor field-effect transistors (Si MOSFET) and insulated-gate bipolar transistors (IGBT), which make power semiconductors made from this material have excellent characteristics such as high withstand voltage, low on-resistance, and small parasitic parameters. However, due to the characteristics of small chip area, large short-circuit current, and concentrated heat generation, SiC MOSFET has a shorter short-circuit withstand time and weaker tolerance. The short-circuit withstand time of IGBT is generally 10us. Compared with traditional IGBT, the short-circuit withstand time of SiC MOSFET is generally only 3-4us. Usually, the action time of the driver chip is at the us level, which greatly increases the risk of reliable protection of SiC MOSFET. There is a high probability that the device cannot be reliably protected. On the other hand, the off-resistance value of SiC MOSFET during normal operation will affect the turn-off speed during short-circuit protection. A single off-resistance value cannot change the turn-off speed. The oscillation amplitude of the peak voltage during the turn-off process is uncontrollable and cannot reliably protect the device. Therefore, when designing the drive protection circuit, the detection and protection circuit response speed is required to be very fast to ensure that SiC MOSFET works within the safe working range.

[0003] At present, the short-circuit protection of SiC MOSFET is mostly directly borrowed from the short-circuit protection method of Si IGBT. From the detection principle, there are mainly the following short-circuit protection detection technologies for SiC MOSFET: desaturation detection, d i / dt detection, shunt detection, gate voltage detection, current sensor detection, etc. In the prior art, only a single protection function can be achieved by using one detection method, and it is impossible to achieve reliable protection of the device from hard switching faults, load short circuit faults and overload faults while ensuring the simplicity of the detection method. Summary of the invention

[0004] The object of the present invention is to provide a iThe dual protection circuit of SiC MOSFET with / dt detection solves the problem in the prior art that a single detection circuit cannot simultaneously achieve reliable protection of the device against hard switching faults, load short circuit faults and overload faults.

[0005] The technical solution adopted by the present invention is based on d i The dual protection circuit of SiC MOSFET with / dt detection includes a current sampling module, the input end of the current sampling module is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L Ss The two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module is respectively connected to the input end of the short-circuit fault judgment module and the input end of the overload fault judgment module, the output end of the short-circuit fault judgment module and the output end of the overload fault judgment module are connected to the input end of the fault signal latch module, the output end of the fault signal latch module is connected to the input end of the output stage and the soft shutdown module, and the output end of the output stage and the soft shutdown module is connected to the gate of the SiC MOSFET.

[0006] The present invention is also characterized in that: The current sampling module includes a current detection circuit and a reset circuit; The current detection circuit includes a capacitor C s , capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end is connected to the input end of the short-circuit fault judgment module and the input end of the overload fault judgment module; Resistor R s The other end is connected to the diode D iode Anode, resistor R g One end connected to resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s One end of the SiC MOSFET is connected to the power source.

[0007] The reset circuit includes a comparator A1, the positive input terminal of the comparator A1 is connected to a reference voltage V th1 Connect the negative input of comparator A1 to the input signal V INThe output end of the comparator A1 is connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the gate of the NMOS tube M1 and one end of the resistor R0, and the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, and the source of the NMOS tube M1 is connected to the capacitor C s One end, resistor R s One end, the input end of the short-circuit fault judgment module, and the input end of the overload fault judgment module are connected.

[0008] The short-circuit fault judgment module includes a comparator A2, the positive input terminal of the comparator A2 and the capacitor C s One end, the source of NMOS tube M1, resistor R s One end is connected to the input end of the overload fault judgment module, and the negative input end of the comparator A2 is connected to the reference voltage V th2 Connection: The output end of comparator A2 is connected to the input end of the fault signal latch module.

[0009] The overload fault judgment module includes a comparator A3, the positive input terminal of the comparator A3 and the capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of comparator A3 is connected to the reference voltage V th3 The output end of the comparator A3 is connected to the D end of the first trigger D1, the Q end of the first trigger D1 is connected to the D end of the second trigger D2, the Q end of the second trigger D2 is connected to the D end of the third trigger D3, the Q end of the third trigger D3 is connected to the three-input AND gate AND, and the output end of the three-input AND gate AND is connected to the input end of the fault signal latch module.

[0010] The input terminals of the three-input AND gate AND are connected to the Q terminal of the first trigger D1, the Q terminal of the second trigger D2, and the Q terminal of the third trigger D3 respectively; the Clk terminal of the first trigger D1, the Clk terminal of the second trigger D2, and the Clk terminal of the third trigger D3 are connected to the input signal V IN connect.

[0011] The first flip-flop D1 The second trigger D2 The third trigger D3 The end is connected to the output end of the inverter INV, and the input end of the inverter INV is connected to the input signal V IN Connect the RST end of the first trigger D1, the RST end of the second trigger D2, the RST end of the third trigger D3 and the reset signal V RST connect.

[0012] The fault signal latch module includes an OR gate OR, the input end of the OR gate OR is respectively connected to the output end of the comparator A2 and the output end of the three-input AND gate AND, the output end of the OR gate OR is connected to the D end of the latch D4, and the Q end of the latch D4 is connected to the input end of the output stage and the soft shutdown module.

[0013] The beneficial effects of the present invention are as follows: the present invention uses a single detection circuit to detect different types of short-circuit faults, namely hard switch faults and load short-circuit faults, and can also detect overload faults at the same time, and has a soft shutdown function, so that the drive protection circuit is more comprehensive and more effective, thereby improving the working life of the power device to increase the reliability of the system; the present invention can realize two protection mechanisms, which can not only realize fast and reliable protection for different types of short-circuit faults and overload faults, but also provide a gate drive chip for SiC MOSFET; the present invention solves the problem in the prior art that only a single protection function can be realized by using one detection method, and it is impossible to simultaneously realize reliable protection of the device against hard switch faults, load short-circuit faults and overload faults while ensuring the simplicity of the detection method. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The present invention is based on i / dt detection SiC MOSFET dual protection circuit structure block diagram; Figure 2 Based on d i Schematic diagram of the circuit structure of the SiC MOSFET dual protection circuit with / dt detection; Figure 3 Based on d i Schematic diagram of the circuit structure of the current sampling module in the SiC MOSFET dual protection circuit with / dt detection.

[0015] In the figure, 1. current sampling module; 110. current detection circuit; 120. reset circuit; 2. short circuit fault judgment module; 3. overload fault judgment module; 4. fault signal latch module; 5. output stage and soft shutdown module. DETAILED DESCRIPTION

[0016] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] Example 1 This embodiment proposes a method based on d i The SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, the input end of the current sampling module 1 is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L SsThe two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module 1 is respectively connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3, the output end of the short-circuit fault judgment module 2 and the output end of the overload fault judgment module 3 are connected to the input end of the fault signal latch module 4, the output end of the fault signal latch module 4 is connected to the input end of the output stage and soft shutdown module 5, and the output end of the output stage and the soft shutdown module 5 is connected to the gate of the SiC MOSFET.

[0018] Example 2 This embodiment proposes a method based on d i The SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, the input end of the current sampling module 1 is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L Ss The two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module 1 is respectively connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3, the output end of the short-circuit fault judgment module 2 and the output end of the overload fault judgment module 3 are connected to the input end of the fault signal latch module 4, the output end of the fault signal latch module 4 is connected to the input end of the output stage and soft shutdown module 5, and the output end of the output stage and the soft shutdown module 5 is connected to the gate of the SiC MOSFET.

[0019] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C s , capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected; the resistor R s The other end is connected to the diode D iode Anode, resistor R g One end connected to resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s One end of the SiC MOSFET is connected to the power source.

[0020] Example 3 This embodiment proposes a method based on d iThe SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, the input end of the current sampling module 1 is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L Ss The two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module 1 is respectively connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3, the output end of the short-circuit fault judgment module 2 and the output end of the overload fault judgment module 3 are connected to the input end of the fault signal latch module 4, the output end of the fault signal latch module 4 is connected to the input end of the output stage and soft shutdown module 5, and the output end of the output stage and the soft shutdown module 5 is connected to the gate of the SiC MOSFET.

[0021] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C s , capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected; the resistor R s The other end is connected to the diode D iode Anode, resistor R g One end connected to resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s The reset circuit 120 includes a comparator A1, the positive input terminal of the comparator A1 is connected to the reference voltage V th1 Connect the negative input of comparator A1 to the input signal V IN The output end of the comparator A1 is connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the gate of the NMOS tube M1 and one end of the resistor R0, and the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, and the source of the NMOS tube M1 is connected to the capacitor C s One end, resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected.

[0022] Example 4 This embodiment proposes a method based on d iThe SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, the input end of the current sampling module 1 is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L Ss The two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module 1 is respectively connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3, the output end of the short-circuit fault judgment module 2 and the output end of the overload fault judgment module 3 are connected to the input end of the fault signal latch module 4, the output end of the fault signal latch module 4 is connected to the input end of the output stage and soft shutdown module 5, and the output end of the output stage and the soft shutdown module 5 is connected to the gate of the SiC MOSFET.

[0023] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C s , capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected; the resistor R s The other end is connected to the diode D iode Anode, resistor R g One end connected to resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s The reset circuit 120 includes a comparator A1, the positive input terminal of the comparator A1 is connected to the reference voltage V th1 Connect the negative input of comparator A1 to the input signal V IN The output end of the comparator A1 is connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the gate of the NMOS tube M1 and one end of the resistor R0, and the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, and the source of the NMOS tube M1 is connected to the capacitor C s One end, resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected.

[0024] The short-circuit fault judgment module 2 includes a comparator A2, the positive input terminal of the comparator A2 and the capacitor C s One end, the source of NMOS tube M1, resistor Rs The negative input terminal of the comparator A2 is connected to the reference voltage V th2 The output terminal of the comparator A2 is connected to the input terminal of the fault signal latch module 4.

[0025] Example 5 This embodiment proposes a method based on d i The SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, the input end of the current sampling module 1 is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L Ss The two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module 1 is respectively connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3, the output end of the short-circuit fault judgment module 2 and the output end of the overload fault judgment module 3 are connected to the input end of the fault signal latch module 4, the output end of the fault signal latch module 4 is connected to the input end of the output stage and soft shutdown module 5, and the output end of the output stage and the soft shutdown module 5 is connected to the gate of the SiC MOSFET.

[0026] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C s , capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected; the resistor R s The other end is connected to the diode D iode Anode, resistor R g One end connected to resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s The reset circuit 120 includes a comparator A1, the positive input terminal of the comparator A1 is connected to the reference voltage V th1 Connect the negative input of comparator A1 to the input signal V IN The output end of the comparator A1 is connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the gate of the NMOS tube M1 and one end of the resistor R0, and the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, and the source of the NMOS tube M1 is connected to the capacitor Cs One end, resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected.

[0027] The short-circuit fault judgment module 2 includes a comparator A2, the positive input terminal of the comparator A2 and the capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of the comparator A2 is connected to the reference voltage V th2 The output terminal of the comparator A2 is connected to the input terminal of the fault signal latch module 4.

[0028] The overload fault judgment module 3 includes a comparator A3, the positive input terminal of the comparator A3 and the capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of the comparator A3 is connected to the reference voltage V th3 The output end of the comparator A3 is connected to the D end of the first trigger D1, the Q end of the first trigger D1 is connected to the D end of the second trigger D2, the Q end of the second trigger D2 is connected to the D end of the third trigger D3, the Q end of the third trigger D3 is connected to the three-input AND gate AND, and the output end of the three-input AND gate AND is connected to the input end of the fault signal latch module 4. The input ends of the three-input AND gate AND are respectively connected to the Q end of the first trigger D1, the Q end of the second trigger D2, and the Q end of the third trigger D3; the Clk end of the first trigger D1, the Clk end of the second trigger D2, and the Clk end of the third trigger D3 are connected to the input signal V IN Connection of the first flip-flop D1 The second trigger D2 The third trigger D3 The end is connected to the output end of the inverter INV, and the input end of the inverter INV is connected to the input signal V IN Connect the RST end of the first trigger D1, the RST end of the second trigger D2, the RST end of the third trigger D3 and the reset signal V RST connect.

[0029] Example 6 This embodiment proposes a method based on d i The SiC MOSFET dual protection circuit for / dt detection includes a current sampling module 1, the input end of the current sampling module 1 is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L SsThe two ends are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module 1 is respectively connected to the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3, the output end of the short-circuit fault judgment module 2 and the output end of the overload fault judgment module 3 are connected to the input end of the fault signal latch module 4, the output end of the fault signal latch module 4 is connected to the input end of the output stage and soft shutdown module 5, and the output end of the output stage and the soft shutdown module 5 is connected to the gate of the SiC MOSFET.

[0030] The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120; the current detection circuit 110 includes a capacitor C s , capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected; the resistor R s The other end is connected to the diode D iode Anode, resistor R g One end connected to resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s The reset circuit 120 includes a comparator A1, the positive input terminal of the comparator A1 is connected to the reference voltage V th1 Connect the negative input of comparator A1 to the input signal V IN The output end of the comparator A1 is connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the gate of the NMOS tube M1 and one end of the resistor R0, and the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, and the source of the NMOS tube M1 is connected to the capacitor C s One end, resistor R s One end, the input end of the short-circuit fault judgment module 2, and the input end of the overload fault judgment module 3 are connected.

[0031] The short-circuit fault judgment module 2 includes a comparator A2, the positive input terminal of the comparator A2 and the capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of the comparator A2 is connected to the reference voltage V th2 The output terminal of the comparator A2 is connected to the input terminal of the fault signal latch module 4.

[0032] The overload fault judgment module 3 includes a comparator A3, the positive input terminal of the comparator A3 and the capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of the comparator A3 is connected to the reference voltage V th3 The output end of the comparator A3 is connected to the D end of the first trigger D1, the Q end of the first trigger D1 is connected to the D end of the second trigger D2, the Q end of the second trigger D2 is connected to the D end of the third trigger D3, the Q end of the third trigger D3 is connected to the three-input AND gate AND, and the output end of the three-input AND gate AND is connected to the input end of the fault signal latch module 4. The input ends of the three-input AND gate AND are respectively connected to the Q end of the first trigger D1, the Q end of the second trigger D2, and the Q end of the third trigger D3; the Clk end of the first trigger D1, the Clk end of the second trigger D2, and the Clk end of the third trigger D3 are connected to the input signal V IN Connection of the first flip-flop D1 The second trigger D2 The third trigger D3 The end is connected to the output end of the inverter INV, and the input end of the inverter INV is connected to the input signal V IN Connect the RST end of the first trigger D1, the RST end of the second trigger D2, the RST end of the third trigger D3 and the reset signal V RST connect.

[0033] The fault signal latch module 4 includes an OR gate OR, the input end of the OR gate OR is respectively connected to the output end of the comparator A2 and the output end of the three-input AND gate AND, the output end of the OR gate OR is connected to the D end of the latch D4, and the Q end of the latch D4 is connected to the input end of the output stage and the soft shutdown module 5.

[0034] The present invention is based on i / dt detection of SiC MOSFET dual protection circuit, such as Figure 1 As shown, it includes a current sampling module 1, a short-circuit fault judgment module 2, an overload fault judgment module 3, a fault signal latch module 4, an output stage and a soft shutdown module 5, the output stage and the soft shutdown module 5 are connected to the gate G of the SiC MOSFET, the power source S of the SiC MOSFET is connected to the current sampling module 1, the auxiliary source s of the SiC MOSFET is grounded, and the parasitic inductance L in the current sampling module 1 is connected between the power source S of the SiC MOSFET and the auxiliary source s. Ss ; The current sampling module 1 includes a current detection circuit 110 and a reset circuit 120. The current detection circuit 110 is used to sample the current signal and convert the induced voltage on the SiC MOSFET parasitic inductance into current for short circuit protection and overload protection, while the reset circuit 120 can ensure that the detection voltage V test The change starts from zero when the SiC MOSFET is turned on, where the NMOS transistor M1 has sufficient current capability to ensure the normal triggering of the short-circuit protection and overload protection functions; The short-circuit fault judgment module 2 is used to judge whether the SiC MOSFET has a hard switch fault or a load short-circuit fault, thereby judging whether a short-circuit fault signal is generated; the overload fault judgment module 3 is used to judge whether the SiC MOSFET has an overload fault, thereby judging whether an overload fault signal is generated; the fault signal latch module 4 is used to receive short-circuit fault and overload fault signals. Regardless of the type of fault signal, once the fault signal is received, the module will be triggered to latch the signal to ensure that the fault signal is accurately input to the output stage and soft shutdown module 5; the output stage and soft shutdown module 5 are used to control the opening and closing of the SiC MOSFET. When the fault signal of the fault signal latch module 4 is received, the drive signal becomes a soft shutdown signal that turns off the power switch to reduce the overcurrent fault voltage spike and achieve fast and reliable protection; otherwise, the output stage and soft shutdown module 5 maintain normal operation.

[0035] like Figure 2 As shown, the current sampling module 1 includes a parasitic inductance L Ss , resistor R0, resistor R g , resistor R s , capacitor C0, capacitor C s 、Diode D iode , NMOS tube M1 and comparator A1, capacitor C s One end is connected with parasitic inductance L Ss One end of the SiC MOSFET, the auxiliary source s of the SiC MOSFET and the drain of the NMOS tube M1, the capacitor C s The other end is connected to a resistor R s The source of NMOS tube M1, the positive input terminal of comparator A2 and the positive input terminal of comparator A3, and capacitor C s Connected with resistor R s The positive input terminal of the comparator A2 and the positive input terminal of the comparator A3 are the output terminal V of the current sampling module 1. test , resistor R s The other end is connected to a diode D iode The anode and resistor R g One end of the resistor R g The other end is connected to a diode D iodeThe cathode and parasitic inductance L Ss The other end of the NMOS tube M1 is connected to the power source S of the SiC MOSFET, the gate of the NMOS tube M1 is connected to one end of the capacitor C0 and one end of the resistor R0, the other end of the resistor R0 is grounded, the other end of the capacitor C0 is connected to the output end of the comparator A1, and the positive input end of the comparator A1 is connected to the reference voltage V th1 , the negative input terminal is connected to the input signal V IN .

[0036] The short-circuit fault judgment module 2 includes a comparator A2, the positive input terminal of the comparator A2 is the input terminal of the short-circuit fault judgment module 2, and is connected to the output terminal V of the current sampling module 1. test The positive input of comparator A3 and the negative input of comparator A2 are connected to the reference voltage V th2 , the output terminal V of comparator A2 Fault_SC It is a short circuit fault signal.

[0037] The overload fault judgment module 3 includes a comparator A3, a first trigger D1, a second trigger D2, a third trigger D3, an inverter INV, and a three-input AND gate AND. The positive input terminal of the comparator A3, i.e., the input terminal of the overload fault judgment module 3, is connected to the output terminal V of the current sampling module 1. test The negative input terminal of the comparator A3 is connected to the reference voltage V th3 , the output terminal V of comparator A3 fault_OL The D terminal of the first trigger D1 is connected, and the Clk terminal of the first trigger D1 is connected to the Clk terminal of the second trigger D2, the Clk terminal of the third trigger D3, the input terminal of the inverter INV and the input signal V IN , the first flip-flop D1 The second trigger D2 is connected to the The third trigger D3 The RST terminal of the first trigger D1 is connected to the RST terminal of the second trigger D2, the RST terminal of the third trigger D3 and the reset signal V RST The Q end of the first trigger D1 is connected to the D end of the second trigger D2 and the first input end Q1 of the three-input AND gate AND, the Q end of the second trigger D2 is connected to the D end of the third trigger D3 and the second input end Q2 of the three-input AND gate AND, the Q end of the third trigger D3 is connected to the third input end Q3 of the three-input AND gate AND, and the output end V Fault_OL Connected to the input end of the fault signal latch module 4.

[0038] The fault signal latch module 4 includes an OR gate OR and a latch D4. The input end of the OR gate OR is connected to the output end V of the short-circuit fault judgment module 2.Fault_SC The other input end is connected to the output end V of the overload fault judgment module 3. Fault_OL , the output terminal V of the OR gate Fault The D end of the latch D4 is connected, and the Q end of the latch D4 is connected to the output stage and the soft shutdown module 5. The output stage and the soft shutdown module 5 are connected to the gate G of the SiC MOSFET.

[0039] like Figure 3 As shown, the current sampling module 1 is composed of a current detection circuit 110 and a reset circuit 120. The current detection circuit 110 includes a parasitic inductance L Ss , capacitor C s , resistor R s , resistor R g 、Diode D iode , capacitor C s One end is connected with parasitic inductance L Ss One end of the SiC MOSFET, the auxiliary source s of the SiC MOSFET and the drain of the NMOS tube M1, the capacitor C s The other end is connected to a resistor R s one end of the resistor R, the source of the NMOS tube M1, the input end of the short-circuit fault judgment module 2 and the input end of the overload fault judgment module 3; s The other end is connected to a diode D iode The anode and resistor R g One end of the resistor R g The other end is connected to a diode D iode The cathode and parasitic inductance L Ss The other end of the reset circuit 120 is connected to the power source S of the SiC MOSFET; the reset circuit 120 includes a comparator A1, a capacitor C0, a resistor R0 and an NMOS tube M1, and the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, the parasitic inductor L Ss One end and capacitor C s The source of NMOS tube M1 is connected to capacitor C s One end of the resistor R s The gate of the NMOS tube M1 is connected to one end of the capacitor C0 and one end of the resistor R0, the other end of the resistor R0 is grounded, the other end of the capacitor C0 is connected to the output end of the comparator A1, and the positive input end of the comparator A1 is connected to the reference voltage V th1 , the negative input terminal is connected to the input signal V IN , a parasitic inductance L is connected between the power source S and the auxiliary source s of the SiC MOSFET Ss , the auxiliary source s of the SiC MOSFET is grounded.

[0040] The current detection circuit 110 of the present invention detects the parasitic inductance L between the power source electrode S and the auxiliary source electrode s. Ss The induced voltage on the overcurrent fault can be integrated to obtain the measured d I D / dt returns to a sharply rising current I D , the actual detection is the fault current level. If most of the short-circuit circuit frequency components are higher than the filter cutoff frequency f c , the current flowing through SiCMOSFETT will be sampled by the sampling capacitor C s The voltage signal on the D Proportional to the detection voltage V test The role of the diode is to use its unidirectional conductivity to avoid the sampling capacitor C caused by the uncertainty of the load short circuit fault. s The reset circuit 120 can ensure that the detection voltage V test The change starts from zero when the SiC MOSFET is turned on, where the NMOS transistor M1 has sufficient current capability to ensure the normal triggering of the short-circuit protection and overload protection functions.

[0041] Overcurrent fault detection signal V test The short-circuit fault judgment module 2 is used as the input signal of the module, and the detection voltage V test With short-circuit fault reference voltage V th2 For comparison, if V test Greater than V th2 , it indicates that a short circuit fault has occurred in the system, and a high-level short-circuit fault signal V is output. Fault_SC .

[0042] Similarly, the overcurrent fault detection signal V test The overload fault judgment module 3 is input as one of the input signals of the module, and the detection voltage V test With overload fault reference voltage V th3 For comparison, if V test Greater than V th3 , then the high level overload judgment signal V is output fault_OL Under the action of the rising edge of the input voltage VIN, that is, the rising edge of the CIK signal, the overload judgment signal V fault_OLThe output voltage of the first trigger D1 is transmitted to the output terminal Q of the first trigger D1, which is recorded as Q1; the output voltage of the first trigger D1 is transmitted to the output terminal Q of the second trigger D2 through the second trigger D2, which is recorded as Q2; the output voltage of the second trigger D2 is transmitted to the output terminal Q of the third trigger D3 through the third trigger D3, which is recorded as Q3. The output voltages of the first trigger D1, the second trigger D2, and the third trigger D3 are used as the three input terminals of the three-input AND gate AND. This process is to accumulate the overload judgment signal, that is, in the three consecutive turn-on cycles of the SiC MOSFET, if the overload judgment signal V fault_OL If all are high level, the output voltages of the first trigger D1, the second trigger D2, and the third trigger D3 are all high level, so that the output voltage of the three-input AND gate AND is the overload fault signal V Fault_OL From low level to high level, it is determined that the system has an overload fault and triggers the overload protection function. Reset signal V RST The high and low levels of the CLK signal can be ignored, and the output of the D flip-flop is initialized to make the output voltage Q low. The overload fault judgment module 3 uses three D flip-flops to detect three consecutive overload faults of the SiC MOSFET to avoid false triggering of the overload protection and increase the flexibility of the overload fault detection response speed.

[0043] Short circuit fault signal V Fault_SC and overload fault signal V Fault_OL The two fault signals are input into the fault signal latch module 4 as the two input signals of the module. The two fault signals are subjected to the OR logic operation of the OR gate and finally output the total fault signal V Fault That is, no matter a short circuit fault or an overload fault occurs, the total fault signal V can be triggered through the OR gate OR. Fault , and then transmit the signal to the latch D4 to latch the fault signal, ensuring that the fault signal is accurately input to the output stage and the soft shutdown module 5.

[0044] When the output stage and soft shutdown module 5 receives the fault signal from the fault signal latch module 4, the module uses logic control to change the drive signal into a soft shutdown signal that turns off the power switch, thereby reducing the overcurrent fault voltage spike and achieving fast and reliable protection. If no short circuit fault or overload fault occurs, the output stage and soft shutdown module 5 maintains normal operation, that is, outputs the drive signal during normal operation.

Claims

1. Based on d i / dt detection SiC MOSFET dual protection circuit, characterized in that: It comprises a current sampling module (1), wherein the input end of the current sampling module (1) is respectively connected to the parasitic inductance L Ss The two ends of the connection, the parasitic inductance L Ss The two ends of the current sampling module (1) are respectively connected to the power source and the auxiliary source of the SiC MOSFET, the auxiliary source of the SiC MOSFET is grounded, the output end of the current sampling module (1) is respectively connected to the input end of the short-circuit fault judgment module (2) and the input end of the overload fault judgment module (3), the output end of the short-circuit fault judgment module (2) and the output end of the overload fault judgment module (3) are connected to the input end of the fault signal latch module (4), the output end of the fault signal latch module (4) is connected to the input end of the output stage and soft shutdown module (5), and the output end of the output stage and soft shutdown module (5) is connected to the gate of the SiC MOSFET.

2. The method according to claim 1 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The current sampling module (1) comprises a current detection circuit (110) and a reset circuit (120); The current detection circuit (110) includes a capacitor C s , the capacitor C s One end is connected to the auxiliary source of SiC MOSFET and the parasitic inductance L Ss One end is connected to the capacitor C s The other end is connected to the source of NMOS tube M1 and resistor R s One end is connected to the input end of the short-circuit fault judgment module (2) and the input end of the overload fault judgment module (3); The resistor R s The other end is connected to the diode D iode Anode, resistor R g One end is connected; the resistor R g The other end is connected to the diode D iode The cathode and parasitic inductance L Ss Capacitor C is not connected to s One end of the SiC MOSFET is connected to the power source.

3. The method according to claim 2 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The reset circuit (120) comprises a comparator A1, wherein the positive input terminal of the comparator A1 is connected to a reference voltage V th1 Connect the negative input of the comparator A1 to the input signal V IN The output end of the comparator A1 is connected to one end of the capacitor C0, the other end of the capacitor C0 is connected to the gate of the NMOS tube M1 and one end of the resistor R0, and the other end of the resistor R0 is grounded; the drain of the NMOS tube M1 is connected to the auxiliary source of the SiC MOSFET, and the source of the NMOS tube M1 is connected to the capacitor C s One end, resistor R s One end, an input end of a short-circuit fault judgment module (2), and an input end of an overload fault judgment module (3) are connected.

4. The method according to claim 3 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The short-circuit fault judgment module (2) comprises a comparator A2, the positive input terminal of the comparator A2 is connected to a capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of the comparator A2 is connected to the input terminal of the overload fault judgment module (3), and the negative input terminal of the comparator A2 is connected to the reference voltage V th2 The output end of the comparator A2 is connected to the input end of the fault signal latch module (4).

5. The method according to claim 4 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The overload fault judgment module (3) comprises a comparator A3, the positive input terminal of the comparator A3 is connected to a capacitor C s One end, the source of NMOS tube M1, resistor R s The negative input terminal of the comparator A3 is connected to the input terminal of the short-circuit fault judgment module (2), and the negative input terminal of the comparator A3 is connected to the reference voltage V th3 The output end of the comparator A3 is connected to the D end of the first trigger D1, the Q end of the first trigger D1 is connected to the D end of the second trigger D2, the Q end of the second trigger D2 is connected to the D end of the third trigger D3, the Q end of the third trigger D3 is connected to a three-input AND gate AND, and the output end of the three-input AND gate AND is connected to the input end of the fault signal latch module (4).

6. The method according to claim 5 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The input terminals of the three-input AND gate AND are respectively connected to the Q terminal of the first trigger D1, the Q terminal of the second trigger D2, and the Q terminal of the third trigger D3; the Clk terminal of the first trigger D1, the Clk terminal of the second trigger D2, and the Clk terminal of the third trigger D3 are connected to the input signal V IN connect.

7. The method according to claim 6 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The first flip-flop D1 The second trigger D2 The third trigger D3 The end is connected to the output end of the inverter INV, and the input end of the inverter INV is connected to the input signal V IN Connect the RST end of the first trigger D1, the RST end of the second trigger D2, and the RST end of the third trigger D3 to the reset signal V RST connect.

8. The method according to claim 7 i / dt detection SiC MOSFET dual protection circuit, characterized in that: The fault signal latch module (4) comprises an OR gate OR, the input end of the OR gate OR is respectively connected to the output end of the comparator A2 and the output end of the three-input AND gate AND, the output end of the OR gate OR is connected to the D end of the latch D4, and the Q end of the latch D4 is connected to the input end of the output stage and soft shutdown module (5).

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