Driving circuit, driving method, driving device and motor

Abstract

The embodiment of the invention discloses a driving circuit, a driving method, a driving device and a motor. A signal processing module of the driving circuit is used for receiving and identifying a driving signal, and when the driving signal is a first type of signal, the signal processing module generates a first enable signal; when the driving signal is a second type signal, the signal processing module generates a second enable signal. A transmission module of the driving circuit is provided with a transmission input end, a transmission output end and an enabling end, the transmission input end is used for receiving the driving signal, the enabling end is electrically connected with the signal processing module, and the transmission module is used for transmitting the driving signal. When the enable end receives a first enable signal, the control transmission output end is used for outputting a driving signal; and when the second enable signal is received, the transmission output end is controlled to stop outputting the driving signal. The driving circuit does not respond to PWM signals with the duty ratio of 0% and 100%, the PWM signals with the duty ratio of 0.1%-99.9% can be normally transmitted, and the rotating speed of the motor is accurately controlled.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of motor technology, and in particular to a drive circuit, a drive method, a drive device and a motor. Background Art

[0002] The motor usually uses a PWM (Pulse width modulation) duty cycle signal as a speed regulation signal, and controls and adjusts the motor speed according to the different duty cycles of the PWM signal. Usually, when the duty cycle of the PWM signal is 0%, the motor does not rotate. As the duty cycle of the PWM signal gradually increases, the motor speed also increases until the duty cycle of the PWM signal is 100%, and the motor rotates at full speed and full duty cycle. There is a problem with the above-mentioned motor speed control method: when the PWM signal output by the current-stage DSP (Digital Signal Processor) control software has an abnormal long-term 100% duty cycle, the motor drive circuit cannot recognize the abnormal 100% duty cycle PWM signal, and thus cannot shut down the subsequent-stage motor in time, resulting in unexpected motor rotation.

[0003] Currently, PWM signals are generally processed to shield PWM signals with a duty cycle of 0% and 100%. However, when this method is used, PWM signals with a duty cycle of 0.1%-99.9% cannot be transmitted normally, and the PWM signal is distorted after passing through the amplification circuit, resulting in a difference between the actual speed of the motor and the expected speed. Summary of the invention

[0004] The object of the present invention is to provide a driving circuit, a driving method, a driving device and a motor, which do not respond to PWM signals with a duty cycle of 0% and 100%, can normally transmit PWM signals with a duty cycle of 0.1%-99.9%, and accurately control the speed of the motor.

[0005] In order to solve the above technical problems, the first aspect of the present invention provides a driving circuit applied to a motor, comprising:

[0006] A signal processing module, the signal processing module is used to receive a drive signal and identify the drive signal, when the drive signal is a first type of signal, the signal processing module generates a first enable signal; when the drive signal is a second type of signal, the signal processing module generates a second enable signal; a transmission module, having a transmission input end, a transmission output end and an enable end, the transmission input end is used to receive the drive signal, the enable end is electrically connected to the signal processing module, and the transmission module is used to transmit the drive signal; the enable end is configured to: when receiving the first enable signal, control the transmission output end to output the drive signal; when receiving the second enable signal, control the transmission output end to stop outputting the drive signal.

[0007] Optionally, the signal processing module includes an identification unit, the identification unit having an identification input terminal and an identification output terminal, the identification input terminal is used to receive the drive signal, and the identification output terminal is electrically connected to the enable terminal; the identification unit is used to receive the drive signal and identify the drive signal, when the drive signal is a first type of signal, the identification unit generates a first level signal, and the identification output terminal outputs the first level signal; when the drive signal is a second type of signal, the identification unit generates a second level signal, and the identification output terminal outputs a second level signal.

[0008] Optionally, the signal processing module also includes a reverse unit, the reverse unit having a reverse input terminal and a reverse output terminal, the reverse input terminal is electrically connected to the identification output terminal, and the reverse output terminal is electrically connected to the enable terminal; when the reverse input terminal receives the first level signal, the first enable signal is generated according to the first level signal, and the reverse output terminal outputs the first enable signal; when the reverse input terminal receives the second level signal, the second enable signal is generated according to the second level signal, and the reverse output terminal outputs the second enable signal.

[0009] Optionally, the signal processing module also includes a unidirectional unit, the identification unit is electrically connected to the reverse unit via the unidirectional unit, the unidirectional unit has a unidirectional input end and a unidirectional output end, the unidirectional input end is electrically connected to the identification output end, and the unidirectional output end is electrically connected to the reverse input end; when the unidirectional input end receives the first level signal, a first preset signal is generated according to the first level signal, and the unidirectional output end outputs the first preset signal; when the unidirectional input end receives the second level signal, a second preset signal is generated according to the second level signal, and the unidirectional output end outputs the second preset signal.

[0010] Optionally, the signal processing module also includes a discharge unit, the unidirectional unit is electrically connected to the reverse unit via the discharge unit, the discharge unit has a discharge input terminal, a ground terminal and a discharge output terminal, the discharge input terminal is electrically connected to the unidirectional output terminal, and the discharge output terminal is electrically connected to the reverse input terminal.

[0011] Optionally, the driving signal is a PWM duty cycle signal, and the identification unit is a falling edge identification unit.

[0012] A second aspect of the present invention further provides a driving circuit, applied to a motor, comprising:

[0013] A signal processing module, the signal processing module is used to receive a drive signal and identify the drive signal, when the drive signal is a first type of signal, the signal processing module generates a first enable signal; a transmission module, having a transmission input end, a transmission output end and an enable end, the transmission input end is used to receive the drive signal, the enable end is electrically connected to the signal processing module, the transmission module is used to transmit the drive signal; the enable end is used to receive the first enable signal, and control the transmission output end to output the drive signal according to the first enable signal.

[0014] A third aspect of the present invention further provides a driving method, applied to any of the above driving circuits, comprising:

[0015] Control the signal processing module to receive a driving signal and identify the driving signal, and if the driving signal is a first type of signal, generate a first enable signal, and if the driving signal is a second type of signal, generate a second enable signal;

[0016] The enable end of the signal transmission module is controlled to receive the first enable signal or the second enable signal, and according to the first enable signal or the second enable signal, it is determined whether to control the transmission output end to output the driving signal.

[0017] A fourth aspect of the present invention further provides a driving device, comprising any one of the above-mentioned driving circuits.

[0018] The fifth aspect of the present invention also provides a motor, comprising the above-mentioned driving device.

[0019] Compared with the related art, the present invention uses a signal processing module to identify the drive signal, generates a first enable signal when the drive signal is a first type signal, and generates a second enable signal when the drive signal is a second type signal. When the enable end of the transmission module receives the first enable signal, the transmission module can normally transmit the received drive signal; when the enable end of the transmission module receives the second enable signal, the transmission module cannot output the drive signal. With such a design, the 0.1%-99.9% duty cycle PWM signal that needs to be transmitted normally can be classified as a first type signal, and the 0% and 100% duty cycle PWM signals can be classified as second type signals. The state control is realized by the enable signal, the control logic is simplified, the stability is high, and it is not easily affected by the environment. The drive signal is directly output through the transmission module to drive the motor, and no filtering, shaping and amplification are required, and there is no problem of signal distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0021] Figure 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a driving circuit with an identification unit according to an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of a driving circuit with an inverting unit according to an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of a driving circuit with a unidirectional unit according to an embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of a driving circuit having a discharge unit according to an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of a driving circuit according to an embodiment of the present invention;

[0027] Figure 7 It is a flowchart of a driving method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it can be understood by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable readers to better understand the present invention. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present invention can be implemented.

[0029] In the embodiments of the present invention, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0030] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0031] In addition, the terms "installed", "set", "provided with", "opened", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] In addition, the terms "first", "second", etc. are mainly used to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, "plurality" means two or more.

[0033] At present, in order to solve the problem that the motor drive circuit cannot recognize the PWM signal with a duty cycle of 0% and 100%, the PWM square wave signal is usually high-pass filtered and shaped to obtain a standard PWM square wave, which can simultaneously shield the PWM signals with a duty cycle of 0% and 100%, thereby achieving no response to the duty cycle of 0% and 100%. However, this method cannot achieve the transmission of the PWM signal with a duty cycle of 0.1%-99.9%, because the transmission circuit of the PWM signal with a duty cycle of 0.1%-99.9% and the control circuit that does not respond to the PWM signal with a duty cycle of 0% and 100% use the same control loop, which causes the following technical problems:

[0034] 1. Since the selected RC high-pass filter circuit contains passive components such as resistors and capacitors, the shaping effect of the high-pass filter circuit on the PWM signal with a changing duty cycle is subject to the resistance and capacitance change characteristics of the resistors and capacitors at high and low temperatures, and the transmission range of the 0.1%-99.9% duty cycle PWM signal is limited at high and low temperatures. In other words, although the above setting can shield 0% and 100% duty cycle PWM signals at high and low temperatures and normal temperatures, it cannot normally transmit 0.1%-99.9% duty cycle PWM signals.

[0035] 2. When transmitting a 0.1%-99.9% duty cycle PWM signal, the above design is implemented by adding an RC high-pass filter to a proportional amplifier circuit. When the 20% duty cycle PWM signal input at the current stage is transmitted to the subsequent stage circuit through this circuit, the duty cycle output by the subsequent stage is not 20%, that is, it is impossible to achieve undistorted transmission of a 0.1%-99.9% duty cycle PWM signal.

[0036] In order to solve the above technical problems, an embodiment of the present invention provides a driving circuit, which is applied to a motor and does not respond to PWM signals with a duty cycle of 0% and 100%, but can normally transmit PWM signals with a duty cycle of 0.1%-99.9%. State control is achieved through an enable signal, and the control logic is simplified. The driving signal has high stability and is not easily affected by the environment. The driving signal is directly output through a transmission module to drive the motor, and no filtering, shaping and amplification are required, so there is no problem of signal distortion.

[0037] The implementation details of the driving circuit of this embodiment are described in detail below. The following content is only provided for easy understanding of the implementation details and is not necessary for implementing this solution.

[0038] See also Figure 1, the driving circuit 1000 applied to the motor provided in this embodiment includes: a signal processing module 1100 and a transmission module 1200, wherein the signal processing module 1100 is used to receive the driving signal and identify the driving signal, and when the driving signal is a first type of signal, the signal processing module 1100 generates a first enable signal. The transmission module 1200 is electrically connected to the signal processing module 1100, and when the transmission module 1200 receives the first enable signal, the transmission module 1200 can normally output the above-mentioned driving signal to control the speed of the motor. When the driving signal is a second type of signal, the signal processing module 1100 generates a second enable signal. When the transmission module 1200 receives the second enable signal, it cannot transmit the driving signal normally. In this way, the PWM signal with a duty cycle of 0.1%-99.9% can be set as the first type of signal, and the PWM signals with a duty cycle of 0% and 100% can be set as the second type of signal, thereby achieving no response to the PWM signals with a duty cycle of 0% and 100%, and normal transmission of the PWM signal with a duty cycle of 0.1%-99.9%.

[0039] In some embodiments, the signal processing module 1100 has a processing input terminal and a processing output terminal, and the processing input terminal is electrically connected to the front-stage circuit for receiving a PWM duty cycle signal as a driving signal. After receiving the PWM duty cycle signal, the signal processing module 1100 identifies the PWM duty cycle signal, and when it is identified that the received PWM duty cycle signal meets the preset first type of signal, a first enable signal is generated, and the first enable signal is sent to the transmission module 1200 through the processing output terminal. Similarly, when the driving signal is identified as a second type of signal, the second enable signal generated is also sent to the transmission module 1200 through the processing output terminal.

[0040] In some embodiments, the transmission module 1200 has a transmission input terminal, a transmission output terminal and an enable terminal. The transmission module 1200 receives the PWM duty cycle signal through the transmission input terminal and sends a corresponding control signal to the motor through the transmission output terminal. It can be understood that the enable terminal of the transmission module 1200 is electrically connected to the signal processing module 1100, for example, electrically connected to the processing output terminal, and the transmission input terminal is used to receive the first enable signal / second enable signal sent by the processing output terminal, and the first enable signal / second enable signal is used to control whether the transmission output terminal can normally output the PWM duty cycle signal.

[0041] In this way, when the driving signal is a 0.1%-99.9% duty cycle PWM signal, the signal processing module 1100 can provide a first enable signal to enable the transmission module 1200 to normally transmit the driving signal, and the driving signal can be normally transmitted to the subsequent circuit and drive the motor to rotate. When the driving signal is a 0% and 100% duty cycle PWM signal, the signal processing module 1100 outputs a second enable signal, so that the transmission module 1200 cannot transmit the driving signal to the subsequent circuit, thereby shielding the 0% and 100% duty cycle signals.

[0042] In some embodiments, the signal processing module 1100 may be a signal processing circuit unit composed of a plurality of different independent electronic devices, or a chip integrated with corresponding functions, or a circuit unit composed of separate electronic devices and chips.

[0043] See also Figure 2 In some embodiments, the signal processing module 1100 includes an identification unit 1110, and the identification unit 1110 has an identification input terminal and an identification output terminal, the identification input terminal is used to receive the driving signal, and the identification output terminal is electrically connected to the enabling terminal. It can be understood that at this time, the identification input terminal is the above-mentioned processing input terminal, and the identification output terminal can be regarded as the above-mentioned processing output terminal.

[0044] When the identification unit 1110 receives a driving signal and identifies that the driving signal is a first type of signal, the identification unit 1110 generates a first level signal, and then outputs the first level signal from the identification output terminal to the enable terminal. The first level signal can be used as a first enable signal to enable the transmission module 1200 to output the driving signal normally.

[0045] If the identification unit 1110 identifies that the driving signal is a second type of signal, the identification unit 1110 generates a second level signal, which can be used as a second enable signal, so that the transmission module 1200 cannot output the driving signal normally, thereby achieving no response to PWM signals with 0% and 100% duty cycles.

[0046] Exemplarily, the first level signal may be a high level signal, and the second level signal may be a low level signal. At this time, the enable terminal is set such that when a high level signal is received, the transmission module 1200 can normally output the drive signal, and when a low level signal is received, the transmission module 1200 cannot normally output the drive signal.

[0047] In some other examples, the first level signal may be a low level signal, and the second level signal may be a high level signal. Accordingly, the enable terminal is configured such that when a low level signal is received, the transmission module 1200 can normally output the drive signal, and when a high level signal is received, the transmission module 1200 cannot normally output the drive signal.

[0048] It can be understood that the high-level signal or the low-level signal can be set as the first enable signal to allow the transmission module 1200 to output a driving signal according to actual conditions, for example, it can be determined according to the specific model and type of the logic control device used as the transmission module 1200.

[0049] In some embodiments, the identification unit 1110 can be configured as a falling edge identification circuit. It is understood that PWM signals with a duty cycle of 0% and 100% do not have a falling edge, while PWM signals with a duty cycle of 0.1%-99.9% have a falling edge. Therefore, the falling edge identification circuit can accurately distinguish between the first type of signal (PWM signals with a duty cycle of 0.1%-99.9% with a falling edge) and the second type of signal (PWM signals with a duty cycle of 0% and 100% without a falling edge).

[0050] See also Figure 3 In some embodiments, the signal processing module 1100 further includes a reverse unit 1120, and the identification unit 1110 is electrically connected to the enable end of the transmission module 1200 via the reverse unit 1120. The reverse unit 1120 is used to reverse the level signal output by the identification unit 1110, for example, to reverse the high level to the low level, and reverse the low level to the high level.

[0051] The reverse unit 1120 has a reverse input terminal and a reverse output terminal, the reverse input terminal is electrically connected to the identification output terminal, and the reverse output terminal is electrically connected to the enable terminal. When the reverse input terminal receives a first level signal, the reverse unit 1120 performs reverse processing on the first level signal to form a first enable signal, and sends it to the enable terminal through the reverse output terminal, so that the transmission module 1200 can normally transmit the drive signal; when the reverse input terminal receives a second level signal, the reverse unit 1120 performs reverse processing on the second level signal to form a second enable signal, and sends it to the enable terminal through the reverse output terminal, so that the transmission module 1200 cannot send the drive signal.

[0052] For example, the transmission module 1200 can be set to transmit the driving signal normally when receiving a low-level enable signal, and cannot transmit the driving signal when receiving a high-level enable signal. When the first-level signal is a high-level signal and the second-level signal is a low-level signal, the first-level signal is converted to a low-level signal after passing through the reverse unit 1120, and the transmission module 1200 receives the low-level signal output by the reverse unit 1120, and can transmit the driving signal normally; and when the second-level signal is converted to a high-level signal after passing through the reverse unit 1120, the transmission module 1200 receives the high-level signal output by the reverse unit 1120, and cannot transmit the driving signal normally.

[0053] Optionally, the reverse unit 1120 may be a device with a reverse function such as a MOS tube, a bipolar transistor or an inverter logic chip, or a functional circuit formed by the coordination and connection of different devices, and the present invention does not make any specific limitation on this.

[0054] See also Figure 4 In some embodiments, the signal processing module 1100 further includes a unidirectional unit 1130, and the identification unit 1110 is electrically connected to the reverse unit 1120 via the unidirectional unit 1130. The unidirectional unit 1130 is used to make the first level signal / second level signal unidirectionally transmitted to avoid backflow, and at the same time, the first level signal / second level signal can also be properly processed.

[0055] The unidirectional unit 1130 has a unidirectional input terminal and a unidirectional output terminal, wherein the unidirectional input terminal is electrically connected to the identification output terminal, and the unidirectional output terminal is electrically connected to the reverse input terminal. When the unidirectional input terminal receives a first level signal, a first preset signal is generated according to the first level signal, and when a second level signal is received, a second preset signal is generated according to the second level signal.

[0056] In some examples, a PWM signal with a duty cycle of 0.1%-99.9% generates a high-level pulse signal (first level signal) after passing through the identification unit 1110. Since the pulse signal has a short duration, it is not suitable as a drive signal for the motor. Therefore, the high-level pulse signal can be rectified by the unidirectional unit 1130 to form a stable high-level signal (first preset signal). Similarly, PWM signals with a duty cycle of 0% and 100% generate a DC level signal (second level signal) after passing through the identification unit 1110, and form a stable low-level signal (second preset signal) after passing through the unidirectional unit 1130.

[0057] Optionally, the unidirectional unit 1130 may be a component with unidirectional conduction performance such as a diode or a thyristor, or a circuit including a unidirectional element, which is not specifically limited in the present invention.

[0058] See also Figure 5In some embodiments, the signal processing module 1100 further includes a discharge unit 1140, and the unidirectional unit 1130 is electrically connected to the reverse unit 1120 via the discharge unit 1140. When the driving signal is a DC level signal with a duty cycle of 0% and 100%, the unidirectional unit 1130 will store energy, and there may be a circuit overload. In addition, the stored energy may also cause the input signal at the reverse input end to be a high level signal when the driving signal is a duty cycle of 0% and 100%, which is an undesirable situation. Therefore, the energy stored in the unidirectional unit 1130 can be discharged through the discharge unit 1140, which not only plays a role in protecting the circuit, but also ensures that when the driving signal is a DC level signal with a duty cycle of 0% and 100%, the signal received by the reverse unit 1120 is a stable low level signal.

[0059] See also Figure 6 In some embodiments, the discharge unit 1140 includes a first resistor 1141 and a second resistor 1142, wherein a first end of the first resistor 1141 is electrically connected to the unidirectional output end, a second end of the first resistor 1141 is electrically connected to the reverse input end, a first end of the second resistor 1142 is electrically connected to the reverse input end, and a second end is grounded. Thus, the first end of the first resistor 1141 can be used as the discharge input end of the discharge unit 1140, the second end of the first resistor 1141 can be used as the discharge output end of the discharge unit 1140, and the second end of the second resistor 1142 can be used as the ground end of the discharge unit 1140.

[0060] In some embodiments, the signal processing module 1100 only recognizes and processes PWM signals with a duty cycle of 0.1%-99.9%, and does not respond to PWM signals with a duty cycle of 0% and 100%.

[0061] For example, when the identification unit 1110 identifies that the driving signal is a PWM signal with a duty cycle of 0.1%-99.9%, that is, a first type of signal, a first level signal is generated and sent to the unidirectional unit 1130. The subsequent functional units process and transmit the received signal accordingly. For the specific processing method and transmission process, please refer to the above content.

[0062] When the driving signal is a PWM signal with a duty cycle of 0% and 100%, since the driving signal does not conform to the preset first type of signal, the identification unit 1110 does not generate any signal, nor does it send any signal to subsequent functional units such as the unidirectional unit 1130. In this way, the PWM signals with a duty cycle of 0% and 100% can also be shielded.

[0063] Please see again Figure 6To further illustrate the core concept of the present invention, a specific driving circuit is introduced below. It should be noted that the driving circuit is only used as an example and does not constitute a limitation to the present invention.

[0064] The identification unit 1110, taking the falling edge identification unit as an example, includes a trigger U1, a resistor R1, a first capacitor C1 and a second capacitor C2. Among them, pin 1 of the trigger U1 is grounded, pin 2 is used as an identification input terminal for receiving a PWM signal, and pin 3 is used as an identification output terminal for outputting a first level signal / a second level signal. Pin 4 of the trigger U1 is connected to a 5V power supply, pin 5 is electrically connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded. Pin 6 and pin 7 of the trigger U1 are short-circuited and electrically connected to one end of the resistor R1 and one end of the second capacitor C2, the other end of the resistor R1 is connected to the 5V power supply, and the other end of the second capacitor C2 is grounded.

[0065] Optionally, the trigger U1 may be a chip with an edge trigger function, such as an RS trigger, a D trigger, or the like, or a circuit composed of discrete electronic devices.

[0066] The unidirectional input end of the unidirectional unit 1130 is electrically connected to the pin 3 for receiving the first level signal / the second level signal, and the unidirectional output end is electrically connected to one end of the first resistor 1141 (R2).

[0067] The discharge unit 1140 includes a first resistor 1141 (R2) and a second resistor 1142 (R3), the other end of the first resistor 1141 is electrically connected to one end of the second resistor 1142 and to the reverse input end of the reverse unit 1120, and the other end of the second resistor 1142 is grounded. The resistance values ​​of the resistor R1, the first resistor 1141 and the second resistor 1142 are 1KΩ-100KΩ.

[0068] The transmission module 1200 includes a logic control unit 1210, a drive unit 1220 and a power inverter unit 1230. The logic control end of the logic control unit 1210 is used to receive a PWM signal, and the reverse output end is electrically connected to the enable end of the logic control unit 1210. Exemplarily, when the enable end is at a high level, the output of the logic control unit 1210 is turned off, no signal is output, and the motor stops; when the enable end is at a low level, the logic control unit 1210 outputs a signal normally, and the output signal is processed in a preset form or according to a preset processing method to output a pulse signal.

[0069] The logic control unit 1210 further includes three ports HA, HB, and HC for receiving Hall input signals. The Hall signals are generally generated by Hall elements for detecting the speed of the motor.

[0070] It is understandable that the logic control unit 1210 also includes functional ports such as a brake terminal and a current limiting shutdown terminal, which can be used to shut down the subsequent stage output.

[0071] The power inverter unit 1230 can be a three-phase output unit, outputting U, V, and W phases respectively.

[0072] The control process of the above drive circuit is as follows:

[0073] Pin 2 of the trigger UI receives a PWM signal. If the PWM signal is a PWM signal with a duty cycle of 0.1%-99.9%, that is, a first type of signal, the trigger U1 generates a high-level pulse signal of a fixed time; if the PWM signal is a PWM signal with a duty cycle of 0% and 100%, the trigger U1 generates a constant low-level signal.

[0074] When the unidirectional unit 1130 receives a high-level pulse signal, the high-level pulse signal forms a constant high-level signal (i.e., the first preset signal) after passing through the unidirectional unit 1130's unidirectional conduction and energy storage. When the unidirectional unit 1130 receives a low-level signal, the low-level signal passes through the unidirectional unit 1130 and outputs a constant low-level signal.

[0075] When the unidirectional unit 1130 outputs a constant high-level signal, a low-level control signal is formed after passing through the reverse unit 1120. When the driving signal is a PWM signal with a duty cycle of 0% and 100%, the low-level signal output after passing through the unidirectional unit 1130 is discharged through the discharge unit 1140 to ensure that it is a low-level signal when input to the reverse unit 1120, and the reverse unit 1120 can convert the low-level signal into a high-level control signal.

[0076] In this way, when the PWM signal is a 0.1%-99.9% duty cycle signal, the low-level control signal generated by the above-mentioned signal processing module 1100 controls the enable end of the logic control unit 1210, so that the logic control unit 1210 outputs normally. In addition, the PWM signal with a duty cycle of 0.1%-99.9% received by the logic control unit 1210 is not affected by the signal processing module 1100, so that the PWM signal with a duty cycle of 0.1%-99.9% can be transmitted without distortion, thereby ensuring that it is not affected by temperature changes. When the PWM signal is a DC level with a duty cycle of 0% and 100%, a high-level control signal is generated through the signal processing module 1100 to control the enable end of the logic control unit 1210, so that the output of the logic control unit 1210 is turned off, reaching no response at a duty cycle of 0% and 100%, and the motor is turned off.

[0077] The second aspect of the present invention further provides a driving device, which includes a driving circuit 1000. The driving device may be a device or component such as a circuit module or chip provided with the driving circuit 1000, and the present invention does not specifically limit this.

[0078] The third aspect of the present invention further provides a motor, comprising the above-mentioned drive device. Optionally, the motor can be a brushless motor, a brushed motor, a DC motor, an AC motor, etc., which can achieve speed control through the drive device, and the present invention does not make specific limitations here.

[0079] See also Figure 7 The fourth aspect of the present invention further provides a driving method, comprising:

[0080] S100. The control signal processing module receives the driving signal and identifies the driving signal. If the driving signal is a first type of signal, a first enable signal is generated. If the driving signal is a second type of signal, a second enable signal is generated.

[0081] S200. The enable end of the control signal transmission module receives the first enable signal or the second enable signal, and determines whether to control the transmission output end to output a driving signal according to the first enable signal or the second enable signal.

[0082] For step S100, it can be understood that the signal processing module can be any one of the signal processing modules of the first aspect mentioned above. When the signal processing module 1100 receives a driving signal (such as a PWM signal), it identifies the driving signal and then processes and transmits the signal in sequence.

[0083] In some embodiments, when the signal processing module 1100 includes an identification unit 1110, the identification unit 1110 can identify the received driving signal, and when the driving signal is a PWM signal with a duty cycle of 0.1%-99.9%, a first level signal is generated to control the transmission module 1200 to normally output the driving signal; when the driving signal is a PWM signal with a duty cycle of 0% and 100%, a second level signal is generated to control the transmission module 1200 to stop outputting the driving signal. In this way, the first level signal is used as the first enable signal and the second level signal is used as the second enable signal, so that the PWM signal with a duty cycle of 0.1%-99.9% can be transmitted normally, and the PWM signal with a duty cycle of 0% and 100% can be shielded.

[0084] In some embodiments, when the signal processing module 1100 includes a reverse unit 1120, the identification unit 1110 is electrically connected to the transmission module 1200 via the reverse unit 1120, and the reverse unit 1120 can reversely process the level signal generated by the identification unit 1110, and use the signal obtained after the reverse processing to control the transmission module 1200. For example, when the first level signal received by the reverse unit 1120 is a high level signal, the reverse unit 1120 can generate a low level signal, and use the low level signal as a first enable signal to control the transmission module 1200 to normally transmit the drive signal; when the second level signal received by the reverse unit 1120 is a low level signal, the unidirectional unit 1120 can generate a high level signal, and use the high level signal as a second enable signal to control the transmission module 1200 to stop transmitting the drive signal.

[0085] Of course, in some other examples, a high-level signal may be used to control the transmission module 1200 to normally transmit the driving signal, and a low-level signal may be used to control the transmission module 1200 to stop transmitting the driving signal.

[0086] In some embodiments, when the signal processing module 1100 includes a unidirectional unit 1130, the identification unit 1110 is electrically connected to the reverse unit 1120 via the unidirectional unit 1130, and the unidirectional unit 1130 can process the level signal output by the identification unit 1110, such as rectifying, to form a preset signal. For example, in some instances, when the driving signal is a PWM signal with a duty cycle of 0.1%-99.9%, the identification unit 1110 generates a high-level pulse signal, and the high-level pulse signal can be converted into a constant high-level signal through the unidirectional unit 1130 to ensure the stability of the control of the motor speed.

[0087] In some embodiments, the signal processing unit 1110 includes a discharge unit 1140, and the unidirectional unit 1130 is electrically connected to the reverse unit 1120 through the discharge unit 1140. When the driving signal is a DC level signal with a duty cycle of 0% and 100%, the unidirectional unit 1130 will store energy, and there may be a circuit overload. In addition, the stored energy may also cause the input signal at the reverse input end to be a high level signal when the driving signal is a duty cycle of 0% and 100%, which is an undesirable situation. Therefore, the energy stored in the unidirectional unit 1130 can be discharged through the discharge unit 1140, which not only plays a role in protecting the circuit, but also ensures that when the driving signal is a DC level signal with a duty cycle of 0% and 100%, the signal received by the reverse unit 1120 is a stable low level signal.

[0088] For step S200, the signal transmission module can be any signal transmission module of the first aspect above. The specific working process can refer to the description of the first aspect above, which will not be elaborated here.

[0089] The driving circuit, driving method, driving device and motor provided in the embodiments of the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above implementation methods is only used to help understand the ideas of the present invention. There may be changes in the specific implementation methods and application scope. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A drive circuit, applied to a motor, characterized in that: include: A signal processing module, the signal processing module is used to receive a driving signal and identify the driving signal, when the driving signal is a first type of signal, the signal processing module generates a first enable signal; when the driving signal is a second type of signal, the signal processing module generates a second enable signal; The transmission module comprises a transmission input terminal, a transmission output terminal and an enable terminal, wherein the transmission input terminal is used to receive the driving signal, the enable terminal is electrically connected to the signal processing module, and the transmission module is used to transmit the driving signal; the enable terminal is configured to: when receiving the first enable signal, control the transmission output terminal to output the driving signal; when receiving the second enable signal, control the transmission output terminal to stop outputting the driving signal.

2. The driving circuit according to claim 1, characterized in that: The signal processing module comprises an identification unit, wherein the identification unit has an identification input terminal and an identification output terminal, wherein the identification input terminal is used to receive the driving signal, and the identification output terminal is electrically connected to the enabling terminal; The identification unit is used to receive the driving signal and identify the driving signal. When the driving signal is a first type of signal, the identification unit generates a first level signal, and the identification output terminal outputs the first level signal. When the driving signal is a second type of signal, the identification unit generates a second level signal, and the identification output terminal outputs the second level signal.

3. The driving circuit according to claim 2, characterized in that: The signal processing module further comprises a reverse unit, wherein the reverse unit has a reverse input terminal and a reverse output terminal, wherein the reverse input terminal is electrically connected to the identification output terminal, and the reverse output terminal is electrically connected to the enable terminal; When the reverse input terminal receives the first level signal, the first enable signal is generated according to the first level signal, and the reverse output terminal outputs the first enable signal; When the inverting input terminal receives the second level signal, the second enable signal is generated according to the second level signal, and the inverting output terminal outputs the second enable signal.

4. The driving circuit according to claim 3, characterized in that: The signal processing module further comprises a unidirectional unit, the identification unit is electrically connected to the reverse unit via the unidirectional unit, the unidirectional unit has a unidirectional input end and a unidirectional output end, the unidirectional input end is electrically connected to the identification output end, and the unidirectional output end is electrically connected to the reverse input end; When the unidirectional input terminal receives the first level signal, a first preset signal is generated according to the first level signal, and the unidirectional output terminal outputs the first preset signal; When the unidirectional input terminal receives the second level signal, a second preset signal is generated according to the second level signal, and the unidirectional output terminal outputs the second preset signal.

5. The driving circuit according to claim 4, characterized in that: The signal processing module also includes a discharge unit, the unidirectional unit is electrically connected to the reverse unit via the discharge unit, the discharge unit has a discharge input terminal, a ground terminal and a discharge output terminal, the discharge input terminal is electrically connected to the unidirectional output terminal, and the discharge output terminal is electrically connected to the reverse input terminal.

6. The driving circuit according to any one of claims 2 to 5, characterized in that: The driving signal is a PWM duty cycle signal, and the identification unit is a falling edge identification unit.

7. A drive circuit, applied to a motor, characterized in that: A signal processing module, the signal processing module is used to receive a driving signal and identify the driving signal, when the driving signal is a first type of signal, the signal processing module generates a first enabling signal; A transmission module, comprising a transmission input terminal, a transmission output terminal and an enable terminal, wherein the transmission input terminal is used to receive the driving signal, the enable terminal is electrically connected to the signal processing module, and the transmission module is used to transmit the driving signal; The enable end is used to receive the first enable signal and control the transmission output end to output the drive signal according to the first enable signal.

8. A driving method, applied to the driving circuit according to any one of claims 1 to 6, characterized in that: Control the signal processing module to receive a driving signal and identify the driving signal, and if the driving signal is a first type of signal, generate a first enable signal, and if the driving signal is a second type of signal, generate a second enable signal; The enable end of the signal transmission module is controlled to receive the first enable signal or the second enable signal, and according to the first enable signal or the second enable signal, it is determined whether to control the transmission output end to output the driving signal.

9. A driving device, characterized in that: include: A drive circuit as claimed in any one of claims 1 to 7.

10. A motor, characterized in that: include: A drive device as claimed in claim 9.

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