Touch detection method and touch detection circuit

Abstract

The invention provides a touch detection method and a touch detection circuit. The method comprises the steps that in the calibration process, the capacitance value of one or more of the multiple internal calibration capacitors is adjusted, so that the sum of the multiple internal calibration capacitors is equal to the external parasitic capacitance, or the multiple of the sum of the multiple internal calibration capacitors is equal to the external parasitic capacitance; in the scanning detection process, the following steps are executed: a, the external parasitic capacitor is charged to a working voltage; b, the external parasitic capacitor and the plurality of internal calibration capacitors participate in charge transfer and charge redistribution; c, enabling only a part of capacitors in the plurality of internal calibration capacitors and an internal integrating capacitor in the touch detection circuit to participate in an integrating process and charge redistribution; d, discharging the external parasitic capacitor and the plurality of internal calibration capacitors to the ground; and e, circulating the step a to the step d for a preset number of times.

Description

Technical Field

[0001] The present invention relates to the field of touch detection, and in particular to a low-cost touch detection circuit and method for improving the number of integration times and stability. Background Art

[0002] There are two types of touch detection circuits at present. The first type requires an external integral capacitor. The capacity of the external integral capacitor can be selected to be greater than 1nf, such as 2.2nf, 10nf, 33nf, etc. The larger the integral capacitor, the more times the integral is, and the better the stability of the touch system. However, the external integral capacitor will increase the cost for application developers, and the chip will have one less IO pin that can be used. It may be necessary to choose a chip with a larger package, which further increases the cost. The second type is a built-in integral capacitor, that is, an integral capacitor is integrated inside the chip. If the integrated capacitor is too small, the number of integral times will be reduced, the touch stability will be poor, and the anti-interference will be poor; if the integrated capacitor is too large, the chip cost will be very high. Summary of the invention

[0003] In order to overcome the defects of the prior art, the present invention proposes a low-cost touch detection circuit and method for improving the number of integration times and stability. The touch detection circuit can integrate the integration capacitor inside the chip, use the internal calibration capacitor and the external parasitic capacitor to transfer and redistribute the charge, and then a part of the internal calibration capacitor and the integration capacitor participate in the integration process, so as to achieve a larger number of integration times using a smaller integration capacitor, thereby improving the sensitivity and stability of touch without increasing the chip cost.

[0004] The present invention discloses a touch detection method, which includes but is not limited to the following steps:

[0005] Providing multiple internal calibration capacitors to the touch detection circuit;

[0006] During the calibration process, adjusting the capacitance value of one or more of the plurality of internal calibration capacitors so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance, or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance;

[0007] The following steps are performed during the scan detection process:

[0008] a. charging the external parasitic capacitor to the operating voltage;

[0009] b. The external parasitic capacitor and the plurality of internal calibration capacitors participate in charge transfer and charge redistribution;

[0010] c. allowing only a portion of the plurality of internal calibration capacitors and the internal integration capacitor in the touch detection circuit to participate in the integration process and charge redistribution;

[0011] d. The external parasitic capacitance and the plurality of internal calibration capacitors are discharged to ground;

[0012] e. Repeat steps a to d for a preset number of times.

[0013] In one embodiment, after step e, the method further comprises:

[0014] f. Sampling and analog-to-digital conversion of the output of the touch detection circuit.

[0015] In one embodiment, the calibration process further includes:

[0016] Determining whether the output voltage of the touch detection circuit is equal to a reference voltage;

[0017] If the output voltage is not equal to the reference voltage, the capacitance value of one or more of the plurality of internal calibration capacitors is adjusted until the output voltage is equal to the reference voltage.

[0018] In one embodiment, the preset number of times is four times.

[0019] In one embodiment, the reference voltage is half of the operating voltage.

[0020] In one embodiment, the reference voltage is one third of the operating voltage.

[0021] The present invention also provides a touch detection circuit, including but not limited to a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, multiple internal calibration capacitors, multiple calibration capacitor control switches, an internal integration capacitor, an operational amplifier, an analog-to-digital conversion circuit, an operating voltage and a reference voltage.

[0022] in:

[0023] A first end of the first switch is coupled to the working voltage, a second end of the first switch is coupled to a first end of the second switch, and a second end of the second switch is grounded;

[0024] A first end of the third switch is coupled to a first end of the second switch, a second end of the third switch is coupled to a first end of the fourth switch, and a second end of the fourth switch is grounded;

[0025] A first end of the fifth switch is coupled to the first end of the fourth switch, and a second end of the fifth switch is coupled to the negative input terminal of the operational amplifier;

[0026] The positive input terminal of the operational amplifier is coupled to the reference voltage;

[0027] Both ends of the internal integral capacitor and the sixth capacitor are connected in parallel between the negative input terminal and the output terminal of the operational amplifier;

[0028] A first end of the seventh switch is coupled to the output end of the operational amplifier, and a second end of the seventh switch is coupled to the input end of the analog-to-digital conversion circuit;

[0029] Each of the plurality of internal calibration capacitors is connected in series with one of the plurality of calibration capacitor control switches, and the series connection is connected in parallel between the second end of the third switch and the ground.

[0030] In one embodiment, the second end of the first switch is coupled to one end of an anti-interference resistor, the other end of the anti-interference resistor is coupled to a first end of an external parasitic capacitor, and the second end of the external parasitic capacitor is grounded.

[0031] In one embodiment, the touch detection circuit further includes a switch control module for controlling the opening and closing of each switch in the touch detection circuit.

[0032] In one embodiment, the touch detection circuit operates according to the following steps:

[0033] During the calibration process, adjusting the capacitance value of one or more of the plurality of internal calibration capacitors so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance, or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance;

[0034] During the scanning process, the following steps are performed:

[0035] a. closing the first switch and opening the other switches to charge the external parasitic capacitor to the operating voltage;

[0036] b. closing the third switch and the plurality of calibration capacitor control switches, and opening the other switches, so that the external parasitic capacitors and the plurality of internal calibration capacitors participate in charge transfer and charge redistribution;

[0037] c. closing a portion of the plurality of calibration capacitor control switches, closing the fifth switch, and opening the other switches, so that only a portion of the plurality of internal calibration capacitors and the internal integration capacitor participate in the integration process and charge redistribution;

[0038] d. closing the second switch, the third switch, and the plurality of calibration capacitor control switches, and opening the other switches, so that the external parasitic capacitor and the plurality of internal calibration capacitors are discharged to ground;

[0039] e. looping steps a to d for a preset number of times;

[0040] f. The seventh switch is closed and the other switches are opened, and the analog-to-digital conversion circuit performs sampling and analog-to-digital conversion.

[0041] In one embodiment, adjusting the capacitance value of one or more of the plurality of internal calibration capacitors so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance, or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance comprises the following steps:

[0042] The first switch is closed, and the other switches are opened, so that the working voltage charges the external parasitic capacitor to reach the working voltage;

[0043] The third switch and the plurality of calibration capacitor control switches are closed, and the other switches are opened, so that the external parasitic capacitor and the plurality of internal calibration capacitors perform charge redistribution;

[0044] The third switch, the multiple calibration capacitor control switches, and the fifth switch are closed, and the other switches are opened. The external parasitic capacitor, the multiple internal calibration capacitors, and the internal integration capacitor redistribute charges. The voltages across the external parasitic capacitor and the multiple internal calibration capacitors are clamped at the reference voltage. If the external parasitic capacitor is equal to the sum of the multiple internal calibration capacitors, the output voltage is equal to the reference voltage. If the external parasitic capacitor is not equal to the sum of the multiple internal calibration capacitors, the output voltage is not equal to the reference voltage. At this time, adjust the capacitance value of one or more of the multiple internal calibration capacitors until the output voltage is equal to the reference voltage.

[0045] In one embodiment, the reference voltage is half of the operating voltage.

[0046] In one embodiment, the reference voltage is one third of the operating voltage.

[0047] In one embodiment, the preset number of times is four times.

[0048] The touch detection circuit of the present invention integrates an integral capacitor inside a chip, uses an internal calibration capacitor and an external parasitic capacitor to transfer and redistribute charges, and then allows a portion of the internal calibration capacitor and the internal integral capacitor to participate in the integration process, thereby achieving a larger number of integration times using a smaller integral capacitor, thereby improving the sensitivity and stability of touch without increasing the cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above invention content and the following specific embodiments of the present invention will be better understood when read in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are only examples of the claimed invention. In the accompanying drawings, the same reference numerals represent the same or similar elements.

[0050] Figure 1 A conventional touch detection circuit with built-in integral capacitor is shown;

[0051] Figure 2 A touch detection circuit according to an embodiment of the present invention is shown;

[0052] Figure 3 A touch detection circuit according to an embodiment of the present invention is shown;

[0053] Figure 4 A touch detection circuit according to an embodiment of the present invention is shown;

[0054] Figure 5 A system detection flow chart according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0055] The detailed features and advantages of the present invention are described in detail in the specific embodiments below, and the content is sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly, and according to the description, claims and drawings disclosed in this specification, those skilled in the art can easily understand the relevant purposes and advantages of the present invention. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this embodiment. On the contrary, the purpose of introducing the invention in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, many specific details will be included in the following description. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description.

[0056] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, channels, components, regions, layers and / or parts, these components, channels, components, regions, layers and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, channels, components, regions, layers and / or parts. In addition, the terms "first", "second", "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0058] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0059] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0060] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0061] There are two types of touch detection circuits at present. The first type requires an external integral capacitor. The capacity of the external integral capacitor can be selected to be greater than 1nf, such as 2.2nf, 10nf, 33nf, etc. The larger the integral capacitor, the more times the integral is applied, and the better the stability of the touch system. However, the external integral capacitor will increase the cost for application developers, and the chip will have one less IO pin that can be used. It may be necessary to choose a chip with a larger package, which further increases the cost. The second type is a built-in integral capacitor, that is, an integral capacitor for touch detection is integrated inside the chip. If the integrated capacitor is too small, the number of integrals will be reduced, the touch stability will be poor, and the anti-interference will be poor; if the integrated capacitor is too large, the chip cost will be very high.

[0062] In order to overcome the defects of the prior art, the present invention proposes a low-cost touch detection circuit that improves the number of integration times and stability. This solution can integrate the integration capacitor inside the chip, use internal calibration capacitors and external parasitic capacitors to transfer and redistribute charge, and then a part of the internal calibration capacitor and the integration capacitor participate in the integration process, thereby achieving a larger number of integration times using a smaller integration capacitor, thereby improving the stability of the touch.

[0063] Figure 1 Schematic diagram of a conventional touch detection circuit with a built-in integral capacitor, wherein Cj is an integral capacitor, VDD is an operating voltage, and Cx is an external parasitic capacitor.

[0064] The working process of the touch detection circuit is as follows:

[0065] 1. VDD charges the external parasitic capacitor Cx to reach VDD

[0066] 2. Cx and C S Charge redistribution

[0067] 3.Cx, Cj, Cs redistribute the charge, Cx and C S The voltage will be clamped at VDD / 2. If Cx = Cs, the charge on Cj will not change, the output sampling voltage will not change, and the output reference voltage will not change. If Cx is not equal to C S , then the charge of Cj will change, resulting in a change in the output sampling voltage, and the output voltage will be greater or less than the reference voltage.

[0068] 4. If the output voltage is not equal to the reference voltage, adjust C S Repeat the process 1-3 until the output voltage is equal to the reference voltage. At this time, Cx = C S , calibration is completed.

[0069] 5. After calibration, normal scanning begins. When a finger is pressed, assuming that the equivalent capacitance of the finger is Cp, VDD charges Cx and Cp to reach VDD, Q = VDD*(Cx+Cp), Cx, Cp, CS, Cj redistribute the charge, and after balancing, the voltage of Cx, Cp, CS is clamped to VDD / 2. The charge change ΔQ = VDD*(Cx+Cp)-VDD / 2(Cx+Cp+CS). Since Cx = C S Therefore, ΔQ=VDD*CP / 2, that is, the charge of VDD*CP / 2 is distributed to Cj. Repeating this process N times, there will be continuous charge distributed to Cj, which will cause the output voltage to change, thereby performing touch recognition.

[0070] The shortcomings of this solution are as follows:

[0071] Due to the limitation of the size of Cj capacitor, the charge Q transmitted each time is Q = VDD*CP / 2, and the charge Q1 transmitted N times is Q = N*VDD*CP / 2; so the number of N cannot be too large, that is, the number of integration times cannot be too large, otherwise the voltage will easily reach the maximum value of the sampling, affecting normal touch. However, if N is too small, that is, the number of integration times is too small, it will affect the stability of the touch and the anti-interference will be poor.

[0072] In order to increase the number of integration times, the present invention has made improvements on the basis of the above circuit. Figure 2 .

[0073] Figure 2 A touch detection circuit according to an embodiment of the present invention is shown. The touch detection circuit includes a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, a plurality of internal calibration capacitors CS1, CS2, ... CSn, a plurality of calibration capacitor control switches Kcs1, Kcs2, ... Kcsn, an internal integration capacitor Cj, an operational amplifier OP, an analog-to-digital conversion circuit, an operating voltage VDD, and a reference voltage VREF.

[0074] A first end of the first switch K1 is coupled to the working voltage VDD, a second end of the first switch K1 is coupled to a first end of the second switch K2, and a second end of the second switch K2 is grounded;

[0075] A first end of the third switch K3 is coupled to a first end of the second switch K2, a second end of the third switch K3 is coupled to a first end of the fourth switch K4, and a second end of the fourth switch K4 is grounded;

[0076] A first end of the fifth switch K5 is coupled to a first end of the fourth switch K4, and a second end of the fifth switch K5 is coupled to a negative input end of the operational amplifier OP;

[0077] The positive input terminal of the operational amplifier OP is coupled to the reference voltage;

[0078] Both ends of the internal integral capacitor Cj and the sixth capacitor K6 are connected in parallel between the negative input terminal and the output terminal of the operational amplifier OP;

[0079] A first end of the seventh switch K7 is coupled to the output end of the operational amplifier OP, and a second end of the seventh switch K7 is coupled to the input end of the analog-to-digital conversion circuit;

[0080] Each of the plurality of internal calibration capacitors CS1, CS2, ... CSn is connected in series with one of the plurality of calibration capacitor control switches Kcs1, Kcs2, ... Kcsn, and then connected in parallel between the second end of the third switch K3 and the ground.

[0081] A second end of the first switch K1 is coupled to one end of the external anti-interference resistor Rx, the other end of the external anti-interference resistor Rx is coupled to a first end of the external parasitic capacitor Cx, and a second end of the external parasitic capacitor is grounded.

[0082] In one embodiment, the external parasitic capacitance Cx represents the equivalent parasitic capacitance of the touch channel and the PCB.

[0083] In one embodiment, the reference voltage VREF is VDD / 2.

[0084] In one embodiment, the reference voltage VREF is VDD / 3.

[0085] It should be pointed out that those skilled in the art should understand that the value of the reference voltage VREF is not limited to the above values, and the value of the reference voltage can be designed according to actual needs.

[0086] In one embodiment, the touch detection circuit of the present invention further includes a switch control module for controlling the opening and closing of each switch in the touch detection circuit.

[0087] In one embodiment, the touch detection circuit of the present invention further includes a judgment module, which is used to judge whether the output of the analog-to-digital conversion circuit is equal to a reference voltage VREF.

[0088] The working process of the touch detection circuit is as follows:

[0089] During the calibration process, adjusting the capacitance value of one or more of the plurality of internal calibration capacitors CS1, CS2, ... CSn so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance (Cx = CS1 + CS2 + ... CSn), or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance (Cx = N*(CS1 + CS2 + ... CSn), N>0);

[0090] During the scanning process, the following steps are performed:

[0091] a. The first switch K1 is closed, and the other switches are opened, so that the external parasitic capacitor Cx is charged to the operating voltage VDD;

[0092] b. The third switch K3 and the plurality of calibration capacitor control switches Kcs1, Kcs2, ... Kcsn are closed, and the other switches are opened, and the external parasitic capacitor Cx and the plurality of internal calibration capacitors CS1, CS2, ... CSn participate in charge transfer and charge redistribution;

[0093] c. closing some of the multiple calibration capacitor control switches Kcs1, Kcs2, ... Kcsn, closing the fifth switch K5, and opening the other switches, so that only some of the multiple internal calibration capacitors and the internal integration capacitor Cj participate in the integration process and charge redistribution;

[0094] d. The second switch K2, the third switch K3, and the plurality of calibration capacitor control switches Kcs1, Kcs2, ... Kcsn are closed, and the other switches are opened, and the external parasitic capacitor Cx and the plurality of internal calibration capacitors CS1, CS2, ... CSn are discharged to the ground GND;

[0095] e. looping steps a to d for a preset number of times;

[0096] f. The seventh switch K7 is closed, and the other switches are opened, and the analog-to-digital conversion circuit performs sampling and analog-to-digital conversion.

[0097] In one embodiment, the preset number of times may be four times.

[0098] In one embodiment, the calibration process may include the following steps:

[0099] The first switch K1 is closed, and the other switches are opened, so that the working voltage VDD charges the external parasitic capacitor Cx to reach the working voltage VDD;

[0100] The third switch K3 and the plurality of calibration capacitor control switches Kcs1, Kcs2, ... Kcsn are closed, and the other switches are opened, and the external parasitic capacitor Cx and the plurality of internal calibration capacitors CS1, CS2, ... CSn are charged and redistributed;

[0101] The third switch K3, the multiple calibration capacitor control switches CS1, CS2, ... CSn, and the fifth switch K5 are closed, and the other switches are opened. The external parasitic capacitor Cx, the multiple internal calibration capacitors CS1, CS2, ... CSn, and the internal integration capacitor Cj redistribute the charge. The voltage across the external parasitic capacitor Cx and the multiple internal calibration capacitors CS1, CS2, ... CSn is clamped at the reference voltage VREF. If the external parasitic capacitor Cx is equal to the sum of the multiple internal calibration capacitors CS1, CS2, ... CSn, the output voltage is equal to the reference voltage VREF; if the external parasitic capacitor Cx is not equal to the sum of the multiple internal calibration capacitors CS1, CS2, ... CSn, the output voltage is not equal to the reference voltage VREF. At this time, the capacitance value of one or more of the multiple internal calibration capacitors CS1, CS2, ... CSn is adjusted until the output voltage is equal to the reference voltage VREF.

[0102] Figure 3The touch detection circuit according to an embodiment of the present invention is shown. There are two internal calibration capacitors: a first internal calibration capacitor CS1 and a second internal calibration capacitor CS2. The first internal calibration capacitor CS1 is connected in series with a switch Kcs1, and the second internal calibration capacitor CS2 is connected in series with a switch Kcs2. The reference voltage VREF is VDD / 2.

[0103] The working process of the touch detection circuit is as follows:

[0104] First, perform the calibration process:

[0105] 1. Switch K1 is closed, other switches are open, and VDD charges Cx to reach VDD.

[0106] 2. Switches K3, Kcs1, and Kcs2 are closed, and other switches are opened, and charge is redistributed between Cx and (CS1+CS2).

[0107] 3. Switches K3, Kcs1, Kcs2, and switch K5 are closed, and other switches are opened. Cx, CS1+CS2, and Cj redistribute the charge, and the voltage of Cx and (CS1+CS2) will be clamped at VDD / 2. If Cx=CS1+CS2, the charge on Cj will not change, the output sampling voltage will not change, and the output reference voltage will be changed; if Cx is not equal to CS1+CS2, the charge on Cj will change, resulting in a change in the output sampling voltage, and the output voltage will be greater than or less than the reference voltage.

[0108] 4. If the output voltage is not equal to the reference voltage, adjust the value of CS1, keep CS2 unchanged, and repeat the process of 1-3 until the output voltage is equal to the reference voltage. At this time, Cx = CS1 + CS2, and the calibration is completed.

[0109] After the calibration is completed, start the normal detection scan:

[0110] 5. Assume that the equivalent capacitance of the finger is Cp, switch K1 is closed, and other switches are open. VDD charges Cx and Cp to reach VDD. The total charge on Cx and Cp is Q = VDD*(Cx+Cp).

[0111] 6. Switches K3, Kcs1, and Kcs2 are closed, and other switches are opened. (Cx+Cp) and (CS1+CS2) are redistributed for charge. The charge on CS2 is Qcs2=VDD*(Cx+CP)*CS2 / (Cx+Cp+CS1+CS2). Since Cx=CS1+CS, Qcs2=VDD*(Cx+CP)*CS2 / (2Cx+Cp).

[0112] 7. Switches Kcs2 and K5 are closed, and other switches are opened. CS2 and Cj share the charge. Since the voltage is clamped to VDD / 2, part of the charge is transferred to Cj. The charge change on CS2 is:

[0113] VDD*(Cx+CP)*CS2 / (2Cx+Cp)-VDD*CS2 / 2

[0114] =(VDD / 2-VDD*Cx / (2Cx+Cp))*CS2

[0115] <(VDD / 2-VDD*Cx / 2(Cx+Cp))*CS2=VDD*CS2*Cp / 2(Cx+Cp)

[0116] <VDD*CS2*Cp / 2Cx=VDD*Cp*(CS2 / 2Cx);

[0117] That is, the charge transferred each time does not exceed VDD*Cp*(CS2 / 2Cx). If the value of CS2 is much smaller than Cx, then VDD*Cp(CS2 / 2Cx) is much smaller than VDD*Cp / 2; this can reduce the capacity of each charge transfer, thereby greatly increasing the number of charging times and improving the number of integration times.

[0118] Generally speaking, Cx is between 10pf and 30pf; Cp is between 0.1pf and 0.5pf; for example: Cx = 10pf, Cp = 0.5p, CS2 = 1pf; using the traditional method, the charge transferred each time is 0.5pf*VDD / 2; using the current detection method, the charge transferred each time is less than 0.5p*VDD*(1 / 20), that is, the charge transferred each time is less than 1 / 10 of the traditional method, which can greatly increase the number of integration times. For example: when Cx = 30pf, CS2 = 1pf, the charge transferred each time is less than 1 / 30 of the traditional method.

[0119] Figure 4 The touch detection circuit according to an embodiment of the present invention is shown. There are two internal calibration capacitors: a first internal calibration capacitor CS1 and a second internal calibration capacitor CS2. The first internal calibration capacitor CS1 is connected in series with a switch Kcs1, and the second internal calibration capacitor CS2 is connected in series with a switch Kcs2. The reference voltage VREF is VDD / 3.

[0120] The working process of the touch detection circuit is as follows:

[0121] 1. During the calibration process, the capacitance values ​​of the first internal calibration capacitor CS1 and the second internal calibration capacitor CS2 are adjusted so that Cx=2(CS1+CS2).

[0122] It should be noted that the external parasitic capacitance Cx here is twice the sum of CS1 and CS2. Those skilled in the art should understand that the external parasitic capacitance Cx can be other multiples of the sum of CS1 and CS2 according to actual applications.

[0123] After the calibration is completed, start the normal detection scan:

[0124] 2. Assume that the equivalent capacitance of the finger is Cp, switch K1 is closed, and other switches are open. VDD charges Cx and Cp to reach VDD. The total charge on Cx and Cp is Q = VDD*(Cx+Cp).

[0125] 3. Switches K3, Kcs1, and Kcs2 are closed, and other switches are opened, and (Cx+Cp) and (CS1+CS2) are redistributed. The charge on CS2 is Qcs2 = VDD*(Cx+CP)*CS2 / (Cx+Cp+CS1+CS2).

[0126] Since Cx=2(CS1+CS2), Qcs2=VDD*(Cx+CP)*CS2 / (3Cx / 2+Cp).

[0127] 4. Switches Kcs2 and K5 are closed, and other switches are opened. CS2 and Cj share the charge. Since the voltage needs to be clamped to VDD / 3, part of the charge is transferred to Cj. The charge change on CS2 is:

[0128] VDD*(Cx+CP)*CS2 / (3Cx / 2+Cp)-VDD*CS2 / 3

[0129] =(2VDD*(Cx+Cp) / (3Cx+2Cp)-VDD / 3)*CS2

[0130] <(2VDD*(Cx+Cp) / 3Cx-VDD / 3)*CS2

[0131] =VDD*CS2(Cx+2Cp) / 3Cx

[0132] Cx is between 10pf and 30pf; Cp is between 0.1pf and 0.5pf; for example: Cx = 10pf, Cp = 0.5p, CS2 = 1pf; using the traditional method, the charge transferred each time is 0.5pf*VDD / 2; using the current detection method, the charge transferred each time is less than 0.5p*VDD (22 / 90), which is about half of the traditional method. At the same time, since VREF = VDD / 3, the maximum charging voltage range is VDD-VDD / 3 = 2VDD / 3; in the traditional method, since VREF = VDD / 2, the maximum charging voltage range is VDD-VDD / 2 = VDD / 2; from the charging voltage range, the current detection method can support more charging times.

[0133] Figure 5 A system detection flow chart according to an embodiment of the present invention is shown.

[0134] Step 501: Start calibration scan.

[0135] Step 502: Determine whether the output voltage is equal to the reference voltage. If not, execute step 503; if yes, execute step 504.

[0136] Step 503 : Adjust the sizes of the internal calibration capacitors CS1 , CS2 , . . . CSn, and return to step 501 .

[0137] Step 504: Calibration ends.

[0138] Step 505: Start detection scanning.

[0139] Step 506: Determine whether the change in the output voltage is greater than a threshold value. If yes, execute step 507; if no, return to step 505.

[0140] Step 507: key processing.

[0141] Those skilled in the art will appreciate that the various illustrative components, modules, blocks, units, circuits, systems, and steps described in conjunction with the embodiments disclosed herein may be implemented by hardware, software (including firmware, resident software, microcode, etc.), or a combination of the two. To clearly illustrate this interchangeability of hardware and software, various illustrative components, modules, blocks, units, circuits, systems, and steps are described above in general terms in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the present invention.

[0142] Flowcharts are used in the present application to illustrate the operations or steps performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations or steps are not necessarily performed accurately in order. On the contrary, various operations or steps may be processed in reverse order or simultaneously. At the same time, other operations or steps may be added to these processes, or one or more operations or steps may be removed from these processes.

[0143] Unless explicitly stated in the claims, the order of the processing elements and sequences, the use of alphanumeric characters, or the use of other names described in the present application are not intended to limit the order of the processes and methods of the present application.

[0144] Furthermore, aspects of the present application may take the form of a computer product embodied in one or more computer-readable media including computer-readable program code.

[0145] A computer readable signal medium may include a propagated data signal containing computer program code, such as in baseband or as part of a carrier wave. The propagated signal may have a variety of forms, including electromagnetic, optical, etc., or a suitable combination. A computer readable signal medium may be any computer readable medium other than a computer readable storage medium, which may be connected to an instruction execution system, device or apparatus to communicate, propagate or transmit a program for use. The program code on the computer readable signal medium may be propagated through any suitable medium, including radio, cable, fiber optic cable, RF, or similar media, or any combination of the above media.

[0146] The computer program coding required for the operation of each part of the application can be written in any one or more programming languages, including object-oriented programming languages ​​such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc., conventional procedural programming languages ​​such as C language, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, dynamic programming languages ​​such as Python, Ruby and Groovy, or other programming languages, etc. The program coding can be run completely on the user's computer, or run on the user's computer as an independent software package, or run partly on the user's computer and partly on the remote computer, or run completely on the remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any network form, such as a local area network (LAN) or a wide area network (WAN), or connected to an external computer (e.g., via the Internet), or in a cloud computing environment, or used as a service such as software as a service (SaaS).

[0147] Those skilled in the art will appreciate that information, signals, and data may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips cited throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0148] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be directly embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read and write information from / to the storage medium. In an alternative, a storage medium may be integrated into a processor. In an alternative, a processor and a storage medium may reside in a user terminal as discrete components.

[0149] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented as a computer program product in software, each function may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a computer. As an example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer. Any connection is also properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, a server, or other remote source using a coaxial cable, a fiber optic cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, wherein disk often reproduces data magnetically, while disc reproduces data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0150] The terms and expressions used above are for descriptive purposes only, and the present invention should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

[0151] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus facilitate the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of this application, multiple features are sometimes combined into one embodiment, drawing or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims.

[0152] Similarly, it should be pointed out that although the present invention has been described with reference to the current specific embodiments, ordinary technicians in this technical field should realize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions may be made without departing from the spirit of the present invention. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the essential spirit of the present invention, they will fall within the scope of the claims of this application.

Claims

1. A touch detection method, characterized in that: The method comprises: Providing multiple internal calibration capacitors to the touch detection circuit; During the calibration process, adjusting the capacitance value of one or more of the plurality of internal calibration capacitors so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance, or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance; The following steps are performed during the scan detection process: a. charging the external parasitic capacitor to the operating voltage; b. The external parasitic capacitor and the plurality of internal calibration capacitors participate in charge transfer and charge redistribution; c. allowing only a portion of the plurality of internal calibration capacitors and the internal integration capacitor in the touch detection circuit to participate in the integration process and charge redistribution; d. The external parasitic capacitance and the plurality of internal calibration capacitors are discharged to ground; e. Repeat steps a to d for a preset number of times.

2. The touch detection method according to claim 1, wherein: After step e, the method further comprises: f. Sampling and analog-to-digital conversion of the output of the touch detection circuit.

3. The touch detection method according to claim 1, wherein: The calibration process also includes: Determining whether the output voltage of the touch detection circuit is equal to a reference voltage; If the output voltage is not equal to the reference voltage, the capacitance value of one or more of the plurality of internal calibration capacitors is adjusted until the output voltage is equal to the reference voltage.

4. The touch detection method according to claim 1, wherein: The preset number of times is four times.

5. The touch detection method according to claim 3, characterized in that: The reference voltage is half of the operating voltage.

6. The touch detection method according to claim 3, characterized in that: The reference voltage is one third of the operating voltage.

7. A touch detection circuit, characterized in that: include: A first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a plurality of internal calibration capacitors, a plurality of calibration capacitor control switches, an internal integration capacitor, an operational amplifier, an analog-to-digital conversion circuit, an operating voltage, and a reference voltage; in: A first end of the first switch is coupled to the working voltage, a second end of the first switch is coupled to a first end of the second switch, and a second end of the second switch is grounded; A first end of the third switch is coupled to a first end of the second switch, a second end of the third switch is coupled to a first end of the fourth switch, and a second end of the fourth switch is grounded; A first end of the fifth switch is coupled to the first end of the fourth switch, and a second end of the fifth switch is coupled to the negative input terminal of the operational amplifier; The positive input terminal of the operational amplifier is coupled to the reference voltage; Both ends of the internal integral capacitor and the sixth capacitor are connected in parallel between the negative input terminal and the output terminal of the operational amplifier; A first end of the seventh switch is coupled to the output end of the operational amplifier, and a second end of the seventh switch is coupled to the input end of the analog-to-digital conversion circuit; Each of the plurality of internal calibration capacitors is connected in series with one of the plurality of calibration capacitor control switches, and the series connection is connected in parallel between the second end of the third switch and the ground.

8. The touch detection circuit according to claim 7, characterized in that: The second end of the first switch is coupled to one end of an anti-interference resistor, the other end of the anti-interference resistor is coupled to a first end of an external parasitic capacitor, and the second end of the external parasitic capacitor is grounded.

9. The touch detection circuit according to claim 7, characterized in that: It also includes a switch control module, which is used to control the opening and closing of each switch in the touch detection circuit.

10. The touch detection circuit according to claim 7, characterized in that: The touch detection circuit works according to the following steps: During the calibration process, adjusting the capacitance value of one or more of the plurality of internal calibration capacitors so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance, or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance; During the scanning process, the following steps are performed: a. closing the first switch and opening the other switches to charge the external parasitic capacitor to the operating voltage; b. closing the third switch and the plurality of calibration capacitor control switches, and opening the other switches, so that the external parasitic capacitors and the plurality of internal calibration capacitors participate in charge transfer and charge redistribution; c. closing a portion of the plurality of calibration capacitor control switches, closing the fifth switch, and opening the other switches, so that only a portion of the plurality of internal calibration capacitors and the internal integration capacitor participate in the integration process and charge redistribution; d. closing the second switch, the third switch, and the plurality of calibration capacitor control switches, and opening the other switches, so that the external parasitic capacitor and the plurality of internal calibration capacitors are discharged to ground; e. looping steps a to d for a preset number of times; f. The seventh switch is closed and the other switches are opened, and the analog-to-digital conversion circuit performs sampling and analog-to-digital conversion.

11. The touch detection circuit according to claim 10, characterized in that: Adjusting the capacitance value of one or more of the plurality of internal calibration capacitors so that the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance, or so that a multiple of the sum of the plurality of internal calibration capacitors is equal to the external parasitic capacitance comprises the following steps: The first switch is closed, and the other switches are opened, so that the working voltage charges the external parasitic capacitor to reach the working voltage; The third switch and the plurality of calibration capacitor control switches are closed, and the other switches are opened, so that the external parasitic capacitor and the plurality of internal calibration capacitors perform charge redistribution; The third switch, the multiple calibration capacitor control switches, and the fifth switch are closed, and the other switches are opened. The external parasitic capacitor, the multiple internal calibration capacitors, and the internal integration capacitor redistribute charges. The voltages across the external parasitic capacitor and the multiple internal calibration capacitors are clamped at the reference voltage. If the external parasitic capacitor is equal to the sum of the multiple internal calibration capacitors, the output voltage is equal to the reference voltage. If the external parasitic capacitor is not equal to the sum of the multiple internal calibration capacitors, the output voltage is not equal to the reference voltage. At this time, adjust the capacitance value of one or more of the multiple internal calibration capacitors until the output voltage is equal to the reference voltage.

12. The touch detection circuit according to claim 7, characterized in that: The reference voltage is half of the operating voltage.

13. The touch detection circuit according to claim 7, characterized in that: The reference voltage is one third of the operating voltage.

14. The touch detection circuit according to claim 7, characterized in that: The preset number of times is four times.

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