System for transmitting CPHY signal in FGPA

Abstract

The invention discloses a system for transmitting CPHY signals in FGPA. The system comprises an MIPI digital module, an HSTX and an LPTX, wherein the MIPI digital module is used for converting data output by the FPGA into 3-path 7-bit wide data and outputting the 3-path 7-bit wide data; the HSTX comprises three data paths, wherein each data path is used for converting one path of seven-bit-width data corresponding to the data path into one-bit-width data; the three-line encoder is connected with the three data paths and is used for encoding the digital signals output by the three data paths to obtain driving signals; the driver is connected with the three-wire encoder and used for converting the driving signal into three paths of analog signals so as to be transmitted in a channel, the LPTX sends a low-speed handshake signal conforming to an MIPI CPHY protocol, informs a receiving end of enabling impedance of the receiving end and enabling a high-speed receiver of the receiving end so as to establish a high-speed communication link, and meanwhile, when high-speed signal communication is finished, the LPTX sends the low-speed handshake signal to the receiving end; and the system enters a low-power-consumption state.

Description

Technical Field

[0001] This article relates to electronic circuit technology, and in particular to a CPHY signal transmission system in a FGPA. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a flexible semi-customized circuit chip, known as the "universal chip" for its versatility. With the development of mobile technology, the demand for video information transmission from camera to display screen has increased significantly, and higher bandwidth communication needs to be achieved in low-frequency and low-speed media. CPHY (Converged PHY) is a better solution.

[0003] CPHY is a physical layer interface standard defined by the MIPI (Mobile Industry Processor Interface) Alliance. It is designed for high-speed data transmission in mobile devices and is mainly used to connect camera sensors and processors of mobile devices. The CPHY interface supports multiple data transmission rates and can be adjusted according to the application scenario. This interface can achieve high data transmission rates while maintaining low power consumption, which is very suitable for the transmission requirements of image and video data in modern mobile devices. Therefore, ensuring the compatibility between CPHY and FPGA to meet the needs of mobile devices for efficient image and video data processing is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiment of the present application provides a CPHY signal transmission system in FGPA, including a MIPI digital module and HSTX; wherein:

[0005] The MIPI digital module is used to convert the data output by the FPGA into 3 channels of 7-bit wide data and output them;

[0006] The HSTX includes:

[0007] 3 data paths, each of which is used to convert a corresponding 7-bit wide data path into 1-bit wide data;

[0008] A 3-line encoder connected to the 3 data paths and used for encoding the digital signals output by the 3 data paths to obtain a driving signal;

[0009] The driver is connected to the 3-wire encoder and is used to convert the driving signal into 3-channel analog signals so as to be transmitted in the channel.

[0010] In the embodiment of the present application, the MIPI digital module is used to convert the data output by the FPGA into three channels of 7-bit wide data and output them, and then three data paths are used to convert the corresponding one channel of 7-bit wide data into one-bit wide data, and the digital signals output by the three data paths are encoded by a three-line encoder to obtain a drive signal, and the drive signal is converted into three channels of analog signals by a driver for transmission over the channel, thereby achieving compatibility of data transmission between CPHY and FPGA and meeting the needs of mobile devices for efficient image and video data processing.

[0011] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0013] Figure 1 A schematic diagram of the structure of a CPHY signal transmission system in an FGPA provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of the structure of the LPTX provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of the HSTX provided in the embodiment of the present application;

[0016] Figure 4 A timing diagram of signals in a data path provided by an embodiment of the present application;

[0017] Figure 5 A schematic diagram of a method for generating Load_en provided in an embodiment of the present application;

[0018] Figure 6 This is a schematic diagram of the application of the data path in the embodiment of the present application;

[0019] Figure 7 A schematic diagram of the structure of the HSTX driver provided in an embodiment of the present application;

[0020] Figure 8 A schematic diagram of the structure of a three-line driver DRV_A provided in an embodiment of the present application;

[0021] Fig. 9 A signal processing schematic diagram of a clock circuit provided in an embodiment of the present application;

[0022] Fig.10 for Fig. 9 Timing diagram of some of the signals shown;

[0023] Fig.11 A schematic diagram of the structure of the MIPI digital module provided in the embodiment of the present application;

[0024] Fig.12 for Figure 1 Another schematic diagram of the system shown. DETAILED DESCRIPTION

[0025] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0026] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0027] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0028] Figure 1This is a schematic diagram of the structure of the CPHY signal transmission system in the FGPA provided in the embodiment of the present application. Figure 1 As shown, the system includes a MIPI digital module, a LPTX (Low Power Transmitter), a HSTX (High Speed ​​Transmitter) and a clock circuit, wherein the signals involved include:

[0029] 1. Txdata_in<31:0>: The 32-bit raw data signal received by the MIPI digital module from the programmable logic of the FPGA. This signal contains the data that needs to be transmitted through the MIPI interface. Similarly, the meaning of Txdata_in<15:0> can be understood.

[0030] 2. Lpdata_A<2:0>, Lpdata_B<2:0>, Lpdata_C<2:0>: 3-bit wide 3-wire parallel data output from the programmable logic of the FPGA as the input signal of LPTX.

[0031] 3.Tx_data_A<6:0>,Tx_data_B<6:0>,Tx_data_C<6:0>: 3 channels of 7-bit wide data output by the MIPI digital module to HSTX, specifically representing 3 data channels, each 7 bits wide.

[0032] 4.byte_clock_dig: Digital byte clock signal, generated by the clock circuit, used to synchronize data transmission within the MIPI digital module.

[0033] 5.Txclk_en: This is the clock enable signal, which is used to control the start and end of data transmission. When Txclk_en is valid, the transmission of the clock signal is enabled, where Txclk_en is output by the MIPI digital module to the clock circuit.

[0034] 6.DA, DB DC: Analog signals output by HSTX or LPTX. Each signal represents the output of a data channel and is used to drive the transmission of the physical layer.

[0035] 7.byte_clock_ana: analog byte clock signal, generated by the clock circuit, where Byte clock_ana and Byte clock_dig are the same clock signals;

[0036] 8.High clock: high-speed clock signal, generated by the clock circuit and used by HSTX;

[0037] 9.rstn: reset signal, used to initialize the system state and ensure that the system starts running from a known starting point, where rstn is output by the MIPI digital module to the clock circuit.

[0038] Among them, Txclk_en and rstn are output to the clock circuit by the MIPI digital module.

[0039] from Figure 1 From the structure, it can be seen that the 3-way analog signals output by HPTX and the 3-way analog signals output by LPTX share the same transmission port, thereby realizing port multiplexing and improving port utilization.

[0040] exist Figure 1 In the system shown, LPTX, HSTX and clock circuits are deployed in TX_PMA (Transmitter Physical Media Attachment).

[0041] exist Figure 1 In the structure shown, LPTX is used to convert 3 channels of 3-bit-wide data output by FPGA into 3 channels of analog signals under the control of the analog byte clock signal for transmission in the channel.

[0042] The following is a detailed description of LPTX:

[0043] Figure 2 This is a schematic diagram of the structure of the LPTX provided in the embodiment of the present application. Figure 2 As shown, the structure is used to send a low-speed handshake signal that complies with the MIPI CPHY protocol, which can notify the receiving end to activate its impedance and activate the high-speed receiver to establish a high-speed communication link; after the high-speed signal communication is completed, the system can automatically enter a low-power state.

[0044] Combination Figure 1 The content shown is Figure 2 The structure shown is explained:

[0045] Input signal: LPTX receives output signals from the FPGA programmable logic fabric, namely Lpdata_A, Lpdata_B and Lpdata_C. These signals are generated according to upper layer instructions and can be Lp111, Lp001 and Lp000, which are used to control the state of the MIPI receiver.

[0046] Output signal: The output signals of LPTX are DA, DB, DC.

[0047] LPTX driver: The driver included in LPTX generates a high level of 1.2V and a low level signal of 0V. The function of the driver is to convert the input logic signal into a voltage signal suitable for transmission.

[0048] Controllable impedance: The impedance of LPTX is controlled by the control signal Lptx_term_ctl. When LPTX is enabled, the impedance is a resistance of about 110 ohms, which helps to match the characteristics of the transmission line, reduce signal reflections, and improve signal integrity. When LPTX is not enabled, the impedance is in a high-impedance state to reduce power consumption and prevent signal leakage.

[0049] Under the above structure, the signal transmission process includes:

[0050] The input signal for controlling the working state of the MIPI receiver is obtained from the programmable logic fabric of the FPGA.

[0051] The LPTX driver receives the input signal and converts it into a 1.2V high level and a 0V low level signal, ready to be sent.

[0052] When LPTX is enabled, the control signal Lptx_term_ctl is activated to adjust the impedance to 110 ohms to optimize signal transmission.

[0053] The output signals DA, DB, DC are sent.

[0054] After the data transmission is completed, the Lptx_term_ctl signal is turned off, the driver stops working, the impedance becomes a high-impedance state, and the system enters a low-power mode.

[0055] Figure 2 The structure shown ensures high-quality signal transmission when needed and reduces power consumption when not needed, achieving energy efficiency optimization. In addition, the use of controlled impedance can adapt to different transmission line characteristics and improve signal reliability and transmission efficiency.

[0056] exist Figure 1 In the structure shown, the MIPI digital module is used to convert the data output by the FPGA into 3 channels of 7-bit wide data and output them;

[0057] The HSTX includes:

[0058] 3 data paths, each of which is used to convert a corresponding 7-bit wide data path into 1-bit wide data;

[0059] A 3-line encoder connected to the 3 data paths and used for encoding the digital signals output by the 3 data paths to obtain a driving signal;

[0060] The driver is connected to the 3-wire encoder and is used to convert the driving signal into 3-channel analog signals so as to be transmitted in the channel.

[0061] The following is a detailed description of HSTX:

[0062] Figure 3 This is a schematic diagram of the structure of the HSTX provided in the embodiment of the present application. Figure 3 As shown, HSTX is responsible for sending high-speed communication signals. Its workflow and components are as follows:

[0063] 3 datapaths (Tx_datapath_A, Tx_datapath_B, Tx_datapath_C)

[0064] Input signal: Each data lane receives 7-bit parallel data signals from the MIPI_DIG module, namely Txdata_a<6:0>, Txdata_b<6:0>, and Txdata_c<6:0>.

[0065] External signals: Each data path receives byte_clock_ana and High clock signals to control the sampling and shifting operations of the data. The Load_en signal is generated by the Load_gen module to control when the data is loaded into the shift chain.

[0066] Output signal: The data path converts parallel data into serial data and outputs them as Hsdata_a, Hsdata_b, and Hsdata_c.

[0067] 3-wire encoder (encode_3_wire)

[0068] Input signal: Receive serial data signals Hsdata_a, Hsdata_b and Hsdata_c from three data paths.

[0069] Output signal: The serial data is encoded into the 3-line code specified by the MIPI CPHY protocol. The output signals are pu_a, pu_b, pu_c, pd_a, pd_b, and pd_c, representing the voltage state after the three-line encoding.

[0070] Driver (DRV)

[0071] Input signal: Receives encoding signals pu_a, pu_b, pu_c, pd_a, pd_b, pd_c from a 3-wire encoder.

[0072] Output signal: Converts the encoded signal into an analog voltage signal and outputs it as DA, DB, and DC to drive the transmission of the physical layer.

[0073] The HSTX workflow is as follows:

[0074] 1. The 3 data paths sample the parallel data Txdata_a<6:0>, Txdata_b<6:0>, Txdata_c<6:0> under the control of byte_clock_ana, and convert them into serial data Hsdata_a, Hsdata_b, Hsdata_c under the control of High clock.

[0075] 2. The 3-line encoder encodes the serial data Hsdata_a, Hsdata_b, and Hsdata_c into 3-line codes under the control of the High clock, and the outputs are pu_a, pu_b, pu_c, pd_a, pd_b, and pd_c.

[0076] 3. Under the control of High clock, the driver converts the encoded signals pu_a, pu_b, pu_c, pd_a, pd_b, pd_c into analog voltage signals DA, DB, DC, ready to be sent to the channel.

[0077] Figure 3 The structure shown ensures that data is efficiently converted from parallel to serial form to meet the needs of high-speed data transmission. The 3-wire encoder and driver process the signal so that the data is transmitted in the channel in the appropriate format and voltage level, improving signal reliability and transmission efficiency.

[0078] Further, in Figure 1 In the structure shown, the MIPI digital module is used to convert the data output by the FPGA into 3 channels of 7-bit wide data and output them under the control of the digital byte clock signal;

[0079] Each data path is used to sample one channel of 7-bit wide data under the control of the analog byte clock signal to obtain sampled data, and load the sampled data into the shift chain under the control of the load signal; and, under the control of the high-speed clock signal, control the data bits in the shift chain to perform a shift operation, wherein in each cycle of the high-speed clock signal, the data bits in the shift chain will move one position;

[0080] Wherein, the frequency of the high-speed clock signal is 7 times the frequency of the analog byte clock signal;

[0081] Wherein, the frequency of the analog byte clock signal is equal to the frequency of the digital byte clock signal.

[0082] Specifically, the analog byte clock signal and the digital byte clock signal are homologous clock signals.

[0083] Optionally, the load signal is generated using the analog byte clock signal and the high-speed clock signal.

[0084] The following is an explanation of the data path in HSTX:

[0085] In the HSTX module, the data path is responsible for converting parallel data into serial data to meet the needs of high-speed transmission. The following is the workflow of the data path:

[0086] Parallel data sampling: Under the control of Byte clock_ana, the data path synchronously samples the 7-bit wide original parallel data Txdata_a<6:0> to generate the sampled data Txdata_a_s<6:0>.

[0087] Data is loaded into the shift chain: The Load_en signal is used as a control signal to ensure that the sampled data is loaded into the shift chain at the correct time. When the Load_en signal is valid, data is allowed to be loaded into the shift chain.

[0088] High-speed shift operation: Under the control of High clock, the data bits in the shift chain are shifted at high speed. The frequency of High clock is higher than Byte clock_ana and is designed for high-speed data transmission.

[0089] Figure 4 The timing diagram of the signals in the data path provided by the embodiment of the present application. Figure 4 As shown, Figure 4 The following signals are shown:

[0090] Txdata_a<6:0>: represents the original data to be transmitted, in a 7-bit wide parallel form.

[0091] Byte clock_ana: A periodic square wave signal used as the clock for sampling operations to ensure that data is sampled at the correct time.

[0092] High clock: Another periodic square wave signal with a frequency higher than Byte clock_ana, used to control high-speed data shift operations.

[0093] Load_en: As a control signal, it indicates when to load the sampled data into the shift chain. When Load_en is valid, the data can be loaded into the shift chain.

[0094] Txdata_a_s<6:0>: At each rising edge of Byte clock_ana, the input parallel data Txdata_a<6:0> is sampled to generate the sampled data Txdata_a_s<6:0>.

[0095] Hsdata_a: After the shift chain loads Txdata_a_s<6:0> according to Load_en, the data bits Txdata_a_s<6:0> in the shift chain are shifted according to the control of High clock. In each High clock cycle, the data bit moves one position to the left or right, and finally realizes the high-speed serial output Hsdata_a.

[0096] Through the above design, the data path can ensure that the data is loaded into the shift chain in the correct clock cycle and shifted under the control of the high-speed clock signal, thereby realizing data serialization and high-speed transmission.

[0097] Figure 5 A schematic diagram of a method for generating Load_en provided in an embodiment of the present application shows how to generate a Load_en signal using three D-type flip-flops (DFF1, DFF2, DFF3) and a logic AND gate.

[0098] The definition of each port in each DFF is as follows:

[0099] Clk: Clock signal input terminal, used to synchronously trigger the state change of the D-type flip-flop. At the rising or falling edge of the clock signal (depending on the design), the DFF will update its output state according to the input of the D terminal.

[0100] D: Data input terminal, used to capture data at the trigger edge of the clock signal. When the clock edge arrives, the data at the D terminal will be sampled and stored.

[0101] Q: Main output terminal, which reflects the data state currently stored in DFF. When the clock edge is triggered, if the D terminal is high, the Q terminal will become high; if the D terminal is low, the Q terminal will become low.

[0102] Qn: The inverted signal output of the Q terminal, which provides a logic state opposite to that of Q. If Q is high, Qn will be low, and vice versa.

[0103] Figure 5 The execution flow of the structure shown is as follows:

[0104] 1. DFF1: receives Byte_clock_ana and samples it at the falling edge of High_clock, and outputs the sampling result through the Q terminal. Among them, High_clock is input to the Clk segment of DFF1 through the logic NOT gate.

[0105] 2.DFF2: Receives the output signal of DFF1, samples it at the falling edge of High_clock, and then outputs it through the Q terminal.

[0106] 3.DFF3: Receives the output signal of DFF2, samples it on the falling edge of High_clock, and outputs it through the QN terminal.

[0107] 4. Logic AND gate: Receives the output signals of the Q terminal of DFF1 and the QN terminal of DFF3. Only when both signals are high, the logic AND gate will generate a high-level Load_en signal to control when data is loaded into the shift chain.

[0108] Figure 5 The circuit design in the circuit precisely controls the timing of data loading through the combination of DFF and logic AND gates, ensuring that the data is loaded into the shift chain at the correct clock cycle, thereby realizing data serialization and high-speed transmission, and optimizing the efficiency and reliability of data transmission.

[0109] Figure 6 Schematic diagram of the application of data path in the embodiment of the present application. Figure 6 As shown, the data path is used to convert parallel data into serial data to meet the requirements of high-speed data transmission. The specific implementation method is as follows:

[0110] 1. Under the control of Byte_clock_ana, the D flip-flop (DFF<6:0>) synchronously samples Txdata_a<6:0> to obtain the sampled data Txdata_a_s<6:0>.

[0111] 2. Txdata_a_s<6:0> is sent to the shift chain and loaded under the control of the Load_en signal. The Load_en signal ensures that the data is received by the shift chain at the correct time.

[0112] 3. Under the control of High_clock, the data bits in the shift chain are shifted at high speed to achieve data serialization. After being processed by the shift chain, the data is output in high-speed serial form as Hsdata_a.

[0113] Figure 6 The circuit shown achieves synchronous sampling of parallel data through Byte_clock_ana, reducing sampling errors. The Load_en signal allows the system to load data only when needed, improving efficiency and reducing power consumption. Under the control of the high-speed clock signal, the data bits are quickly shifted to achieve high-speed data transmission. In addition, the data sampling, loading and shifting operations are separated into independent modules to facilitate system maintenance, upgrades and reuse.

[0114] The above structure not only improves the efficiency and reliability of data transmission, but also enhances the flexibility and maintainability of the system through modular design.

[0115] In summary, the data path provided by the embodiment of the present application adopts a synchronous sampling mechanism, and uses an analog byte clock that is homologous to the digital byte clock to accurately and synchronously sample parallel data, ensuring that data is captured at the right time, thereby reducing the possibility of data sampling errors; using two clock signals of different frequencies, Byte clock_ana and High clock, to generate Load_en, so that the most suitable clock frequency can be used in different stages of data sampling and shifting operations, optimizing the overall performance; in addition, using Load_en to achieve flexible data loading control, allowing the system to load data into the shift chain at the appropriate time as needed, which not only improves efficiency but also helps to reduce power consumption; by setting up a shift chain, data is allowed to shift quickly under the control of a high-speed clock signal, thereby supporting high-speed data transmission. A modular approach is adopted to separate data sampling, loading and shifting operations into independent modules. The above implementation method is not only easy to maintain and upgrade, but also improves the flexibility and reusability of the design, so that it can adapt to different application requirements.

[0116] According to the MIPI CPHY protocol, the output of the CPHY signal has a combination of 6 states. The 6 states are +x, -x, +y, -y, +z and -z, which correspond to the voltages of the HSTX output ports DA, DB, and DC as shown in Table 1:

[0117] wire state DA DB DC +x 3 / 4V 1 / 4V 1 / 2V -x 1 / 4V 3 / 4V 1 / 2V +y 1 / 2V 3 / 4V 1 / 4V -y 1 / 2V 1 / 4V 3 / 4V +z 1 / 4V 1 / 2V 3 / 4V -z 3 / 4V 1 / 2V 1 / 4V

[0118] Table 1

[0119] In HSTX, the data output from the three data channels needs to be converted into the level requirements of the protocol specification, which requires a 3-wire encoder and a matching driver.

[0120] The input of the three-line code encoder is hsdata_a, hsdata_b and hsdata_c, and the output is pu_a, pu_ta, pu_b, pu_tb, pu_c, pu_tc, pd_a, pd_ta, pd_b, pd_tb, pd_c, pd_tc.

[0121] The six states +x, -x, +y, -y, +z and -z corresponding to Hsdata_a, hsdata_b and hsdata_c are shown in Table 2:

[0122]

[0123]

[0124] Table 2

[0125] Among them, the input and output relationship of the three-line code encoder satisfies the following truth table relationship as shown in Table 3:

[0126] hsdata_a hsdata_b hsdata_c pu_a pd_a pu_ta pd_ta pu_b pd_b pu_tb pd_tb pu_c pd_c pu_tc pd_tc 1 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 1

[0127] Table 3

[0128] Figure 7 This is a schematic diagram of the structure of the HSTX driver provided in the embodiment of the present application. Figure 7 As shown, Figure 7 The driver shown includes a voltage regulator (Hstx_reg) and three three-line drivers (DRV_A, DRV_B, DRV_C).

[0129] The voltage regulator (Hstx_reg) uses the system power supply voltage VDD to generate a stable low voltage output vreg, usually 0.5 V. The size of the low voltage is determined according to the three drivers DRV_A, DRV_B and DRV_C to meet their driving voltage requirements, thereby reducing power consumption and improving circuit efficiency.

[0130] Each three-line driver controls the state of the output signal through three control signals to achieve precise driving of the load.

[0131] Taking the three-line driver DRV_A as an example, the input signals are pu_a, pd_a, pu_ta, pd_ta, and the output signal is DA; where:

[0132] The input signal pu_a and the input signal pd_a represent the pull-up (Pull Up) and pull-down (Pull Down) control signals of the driver A, which are used to control the high and low states of the output signal.

[0133] The input signal pu_ta and the input signal pd_ta represent auxiliary pull-up and pull-down control signals of driver A, which are used to implement more complex driving logic or protection mechanism.

[0134] The output signal DA drives the load according to the state of the input signal.

[0135] Similarly, the functions of the input signals pu_b, pd_b, pu_tb, and pd_tb in the three-line driver DRV_B are similar to those of the input signals of DRV_A; and the output signal DB is used to control the corresponding load.

[0136] Similarly, the functions of the input signals pu_c, pd_c, pu_tc, and pd_tc in the three-line driver DRV_C are similar to those of the input signals of DRV_A and DRV_B; the output signal DC is used to control its corresponding load.

[0137] exist Figure 7In the structure shown, the low-voltage drive provided by Hstx_reg can reduce the power consumption of the entire system and improve efficiency. The use of three three-line drivers allows fine control of the output signal, which helps to maintain signal integrity. Driving capability: Each driver can effectively drive its load according to the state of the input signal to ensure the reliability of data transmission.

[0138] Figure 8 Schematic diagram of the structure of the three-line driver DRV_A provided in the embodiment of the present application. Figure 8 As shown, the three-line driver DRV_A is powered by a voltage regulator (vreg), which is the output of hstx_reg and provides a stable low voltage to drive four NMOS tubes.

[0139] There are four NMOS tubes, namely M0, M1, M2 and M3. Among them, the drains of M0 and M2 are connected to vreg, and the gates of M0 and M2 are controlled by the input signals pu_a and pu_ta respectively; the source of M0 is connected to the resistor R0, and the source of M2 is connected to the resistor R2. The sources of M1 and M3 are grounded, and the gates are controlled by the input signals pd_a and pd_ta respectively; the drains of M1 and M3 are connected to the resistors R1 and R3 respectively.

[0140] Resistors R0, R1, R2 and R3 have the same resistance value and are commonly connected to the output signal DA. The above resistors are used to limit current, protect the circuit, and provide biasing and channel impedance matching in some cases.

[0141] The input signal pu_a and the input signal pu_ta are used to control the conduction of M0 and M2 to achieve the pull-up of the output signal DA;

[0142] The input signal pd_a and the input signal pd_ta are used to control the conduction of M1 and M3 to achieve the pull-down of the output signal DA;

[0143] The combination of the input signal Pu_ta and the input signal Pd_ta may be used to implement more complex control logic, such as enhancing the driving capability under certain conditions or implementing a specific signal waveform.

[0144] When the input signals pu_a and pu_ta are high, M0 and M2 are turned on, and the current flows through R0 and M0, and outputs DA through R2 and M2, realizing pull-up. When the input signals pd_a and pd_ta are high, M1 and M3 are turned on, and the current flows through R1 and M1, and the current flows to the ground through R3 and M3, realizing pull-down. When pu_a=0, pd_a=0, pu_ta=1, pd_ta=1, the current flows to the ground through M2, R2, R3 and M3, and DA is at an intermediate level. When DA is pulled up, DA is pulled down, and DA is at an intermediate level, the output impedance of DA remains consistent. Resistors R1 and R3 may be used to provide bias or limit the current through M1 and M3, while R0 and R2 may be used to limit the current through M0 and M2.

[0145] The above three-line driver design allows fine control of the state of the output signal DA through three control signals (pu_a, pd_a, pu_ta / pd_ta), achieving high-speed data transmission. By using MOSFETs, low power consumption and high-efficiency signal driving can be achieved. The use of resistors helps protect the circuit and prevent excessive current from damaging components.

[0146] exist Figure 8 In the structure shown, precise control of the output signal is achieved by precisely controlling the on and off of the MOSFET.

[0147] In an exemplary embodiment, the clock circuit comprises:

[0148] A clock gating module, used for performing an output operation on the received basic clock signal to obtain the high-speed clock signal;

[0149] A first frequency divider, connected to the clock gating module, for performing a 7-fold frequency division process on the signal output by the clock gating module to obtain the analog byte clock signal;

[0150] A phase control module is connected to the first frequency divider and is used to perform phase adjustment on the signal output by the first frequency divider to obtain the digital byte clock signal.

[0151] Optionally, the clock circuit further includes at least one of a clock enable synchronization module and a clock and reset synchronization module, wherein:

[0152] The clock enable synchronization module is connected to the clock gating module, and is used to receive the basic clock signal and the clock enable signal, and perform synchronization processing on the clock enable signal according to the basic clock signal to obtain a synchronized enable signal; wherein, when the synchronized enable signal is valid, the clock gating module performs an output operation of the clock signal;

[0153] The reset synchronization module is connected to the first frequency divider, and is used to receive the basic clock signal and the reset signal, and synchronize the reset signal according to the basic clock signal to obtain a synchronized reset signal; wherein, when the synchronized reset signal is valid, the first frequency divider performs a reset operation.

[0154] Wherein, the MIPI module is also used to output the clock enable signal and the reset signal.

[0155] Optionally, the clock circuit further includes:

[0156] An initial clock module, used for generating an initial clock signal;

[0157] A frequency adjustment module, connected to the initial clock module, for generating clock signals of different frequencies according to the initial clock signal to obtain at least two candidate signals;

[0158] The selection module is connected to the frequency adjustment module and is used to select a signal from at least two candidate signals as the basic clock signal.

[0159] Wherein, the initial clock module includes:

[0160] Phase-locked loop, used to generate the original clock signal;

[0161] A multiplier is used to increase the frequency of the original clock signal by a preset multiple to obtain the initial clock signal, wherein the value of the multiple is greater than 1.

[0162] The clock circuit is described in detail below:

[0163] Fig. 9 This is a signal processing diagram of a clock circuit provided in an embodiment of the present application. Fig. 9 As shown, the clock circuit provides efficient and flexible clock signal generation, control and adjustment, which is specifically implemented as follows:

[0164] A basic clock signal is generated by a phase-locked loop, a frequency multiplier, a second frequency divider and a multiplexer MUX1, wherein:

[0165] As the core clock source, the phase-locked loop generates a clock signal and provides a starting point for the entire clock generation process. The phase-locked loop can be a GPLL (Global Phase-Locked Loop). Fig. 9 As shown, the original clock signal generated by the phase-locked loop is Clk<3:0>, which represents a 4-bit wide clock signal. The 4-bit wide clock signal is a clock signal with phases of 0 degree, 90 degree, 180 degree and 270 degree respectively.

[0166] The frequency multiplier increases the frequency of the clock signal generated by the phase-locked loop by an integer multiple and outputs the clock signal clk0. If the maximum frequency generated by the phase-locked loop is f, when the required frequency is f, the phase-locked loop can be controlled to generate 0.5f, and then the frequency of the received clock signal is doubled by the frequency multiplier to obtain the required frequency, so that the phase-locked loop can operate at half the rate and reduce the power consumption of the phase-locked loop.

[0167] The second frequency divider performs frequency division processing on the clock signal output by the frequency multiplication circuit, wherein the frequency division ratio is adjustable to meet different system rate requirements.

[0168] MUX1 has two input terminals and one output terminal, wherein the signal transmitted by one of the input terminals is the clock signal output by the frequency multiplication circuit, the signal transmitted by the other input terminal is the signal output by the second frequency divider, and the signal transmitted by the output terminal is the signal transmitted from one of the two input terminals, wherein the signal output by the output terminal of MUX1 serves as the basic clock signal clk1 to provide flexible clock selection, allowing the system to select the most appropriate clock frequency under different working conditions, thereby optimizing performance and power consumption.

[0169] Clock control and synchronization are achieved through the clock gating module, the clock enable synchronization (Clken_sync) module, the reset synchronization (rstn_sync) module and the first frequency divider. Among them:

[0170] First, the signals involved in this stage are explained:

[0171] Basic clock signal clk1;

[0172] Clock enable signal Txclk_en, used to enable or disable the clock signal;

[0173] The synchronized enable signal Txclk_en_sync indicates the signal obtained after the clock enable synchronization module synchronizes Txclk_en according to clk1, ensuring that the clock enable control is synchronized with the system clock;

[0174] Reset signal rstn: resets all registers of the first frequency divider to the initial state after the first frequency divider is powered on or when counting needs to be restarted;

[0175] Synchronized reset signal rstn_sync: The reset synchronization module obtains the signal after synchronizing rstn according to clk1, ensuring that the reset control is synchronized with the system clock.

[0176] The clock gating module is used to receive clk1 and Txclk_en_sync. When Txclk_en_sync is valid, the clock signal without burrs processed by the clock gating module on clk1 is output, wherein the clock signal output by the clock gating module is a high-speed clock signal High clock; when Txclk_en_sync is invalid, the clock signal without burrs processed by the clock gating module on clk1 is stopped from being output, so as to reduce power consumption. In addition, by setting the clock gating module, transient fluctuations when the clock is turned off can be avoided, thereby improving system stability.

[0177] The clock enable synchronization module receives clk1 and Txclk_en, and synchronizes Txclk_en with clk1 as the reference to generate Txclk_en_sync, wherein Txclk_en_sync cooperates with the clock gating module to ensure that the clock enable signal is synchronized with the system clock.

[0178] The reset synchronization module receives clk1 and rstn, and synchronizes rstn with clk1 as the reference to generate rstn_sync, where rstn_sync cooperates with the N divider to ensure that the reset control is synchronized with the system clock.

[0179] The first frequency divider receives High clock and rstn_sync, wherein when Txclk_en_sync is valid, the first frequency divider performs a reset operation; when Txclk_en_sync is invalid, the first frequency divider releases the reset operation. The signal output by the first frequency divider is the High clock after frequency division, which is used as the analog byte clock signal byte_clock_ana. For example, when the parallel data received by the data path is 7-bit data, the first frequency divider is used to obtain a clock signal after dividing the frequency of the received clock signal by 7.

[0180] In addition, a phase adjustment module and a multiplexer MUX2 may be used to generate a digital byte clock signal byte_clock_dig.

[0181] in:

[0182] The phase adjustment module adjusts the phase of byte_clock_ana to obtain a clock signal after the phase adjustment.

[0183] MUX2 has two input terminals and one output terminal, wherein the signal transmitted by one input terminal is byte_clock_ana, the signal transmitted by the other input terminal is a phase-adjusted clock signal, and the signal transmitted by the output terminal is a signal transmitted from one of the two input terminals, wherein the signal output by the output terminal of MUX2 is byte_clock_dig.

[0184] For example, the phase adjustment module is a logic NOT gate, which implements the positive edge and negative edge of the byte_clock_ana clock to be optionally output to byte_clock_dig through MUX2.

[0185] The above solution has obvious advantages in power management, signal integrity and driving capability, including:

[0186] Dual-mode PLL operation: half-rate operation of the PLL is achieved through a multiplier (eg, a 2x multiplier), reducing the power consumption of the PLL while maintaining the highest frequency required by the system.

[0187] Second frequency divider: Provides flexibility to accommodate different rate requirements without having to design a different PLL for each rate.

[0188] Flexible use of multiplexers: allows the system to select the most appropriate clock frequency, optimizing performance and power consumption.

[0189] Glitch-free clock gating: Reduces power consumption and avoids transient fluctuations when the clock is turned off.

[0190] Application of synchronization modules: reduce problems that may be caused by asynchronous signals and improve system reliability.

[0191] First divider: Optimized for specific data transfer rates, providing precise clock control.

[0192] Optional output of digital byte clock: adapt to different digital interface requirements.

[0193] Integrated clock and reset management: Simplifies clock and reset management and reduces design complexity.

[0194] Fig.10 for Fig. 9 The timing diagram of some signals is shown in Figure 2. Fig.10 As shown, in Fig.10 The signals in the timing diagram shown are key components in the clock enable control and synchronization process. The following is a description of each signal and its level changes:

[0195] Txclk_en is used to control the clock on and off. Fig.10 In the example, Txclk_en enables the clock when it is high and disables the clock when it is low. The level change shows whether the clock is enabled or disabled at a specific moment.

[0196] clk1 is the base clock signal with a fixed frequency. Fig.10 It appears as a regular series of pulses that define the period of the system clock.

[0197] Txclk_en_sync is the clock enable signal after synchronization. Txclk_en is first synchronized to clk1 through the clken_sync module to ensure that the clock enable control is synchronized with the system clock. In the figure, the Txclk_en_sync signal samples Txclk_en on the falling edge of clk1 and remains stable in the next three clk1 cycles, and then performs a logical AND operation with the clk1 signal to generate a stable high clock.

[0198] High clock: The high-speed clock signal after the clock gating module and synchronization processing. Fig.10 It is manifested as a series of pulses. When the Txclk_en_sync signal is high, it is synchronized with the clk1 signal; when the Txclk_en_sync signal is low, the High clock will be turned off accordingly to achieve glitch-free clock shutdown.

[0199] The level changes of the above four signals are described as follows:

[0200] When Txclk_en becomes high, after being processed by the clock enable synchronization module, Txclk_en_sync becomes high at the falling edge of clk1 and remains high in the next three clk1 cycles, and then performs a logical AND operation with clk1 to make the High clock become high.

[0201] When Txclk_en becomes low, Txclk_en_sync becomes low at the next falling edge of clk1, causing High clock to also become low, thus turning off the clock.

[0202] The above implementation ensures the stable enabling and disabling of the clock, avoids problems that may be caused by asynchronous signals, and improves the reliability of the system. At the same time, through clock gating technology, the clock can be turned off when it is not needed to reduce power consumption.

[0203] Fig.11 This is a schematic diagram of the structure of the MIPI digital module provided in the embodiment of the present application. Fig.11 As shown, the output signals tx_data_A<6:0>, tx_data_B<6:0>, and tx_data_C<6:0> of the MIPI digital module block are digital signals. The output signals represent the digital data after encoding and mapping, and they are processed in the format specified by the MIPI CPHY protocol.

[0204] The MIPI digital module is responsible for the following functions:

[0205] 1. Data interface: Receives transmission data from the FPGA programmable logic (Fabric), where the transmission data can be 32 bits or 16 bits wide.

[0206] 2. Rate conversion: The rate of effective transmission data is converted to meet the requirements of the MIPI CPHY protocol.

[0207] 3. Format conversion: Use the 16-21mapping module to map the 16-bit data into the 21-bit data format required by CPHY.

[0208] 4. Synchronization sequence generation: Generate preamble, sync word and post-amble. These synchronization-related codes are packaged into the data packet when the data packet is officially sent.

[0209] 5. Data encoding: Encode the FRP (Flip Rotation Polarity) data generated by the 16-21mapping module into 3-line parallel data to meet the level requirements of the MIPI CPHY protocol.

[0210] Fig.11 The structure shown is capable of converting the received signal into data required to comply with the MIPI CPHY protocol for subsequent processing by HSTX.

[0211] Fig.12 for Figure 1 Another schematic diagram of the system shown. Fig.12 As shown, the system also includes:

[0212] A clock selector is connected to the clock circuit and is used to output the digital byte clock signal to the FPGA, so that the FPGA outputs data to the MIPI digital module and LPTX under the control of the digital byte clock signal. The digital byte clock signal can be output to the programmable logic in the FPGA. The clock selector can be specifically a multiplexer that provides clock management and clock balancing.

[0213] In addition, the system comprises:

[0214] Interface module, used to configure the MIPI CPHY register.

[0215] Specifically, the register settings are modified by accessing the MDRP module through fabric logic to achieve real-time control of MIPI CPHY, allowing users to dynamically adjust and configure the parameters of the physical layer to adapt to different operating conditions or optimize performance.

[0216] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A CPHY signal transmission system in FGPA, comprising a MIPI digital module and HSTX; wherein: The MIPI digital module is used to convert the data output by the FPGA into 3 channels of 7-bit wide data and output them; The HSTX includes: 3 data paths, each of which is used to convert a corresponding 7-bit wide data path into 1-bit wide data; A 3-line encoder connected to the 3 data paths and used for encoding the digital signals output by the 3 data paths to obtain a driving signal; The driver is connected to the 3-wire encoder and is used to convert the driving signal into 3-channel analog signals so as to be transmitted in the channel.

2. The system according to claim 1, characterized in that: The MIPI digital module is used to convert the data output by the FPGA into 3-channel 7-bit wide data and output it under the control of the digital byte clock signal; Each data path is used to sample one channel of 7-bit wide data under the control of the analog byte clock signal to obtain sampled data, and load the sampled data into the shift chain under the control of the load signal; and, under the control of the high-speed clock signal, control the data bits in the shift chain to perform a shift operation, wherein in each cycle of the high-speed clock signal, the data bits in the shift chain are shifted by one position; Wherein, the frequency of the high-speed clock signal is 7 times the frequency of the analog byte clock signal; Wherein, the frequency of the analog byte clock signal is equal to the frequency of the digital byte clock signal.

3. The system according to claim 2, characterized in that: The load signal is generated using the analog byte clock signal and the high-speed clock signal.

4. The system according to claim 2, characterized in that The system further comprises: LPTX is used to convert three channels of 3-bit-wide data output by the FPGA into three channels of analog signals under the control of the analog byte clock signal so as to be transmitted in the channel.

5. The system according to claim 4, characterized in that: The 3-channel analog signals output by HPTX and the 3-channel analog signals output by LPTX share the same transmission port.

6. The system according to claim 2, characterized in that The system further comprises: A clock circuit is used to generate the digital byte clock signal, the analog byte clock signal and the high-speed clock signal.

7. The system according to claim 6, characterized in that The clock circuit comprises: A clock gating module, used for performing an output operation on the received basic clock signal to obtain the high-speed clock signal; A first frequency divider, connected to the clock gating module, for performing a 7-fold frequency division process on the signal output by the clock gating module to obtain the analog byte clock signal; A phase control module is connected to the first frequency divider and is used to perform phase adjustment on the signal output by the first frequency divider to obtain the digital byte clock signal.

8. The system according to claim 7, characterized in that The clock circuit further comprises at least one of a clock enable synchronization module and a clock and reset synchronization module, wherein: The clock enable synchronization module is connected to the clock gating module, and is used to receive the basic clock signal and the clock enable signal, and perform synchronization processing on the clock enable signal according to the basic clock signal to obtain a synchronized enable signal; wherein, when the synchronized enable signal is valid, the clock gating module performs an output operation of the clock signal; The reset synchronization module is connected to the first frequency divider, and is used to receive the basic clock signal and the reset signal, and synchronize the reset signal according to the basic clock signal to obtain a synchronized reset signal; wherein, when the synchronized reset signal is valid, the first frequency divider performs a reset operation.

9. The system according to claim 8, characterized in that: The MIPI module is also used to output the clock enable signal and the reset signal.

10. The system according to any one of claims 7 to 9, characterized in that: The clock circuit also includes: An initial clock module, used for generating an initial clock signal; A frequency adjustment module, connected to the initial clock module, for generating clock signals of different frequencies according to the initial clock signal to obtain at least two candidate signals; The selection module is connected to the frequency adjustment module and is used to select a signal from at least two candidate signals as the basic clock signal.

11. The system according to claim 10, characterized in that The initial clock module comprises: Phase-locked loop, used to generate the original clock signal; A multiplier is used to increase the frequency of the original clock signal by a preset multiple to obtain the initial clock signal, wherein the value of the multiple is greater than 1.

12. The system according to claim 8, characterized in that The system further comprises: A clock selector is connected to the clock circuit and is used to output the digital byte clock signal to the FPGA, so that the FPGA outputs data to the MIPI digital module and LPTX under the control of the digital byte clock signal.

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