Verilog-based multi-code rate ldpc encoder and encoding method under ccstds standard

Abstract

The application provides a multi-code rate LDPC encoder based on Verilog under the CCSDS standard and a coding method, belongs to the technical field of information coding, solves the problems of waste of storage space of the LDPC code encoder and high consumption of storage generation matrix resources of the encoder, and the LDPC encoder comprises a control module, a storage module, a cyclic shift module, a check bit calculation module and a code word register module; the application realizes the design and construction of the multi-code rate LDPC code encoder, improves the flexibility of the LDPC code encoder, is more conducive to the realization of coding in practical application, meanwhile, the application can save the storage space of the LDPC code encoder, save storage resources, and is conducive to the realization of the satellite encoder in the deep space environment.

Description

Technical Field

[0001] This invention relates to a Verilog-based multi-rate LDPC encoder and encoding method under the CCSDS standard, belonging to the field of information encoding technology. Background Technology

[0002] The CCSDS (Consultative Committee for Data Systems) is dedicated to developing standards for space communication data processing systems, and its communication standards are currently used in many countries around the world. In 2007, the CCSDS committee incorporated LDPC codes into the CCSDS standard. LDPC codes are high-performance linear block codes with sparse parity-check matrices. When using an iterative decoding algorithm based on belief propagation, they exhibit good performance approaching the Shannon limit, and the sparse parity-check matrix results in low decoding complexity.

[0003] In the field of satellite communications, hardware resources and energy requirements are extremely demanding, making it difficult to withstand excessive resource consumption. For example, in deep space communications, the CCSDS-recommended standard 131.1-0-2 covers nine codewords, with code lengths ranging from a minimum of 1280 to a maximum of 32768. When the code length is long, if an encoding method that directly multiplies the information bits by the generator matrix is ​​used, the complexity increases quadratically with the code length, which consumes a significant amount of hardware resources in engineering practice. Summary of the Invention

[0004] To address the issues of wasted storage space and high resource consumption in LDPC code encoders, this invention proposes a Verilog-based multi-rate LDPC encoder and encoding method under the CCSDS standard. The LDPC encoder includes:

[0005] The module includes a control module, a storage module, a circular shift module, a parity calculation module, and a codeword register module.

[0006] The control module sends corresponding control signals to the storage module and the parity calculation module based on the code rate RATE input by the encoder.

[0007] The storage module is used to store the row generators of the rate generation matrix and provide them to the circular shift register;

[0008] The cyclic shift module is used to select the corresponding cyclic shift register according to the row generator of the matrix formed by the code rate input by the control module, generate the matrix information of the cyclic submatrix, and pass the matrix information to the parity calculation module after cyclic shifting.

[0009] The parity calculation module performs parity calculation, and after all parity bits have been calculated, they are passed to the codeword register.

[0010] The codeword w is output by concatenating the MK bit information source in the matrix after the codeword register module calculates the parity bit and the 2M bit parity bit.

[0011] Preferably, the internal data of the storage module consists of row generators of three rate generation matrices for a 1024-bit LDPC code, including a 1 / 2 rate generation matrix, a 2 / 3 rate generation matrix, and a 4 / 5 rate generation matrix.

[0012] The 2 / 3 bitrate generation matrix is ​​rectangular and located in the lower left corner of the storage module generation matrix. It has a width of 512 bits and a depth of 16. The 4 / 5 bitrate generation matrix is ​​located to the right of the 2 / 3 bitrate generation matrix. It has a width of 512 bits and a depth of 32. The 4 / 5 bitrate generation matrix includes two completely identical 4 / 5 bitrate sub-generation matrices. The width of the 4 / 5 bitrate sub-generation matrix is ​​256 bits. The 1 / 2 bitrate generation matrix is ​​located above the 2 / 3 bitrate generation matrix and the 4 / 5 bitrate generation matrix. It has a width of 1024 bits.

[0013] Preferably, the cyclic shift module includes a 128-bit cyclic shift register, a 68-bit cyclic shift register, and a 32-bit cyclic shift register, all of which are 0 when reset.

[0014] The encoding methods of Verilog-based multi-rate LDPC encoders under the CCSDS standard include:

[0015] Step 1: Input the clock signal clk, reset signal rst, information sequence u(i), and code rate RATE into the LDPC encoder;

[0016] Step 2: Input the clock signal clk, reset signal rst, information sequence u(i), and code rate RATE as the en_in signal to the control module. Through analysis of the code rate RATE, the LDPC encoder enters the encoding state. Different code rate RATEs generate the en_out12, en_out23, and en_out45 signals in the encoding state. The en_out12 signal indicates that the codeword is at 1 / 2 code rate, and the encoding begins at 1 / 2 code rate; the en_out23 signal indicates that the codeword is at 2 / 3 code rate, and the encoding begins at 2 / 3 code rate; the en_out45 signal indicates that the codeword is at 4 / 5 code rate, and the encoding begins at 4 / 5 code rate. The working order of all modules in the LDPC encoder is determined according to the clock signal clk. The control module sends the en_rom enable signal to the cyclic shift module and the enmul enable signal to the parity calculation module according to the code rate RATE input by the encoder.

[0017] Step 3: The storage module receives the en_rom enable signal, stores the row generators of the code rate (RATE) generation matrix, and provides a circular shift register;

[0018] Step 4: The cyclic shift module receives the row generators of the code rate matrix input from the control module, generates the matrix information of the cyclic submatrix, and then passes the matrix information to the parity calculation module after cyclic shifting.

[0019] Step 5: After receiving the enmul enable signal, the parity bit calculation module performs parity bit calculation. After each calculation, it is reset by the reset signal rst, and steps 3-4 are repeated until all parity bits are calculated. After all parity bits are calculated, they are passed to the codeword register.

[0020] Step 6: After the calculation is completed, set the en_finish signal to high level. The LDPC encoder enters the out state. The codeword register module calculates the check bits and then concatenates the MK bit information source in the matrix with the 2M bit check bits to output the codeword w.

[0021] Preferably, in step 2, the control module sends corresponding control signals to the cyclic shift module, the parity calculation module, and the codeword register module based on the code rate RATE input from the encoder, including:

[0022] The control module transmits the start bit of the read address of the storage module according to the code rate RATE input by the encoder, and at the same time transmits the enable signal from the circular shift register module to the storage module. The control module selects the corresponding shift register in the circular shift module to work according to the code rate RATE. The control module transmits the enable signal from the circular shift register module to the parity calculation module. The control module transmits the parity calculation completion signal from the parity calculation module as the enable signal of the codeword register output, where the enable signal of the codeword register output is the encoded codeword sequence.

[0023] Preferably, step 3 specifically includes:

[0024] The rate generator matrix is ​​divided into blocks according to its own cyclic submatrix. The first row of each cyclic submatrix is ​​stored, and then each block is iterated through using a block-by-block cyclic generation method. For a generator matrix with 1024 information bits, 8192 bits need to be stored per rate; for a generator matrix with 4096 information bits, 32768 bits need to be stored; and for a generator matrix with 16384 information bits, 131072 bits need to be stored. Under the CCSDS standard, the generator matrix G = [I...] MK×MK W MK×3M The first MK bits of the generated codeword are the original information source, and the left-hand unit matrix I... MK×MKThe generated complete parity bit set is 3M bits, with the last M bits being punched and not transmitted. The matrix W on the right... MK×3M Only the first W needs to be stored MK×2M The relevant values ​​of the columns, the generator matrix under the CCSDS standard has a cyclic structure, storing only the first row of each cyclic submatrix, and the remaining rows can be obtained from the first row through cyclic shifting. The order of the cyclic submatrix of the generator matrix is ​​M / 4, and the W of each generator matrix is... MK×2M There are 32K cyclic submatrices, and the element values ​​of the generator matrix need to be stored in 32K×M / 4=8k bits, where k is the number of bits of information;

[0025] The expression for the generating matrix is:

[0026]

[0027] In formula (1), W i,j For a cyclic matrix of size M / 4, K equals 2 when the code rate R = 1 / 2; K equals 4 when R = 2 / 3; and K equals 8 when R = 4 / 5.

[0028] Preferably, in step 4, the code rate RATE of the cyclic submatrix adopts a parallel encoding structure, including three code rates: 1 / 2 code rate, 2 / 3 code rate, and 4 / 5 code rate. The 1 / 2 code rate is binary 00 input and performs 8 information bits in parallel encoding. The 2 / 3 code rate is binary 01 input and performs 4 information bits in parallel encoding. The 4 / 5 code rate is binary 10 input and performs 2 information bits in parallel encoding.

[0029] Preferably, the internal states of the cyclic shift module in step 4 include start state, input state, assign state, shift state and output state. The start state indicates that the cyclic shift operation has started. The input state indicates that the information transmitted from the storage module has been received. The assign state transmits the row generator to the parity calculation module. The shift state indicates that the cyclic shift is performed. The output state transmits the enable signal of the parity calculation module.

[0030] In the start state, set State = 00 to enter the input state, pass the en_rom signal to 1 to the storage module as an enable, and send the row generator. After receiving the row generator, pass it to shift_data, and set State = 01 to enter the assign state.

[0031] In the assign state, set en_rom = 0; pass the value of shift_data to data as the output to the generator matrix of the parity calculation module, and set State = 11 to enter the output state.

[0032] In the output state, set enmul=1 as the enable signal for the parity calculation module. Here, Num plus 1 indicates that data has been transmitted once. At the same time, set State=10 to enter the shift state.

[0033] In the shift state, check the value of Num. If the value of Num is less than L, and L = 16 indicates that a circular submatrix has not been completely transmitted, then perform a circular shift on shift_data, and set enmul = 0, State = 01, and enter the assign state. If the value of Num is greater than L, set State = 00 and enter the input state.

[0034] Preferably, step 5, which involves calculating the check bit, includes:

[0035] Step 5.1: u1 is serially input, and W is stored in the corresponding circular shift register. 1,1 The first line of the M / 4 bit 1,1 Input information source u1(1), and combine information source u1(1) with row generator w 1,1 The result of the AND operation is stored in the codeword register module, where u i (i = 1, 2, ..., 4K) This involves dividing the information sequence u(i) into 4K equal parts, each part containing M / 4 bits, s i (i = 1, 2, ..., 8) means dividing the parity bit s into 8 equal parts in sequence, with each part containing M / 4 bits;

[0036] Step 5.2: Input the second information bit u1(2), and the row generator w 1,1 After shifting by one bit, AND the result with u1(2). The result of the AND operation is different from the result calculated in step 5.1 of the codeword register module.

[0037] Step 5.3: Repeat step 5.2 until the last bit u1(M / 4) of u1 is calculated. Then input the next set of information source u2. Clear all values ​​in the circular shift register and then store the parity matrix W in the corresponding column of the next row. 2,1 The first line of w 2,1 ;

[0038] Step 5.4: Repeat steps 5.1-5.3 until all u i After all traversals are completed, the task of one basic computational unit is finished, and the codeword register module outputs the first part s1 of the complete codeword s.

[0039] The formula for calculating the check bit s is:

[0040]

[0041] Preferably, in step 5.4, a set of s is calculated in one basic computational unit. i It requires cyclic shifting (M / 4-1)×4K times, reloading the value of the cyclic shift register 4K times, and one information bit and eight smallest units participate in the operation in parallel.

[0042] The beneficial effects of this invention are:

[0043] (1) The present invention can save the storage space of LDPC code encoder, save storage resources, and is conducive to the realization of satellite encoder in deep space environment.

[0044] (2) By implementing the design and construction of a multi-rate LDPC code encoder, this invention improves the flexibility of the LDPC code encoder and is more conducive to encoding in practical applications. Attached Figure Description

[0045] Figure 1 A schematic diagram of the structure of a Verilog-based multi-rate LDPC encoder under the CCSDS standard provided by this invention;

[0046] Figure 2 This is a schematic diagram of the structure of the cyclic shift module provided by the present invention;

[0047] Figure 3 This is a schematic diagram of the structure of the check bit calculation module provided by the present invention;

[0048] Figure 4 This is a schematic diagram of the structure of the control module provided by the present invention;

[0049] Figure 5 Sequential storage memory diagram of the storage module prior to the improvement provided by the present invention;

[0050] Figure 6 Data storage memory diagram of the improved storage module provided by the present invention;

[0051] Figure 7 The encoder state transition diagram provided by the present invention;

[0052] Figure 8 This is a schematic diagram illustrating the workflow of the check bit calculation module provided by the present invention.

[0053] Figure 9 This invention provides a state transition diagram for a cyclic shift module.

[0054] Figure 10 This is a structural diagram of the 1 / 2 bit rate cyclic shift module provided by the present invention;

[0055] Figure 11 The encoder 1 / 2 bit rate simulation waveform diagram provided by the present invention;

[0056] Figure 12 The encoder 2 / 3 bit rate simulation waveform diagram provided by this invention;

[0057] Figure 13 The encoder 4 / 5 bit rate simulation waveform diagram provided by this invention;

[0058] Figure 14 A comparison diagram of codeword text generated by the encoder at 1 / 2 bit rate provided by the present invention;

[0059] Figure 15 A comparison diagram of the codeword text generated by the encoder at 2 / 3 bit rate provided by this invention;

[0060] Figure 16 This is a comparison diagram of the codeword text generated by the encoder at a 4 / 5 bitrate provided by the present invention. Detailed Implementation

[0061] Specific implementation method one: Combining Figure 1-6 This implementation method is described as follows: Figure 1 As shown in this embodiment, the structure of the Verilog-based multi-rate LDPC encoder under the CCSDS standard includes:

[0062] The module includes a control module, a storage module (ROM), a circular shift module, a parity calculation module (MUL), and a codeword register module.

[0063] Encoder input signals: clock signal clk, reset signal rst, information sequence u(i), and code rate RATE. The code rate RATE is two bits. LDPC code has three code rates: a code rate of 1 / 2 is used as binary 00 input, a code rate of 2 / 3 is used as binary 01 input, and a code rate of 4 / 5 is used as binary 10 input. The output signal is the encoded codeword sequence.

[0064] The control module sends (or transmits) control signals to each module based on the input code rate and the pipelined operation relationships between modules. For the memory module, the control module transmits the start bit of the memory module's read address based on the input code rate, and simultaneously transmits the enable signal from the circular shift register module to the ROM. For three circular shift register modules, the control module selects the corresponding shift register to operate based on the code rate. For the parity calculation module, the control module transmits the enable signal from the circular shift register module to the parity calculation module. For the codeword register module, the control module transmits the parity calculation completion signal from the parity calculation module as the enable signal for the codeword register output.

[0065] Data transfer between modules, such as Figure 1As shown by the wide arrow, the storage module passes the information to the three circular shift register modules to generate the matrix; the circular shift register module passes the generated matrix information to the parity bit calculation module after circular shifting; after the parity bit calculation module has completed the calculation of all parity bits, it passes it to the codeword register; the codeword register concatenates the MK bit information source with the 2M bit parity bits and outputs the codeword w.

[0066] like Figure 4 As shown, the control module has three ROM address start bit selection data options. Upon receiving the input RATE signal, it selects the corresponding address start bit selection data signal for output. It has three cyclic shift register enable signals, all of which are 0 upon reset. The input RATE signal pulls the corresponding cyclic shift register enable signal high to initiate operation. The MUL corresponds to a specific code rate and has a corresponding calculation state; the appropriate state is enabled based on the code rate signal. During cyclic shift register operation, data is transferred once per cycle, simultaneously pulling the MUL enable signal high for calculation. After completing each cyclic submatrix cycle, the ROM enable signal is pulled high to transfer the row generators of the new cyclic submatrix.

[0067] The structure of the circular shift module is as follows: Figure 2 The structure of the check digit calculation module is shown below. Figure 3 As shown, the storage module provides row generators for the circular submatrix of the generated matrix from the circular shift register. Its internal data consists of row generators for the generated matrices of the 1024-bit LDPC code at three different rates. For a 1 / 2 rate, the row generator occupies a memory space with a width of 128 × 8 bits and a depth of 8; for a 2 / 3 rate, it occupies a memory space with a width of 64 × 8 bits and a depth of 16; and for a 4 / 5 rate, it occupies a memory space with a width of 32 × 8 bits and a depth of 32. If... Figure 5 The sequential storage method shown would occupy 64K of space, but in reality, the row generators of the generator matrices for the three code rates only require 8192×3 bits of memory space, resulting in a storage resource utilization rate of only 37.5%, which is a huge waste. Therefore, this implementation design adopts the following... Figure 6 The storage method involves splitting the 4 / 5 bitrate matrix in the middle and storing it side-by-side on the right side of the 2 / 3 bitrate generator matrix. Since the depth of the 4 / 5 bitrate generator matrix is ​​32 bits, and that of the 2 / 3 bitrate matrix is ​​16 bits, the depths on both sides are consistent after concatenation. The width of the row generators in the 1 / 2 bitrate generator matrix is ​​1024 bits, the width of the 2 / 3 bitrate matrix is ​​512 bits, and the width of the 4 / 5 bitrate matrix is ​​256 bits, resulting in consistent widths at the top and bottom after concatenation. This avoids memory waste.

[0068] Specific Implementation Method Two: Combining Figure 7-16 This embodiment will be described as follows: Figure 7As shown in this embodiment, the Verilog-based multi-rate LDPC encoding method under the CCSDS standard includes:

[0069] The LDPC encoder has three states. When the `en_in` signal is high, it indicates that the information source is input, and the encoder enters the `begin` state. Based on the analysis of the bitrate signal, it enters the `encode` state. Different bitrates trigger different enable signals for this state: `en_out12` indicates a 1 / 2 bitrate codeword, and the encoder enters the 1 / 2 bitrate portion; `en_out23` indicates a 2 / 3 bitrate codeword, and the encoder enters the 2 / 3 bitrate portion; `en_out45` indicates a 4 / 5 bitrate codeword, and the encoder enters the 4 / 5 bitrate portion. The `encode` state has two enable signals: `en_rom` drives the storage module to pass the row generators of the generator matrix, and `enmul` drives the parity calculation module to perform an XOR operation. After the calculation, the `en_finish` signal is set high, and the encoder enters the `out` state to output the encoded codeword.

[0070] The generated matrix in the storage module is divided into blocks according to its own cyclic submatrix. The first row of the cyclic submatrix is ​​stored, and then each block is iterated through in a block-by-block cyclical manner to generate the generated submatrix. The generated matrix G = [I...] in the CCSDS standard. MK×MK W MK×3M The first MK bits of the generated codeword are the original information source, therefore the left-hand unit matrix I... MK×MK No storage is required. The generated complete parity bit set has 3M bits, with the last M bits being punched and not transmitted. Therefore, the matrix W on the right... MK×3M Only the first W needs to be stored MK×2M Regarding the column-related values, the generator matrix under the CCSDS standard has a cyclic structure, storing only the first row of each cyclic submatrix; the remaining rows can be obtained from the first row through cyclic shifting. If the order of the cyclic submatrix of the generator matrix is ​​M / 4, then the W value of each generator matrix... MK×2M There are 32K cyclic submatrices in total. The generator matrix needs to store the element values ​​of 32K×M / 4=8k (k is the number of information bits) bits. In summary, for a generator matrix with 1024 information bits, each code rate needs to store 8192 bits; for a generator matrix with 4096 information bits, it needs to store 32768 bits; and for a generator matrix with 16384 information bits, it needs to store 131072 bits.

[0071] Internal state transitions of the cyclic shift module, such as Figure 9As shown, there are a total of 5 states. The start state indicates the start of the cyclic shift operation. The input state receives information from the storage module. The assign state passes the row generator or the vector after the row generator is shifted to the check bit calculation module. The shift state performs the cyclic shift. The output state passes the enable signal of the check bit calculation module. The function description of the signals used by the module is shown in Table 1.

[0072] Table 1

[0073]

[0074] When the enable signal en_out arrives, the circular shift register starts working and enters the start state. Enable signals for different code rates are provided by the control module; there are three types of enable signals corresponding to three types of circular shift registers.

[0075] like Figure 9 As shown, in the start state, State is set to 00, entering the input state. In this state, the en_rom signal is set to 1 to enable the storage module, causing it to send the row generator. After receiving the row generator, it is passed to shift_data, and State is set to 01, entering the assign state.

[0076] In the assign state, set en_rom = 0; pass the value of shift_data to data as the generator matrix information to be output to the verification calculation unit; at the same time, set State = 11 to enter the output state.

[0077] In the output state, set enmul=1 as the enable signal for the verification calculation unit, increment Num by 1 to indicate that data has been transmitted once, and set State=10 to enter the shift state.

[0078] In the shift state, the value of Num is first checked. If it is less than L = 16, it indicates that a circular submatrix has not been completely transmitted. Then, shift_data is shifted once, and enmul is set to 0, State to 01, entering the assign state. Otherwise, State is set to 00, entering the input state. To achieve partial parallel encoding, the number of bits shifted by the circular shift register varies depending on the code rate. For a 1 / 2 code rate, it is 8-bit parallel encoding, so one shift is 8 bits, and 8 circular shift registers are working for a circular submatrix of the generator matrix. For a 2 / 3 code rate, it is 4-bit parallel encoding, so one shift is 4 bits, and 4 circular shift registers are working for a circular submatrix of the generator matrix. For a 1 / 2 code rate, it is 2-bit parallel encoding, so one shift is 2 bits, and 2 circular shift registers are working for a circular submatrix of the generator matrix. Taking the 1 / 2 code rate circular shift register as an example, its internal structure is as follows: Figure 10 As shown, the basic unit of LDPC encoding under the CCSDS standard is implemented using a shift register accumulator. The form of the shift register accumulator in LDPC encoding is as follows: Figure 2 As shown. The generating matrix W can be written as shown in formula (1), where each submatrix W i,j All are cyclic matrices of size M / 4. When the bit rate R = 1 / 2, K equals 2; when R = 2 / 3, K equals 4; when R = 4 / 5, K equals 8.

[0079]

[0080] The function of the parity bit calculation module is to perform a bitwise AND operation between the information source and the value passed from the loop register. The MUL signal is a status selection signal sent by the control module to the parity bit calculation module so that when the enable signal enmul arrives, the parity bit calculation module can correctly select the sub-parity bit calculation module with different code rates. After a calculation is completed, the sub-parity bit calculation module sends the calculated value to the storage module and XORs it with the value already stored in the shorten module. This process continues until all information bits have been calculated, at which point a finish signal is output as the enable of the codeword register module. Upon receiving this enable signal, the codeword register module concatenates the information source with the calculated parity bit and outputs the complete codeword.

[0081] Calculate the check bit s = uW T The steps include:

[0082] S1: u1 serial input, W is stored in the corresponding circular shift register. 1,1 The first line of the M / 4 bit 1,1 Input information source u1(1), and combine information source u1(1) with row generator w 1,1 The result of the AND operation is stored in the codeword register module, where ui (i = 1, 2, ..., 4K) This involves dividing the information sequence u(i) into 4K equal parts, each part containing M / 4 bits, s i (i = 1, 2, ..., 8) means dividing the parity bit s into 8 equal parts in sequence, with each part containing M / 4 bits;

[0083] S2: Input of the second information bit u1(2), row generator w 1,1 After shifting by one bit, AND the result with u1(2). The result of the AND operation is different from the result calculated in step 5.1 of the codeword register module.

[0084] S3: Repeat S2 until the last bit of u1 (M / 4) is calculated. Then input the next set of information source u2. Clear all values ​​in the circular shift register and then store the parity matrix W in the corresponding column of the next row. 2,1 The first line of w 2,1 ;

[0085] S4: Repeat S1-S3 until all u i After all iterations are complete, completing the task of one basic computational unit, the codeword register module outputs the first part s1 of the complete codeword s. From the composition of matrix W, it can be seen that... Figure 8 As shown, a basic unit needs to calculate a set of s in the check bits. i It requires (M / 4-1)×4K circular shifts and reloading the value of the circular shift register 4K times. Simultaneously, there are a total of 8 groups of s... i Parallel computing therefore requires eight basic computational units to operate simultaneously. The overall check bit calculation module should be as follows: Figure 8 As shown. Each of the SRAAs is Figure 8 The smallest unit shown is a single information bit that participates in the operation in parallel with eight other smallest units.

[0086] The formula for calculating the check bit s is:

[0087]

[0088] The encoder was first simulated using Multisim, and the interface signal table function description is shown in Table 2. When finish is high, it indicates that the codeword has been written and the encoder is in a waiting state. Only when the next information source arrives will en_in be set high to write the next codeword. When finish is low, it indicates that the encoder is working and cannot encode the next codeword.

[0089] Table 2

[0090]

[0091] According to the theoretical design, for a 1 / 2 code rate, the parity calculation module needs to calculate one codeword 1024 / 8 = 128 times; for a 2 / 3 code rate, it needs to calculate one codeword 1024 / 4 = 256 times; and for a 4 / 5 code rate, it needs to calculate one codeword 1024 / 2 = 512 times. Each calculation requires the cyclic shift module to transmit data to the parity calculation module. The cyclic shift module needs 2 clock cycles to shift data once, so a total of 3 clock cycles are required for one calculation. In addition, the cyclic shift module needs an extra 3 clock cycles to receive the row generators of the cyclic submatrix from the storage module. For a 1 / 2 code rate, this requires 8 row generators; for a 2 / 3 code rate, it requires 16 row generators; and for a 4 / 5 code rate, it requires 32 row generators. If the system clock is 200MHz, according to the throughput calculation formula:

[0092]

[0093] In formula (1), k is the number of information bits, and num... code The number of clocks used is 'f', and the clock frequency is 'f'. The calculated throughput of the 1 / 2 bit rate encoder is 501.96 Mbps; the throughput of the 2 / 3 bit rate encoder is 250.98 Mbps; and the throughput of the 4 / 5 bit rate encoder is 125.49 Mbps.

[0094] The waveforms of Modelsim encoded with three bitrates are shown below. Figure 11-13 As shown in the figure, when en_finish is set to high, the encode outputs the codeword with the specified number. The codeword obtained from the encoder simulation is compared with the codeword calculated by the MATLAB program, and the result is correct. The display result of the text comparator is as follows. Figure 14-16 As shown.

[0095] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A multi-rate LDPC encoder based on Verilog under CCSDS standard, characterized in that, The structure of the Verilog-based multi-code rate LDPC encoder under the CCSDS standard comprises: a control module, a storage module, a cyclic shift module, a check bit calculation module and a codeword register module; The control module sends corresponding control signals to the storage module and the check bit calculation module according to the code rate RATE input by the encoder; The storage module is used for storing the row generating elements of the code rate RATE generating matrix and providing the row generating elements to the cyclic shift register; The cyclic shift module is used for selecting corresponding cyclic shift registers according to the row generating elements of the code rate RATE generating matrix input by the control module, generating matrix information of the generating matrix cyclic submatrix, and transmitting the matrix information to the check bit calculation module after the matrix information is subjected to cyclic shift; The check bit calculation module performs check bit calculation, and transmits the check bits to the codeword register after the check bit calculation is completed; The code word register module checks the bit information source and The bit information source and The bit check bit splicing output code word .

2. The CCSDS standard based Verilog based multi code rate LDPC encoder as claimed in claim 1, wherein, The internal data of the storage module is the row generating elements of the 3 code rate generating matrices of the 1024-bit LDPC code, including the 1 / 2 code rate generating matrix, the 2 / 3 code rate generating matrix and the 4 / 5 code rate generating matrix; The 2 / 3 code rate generating matrix is a rectangle, located at the lower left corner of the generating matrix of the storage module, with a width of 512 bits and a depth of 16, the 4 / 5 code rate generating matrix is located to the right of the 2 / 3 code rate generating matrix, with a width of 512 bits and a depth of 32, the 4 / 5 code rate generating matrix comprises two identical 4 / 5 code rate sub-generating matrices, the width of the 4 / 5 code rate sub-generating matrix is 256 bits, and the 1 / 2 code rate generating matrix is located above the 2 / 3 code rate generating matrix and the 4 / 5 code rate generating matrix, with a width of 1024 bits.

3. The CCSDS standard based Verilog based multi code rate LDPC encoder as claimed in claim 1, wherein, The cyclic shift module comprises a 128-bit cyclic shift register, a 68-bit cyclic shift register and a 32-bit cyclic shift register, and the 128-bit cyclic shift register, the 68-bit cyclic shift register and the 32-bit cyclic shift register are all 0 when reset.

4. The encoding method of the multi-rate LDPC encoder based on Verilog under the CCSDS standard, applied to the multi-rate LDPC encoder based on Verilog under the CCSDS standard of any one of claims 1-3, characterized in that, It comprises: Step 1: input the clock signal clk, the reset signal rst, the information sequence u(i) and the code rate RATE into the LDPC encoder; Step 2: input the clock signal clk, the reset signal rst, the information sequence u(i) and the code rate RATE into the control module as en_in signals, through analysis of the code rate RATE, the LDPC encoder enters the encode state, different code rates RATE enter the encode state to generate en_out12 signals, en_out23 signals and en_out45 signals, the en_out12 signals indicate that the codeword is a 1 / 2 code rate, and the 1 / 2 code rate part is entered for coding; the en_out23 signals indicate that the codeword is a 2 / 3 code rate, and the 2 / 3 code rate part is entered for coding; the en_out45 signals indicate that the codeword is a 4 / 5 code rate, and the 4 / 5 code rate part is entered for coding, the working order of all modules in the LDPC encoder is determined according to the clock signal clk, the control module sends an en_rom enable signal to the cyclic shift module and an enmul enable signal to the check bit calculation module according to the code rate RATE input by the encoder; Step 3: The storage module receives the en_rom enable signal, generates the row generator of the code rate RATE generating matrix, and provides a cyclic shift register; Step 4: The cyclic shift module receives the row generator of the code rate matrix input by the control module, generates the matrix information of the cyclic submatrix of the matrix, and transmits the matrix information after cyclic shift to the check bit calculation module; Step 5: The check bit calculation module performs check bit calculation after receiving the enmul enable signal, resets through the reset signal rst after single calculation, and repeats steps 3-4 until all check bits are calculated, and then transmits to the code word register; Step 6: After the calculation is completed, the en_finish signal is set to high level, the LDPC encoder enters the out state, and the parity bit in the code word register module after the matrix is checked bit information source and bit parity splicing to output code word .

5. The encoding method of a Verilog-based multi-code rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that, The control module according to the code rate RATE input by the encoder transmits the starting bit of the read address of the storage module, and simultaneously transmits the enable signal of the cyclic shift register module to the storage module, the control module selects the corresponding shift register in the cyclic shift module to work according to the code rate RATE, the control module transmits the enable signal of the cyclic shift register module to the check bit calculation module, and the control module transmits the check bit calculation completion signal of the check bit calculation module as the enable signal of the code word register output, wherein the enable signal of the code word register output is the coded code word sequence. Step 3 specifically includes:

6. The encoding method of a Verilog-based multi-code rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that, The expression of the generating matrix is: The code rate RATE generating matrix is blocked according to the form of the block circulant submatrix, and the first row of the generating matrix circulant submatrix is stored, and then each block circulant generating matrix submatrix is traversed in the block circulation manner. For the generating matrix with the information bit of 1024, 8192 bits of values need to be stored for each code rate; for the generating matrix with the information bit of 4096, 32768 bits of values need to be stored; and for the generating matrix with the information bit of 16384, 131072 bits of values need to be stored. The generating matrix under the CCSDS standard has the form of The first bit of the generated code word is the original information source, the left unit matrix is not stored, the generated complete check bit has bits, the last bit is punctured and not transmitted, and the right matrix only needs to store the related values of the first column. The generating matrix under the CCSDS standard has the circulation structure, only the first row of each circulant submatrix is stored, and the remaining rows can be obtained by the circulation shift of the first row. The order of the circulant submatrix of the generating matrix is , the circulant submatrix of each generating matrix has , and the element value of the generating matrix needs to be stored bits, wherein is the number of information bits. In step 4, the code rate RATE of the cyclic submatrix of the array adopts a parallel encoding structure, including 1 / 2 code rate, 2 / 3 code rate and 4 / 5 code rate, the 1 / 2 code rate is binary 00 input, the 1 / 2 code rate is 8 information bit parallel encoding, the 2 / 3 code rate is binary 01 input, the 2 / 3 code rate is 4 information bit parallel encoding, and the 4 / 5 code rate is binary 10 input, and the 4 / 5 code rate is 2 information bit parallel encoding. （1）； In formula (1), is a circulant matrix of size When the code rate R = 1 / 2, K is equal to 2; when R = 2 / 3, K is equal to 4; when R = 4 / 5, K is equal to 8.

7. The encoding method of a Verilog-based multi-code rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that, The internal state of the cyclic shift module in step 4 includes start state, input state, assign state, shift state and output state, the start state indicates that the cyclic shift work is started, the input state indicates that the information transmitted from the storage module is received, the assign state transmits the row generator to the check bit calculation module, the shift state indicates that the cyclic shift is performed, and the output state transmits the enable signal of the check bit calculation module; 8. The encoding method of a Verilog-based multi-code rate LDPC encoder under the CCSDS standard according to claim 4, wherein, In the start state, State=00 is set, the input state is entered, the en_rom signal is transmitted to the storage module as an enable signal, the row generator is input, after the row generator is received, the shift_data is transmitted, and State=01 is set, and the assign state is entered; In the assign state, en_rom=0 is set, the value of shift_data is transmitted to data as the generating matrix signal output to the check bit calculation module, State=11 is set, and the output state is entered; In the output state, en_rom=0 is set, the value of shift_data is transmitted to data as the generating matrix signal output to the check bit calculation module, State=11 is set, and the output state is entered; In the output state, enmul=1 is set as the enable signal of the check bit calculation module, wherein Num+1 indicates that data has been transmitted once, and State=10 is set to enter the shift state; In the shift state, the value of Num is determined. If the value of Num is less than L, L=16 indicates that a cyclic submatrix has not been transmitted completely, and shift_data is cyclically shifted once, enmul=0 is set, and State=01 is set to enter the assign state. If the value of Num is greater than L, State=00 is set to enter the input state.

9. The encoding method of a Verilog-based multi-code rate LDPC encoder under the CCSDS standard according to claim 4, characterized in that, The step of performing check bit calculation in step 5 comprises: Step 5.1: Serial input, the corresponding cyclic shift register stores the first row of M / 4 bits , the input information source , the information source is ANDed with the row generator and then stored in the code word register module, wherein, to equally divide the information sequence u(i) into 8 parts, M / 4 bits each, to equally divide the check bits into 8 parts, M / 4 bits each; Step 5.2: 2nd information bit Input, row generator XOR, XOR value is different from the value calculated in step 5.1 in the code word register module XOR, XOR value is different from the value calculated in step 5.1 in the code word register module Step 5.3: Repeat Step 5.2 until the last bit of the last row of the parity check matrix After the calculation is completed, input the next set of information sources , and the first row of the parity check matrix is emptied first in the circular shift register and then stored in the corresponding column of the next row the first row of the parity check matrix ; Step 5.4: Repeat Step 5.1 - Step 5.3 until all of The entire traversal is completed, a task of a basic unit of computation is completed, and the codeword register module outputs a complete codeword The first part of the codeword ; Check bit The calculation formula is: （2）。 10. The encoding method of a Verilog-based multi-code rate LDPC encoder under the CCSDS standard according to claim 4, wherein, A group of The cyclic shift needs to be performed The value of the cyclic shift register is reloaded An information bit participates in the operation with 8 minimum units in parallel.

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