Signal receiver with offset voltage correction function and offset voltage correction method

Abstract

The invention discloses a signal receiver with an offset voltage correction function and an offset voltage correction method. The signal receiver comprises an amplification circuit, a comparison circuit and an offset correction circuit. The amplification circuit comprises a primary amplification module, a secondary amplification module and a primary correction control module. And the primary correction control module is separated from a high-speed signal path in the signal receiver. In the offset correction stage, the primary correction control module controls the primary amplification module to be in a forbidden state, and the secondary amplification module provides a secondary amplification output signal generated according to rated voltage and preset compensation current output by the offset correction circuit to the comparison circuit. The offset correction circuit executes successive approximation correction operation to determine a target compensation current and outputs the target compensation current to the secondary amplification module; in a data transmission stage, the primary correction control module controls the primary amplification module to be in an enabling state, and the secondary amplification module generates a secondary amplification signal according to a rated voltage, a primary amplification signal output by the primary amplification module and a target compensation current.

Description

Technical Field

[0001] The present application relates to the field of signal transmission technology, and in particular to a signal receiver with an offset voltage correction function and an offset voltage correction method. Background Art

[0002] With the continuous development of the field of communication technology, in the communication system, the circuit components of the signal receiver, such as loads, transistors, and bias current units, will produce variations due to process steps and other reasons, thereby causing the signal received by the signal receiver to produce a DC voltage offset phenomenon. Even if the circuit components use exactly the same area and layout, the DC voltage offset cannot be completely avoided. Especially in high-frequency application environments, the variation of circuit components has a great impact on the circuit bandwidth and signal receiving capability of the signal receiver. In the prior art, in order to eliminate the offset phenomenon of the signal receiver, an offset calibration circuit is usually used, and multiple switch elements are set on the signal transmission path of the signal receiver. Multiple switch elements control the signal receiver to switch between the offset calibration mode and the data transmission mode. Due to the presence of the switch elements, the circuit structure of the offset correction circuit in the offset calibration mode and the data transmission mode is different. That is, some switch elements are in a disconnected state in the offset calibration mode, but in a conductive state in the data transmission mode. Therefore, the offset correction effect is poor. On the other hand, the configuration of these switch elements will cause additional parasitic resistance and / or capacitance on the signal transmission path of the signal receiver, thereby affecting the operating speed of the signal receiver, that is, reducing the transmission signal bandwidth. Summary of the invention

[0003] The main purpose of the present application is to provide a signal receiver with an offset voltage correction function and an offset voltage correction method, aiming to solve the problem in the prior art of optimizing the offset correction effect while maintaining a high frequency bandwidth.

[0004] A signal receiver with an offset voltage correction function receives a positive input signal and a negative input signal from a transmitter; the working phase of the signal receiver includes an offset correction phase and a data transmission phase; the signal receiver includes:

[0005] The amplifier circuit is used to receive a positive input signal and a negative input signal, and the amplifier circuit includes:

[0006] A primary amplification module electrically connected to the transmitter;

[0007] A secondary amplifying module electrically connected to the primary amplifying module; and

[0008] A primary correction control module, electrically connected to the primary amplification module;

[0009] A comparison circuit electrically connected to the secondary amplifier module; and

[0010] An offset correction circuit is electrically connected to the comparison circuit and the secondary amplifier module;

[0011] In which, there is a high-speed signal path in the signal receiver, and the primary correction control module is separately set from the high-speed signal path; in the offset correction stage, the primary correction control module controls the primary amplification module to be in a disabled state, the secondary amplification module generates a secondary amplification signal according to the rated voltage and the preset compensation current output by the offset correction circuit, the comparison circuit generates a comparison signal according to the secondary amplification signal, the offset correction circuit performs a successive approximation correction operation according to the comparison signal to determine the target compensation current and outputs it to the secondary amplification module, in the data transmission stage, the primary correction control module controls the primary amplification module to be in an enabled state and generates a primary amplification signal, the offset correction circuit continuously outputs the target compensation current to the secondary amplification module, the secondary amplification module receives the rated voltage, the primary amplification signal and the target compensation current and generates a secondary amplification signal, and the comparison circuit outputs the secondary amplification signal.

[0012] In addition, in order to achieve the above-mentioned purpose, the present application also proposes an offset voltage correction method, which is applied to a signal receiver; a high-speed signal path exists in the signal receiver; the signal receiver works in an initial stage, an offset correction stage and a data transmission stage in sequence; the signal receiver includes an amplification circuit, a comparison circuit and an offset correction circuit; the amplification circuit includes a primary amplification module, a secondary amplification module and a primary correction control module; the primary correction control module is separated from the high-speed signal path; the offset voltage correction method includes:

[0013] In the offset correction stage, under the control of the primary correction control module, the primary amplification module is in a disabled state;

[0014] In the offset correction stage, the secondary amplifier module generates a secondary amplification signal according to the rated voltage and the preset compensation current output by the offset correction circuit, the comparison circuit obtains a comparison signal according to the secondary amplification signal, and the offset correction circuit performs a successive approximation correction operation according to the comparison signal to determine the target compensation current and provides it to the secondary amplifier module; wherein, when performing the successive approximation correction operation, the offset correction circuit outputs different preset compensation currents, and the secondary amplification signal changes with the change of the preset compensation current;

[0015] In the data transmission stage, under the control of the primary calibration control module, the primary amplification module is in an enabled state; and

[0016] During the data transmission stage, the offset correction circuit maintains providing the target compensation current to the secondary amplifier module. The secondary amplifier module generates a secondary amplification signal based on the rated voltage, the primary amplification signal output by the primary amplifier module and the target compensation current. The comparison circuit outputs the secondary amplification signal to the signal processor.

[0017] The receiver with offset voltage correction function and the offset voltage correction method of the present application utilize a primary correction control module that is isolated from the signal transmission path, which not only achieves mode switching without setting an additional switch element on the signal transmission path of the signal receiver, but also reduces the difference in circuit architecture between the signal receiver in the offset correction stage and the signal receiver in the data transmission stage, thereby optimizing the offset correction effect of the signal receiver while maintaining a high bandwidth. In addition, during the offset correction stage, the transmitter can continue to transmit normal signals without affecting the offset correction operation of the signal receiver, so there is no need to change the operation of the transmitter, thereby reducing the complexity of system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0019] Figure 1 A module diagram of an application environment of a signal receiver according to a preferred embodiment of the present application.

[0020] Figure 2 for Figure 1 FIG. 1 is a partial circuit diagram of an amplifier circuit in a signal receiver of the first embodiment.

[0021] Figure 3 for Figure 2 A circuit diagram of a primary bias control unit and a first primary correction control unit of the first embodiment.

[0022] Figure 4 for Figure 2 A circuit diagram of a primary bias control unit and a first primary correction control unit of a second embodiment of the present invention.

[0023] Figure 5 for Figure 2 FIG. 1 is a block diagram of an offset correction circuit according to a first embodiment of the present invention.

[0024] Figure 6 for Figure 2 FIG. 4 is a block diagram of an offset correction circuit according to a second embodiment of the present invention.

[0025] Figure 7 for Figure 1 A timing diagram of a positive input signal, a negative input signal, an offset correction control signal, an offset correction clock signal, a compensation indication signal, a signal at an output node, a correction bit, and a DC voltage offset.

[0026] Figure 8 For existing technology and Figure 1 Schematic diagram of the gain and input signal frequency characteristic curve of the signal receiver.

[0027] Fig. 9 The eye diagram is an eye diagram of a comparison signal output by a comparison output node when a signal receiver in the prior art receives a positive input signal and a negative input signal of a specified frequency.

[0028] Fig.10 for Figure 1 The eye diagram of the comparison signal output by the comparison output node when the signal receiver receives positive and negative input signals of the specified frequency.

[0029] Fig.11A and Fig. 11B for Figure 1 Schematic diagram of the distribution of DC voltage offset after multiple Monte Carlo simulations are performed on the signal receiver when the offset correction function is not activated and when the offset correction function is activated.

[0030] Fig.12 for Figure 1 Module diagram of a signal receiver in the second embodiment.

[0031] Fig.13 for Figure 1 Module diagram of a signal receiver in the third embodiment.

[0032] Fig.14 for Figure 1 Module diagram of a signal receiver in the fourth embodiment.

[0033] Fig.15 for Figure 1 Module schematic diagram of a signal receiver in the fifth embodiment.

[0034] Fig.16 for Figure 1 Module diagram of a signal receiver in the sixth embodiment.

[0035] Fig.17 for Figure 1 Module diagram of a signal receiver in the seventh embodiment.

[0036] Figures 18A-18D for Fig.14 or Fig.16A circuit diagram of a secondary bias control module and a first secondary correction control unit in the first embodiment.

[0037] Figures 19A-19D for Fig.15 or Fig.17 A circuit diagram of a secondary bias control module and a second secondary correction control unit in a second embodiment of the present invention.

[0038] Fig. 20 This is a flow chart of an offset voltage calibration method according to the first embodiment of the present application.

[0039] Fig.21 This is a flow chart of an offset voltage calibration method according to a second embodiment of the present application.

[0040] Main component symbols

[0041] Signal receiver 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G

[0042] The first signal input terminal 1_1

[0043] The second signal input terminal 1_2

[0044] Transmitter 2

[0045] Signal Processor 3

[0046] Positive input signal TXP

[0047] Negative input signal TXN

[0048] Amplifier circuit 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G

[0049] The first amplification input terminal 101

[0050] The second amplification input terminal 102

[0051] The first amplified output terminal 103

[0052] The second amplified output terminal 104

[0053] Primary amplifier modules 11, 11A, 11B, 11C, 11D

[0054] The first primary input terminal 111

[0055] The second primary input terminal 112

[0056] The first primary output terminal 113

[0057] The second primary output terminal 114

[0058] Secondary amplifier modules 12, 12A, 12B, 12C, 12D

[0059] The first secondary input terminal 120

[0060] The second secondary input terminal 121

[0061] The first secondary output terminal 122

[0062] Second secondary output terminal 123

[0063] Comparison circuit 20

[0064] The first comparison input terminal 20A

[0065] The second comparison input terminal 20B

[0066] Offset correction circuit 30

[0067] Compensation indication module 31

[0068] Successive approximation module 32

[0069] Digital-to-analog conversion modules 33A, 33B

[0070] Primary correction control module 13

[0071] First primary correction control unit 131

[0072] First primary bias control unit 115, 115A, 115B

[0073] The first control switch S1

[0074] The second control switch S2

[0075] Bias control switch S3

[0076] Working voltage VDD

[0077] The first transistor Q1

[0078] The second transistor Q2

[0079] The first load 116

[0080] The second load 117

[0081] The first primary output node N1

[0082] The second primary output node N2

[0083] Rated voltage VB

[0084] First secondary input node N3

[0085] Second secondary input node N4

[0086] First secondary bias current source 124

[0087] Second secondary bias current source 125

[0088] The third transistor Q3

[0089] The fourth transistor Q4

[0090] The third load 126

[0091] Fourth load 127

[0092] First secondary output node N5

[0093] Second secondary output node N6

[0094] First secondary correction node N7

[0095] Second secondary correction node N8

[0096] Digital to Analog Converter 331

[0097] Switch unit 333

[0098] The first switching element S4

[0099] The second switching element S5

[0100] The first inverter IN1

[0101] Second primary correction control unit 132

[0102] Second primary bias control unit 118

[0103] The fifth transistor Q5

[0104] The sixth transistor Q6

[0105] Secondary bias control modules 15A, 15A_1, 15A_2, 15A_3, 15A_4, 15B, 15B_1,

[0106] 15B_2, 15B_3, 15B_4

[0107] The seventh transistor Q7

[0108] The eighth transistor Q8

[0109] Secondary correction control module 16

[0110] First secondary correction control unit 161, 161A

[0111] The second inverter IN2

[0112] The third switching element S6

[0113] The fourth switching element S7

[0114] Connect Node N9

[0115] The first current source 151

[0116] The second current source 152

[0117] The third inverter IN3

[0118] The fifth switching element S8

[0119] The ninth transistor Q9

[0120] The tenth transistor Q10

[0121] The eleventh transistor Q11

[0122] The first voltage dividing resistor R2

[0123] The second voltage dividing resistor R3

[0124] Second secondary correction control unit 162

[0125] Compensation indicator signal Plus

[0126] Offset correction bits Bit(0) to Bit(N-1)

[0127] Target calibration bit Bit(target)

[0128] Offset correction control signal OFCZ

[0129] Compare output node COM_OUT

[0130] Initial stage T0

[0131] Offset Correction Phase T1

[0132] Data transmission phase T2

[0133] Resistor R1

[0134] Capacitor C1

[0135] Steps S2001 to S2005, S2101 to S2105

[0136] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0137] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0138] The terms "first", "second", and "third" in the specification of this application and the above drawings are used to distinguish different objects rather than to describe a specific order. In addition, the term "includes" and any of their variations are intended to cover non-exclusive inclusions.

[0139] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0140] The specific implementation of the signal receiver with offset voltage correction function and the offset voltage correction method of the present application will be described below in conjunction with the accompanying drawings.

[0141] See also Figure 1 , which is a module schematic diagram of a signal receiver 1 of the first embodiment. The signal receiver 1 is electrically connected between the transmitter 2 and the signal processor 3, and is used to process the signal transmitted by the transmitter 2 and output the signal to the signal processor 3. In at least one embodiment of the present application, the signal receiver 1 receives a positive input signal TXP and a negative input signal TXN from the transmitter 2, and performs signal processing on the positive input signal TXP and the negative input signal TXN in various ways and then outputs the corresponding signal to the signal processor 3. The positive input signal TXP and the negative input signal TXN form differential signals. In addition, in some embodiments, the signal receiver 1 and the signal processor 3 can also be integrated to form a circuit.

[0142] The signal receiver 1 receives the positive input signal TXP and the negative input signal TXN sent by the transmitter 2 through the first signal input terminal 1_1 and the second signal input terminal 1_2 respectively, processes the received positive input signal TXP and the negative input signal TXN, and then outputs a comparison signal to the signal processor 3 through the comparison output node COM_OUT.

[0143] The signal receiver 1 further includes an amplification circuit 10, a comparison circuit 20 and an offset correction circuit 30. At the same time, after the signal receiver 1 is powered on, it operates in the initial stage T0, the offset correction stage T1 and the data transmission stage T2 in sequence. In the initial stage T0, the signal receiver 1 performs an initialization operation, for example, the signal receiver 1 performs the initial setting of circuit parameters and makes the internal voltage reach a preset level, but is not limited to this; in the offset correction stage T1, the signal receiver 1 corrects the offset of the internal DC voltage; in the data transmission stage T2, the signal receiver 1 is used to process the signal from the transmitter 2 and transmit it to the signal processor 3. In at least one embodiment of the present application, there is only one offset correction stage T1 in the operation process of the signal receiver 1. That is, the signal receiver 1 only performs an offset correction operation once. In other embodiments, the operation process of the signal receiver 1 can set multiple offset correction stages T1 according to actual needs, and multiple offset correction stages T1 and data transmission stages T2 exist alternately.

[0144] The amplifier circuit 10 has a first amplifier input terminal 101, a second amplifier input terminal 102, a first amplifier output terminal 103 and a second amplifier output terminal 104. The first amplifier input terminal 101 and the second amplifier input terminal 102 of the amplifier circuit 10 serve as signal input terminals of the signal receiver 1. In at least one embodiment of the present application, the first amplifier input terminal 101 is used to receive a positive input signal TXP, and the second amplifier input terminal 102 is used to receive a negative input signal TXN. In other embodiments, the first amplifier input terminal 101 is used to receive a negative input signal TXN, and the second amplifier input terminal 102 is used to receive a positive input signal TXP. In at least one embodiment of the present application, the amplifier circuit 10 includes a primary amplifier module 11, a secondary amplifier module 12 and a primary correction control module 13 (such as Figure 2 shown).

[0145] The primary amplifier module 11 has a first primary input terminal 111, a second primary input terminal 112, a first primary output terminal 113 and a second primary output terminal 114. The secondary amplifier module 12 has a first secondary input terminal 120, a second secondary input terminal 121, a first secondary output terminal 122 and a second secondary output terminal 123. The comparison circuit 20 has a first comparison input terminal 20A and a second comparison input terminal 20B. The first signal input terminal 1_1 is electrically connected to the first amplifier input terminal 101, and there is no additional switch element required to change the stage of the signal receiver 1 between the two. The second signal input terminal 1_2 is electrically connected to the second amplifier input terminal 102, and there is no additional switch element required to change the stage of the signal receiver 1 between the two. The first amplifier input terminal 101 is directly electrically connected to the first primary input terminal 111, and the second amplifier input terminal 102 is directly electrically connected to the second primary input terminal 112. The first primary output terminal 113 is directly electrically connected to the first secondary input terminal 120, and the second primary output terminal 114 is directly electrically connected to the second secondary input terminal 121. The first secondary output terminal 122 is directly electrically connected to the first amplified output terminal 103, and the second secondary output terminal 123 is directly electrically connected to the second amplified output terminal 104. The first amplified output terminal 103 is directly electrically connected to the first comparison input terminal 20A, and the second amplified output terminal 104 is directly electrically connected to the second comparison input terminal 20B.

[0146] There are a high-speed signal path for transmitting a positive input signal TXP and a high-speed signal path for transmitting a negative input signal TXN in the signal receiver 1. The high-speed signal path for transmitting the positive input signal TXP is composed of a plurality of sections, which specifically include: a first signal input section is formed between the first signal input terminal 1_1 for receiving the positive input signal TXP and the first amplifying input terminal 101 in the signal receiver 1, a first primary input section is formed between the first amplifying input terminal 101 and the first primary input terminal 111, a first primary transmission section is formed between the first primary output terminal 113 and the first secondary input terminal 120, a first secondary transmission section is formed between the first secondary output terminal 122 and the first amplifying output terminal 103, and a first signal transmission section is formed between the first amplifying output terminal 103 and the first comparison input terminal 20A of the comparison circuit 20. The high-speed signal path for transmitting the negative input signal TXN is also composed of several sections, which may specifically include: a second signal input section formed between the second signal input terminal 1_2 for receiving the negative input signal TXN and the second amplifying input terminal 102 in the signal receiver 1, a second primary input section formed between the second amplifying input terminal 102 and the second primary input terminal 112, a second primary transmission section formed between the second primary output terminal 114 and the second secondary input terminal 121, a second secondary transmission section formed between the second secondary output terminal 123 and the second amplifying output terminal 104, and a second signal transmission section formed between the second amplifying output terminal 104 and the second comparison input terminal 20B of the comparison circuit 20. There is no additional switching element (such as a transistor, a mechanical switch, etc., but not limited to this) required for switching the stage of the signal receiver 1 on the high-speed signal path, so there is no additional parasitic resistance and / or capacitance, so the operating speed of the signal receiver 1 can be maintained, so that the signal receiver 1 can meet the requirements of high bandwidth, and therefore, this signal path is called a high-speed signal path in this case. It should be noted that, in some embodiments, components with specific functions, such as electrostatic protection resistors, may be included between the first signal input terminal 1_1 and the first amplifying input terminal 101 and between the second signal input terminal 1_2 and the second amplifying input terminal 102 .

[0147] The primary correction control module 13 is used to control the primary amplification module 11 to be enabled or disabled according to the offset correction control signal OFCZ, and the primary correction control module 13 is separated from the high-speed signal path. That is, the primary correction control module 13 is located outside the high-speed signal path, and is not directly connected to the high-speed signal path. Figure 2 as well as Figures 12 to 17 As shown, the offset correction control signal OFCZ is used to indicate whether the signal receiver 1 is in the offset correction mode.

[0148] The amplifier circuit 10 is used to perform offset correction on the signal at its own output end according to the offset correction signal (such as a voltage or current signal) output by the offset correction circuit 30 in the offset correction stage T1, and to output the first amplified output signal and the second amplified output signal to the comparison circuit 20 through the first amplified output terminal 103 and the second amplified output terminal 104 after multiple amplification of the signals input by the first amplified input terminal 101 and the second amplified input terminal 102 in the data transmission stage T2.

[0149] Specifically, the primary amplification module 11 is used to be in a disabled state during the offset correction stage T1. The primary amplification module 11 in the disabled state stops outputting the primary amplified signal through the first primary output terminal 113 and the second primary output terminal 114. The primary amplified signal includes the first primary output signal and the second primary output signal. The primary amplification module 11 is also used to be in an enabled state during the data transmission stage T2. The primary amplification module 11 in the enabled state is used to perform primary amplification on the positive input signal TXP and the negative input signal TXN received by the first primary input terminal 111 and the second primary input terminal 112, and then output the first primary output signal and the second primary output signal to the secondary amplification module 12 through the first primary output terminal 113 and the second primary output terminal 114.

[0150] Please also read Figure 2, which is a partial circuit diagram of the amplifier circuit 10A in the signal receiver 1A of the first embodiment. The primary amplifier module 11A includes a first primary bias control unit 115, a first transistor Q1, a second transistor Q2, a first load 116 and a second load 117. The control end of the first primary bias control unit 115 is electrically connected to the primary correction control module 13, the first connection end of the first primary bias control unit 115 receives the working voltage VDD, and the second connection end of the first primary bias control unit 115 is electrically connected to the first transistor Q1 and the second transistor Q2. The control end of the first transistor Q1 is electrically connected to the first primary input end 111, the first connection end of the first transistor Q1 is electrically connected to the first primary bias control unit 115, and the second connection end of the first transistor Q1 is electrically connected to the first load 116 through the first primary output node N1. The control end of the second transistor Q2 is electrically connected to the second primary input end 112, the first connection end of the second transistor Q2 is electrically connected to the first primary bias control unit 115; the second connection end of the second transistor Q2 is electrically connected to the second load 117 through the second primary output node N2. One end of the first load 116 is electrically connected to the first primary output node N1, and the other end receives the ground voltage GND. One end of the second load 117 is electrically connected to the second primary output node N2, and the other end receives the ground voltage GND. The first primary output node N1 is further directly electrically connected to the first primary output terminal 113, and the second primary output node N2 is further directly electrically connected to the second primary output terminal 114. In at least one embodiment of the present application, the primary amplifier module 11A is a common source amplifier module; the first transistor Q1 and the second transistor Q2 are P-type field effect transistors (PMOS); the control end is the gate, the first connection end is the source, and the second connection end is the drain; the first load 116 and the second load 117 can be transistors or resistors.

[0151] The secondary amplifier module 12 is electrically connected between the primary amplifier module 11 and the comparison circuit 20, and is electrically connected to the offset correction circuit 30. The secondary amplifier module 12 is used to output a secondary amplified signal to the comparison circuit 20. The secondary amplified signal includes a first secondary output signal and a second secondary output signal. In the offset correction stage T1 (when the primary amplifier module 11 is in a disabled state), the secondary amplifier module 12 outputs a first secondary output signal and a second secondary output signal according to the rated voltage VB and the preset compensation current output by the offset correction circuit 30. That is, the first secondary output signal and the second secondary output signal are the first internal voltage signal and the second internal voltage signal generated by the secondary amplifier module 12 based on the rated voltage VB and the preset compensation current output by the offset correction circuit 30. In addition, although the primary amplifier module 11 is in a disabled state, it only disables the amplification function of the positive input signal TXP and the negative input signal TXN, but the first load 116 and the second load 117 therein have an influence on the first secondary output signal and the second secondary output signal. In the data transmission stage T2 (at this time, the primary amplifier module 11 is in the enabled state), the secondary amplifier module 12 performs an amplification function and outputs a first secondary output signal and a second secondary output signal according to the rated voltage VB, the first primary output signal, the second primary output signal, and the target compensation current output by the offset correction circuit 30. Taking the offset correction circuit 30 compensating the second secondary output signal of the secondary amplifier module 12 as an example, the first secondary output signal is the superposition of the first primary output signal output by the first primary output terminal 113 and the first internal voltage signal, and the second secondary output signal is the superposition of the first primary output signal output by the second primary output terminal 114, the second internal voltage signal, and the target compensation current output by the offset correction circuit 30.

[0152] In addition, the rated voltage VB may be provided by an internal power generation circuit (not shown) of the signal receiver 1A, or may be provided by an external power source of the signal receiver 1A.

[0153] Specifically, if Figure 2In the signal receiver 1A of the first embodiment shown, the secondary amplifier module 12A includes a first secondary bias current source 124, a second secondary bias current source 125, a third transistor Q3, a fourth transistor Q4, a third load 126 and a fourth load 127. The first secondary bias current source 124 is used to provide a first secondary bias current to the third transistor Q3 through the first secondary input node N3. One end of the first secondary bias current source 124 is electrically connected to the ground voltage GND, and the other end is electrically connected to the first connection end of the third transistor Q3 through the first secondary input node N3. The first secondary input node N3 is further electrically connected to the first secondary input terminal 120. The second secondary bias current source 125 is used to provide a second secondary bias current to the fourth transistor Q4 through the second secondary input node N4. One end of the second secondary bias current source 125 is electrically connected to the ground voltage GND, and the other end is electrically connected to the first connection end of the fourth transistor Q4 through the second secondary input node N4. The second secondary input node N4 is further electrically connected to the second secondary input terminal 121. The control terminal of the third transistor Q3 receives the rated voltage VB, the first connection terminal of the third transistor Q3 is electrically connected to the first secondary bias current source 124 through the first secondary input node N3, and the second connection terminal of the third transistor Q3 is electrically connected to the third load 126 through the first secondary output node N5. The first secondary output node N5 is further electrically connected to the first secondary output terminal 122. The control terminal of the fourth transistor Q4 receives the rated voltage VB, the first connection terminal of the fourth transistor Q4 is electrically connected to the second secondary bias current source 125 through the second secondary input node N4, and the second connection terminal of the fourth transistor Q4 is electrically connected to the fourth load 127 through the second secondary output node N6. The second secondary output node N6 is further electrically connected to the second secondary output terminal 123. One end of the third load 126 is electrically connected to the first secondary output node N5, and the other end receives the operating voltage VDD. One end of the fourth load 127 is electrically connected to the second secondary output node N6, and the other end receives the operating voltage VDD. At the same time, the first secondary input node N3 is multiplexed as the first secondary correction node N7, and the second secondary input node N4 is multiplexed as the second secondary correction node N8. In at least one embodiment of the present application, the secondary amplifier module 12A is a common gate amplifier module; the third transistor Q3 and the fourth transistor Q4 are N-type field effect transistors (NMOS); the control terminal is the gate, the first connection terminal is the source, and the second connection terminal is the drain; the third load 126 and the fourth load 127 can be transistors or resistors.

[0154] The primary calibration control module 13 is electrically connected to the primary amplifier module 11. The primary calibration control module 13 is used to control the primary amplifier module 11A to be enabled or disabled according to the offset calibration control signal OFCZ, and the primary calibration control module 13 is separated from the high-speed signal path in the amplifier circuit 10A. Figure 2 In the embodiment shown, the primary correction control module 13 is located outside the high-speed signal path formed by the first signal input terminal 1_1, the first amplifying input terminal 101, the first primary input terminal 111, the first primary output terminal 113, the first secondary input terminal 120, the first secondary output terminal 122, the first amplifying output terminal 103, the first comparison input terminal 20A and the second signal input terminal 1_2, the second amplifying input terminal 102, the second primary input terminal 112, the second primary output terminal 114, the second secondary input terminal 121, the second secondary output terminal 123, the second amplifying output terminal 104, and the second comparison input terminal 20B.

[0155] The primary correction control module 13 includes a first primary correction control unit 131. The first primary correction control unit 131 receives a first bias voltage Vbias1 and an offset correction control signal OFCZ, and is used to output a first primary bias switching signal to the first primary bias control unit 115 according to the first bias voltage Vbias1 and the offset correction control signal OFCZ. The offset correction control signal OFCZ can be switched between a first level and a second level, so that the signal receiver 1 operates in an offset correction phase T1 and a data transmission phase T2, respectively. In the offset correction phase T1, the offset correction control signal OFCZ is at a first level (e.g., a ground voltage GND), and the first primary correction control unit 131 uses the operating voltage VDD as the first primary bias switching signal and outputs it to the first primary bias control unit 115. That is, the first primary bias switching signal is at a first voltage. In the data transmission phase T2, the offset correction control signal OFCZ is at a second level (e.g., an operating voltage VDD), and the first primary correction control unit 131 uses the first bias voltage Vbias1 as the first primary bias switching signal and outputs it to the first primary bias control unit 115. That is, the first primary bias switching signal is at the second voltage. The first bias voltage Vbias1 is greater than the ground voltage GND and less than the working voltage VDD, and is used to control the primary amplification module 11A to be in an enabled state during the data transmission stage T2 to achieve amplification of the positive input signal TXP and the negative input signal TXN. Figure 3 or Figure 4Taking the circuit of the first primary correction control unit 131 shown as an example, the first primary correction control unit 131 includes a first control switch S1 and a second control switch S2. The first connection end of the first control switch S1 receives the first bias voltage Vbias1, and the second connection end of the first control switch S1 is electrically connected to the first primary bias control unit 115A / 115B; the control end of the first control switch S1 receives the offset correction control signal OFCZ. The control end of the second control switch S2 receives the offset correction control signal OFCZ, the first connection end of the second control switch S2 receives the working voltage VDD, and the second connection end of the second control switch S2 is electrically connected to the first primary bias control unit 115A / 115B. In at least one embodiment of the present application, the first level is a low level (for example, a ground voltage GND), and the second level is a high level (for example, a working voltage VDD); the first control switch S1 can be an NMOS, and the second control switch S2 can be a PMOS. That is, in the offset correction stage T1, the offset correction control signal OFCZ is at a low level, the first control switch S1 is turned off, and the second control switch S2 is turned on, so that the operating voltage VDD is provided to the first primary bias control unit 115A / 115B as a first primary bias switching signal. The first primary bias control unit 115A / 115B stops outputting the first primary bias current to the first transistor Q1 and the second transistor Q2 according to the operating voltage VDD. In the data transmission stage T2, the offset correction control signal OFCZ is at a high level, the first control switch S1 is turned on, and the second control switch S2 is turned off, so that the first bias voltage Vbias1 is provided to the first primary bias control unit 115A / 115B as a first primary bias switching signal. The first primary bias control unit 115A / 115B outputs the first primary bias current to the first transistor Q1 and the second transistor Q2 according to the first bias voltage Vbias1.

[0156] like Figure 3 As shown, it is a circuit diagram of the first primary bias control unit 115A and the first primary correction control unit 131 of the first embodiment. The first primary bias control unit 115A includes two bias control switches S3. Among them, the control end of each bias control switch S3 receives the first primary bias switching signal, and the first connection end of each offset control switch S3 receives the working voltage VDD, wherein the second connection end of one offset control switch S3 is electrically connected to the first connection end of the first transistor Q1, and the second connection end of the other offset control switch S3 is electrically connected to the first connection end of the second transistor Q2. In at least one embodiment of the present application, the bias control switch S3 is a PMOS.

[0157] like Figure 4FIG. 1 is a circuit diagram of the first primary bias control unit 115B and the first primary correction control unit 131 of the second embodiment. Figure 3 The first primary correction control unit 131 in the first embodiment is the same as that in the first embodiment, and the specific electrical connection relationship is not repeated here. The first primary bias control unit 115B of the second embodiment has roughly the same structure as the first primary bias control unit 115A of the first embodiment. That is to say, the description of the first primary bias control unit 115A of the first embodiment is basically applicable to the first primary bias control unit 115B of the second embodiment. The main difference between the two is that the first primary bias control unit 115B only includes one bias control switch S3. The second connection end of the bias control switch S3 is electrically connected to the first connection end of the first transistor Q1 and the first connection end of the second transistor Q2 at the same time.

[0158] The comparison circuit 20 is electrically connected between the amplifier circuit 10 and the offset correction circuit 30. The comparison circuit 20 has a first comparison input terminal 20A and a second comparison input terminal 20B. The first comparison input terminal 20A is directly electrically connected to the first amplifier output terminal 103, and the second comparison input terminal 20B is directly electrically connected to the second amplifier output terminal 104. The comparison circuit 20 is used to process the received first secondary output signal and the second secondary output signal and output the comparison signal to the offset correction circuit 30 through the comparison output node COM_OUT. In at least one embodiment of the present application, the comparison signal of the comparison output node COM_OUT can be a single-ended signal (analog or digital signal) or a differential signal. In at least one embodiment of the present application, when the comparison signal is a digital signal, it can change between 0 and 1. When the comparison signal is 0, it indicates that the compensation current provided by the offset correction circuit 30 is too large; when the comparison signal is 1, it indicates that the compensation current provided by the offset correction circuit 30 is too small. In at least one embodiment of the present application, the comparison circuit 20 may also include a buffer as an output stage.

[0159] Other amplifiers (not shown) may be further provided between the amplifier circuit 10 and the comparison circuit 20. In at least one embodiment of the present application, these amplifiers may be equalizers (EQ) and / or current-mode logic (CML) circuits, but are not limited thereto and may be determined according to actual application requirements.

[0160] The offset correction circuit 30 is electrically connected between the comparison circuit 20 and the amplifier circuit 10. The offset correction circuit 30 is used to perform a successive approximation correction operation to determine a target compensation current according to the comparison signal of the comparison output node COM_OUT, the compensation indication signal Plus and the offset correction clock signal OFC_CLK in the offset correction stage T1, and output the target compensation current to the first secondary correction node N7 or the second secondary correction node N8 in the secondary amplifier module 12. Each successive approximation correction operation corresponds to a different preset compensation current, and the secondary amplification signal generated by the secondary amplifier module 12 changes with the change of the preset compensation current. The offset correction circuit 30 is also used to maintain the provision of the target compensation current to the first secondary correction node N7 or the second secondary correction node N8 in the secondary amplifier module 12 in the data transmission stage T2, thereby correcting the offset voltage.

[0161] Please also read Figure 5 , which is a module diagram of the offset correction circuit 30A of the first embodiment. In at least one embodiment of the present invention, the offset correction circuit 30A includes a compensation indication module 31, a successive approximation register (SAR) module 32, and a digital-to-analog converter module 33A (DAC). In at least one embodiment of the present application, the digital-to-analog converter module 33A can be a voltage DAC or a current DAC.

[0162] The compensation indication module 31 is electrically connected between the comparison circuit 20 and the digital-to-analog conversion module 33. The compensation indication module 31 is used to output a compensation indication signal Plus to the digital-to-analog conversion module 33 according to the initial comparison signal of the comparison output node COM_OUT. The compensation indication signal Plus is used to indicate that one of the first secondary correction node N7 and the second secondary correction node N8 in the secondary amplifier module 12 needs to be compensated. In at least one embodiment of the present application, when the initial comparison signal of the comparison output node COM_OUT is a low level (for example, the ground voltage GND), the compensation indication signal Plus indicates that the first secondary correction node N7 in the secondary amplifier module 12 needs to be compensated; when the comparison signal received from the comparison output node COM_OUT is a high level (for example, the operating voltage VDD), the compensation indication signal Plus determines that the second secondary correction node N8 in the secondary amplifier module 12 needs to be compensated.

[0163] The successive approximation module 32 is electrically connected between the comparison circuit 20 and the digital-to-analog conversion module 33. The successive approximation module 32 is used to output a plurality of offset correction bits Bit(0) to Bit(N-1) to the digital-to-analog conversion module 33 according to the comparison signal of the comparison output node COM_OUT and the offset correction clock signal OFC_CLK. In the compensation correction operation, the successive approximation module 32 adjusts the offset correction bit Bit(i) one by one. Specifically, taking the output of N offset correction bits Bit(0) to Bit(N-1) in the successive approximation correction operation as an example, wherein N is a positive integer greater than or equal to 1, the successive approximation module 32 starts from the most significant bit Bit(MSB) and adjusts to the least significant bit Bit(LSB) in sequence, wherein different correction bits Bit(i) correspond to different preset compensation currents. wherein i is an integer from 0 to N-1.

[0164] The digital-to-analog conversion module 33A is electrically connected between the successive approximation module 32 and the secondary amplifier module 12, and is electrically connected to the compensation indication module 31. The digital-to-analog conversion module 33A is used to obtain a plurality of different preset compensation currents according to the offset correction bits Bit(0) to Bit(N-1) in the offset correction stage T1 and provide the preset compensation currents to the first secondary correction node N7 or the second secondary correction node N8 according to the compensation indication signal Plus. After the successive approximation correction operation, the target value of each offset correction bit Bit(0) to Bit(N-1) can be determined at the end of the offset correction stage T1, and the corresponding sum of the preset compensation currents is used as the target compensation current. The digital-to-analog conversion module 33A is also used to continuously output the target compensation current to the first secondary correction node N7 or the second secondary correction node N8 in the data transmission stage T2. In at least one embodiment of the present application, the digital-to-analog conversion module 33A includes two digital-to-analog converters 331, one end of one digital-to-analog converter 331 is electrically connected to the successive approximation module 32, and the other end is electrically connected to the first secondary correction node N7; one end of the other digital-to-analog converter 331 is electrically connected to the successive approximation module 32, and the other end is electrically connected to the second secondary correction node N8.

[0165] See also Figure 6 , which is a schematic diagram of a module of an offset correction circuit 30B according to a second embodiment of the present application. The offset correction circuit 30B in the second embodiment is Figure 5The structure and operation mode of the offset correction circuit 30A in the first embodiment are roughly the same. That is to say, the description of the offset correction circuit 30A in the first embodiment can basically be applied to the offset correction circuit 30B in the second embodiment, and the main difference between the two is: a digital-to-analog conversion module 33B. The digital-to-analog conversion module 33B includes a digital-to-analog converter 331 and a switch unit 333. The switch unit 333 includes a first switch element S4 and a second switch element S5. The control end of the first switch element S4 receives the compensation indication signal Plus, the first connection end and the second connection end of the first switch element S4 are electrically connected to the digital-to-analog converter 331 and the first secondary correction node N7, respectively, and the control end of the second switch element S5 receives the compensation indication signal Plus through the first inverter IN1, and the first connection end and the second connection end of the second switch element S5 are electrically connected to the digital-to-analog converter 331 and the second secondary correction node N8, respectively. Among them, the digital-to-analog converter 331 is electrically connected to the successive approximation module 32. The switch unit 333 receives the compensation indication signal Plus, and the digital-to-analog converter 331 receives the offset correction bits Bit(0) to Bit(N-1) and the offset correction clock signal OFC_CLK output by the successive approximation module 32. The switch unit 333 selects the target compensation current of the digital-to-analog converter 331 to be output to the first secondary correction node N7 or the second secondary correction node N8 according to the compensation indication signal Plus. Specifically, when the compensation indication signal Plus is at a high level (e.g., the operating voltage VDD), the first switch element S4 is closed, the second switch element S5 is opened, and the target compensation current is provided to the first secondary correction node N7 through the first switch element S4; when the compensation indication signal Plus is at a low level (e.g., the ground voltage GND), the first switch element S4 is opened, the second switch element S5 is closed, and the target compensation current is provided to the second secondary correction node N8 through the second switch element S5.

[0166] In the offset correction circuit 30B, the digital-to-analog conversion module 33B adopts a structure of a digital-to-analog converter 331 and a switch unit 333 , which reduces the number of digital-to-analog converters 331 and further reduces the manufacturing cost of the signal receiver 1 .

[0167] Next, Figure 3 The working principle of the signal receiver 1A is explained by taking the first primary bias control unit 115A and the first primary correction control unit 131 and the five correction bits Bit(0) to Bit(4) used in the successive approximation module 32 as an example. Figure 7, which is a schematic diagram of the timing of multiple signals inside the signal receiver 1A. In at least one embodiment of the present application, the multiple signals include a positive input signal TXP, a negative input signal TXN, an offset correction control signal OFCZ, an offset correction clock signal OFC_CLK, a compensation indication signal Plus, a comparison signal of a comparison output node COM_OUT, 5 correction bits Bit(0) to Bit(4), and a DC voltage offset Offset. The DC voltage offset Offset represents the voltage difference between the first comparison input terminal 20A and the second comparison input terminal 20B of the comparison circuit 20, which can be regarded as the total voltage offset on the high-speed signal path.

[0168] In the initial stage T0, the signal receiver 1A is powered on and performs initialization operations. The primary amplification module 11A, the secondary amplification module 12A, the primary calibration control module 13, the comparison circuit 20, the successive approximation module 32 and the digital-to-analog conversion module 33 are not yet in operation.

[0169] In the offset correction stage T1, the signal receiver 1A operates in the offset correction mode. The first primary input terminal 111 of the primary amplifier module 11A receives the positive input signal TXP through the first amplifier input terminal 101, and the second primary input terminal 112 of the primary amplifier module 11A receives the negative input signal TXN through the second amplifier input terminal 102. The offset correction control signal OFCZ is at a low level, the first control switch S1 is turned off, and the second control switch S2 is turned on, so as to provide the working voltage VDD received by the first connection terminal of the second control switch S2 as the first primary bias switching signal to the control terminal of the bias control switch S3. According to the first primary bias switching signal, the bias control switch S3 is turned off. At this time, the primary amplifier module 11A operates in the offset correction mode, that is, the primary amplifier module 11A is in a disabled state. The first transistor Q1 and the second transistor Q2 do not perform signal amplification, so that the positive input signal TXP and the negative input signal TXN are not output to the secondary amplifier module 12A through the primary amplifier module 11A, and the first primary output node N1 and the second primary output node N2 stop outputting the first primary output signal and the second primary output signal. The secondary amplifier module 12A outputs the first internal output signal as the first secondary output signal to the first comparison input terminal 20A of the comparison circuit 20 through the first secondary output node N5 and the first amplifier output terminal 103 according to the rated voltage VB and the preset compensation current output by the offset correction circuit 30, and outputs the second internal output signal as the second secondary output signal to the second comparison input terminal 20B of the comparison circuit 20 through the second secondary output node N6 and the second amplifier output terminal 104. After the comparison circuit 20 processes the first secondary output signal received by the first comparison input terminal 20A and the second secondary output signal received by the second comparison input terminal 20B, it outputs the comparison signal to the compensation indication module 31 and the successive approximation module 32 through the comparison output node COM_OUT. The compensation indication module 31 outputs the compensation indication signal Plus to the digital-to-analog conversion module 33A according to the initial comparison signal of the comparison output node COM_OUT. The successive approximation module 32 sequentially outputs a plurality of offset correction bits Bit(0) to Bit(N-1) to the digital-to-analog conversion module 33A according to the comparison signal of the comparison output node COM_OUT and the offset correction clock signal OFC_CLK. When the DC voltage offset Offset is a positive number, it indicates that the preset compensation current corresponding to the current offset correction bit Bit(N-1) to Bit(0) of the successive approximation module 32 is too large; when the DC voltage offset Offset is a negative number, it indicates that the preset compensation current corresponding to the current offset correction bit Bit(N-1) to Bit(0) of the successive approximation module 32 is too small. Figure 7As shown in the example of FIG. 1 , in the offset correction stage T1 , the successive approximation module 32 sequentially adjusts the values ​​of the offset correction bits Bit(N-1) to Bit(0) to gradually reduce the DC voltage offset Offset and converge to a minimum value (ideally, 0V). The digital-to-analog conversion module 33A controls the first digital-to-analog converter 331 to provide the target compensation current to the first secondary correction node N7 according to the compensation indication signal Plus.

[0170] In the data transmission stage T2, the signal receiver 1A operates in the data transmission mode. The first primary input terminal 111 of the primary amplifier module 11A receives the positive input signal TXP through the first amplifier input terminal 101, and the second primary input terminal 112 of the primary amplifier module 11A receives the negative input signal TXN through the second amplifier input terminal 102. The offset correction control signal OFCZ is switched to a high level, the first control switch S1 is turned on, and the second control switch S2 is turned off, so as to provide the first bias voltage Vbias1 received by the first connection terminal of the first control switch S1 to the control terminal of the bias control switch S3. According to the first bias voltage Vbias1, the bias control switch S3 is turned on and provides a bias current to the first connection terminal of the first transistor Q1 and the second transistor Q2. At this time, the primary amplifier module 11A operates in the data transmission mode, that is, the primary amplifier module 11A is in an enabled state. The positive input signal TXP is amplified by the first transistor Q1 and outputs the first primary output signal to the first secondary input terminal 120 through the first primary output node N1 and the first primary output terminal 113. The negative input signal TXN is amplified by the second transistor Q2 and provides the second primary output signal to the second secondary input terminal 121 through the second primary output node N2 and the second primary output terminal 114. The secondary amplifier module 12A amplifies the first primary output signal according to the rated voltage VB and outputs the first secondary output signal to the first comparison input terminal 20A of the comparison circuit 20 through the first secondary output node N5, the first secondary output terminal 122 and the first amplified output terminal 103, and amplifies the second primary output signal according to the rated voltage VB and the preset compensation current output by the offset correction circuit 30 and outputs the second secondary output signal to the second comparison input terminal 20B of the comparison circuit 20 through the second secondary output node N6, the second secondary output terminal 123 and the second amplified output terminal 104. At this time, the first secondary output signal is the superposition result of the first primary output signal and the first internal voltage signal; the second secondary output signal is the superposition result of the second primary output signal, the second internal voltage signal and the target compensation current. After the comparison circuit 20 performs signal processing on the first secondary output signal and the second secondary output signal, it outputs the comparison signal to the signal processor 3 through the comparison output node COM_OUT.

[0171] As can be seen from the above, in the offset correction stage T1, the comparison signal on the comparison output node COM_OUT represents the comparison result of the successive approximation correction process of the signal receiver 1A; and in the data transmission stage T2, the comparison signal on the comparison output node COM_OUT serves as the output data of the signal receiver 1A.

[0172] In at least one embodiment of the present application, the operation process of the signal receiver 1 may have only one offset correction stage T1. That is, the signal receiver 1 performs only one offset correction operation. In other embodiments, the operation process of the signal receiver 1 may be set with multiple offset correction stages T1 according to actual needs, and multiple offset correction stages T1 and data transmission stages T2 alternately exist, so that correction can be performed in real time to reduce the DC voltage offset Offset.

[0173] Please also read Figure 8 , which is a schematic diagram of the gain and input signal frequency characteristic curves of the signal receiver of the prior art (a switch element for switching the operation mode is provided on the signal transmission path) and the signal receiver 1A of the first embodiment of the present case. Among them, the dotted line part is the gain and input signal frequency characteristic curve of the signal receiver of the prior art, and the solid line part is the gain and input signal frequency characteristic curve of the signal receiver 1A of the first embodiment of the present case.

[0174] By comparison, it can be seen that the -3dB bandwidth of the signal receiver in the prior art is about 1.67GHz, while the -3dB bandwidth of the signal receiver 1A of the first embodiment of the present application is about 17.1GHz. Therefore, the signal receiver 1A of the present application can receive higher frequency input signals and reduce the gain loss on high frequency signals, thereby optimizing the application range of the signal receiver 1A.

[0175] Please also read Fig. 9 as well as Fig.10 , Fig. 9 The eye diagram of the comparison signal outputted from the comparison output node COM_OUT when the signal receiver of the prior art (a switch element for switching the stage where the signal receiver 1 is located is provided on the signal transmission path) receives the positive input signal TXP and the negative input signal TXN of the specified data rate, Fig.10 This is an eye diagram of a comparison signal outputted from the comparison output node COM_OUT when the signal receiver 1A of the first embodiment of the present application receives a positive input signal TXP and a negative input signal TXN of a specified data rate. In at least one embodiment of the present application, the specified data rate is 4 Gbps.

[0176] from Fig. 9 as well as Fig.10It can be seen from the comparison that when receiving input signals of the same specified data rate, the eye width of the signal receiver in the prior art is 132ps and the eye height is 187mV. The eye width of the signal receiver 1A of the first embodiment of the present application is 182ps and the eye height is 473mV. That is, the signal receiver 1A of the first embodiment of the present application has better stability in signal transmission, and optimizes the stability of signal transmission of the signal receiver 1A.

[0177] Please also read Fig.11A and Fig. 11B , Fig.11A and Fig. 11B The results of 1000 Monte Carlo simulations of the signal receiver 1A in the first embodiment of the present application when the offset correction is not started and when the offset correction is started are shown in the figure. The distribution diagram of the DC voltage offset between the first comparison input terminal 20A and the second comparison input terminal 20B of the signal receiver 1A is shown in the figure. By comparison, it can be seen that Fig.11A When the offset correction is not started, the standard deviation σ is 78.6 mV, and the DC voltage offset between the first comparison input terminal 20A and the second comparison input terminal 20B is relatively dispersed. Fig. 11B When the offset correction is enabled, the standard deviation σ is greatly reduced to 11.5 mV, and the DC voltage offset between the first comparison input terminal 20A and the second comparison input terminal 20B is concentrated near 0V.

[0178] By comparison, it can be seen that the correction function of the signal receiver 1A of the first embodiment of the present invention can indeed improve the DC voltage offset phenomenon, so that the DC voltage offset distribution is more concentrated and the offset degree is lower.

[0179] In the above-mentioned signal receiver 1A, the primary amplifier module 11A can receive both the positive input signal TXP and the negative input signal TXN in both the offset correction stage T1 and the data transmission stage T2 (i.e., it is not necessary to shut down the transmitter 2 in the offset correction stage T1), and the correction effect is not affected, so it is not necessary to modify the transmission operation mode of the transmitter 2, thereby reducing the complexity of the overall system design. In addition, the signal receiver 1A uses the primary correction control module 13 isolated from the high-speed signal path to control whether the primary amplifier module 11A outputs the first primary output signal and the second primary output signal, thereby reducing the circuit architecture difference between the signal receiver 1A in the offset correction stage T1 and in the data transmission stage T2, thereby optimizing the offset correction effect of the signal receiver 1A.

[0180] See also Fig.12, which is a module schematic diagram of a signal receiver 1B in the second embodiment of the present application. The structure and operation mode of the signal receiver 1B in the second embodiment are roughly the same as those of the signal receiver 1A in the first embodiment. That is to say, the description of the signal receiver 1A in the first embodiment can basically be applied to the signal receiver 1B in the second embodiment. The main difference between the two is: a secondary amplification module 12B. The secondary amplification module 12B further includes a resistor R1 and a capacitor C1 connected in parallel. The two ends of the resistor R1 are electrically connected to the first secondary correction node N7 and the second secondary correction node N8, respectively. The two ends of the capacitor C1 are electrically connected to the first secondary correction node N7 and the second secondary correction node N8, respectively. In an embodiment of the present application, the resistor R1 is a variable resistor and the capacitor C1 is a variable capacitor.

[0181] The signal receiver 1B not only has the functions of the above-mentioned signal receiver 1A, but also can optimize the gain and linearity of the secondary amplifier module 12B by adjusting the resistance value of the resistor R1 and the capacitance value of the capacitor C1 in the secondary amplifier module 12B, and can reduce the signal attenuation when receiving high-frequency signals.

[0182] See also Fig.13 , which is a module diagram of a signal receiver 1C in the third embodiment of the present application. The structure and operation mode of the signal receiver 1C in the third embodiment are roughly the same as those of the signal receiver 1B in the second embodiment. That is to say, the description of the signal receiver 1B in the second embodiment is basically applicable to the signal receiver 1C in the third embodiment, and the main difference between the two is: the primary amplification module 11B and the primary correction control module 13. The primary correction control module 13 only includes the second primary correction control unit 132. The primary amplification module 11B is an N-type architecture. The first connection end of the first primary bias control unit 115 receives the ground voltage GND and is electrically connected, and the second connection end of the first primary bias control unit 115 is electrically connected to the first connection end of the first transistor Q1 and the first connection end of the second transistor Q2. One end of the first load 116 is electrically connected to the first primary output node N1, and the other end receives the working voltage VDD. One end of the second load 117 is electrically connected to the second primary output node N2, and the other end receives the working voltage VDD. The second primary correction control unit 132 receives the second bias voltage Vbias2 and the offset correction control signal OFCZ. The second primary correction control unit 132 has the same function as the first primary correction control unit 131 , and the specific operation process is not repeated here.

[0183] The signal receiver 1C not only has the functions of the signal receiver 1B, but also uses different types of first transistors Q1 and second transistors Q2 according to different common-mode levels of input signals to reduce gain loss in the signal receiver 1C.

[0184] See also Fig.14, which is a module schematic diagram of a signal receiver 1D in the fourth embodiment of the present application. The structure and operation mode of the signal receiver 1D in the fourth embodiment are roughly the same as those of the signal receiver 1A in the first embodiment. That is to say, the description of the signal receiver 1A in the first embodiment is basically applicable to the signal receiver 1D in the fourth embodiment. The main difference between the two is that the secondary amplification module 12C and the signal receiver 1D further include a secondary bias control module 15A and a secondary correction control module 16. In the secondary amplification module 12C, the control end of the third transistor Q3 serves as the first secondary input node N3 and is electrically connected to the first primary output terminal 113 through the first secondary input terminal 120. The control end of the fourth transistor Q4 serves as the second secondary input node N4 and is electrically connected to the second primary output terminal 114 through the second secondary input terminal 121. The first connection end of the secondary bias control module 15A receives the working voltage VDD, the second connection end thereof is electrically connected to the first primary output node N1 and the second primary output node N2, and the control end thereof is electrically connected to the secondary correction control module 16. The secondary correction control module 16 is used to control the secondary bias control module 15A to be in an enabled or disabled state according to the offset correction control signal OFCZ, and the secondary correction control module 16 is separated from the high-speed signal path in the signal receiver 1D. The secondary correction control module 16 only includes a first secondary correction control unit 161. The first secondary correction control unit 161 receives the offset correction control signal OFCZ and the third bias voltage Vbias3. The first secondary correction control unit 161 is used to control the secondary bias control module 15A to be in an enabled state during the offset correction stage T1, and to control the secondary bias control module 15A to be in a disabled state during the data transmission stage T2. In the fourth embodiment, during the offset correction stage T1, the first secondary correction control unit 161 controls the secondary bias control module 15A to establish an electrical connection between the working voltage VDD and the first primary output node N1 and the second primary output node N2. At this time, the first primary bias control unit 115 is in a disabled state, and the secondary correction control module 16 controls the secondary bias control module 15A to be in an enabled state. The secondary bias control module 15A and the first load 116 form a conductive path between the operating voltage VDD and the ground voltage GND. Therefore, a voltage division is generated on the first primary output node N1 and is provided to the control end of the third transistor Q3 as a secondary bias voltage. Similarly, the secondary bias control module 15A and the second load 117 form a conductive path between the operating voltage VDD and the ground voltage GND. Therefore, a voltage division is generated on the second primary output node N2 and is provided to the control end of the fourth transistor Q4 as a secondary bias voltage. The third transistor Q3 and the fourth transistor Q4 are in a conducting state. In the data transmission stage T2, the first primary bias control unit 115 is in an enabled state, and the secondary bias control module 15A is in a disabled state.The first secondary correction control unit 161 controls the secondary bias control module 15A to disconnect the electrical connection between the working voltage VDD and the first primary output node N1 and the second primary output node N2. At this time, the first primary output node N1 outputs the first primary output signal to the first secondary input node N3, the second primary output node N2 outputs the second primary output signal to the second secondary input node N4, and the third transistor Q3 and the fourth transistor Q4 respectively re-amplify the first primary output signal and the second primary output signal.

[0185] In other embodiments, the signal receiver 1D may further include a resistor R1 and a capacitor C1 connected in parallel between the first secondary correction node N7 and the second secondary correction node N8. By adjusting the resistance value of the resistor R1 and the capacitance value of the capacitor C1, the gain and linearity of the secondary amplifier module 12C can be optimized, and the signal attenuation can be reduced when receiving high-frequency signals.

[0186] The signal receiver 1D has not only the functions of the signal receiver 1A, but also the secondary bias voltage of the secondary amplifier module 12C is provided by the secondary bias control module 15A and the primary amplifier module 11A during the offset correction stage T1, so the area of ​​the related circuit can be reduced.

[0187] See also Fig.15, which is a module schematic diagram of a signal receiver 1E in the fifth embodiment of the present application. The structure and operation mode of the signal receiver 1E in the fifth embodiment are roughly the same as those of the signal receiver 1C in the third embodiment. That is to say, the description of the signal receiver 1C in the third embodiment is basically applicable to the signal receiver 1E in the fifth embodiment. The main difference between the two is: a secondary amplifier module 12C and a primary correction control module 13, and the signal receiver 1E further includes a secondary bias control module 15B and a secondary correction control module 16. The primary correction control module 13 only includes a second primary correction control unit 132. The secondary correction control module 16 is used to control the secondary bias control module 15B to an enabled or disabled state according to the offset correction control signal OFCZ, and the secondary correction control module 16 is separated from the high-speed signal path in the signal receiver 1E. The secondary correction control module 16 only includes a second secondary correction control unit 162. In the secondary amplifier module 12C, the control end of the third transistor Q3 serves as the first secondary input node N3, and is electrically connected to the first primary output terminal 113 through the first secondary input terminal 120. The control terminal of the fourth transistor Q4 serves as the second secondary input node N4, and is electrically connected to the second primary output terminal 114 through the second secondary input terminal 121. The second secondary correction control unit 162 receives the offset correction control signal OFCZ and the fourth bias voltage Vbias4. The first connection terminal of the secondary bias control module 15B is electrically connected to the ground voltage GND, the second connection terminal is electrically connected to the first primary output node N1 and the second primary output node N2, and the control terminal is electrically connected to the second secondary correction control unit 162. The secondary bias control module 15B of the fifth embodiment has the same function as the secondary bias control module 15A of the fourth embodiment, and the specific operation process is not repeated here.

[0188] The signal receiver 1E not only has the functions of the signal receiver 1C, but also has the functions of the signal receiver 1C. In the offset correction stage T1, the secondary bias voltage of the secondary amplifier module 12C is provided by the secondary bias control module 15A and the primary amplifier module 11A, so the relevant circuit area can be reduced.

[0189] See also Fig.16, which is a module diagram of a signal receiver 1F in the sixth embodiment of the present application. The structure and operation mode of the signal receiver 1F in the sixth embodiment are roughly the same as those of the signal receiver 1D in the fourth embodiment. That is to say, the description of the signal receiver 1D in the fourth embodiment is basically applicable to the signal receiver 1F in the sixth embodiment, and the main difference between the two is: a primary amplification module 11C, a primary correction control module 13 and a secondary amplification module 12D. In addition to the first primary correction control unit 131, the primary correction control module 13 also includes a second primary correction control unit 132. Compared with the primary amplification module 11A in the fourth embodiment, the primary amplification module 11C in the sixth embodiment also includes a second primary bias control unit 118 and a fifth transistor Q5 and a sixth transistor Q6. Among them, the control end of the fifth transistor Q5 is electrically connected to the first primary input end 111, its first connection end is electrically connected to the second primary bias control unit 118, and its second connection end is electrically connected to the second secondary output node N6. The control terminal of the sixth transistor Q6 is electrically connected to the second primary input terminal 112, the first connection terminal thereof is electrically connected to the second primary bias control unit 118, and the second connection terminal thereof is electrically connected to the first secondary output node N5. The first connection terminal of the second primary bias control unit 118 receives the ground voltage GND, the second connection terminal thereof is electrically connected to the first connection terminal of the fifth transistor Q5 and the first connection terminal of the sixth transistor Q6, and the control terminal of the second primary bias control unit 118 is electrically connected to the second primary correction control unit 132. The working principle of the second primary bias control unit 118 is substantially the same as that of the first primary bias control unit 115, and will not be described in detail herein. Compared with the secondary amplifier module 12C in the fourth embodiment, the secondary amplifier module 12D in the sixth embodiment does not have the first secondary bias current source 124 and the second secondary bias current source 125. In the secondary amplifier module 12D, the first primary output node N1 is electrically connected to the control end of the third transistor Q3 through the first secondary input node N3, and the offset correction circuit 30 is electrically connected to the first secondary output node N5; at the same time, the second primary output node N2 is electrically connected to the control end of the fourth transistor Q4 through the second secondary input node N4, and the offset correction circuit 30 is electrically connected to the second secondary output node N6. That is, the first secondary output node N5 is multiplexed as the first secondary correction node N7, and the second secondary output node N6 is multiplexed as the second secondary correction node N8. The function of the first primary correction control unit 131 in the sixth embodiment is the same as that of the second primary correction control unit 132, and the specific operation process is not repeated here. In the sixth embodiment, the first transistor Q1 and the second transistor Q2 are PMOS, and the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5 and the sixth transistor Q6 are NMOS.

[0190] The signal receiver 1F has the same functions as the above-mentioned signal receiver 1D, which will not be described in detail here.

[0191] See also Fig.17, which is a module diagram of a signal receiver 1G of the seventh embodiment of the present application. The structure and operation mode of the signal receiver 1G in the seventh embodiment are roughly the same as those of the signal receiver 1E in the fifth embodiment. That is to say, the description of the signal receiver 1E in the fifth embodiment can basically be applied to the signal receiver 1G in the seventh embodiment. The main difference between the two is: a primary amplification module 11D, a primary correction control module 13 and a secondary amplification module 12D. The primary correction control module 13 also includes a first primary correction control unit 131 and a second primary correction control unit 132. Compared with the primary amplification module 11B in the fifth embodiment, the primary amplification module 11D in the seventh embodiment also includes a second primary bias control unit 118 and a fifth transistor Q5 and a sixth transistor Q6. Among them, the control end of the fifth transistor Q5 is electrically connected to the first primary input end 111, its first connection end is electrically connected to the second primary bias control unit 118, and its second connection end is electrically connected to the second secondary output node N6. The control end of the sixth transistor Q6 is electrically connected to the second primary input end 112, the first connection end thereof is electrically connected to the second primary bias control unit 118, and the second connection end thereof is electrically connected to the first secondary output node N5. The first connection end of the second primary bias control unit 118 receives the operating voltage VDD, the second connection end thereof is electrically connected to the first connection ends of the fifth transistor Q5 and the sixth transistor Q6, and the control end of the second primary bias control unit 118 is electrically connected to the second primary correction control unit 132. The working principle of the second primary bias control unit 118 is substantially the same as the structure and operation process of the first primary bias control unit 115, and will not be described in detail herein. Compared with the secondary amplifier module 12C in the fifth embodiment, the secondary amplifier module 12D in the seventh embodiment removes the first secondary bias current source 124 and the second secondary bias current source 125. In the secondary amplifier module 12D, the first primary output node N1 is electrically connected to the control end of the third transistor Q3 through the first secondary input node N3, and the offset correction circuit 30 is electrically connected to the first secondary output node N5; at the same time, the second primary output node N2 is electrically connected to the control end of the fourth transistor Q4 through the second secondary input node N4, and the offset correction circuit 30 is electrically connected to the second secondary output node N6. That is, the first secondary output node N5 is multiplexed as the first secondary correction node N7, and the second secondary output node N6 is multiplexed as the second secondary correction node N8. Among them, the first secondary output node N5 and the second secondary output node N6 are multiplexed as the first secondary correction node N7 and the second secondary correction node N8. In the seventh embodiment, the function of the second primary correction control unit 132 is the same as that of the first primary correction control unit 131, and the specific operation process is not repeated here.In the seventh embodiment, the first transistor Q1 and the second transistor Q2 are PMOS, and the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 are NMOS.

[0192] The signal receiver 1G has the same functions as the above-mentioned signal receiver 1D, which will not be described in detail here.

[0193] In the first to seventh embodiments, the specific structures of the first primary bias control unit 115 and the second primary bias control unit 118 can be adjusted according to the different connection relationships between them and other electronic components in the primary amplification modules 11A-11D. In addition, in the first to seventh embodiments, the first primary bias control unit 115 and the second primary bias control unit 118 are switched between an enabled state and a disabled state under the control of the primary correction control module 13. In the offset correction stage T1, the first primary bias control unit 115 and the second primary bias control unit 118 are controlled by the primary correction control module 13 to be in a disabled state at the same time, the first primary bias control unit 115 stops providing the first primary bias current to the corresponding first transistor Q1 and the second transistor Q2, and the second primary bias control unit 118 stops providing the second primary bias current to the corresponding fifth transistor Q5 and the sixth transistor Q6. In the data transmission stage T2, the primary correction control module 13 controls the first primary bias control unit 115 and the second primary bias control unit 118 to be in an enabled state at the same time. The first primary bias control unit 115 provides a first primary bias current to the corresponding first transistor Q1 and the second transistor Q2, and the second primary bias control unit 118 provides a second primary bias current to the corresponding fifth transistor Q5 and the sixth transistor Q6.

[0194] See also Figures 18A-18D , which is a circuit diagram of the secondary bias control module 15A of the first to fourth embodiments. Fig.18AAs shown, in the first embodiment, the secondary bias control module 15A_1 includes a seventh transistor Q7 and an eighth transistor Q8. The control end of the seventh transistor Q7 and the control end of the eighth transistor Q8 are electrically connected to the first secondary correction control unit 161 through the connection node N9, the first connection end of the seventh transistor Q7 and the first connection end of the eighth transistor Q8 receive the working voltage VDD, and the second connection end of the seventh transistor Q7 and the second connection end of the eighth transistor Q8 are electrically connected to the first primary output node N1 and the second primary output node N2 respectively. The first secondary correction control unit 161 includes a second inverter IN2, a third switch element S6 and a fourth switch element S7. The input end of the second inverter IN2 receives the offset correction control signal OFCZ, and the output end thereof is electrically connected to the control end of the third switch element S6. The first connection end of the third switch element S6 receives the third bias voltage Vbias3, and the second connection end thereof is electrically connected to the control ends of the seventh transistor Q7 and the eighth transistor Q8 through the connection node N9. The control terminal of the fourth switch element S7 receives the offset correction control signal OFCZ, the first connection terminal receives the working voltage VDD, and the second connection terminal is electrically connected to the control terminals of the seventh transistor Q7 and the eighth transistor Q8 through the connection node N9. In this embodiment, the seventh transistor Q7 and the eighth transistor Q8 are PMOS.

[0195] like Fig.18B As shown, in the second embodiment, the secondary bias control module 15A_2 includes a third inverter IN3, a fifth switch element S8, a first current source 151 and a second current source 152. Among them, the input end of the third inverter IN3 is electrically connected to the first secondary correction control unit 161, and the output end thereof is electrically connected to the control end of the fifth switch element S8. The first connection end of the fifth switch element S8 receives the working voltage VDD, and the second connection end thereof is electrically connected to the first current source 151 and the second current source 152. The input end of the first current source 151 is electrically connected to the second connection end of the fifth switch element S8, and the output end thereof is electrically connected to the first primary output node N1. The input end of the second current source 152 is electrically connected to the second connection end of the fifth switch element S8, and the output end thereof is electrically connected to the second primary output node N2. In the second embodiment, the first secondary correction control unit 161 is used to directly output the received offset correction control signal OFCZ to the secondary bias control module 15A_2, and its internal circuit structure is again not specifically limited.

[0196] like Fig.18CAs shown, in the third embodiment, the secondary bias control module 15A_3 includes a ninth transistor Q9, a first voltage-dividing resistor R2, and a second voltage-dividing resistor R3. Among them, the control end of the ninth transistor Q9 is electrically connected to the first secondary correction control unit 161, and its first connection end receives the working voltage VDD, and its second connection end is electrically connected to the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3. One end of the first voltage-dividing resistor R2 is electrically connected to the second connection end of the ninth transistor Q9, and the other end is electrically connected to the first primary output node N1. One end of the second voltage-dividing resistor R3 is electrically connected to the second connection end of the ninth transistor Q9, and the other end is electrically connected to the second primary output node N2. In the third embodiment, the first secondary correction control unit 161 is used to directly output the received offset correction control signal OFCZ to the secondary bias control module 15A_3, and its internal circuit structure is not specifically limited here.

[0197] like Fig.18D As shown, in the fourth embodiment, the secondary bias control module 15A_4 includes a tenth transistor Q10 and an eleventh transistor Q11. The control end of the tenth transistor Q10 and the control end of the eleventh transistor Q11 receive an offset correction control signal OFCZ. The first connection end of the tenth transistor Q10 and the first connection end of the eleventh transistor Q11 receive an operating voltage VDD, and the second connection end of the tenth transistor Q10 and the second connection end of the eleventh transistor Q11 are electrically connected to the first primary output node N1 and the second primary output node N2, respectively. The first secondary correction control unit 161 is used to directly output the received offset correction control signal OFCZ to the secondary bias control module 15A_4, and its internal circuit structure is not specifically limited here. In this embodiment, the tenth transistor Q10 and the eleventh transistor Q11 are long channel PMOS, which can be directly used as a resistive element.

[0198] like Figures 18A-18D The secondary bias control modules 15A_1 to 15A_4 are used to form a conductive path between the working voltage VDD and the ground voltage GND with the first load 116 and the second load 117 in the offset correction stage T1, thereby generating a divided voltage at the first primary output node N1 and the second primary output node N2, and providing the divided voltage to the control terminal of the third transistor Q3 and the control terminal of the fourth transistor Q4 as a secondary bias voltage. Fig.14 The signal receiver 1D and Fig.16 The signal receiver 1F does not need to provide a power supply generating circuit with a rated voltage VB. Figures 18A-18D The circuit structures of the secondary bias control modules 15A_1 to 15A_4 are shown only for illustrating different implementations and are not intended to be limiting.

[0199] See also Figures 19A-19D , which is a circuit diagram of the secondary bias control module 15B of the first to fourth embodiments. Fig.19A As shown, in the first embodiment, the secondary bias control module 15B_1 and Fig.18A The structures of the secondary bias control module 15A_1 are similar, and the main difference between the two lies in the connection mode of the seventh transistor Q7 and the eighth transistor Q8. The control terminals of the seventh transistor Q7 and the eighth transistor Q8 are electrically connected to the first secondary correction control unit 161 through the connection node N9, the first connection terminals of the seventh transistor Q7 and the eighth transistor Q8 receive the ground voltage GND, and the second connection terminals of the seventh transistor Q7 and the eighth transistor Q8 are electrically connected to the first primary output node N1 and the second primary output node N2 respectively. The second secondary correction control unit 162 receives the fourth bias voltage Vbias4 and the offset correction control signal OFCZ, and its circuit structure is the same as Fig.18A The structure of the first secondary correction control unit 161 is the same as that of the first secondary correction control unit 161, which will not be repeated here.

[0200] like Fig.19B As shown, in the second embodiment, the secondary bias control module 15B_2 and Fig.18B The structure of the secondary bias control module 15A_2 in FIG. 1 is similar to that of the secondary bias control module 15A_2 in FIG. 1 , and the main difference between the two is the connection mode of the first current source 151 and the second current source 152. The input end of the first current source 151 is electrically connected to the first primary output node N1, and the output end is electrically connected to the second connection end of the fifth switch element S8. The input end of the second current source 152 is electrically connected to the second primary output node N2, and the output end is electrically connected to the second connection end of the fifth switch element S8.

[0201] like Fig.19C As shown, in the third embodiment, the secondary bias control module 15B_3 and Fig.18C The structure of the secondary bias control module 15A_3 in the embodiment is similar, and the main difference between the two is: the connection mode of the ninth transistor Q9, and the secondary bias control module 15B_3 further includes a third inverter IN3. The control end of the ninth transistor Q9 is electrically connected to the second secondary correction control unit 162 through the third inverter IN3, the first connection end of the ninth transistor Q9 receives the ground voltage GND, and the second connection end of the ninth transistor Q9 is electrically connected to the first voltage-dividing resistor R2 and the second voltage-dividing resistor R3 respectively.

[0202] like Fig.19D As shown, in the fourth embodiment, the secondary bias control module 15B_4 and Fig.18DThe structure of the secondary bias control module 15A_3 in the embodiment is similar, and the main difference between the two is: the connection mode of the tenth transistor Q10 and the eleventh transistor Q11, and the secondary bias control module 15B_3 further includes a third inverter IN3. The control ends of the tenth transistor Q10 and the eleventh transistor Q11 are electrically connected to the second secondary correction control unit 162 through the third inverter IN3, the first connection ends of the tenth transistor Q10 and the eleventh transistor Q11 receive the ground voltage GND, and the second connection ends of the tenth transistor Q10 and the eleventh transistor Q11 are electrically connected to the first primary output node N1 and the second primary output node N2 respectively.

[0203] Similarly, if Figures 19A-19D The secondary bias control modules 15B_1 to 15B_4 shown are used to form a conductive path between the working voltage VDD and the ground voltage GND with the first load 116 and the second load 117 in the offset correction stage T1, thereby generating a divided voltage on the first primary output node N1 and the second primary output node N2, and providing the divided voltage to the control end of the third transistor Q3 and the control end of the fourth transistor Q4 as a secondary bias voltage. Fig.15 The signal receiver 1E and Fig.17 The signal receiver 1G does not need to provide a power supply generating circuit of the rated voltage VB. Figures 19A-19D The circuit structures of the secondary bias control modules 15B_1 to 15B_4 are shown only for illustrating different implementations and are not intended to be limiting.

[0204] In addition, the first to fourth bias voltages Vbias1 - Vbias4 may be provided by an internal power generation circuit (not shown) of the signal receiver 1 , or provided by an external power source of the signal receiver 1 .

[0205] See also Fig. 20 , which is a flow chart of the offset voltage correction method of the first embodiment of the present application. In at least one embodiment of the present application, the offset voltage correction method can be applied to the signal receiver 1A-1C. The signal receiver 1A-1C may include a ratio Figures 1 to 6 as well as Figure 12 to Figure 13 More or less hardware, or different component configurations. It is understood that the implementation of the offset voltage correction method is not limited to application to Figures 1 to 6 as well as Figure 12 to Figure 13 The signal receivers 1A-1C shown are illustrated with reference to the figures for convenience of explanation only. The offset voltage calibration method includes the following steps:

[0206] Step S2001 , in the initial stage T0 , the signal receivers 1A-1C are powered on and perform initialization operations.

[0207] In at least one embodiment of the present application, the initialization operation includes performing initial settings of circuit parameters and making the internal voltage reach a preset level, but is not limited thereto.

[0208] Step S2002 , in the offset correction stage T1 , under the control of the primary correction control module 13 , the primary amplification module 11 is in a disabled state.

[0209] In at least one embodiment of the present application, the primary amplifying module 11A / 11B in the disabled state stops outputting the first primary output signal and the second primary output signal through the first primary output terminal 113 and the second primary output terminal 114 .

[0210] exist Figure 2 as well as Fig.12 In the illustrated embodiment, in the offset correction stage T1, the primary amplification module 11A is in a disabled state under the control of the first primary correction control unit 131; Fig.13 In the illustrated embodiment, the primary amplification module 11B is in a disabled state under the control of the second primary correction control unit 132 .

[0211] The first primary correction control unit 131 and the second primary correction control unit 132 are both separated from the high-speed signal path (i.e., the first primary correction control unit 131 and the second primary correction control unit 132 are located outside the high-speed signal path in the signal receiver 1, and are not directly connected to the high-speed signal path). The definition of the high-speed signal path is consistent with that of the high-speed signal path in the signal receiver 1, and is not described in detail here.

[0212] In step S2003, in the offset correction stage T1, the secondary amplifier module 12 generates a secondary amplification signal according to the rated voltage VB and the preset compensation current output by the offset correction circuit 30, the comparison circuit 20 obtains a comparison signal according to the secondary amplification signal, and the offset correction circuit 30 performs a successive approximation correction operation according to the comparison signal to determine the target compensation current and provides it to the secondary amplifier module 12.

[0213] The offset correction circuit 30 may be implemented using Figure 5 or Figure 6 The offset correction circuit 30 determines the target compensation current according to the comparison signal of the comparison output node COM_OUT and provides the target compensation current to one of the first secondary correction node N7 and the second secondary correction node N8 in the secondary amplifier module 12. For the specific operation process, please refer to the description in the above signal receiver 1A, which will not be repeated here.

[0214] exist Figure 2 , Fig.12 as well as Fig.13In the illustrated embodiment, the secondary amplifier modules 12A / 12B are controlled by a constant rated voltage VB.

[0215] exist Figure 2 , Fig.12 as well as Fig.13 In the illustrated embodiment, the first secondary correction node N7 is a node between the first connection terminal of the third transistor Q3 and the first secondary bias current source 124, and the second secondary correction node N8 is a node between the first connection terminal of the fourth transistor Q4 and the second secondary bias current source 125. Figure 2 and Fig.12 In the illustrated embodiment, the first secondary correction node N7 is multiplexed as the first secondary input node N3, and the second secondary correction node N8 is multiplexed as the second secondary input node N4.

[0216] In this embodiment, reference Figure 2 , and taking the compensation of the second secondary correction node N8 by the offset correction circuit 30 as an example, in the offset correction stage T1, the third load 126, the third transistor Q3, the first load 116, the first secondary bias current source 124 and the offset correction circuit 30 form a current path, and the fourth load 127, the fourth transistor Q4, the second secondary bias current source 125 and the offset correction circuit 30 form another current path. The secondary amplification signal generated by the secondary amplifier module 12 includes a first secondary output signal and a second secondary output signal. The first secondary output signal is the voltage of the first secondary output node N5, and the second secondary output signal is the voltage of the second secondary output node N6. Among them, the voltage of the first secondary output node N5 is an internal voltage signal, and its magnitude is related to the third load 126, the third transistor Q3, the first load 116 and the first secondary bias current source 124; the second secondary output node N6 is an internal voltage signal, and its magnitude is related to the fourth load 127, the fourth transistor Q4, the second load 117, the second secondary bias current source 125 and the offset correction circuit 30. When the offset correction circuit 30 performs the successive approximation correction operation, the voltage of the second secondary output node N6 changes with the change of the preset compensation current.

[0217] In step S2004 , in the data transmission phase T2 , under the control of the primary calibration control module 13 , the primary amplification module 11 is in an enabled state.

[0218] In at least one embodiment of the present application, in the data transmission phase T2, the offset correction control signal OFCZ is at a high level, the first control switch S1 is turned on, and the second control switch S2 is turned off, so that the first bias voltage Vbias1 is provided to the first primary bias control unit 115A / 115B as a bias switching signal.

[0219] The primary amplifier module 11 in the enabled state is used to perform primary amplification processing on the positive input signal TXP and the negative input signal TXN received by the first primary input terminal 111 and the second primary input terminal 112, and then output the first primary output signal and the second primary output signal to the secondary amplifier module 12 through the first primary output terminal 113 and the second primary output terminal 114.

[0220] Step S2005, in the data transmission stage T2, the offset correction circuit 30 maintains providing the target compensation current to the secondary amplifier module 12, the secondary amplifier module 12 generates a secondary amplified signal according to the rated voltage VB, the primary amplified signal output by the primary amplifier module 11 and the target compensation current output by the offset correction circuit 30, and the comparison circuit 20 outputs the secondary amplified signal to the signal processor 3.

[0221] In this embodiment, reference Figure 2 , and taking the compensation of the second secondary input node N4 by the offset correction circuit 30 as an example, in the data transmission stage T2, the first primary output node N1 is electrically connected to the first secondary input node N3, and the second primary output node N2 is electrically connected to the second secondary input node N4, so that the primary amplified signal output by the primary amplifier module 11A is output to the secondary amplifier module 12A. At this time, the first secondary output node N5 is the superposition of the first primary output signal and the internal voltage signal, and the second secondary output node N6 is the superposition of the second primary output signal and the internal voltage signal. That is, the voltage of the first secondary output node N5 is related to the primary amplified signal output by the primary amplifier module 11A, the third load 126, the third transistor Q3, the first load 116, and the first secondary bias current source 124; the voltage of the second secondary output node N6 is related to the primary amplified signal output by the primary amplifier module 11A, the fourth load 127, the fourth transistor Q4, the second load 117, the second secondary bias current source 125, and the offset correction circuit 30. Therefore, the voltages of the first secondary output node N5 and the second secondary output node N6 change with the primary amplified signal output by the primary amplification module 11A to achieve the signal amplification function, and since the offset correction circuit 30 maintains providing the target compensation current, the influence of the offset voltage of the signal receiver 1 can be reduced.

[0222] In the above offset voltage correction method, by maintaining the primary amplifier module 11 to receive the positive input signal TXP and the negative input signal TXN in both the offset correction stage T1 and the data transmission stage T2, and using the primary correction control module 13 isolated from the high-speed signal path to control whether the primary amplifier module 11 is disabled, the circuit architecture difference between the signal receiver 1 in the offset correction stage T1 and the signal receiver 1 in the data transmission stage T2 is reduced, thereby optimizing the offset correction effect of the signal receiver 1. In addition, compared with the receiver of the prior art, since there is no additional switching element required for switching the stage of the signal receiver 1 on the high-speed signal path, the signal receiver 1 of the present application can receive higher frequency input signals and reduce the gain loss on high-frequency signals, thereby optimizing the application scope of the signal receiver 1. At the same time, from Fig.10 It can be seen from the simulated eye diagram that the signal receiver 1 of the present application has better stability in signal transmission, and optimizes the stability of signal transmission of the signal receiver 1. Fig. 11B When the signal receiver 1 of the present application performs offset correction, the DC voltage offset distribution of the first comparison input terminal 20A and the second comparison input terminal 20B of the comparison circuit 20 is more concentrated and the offset degree is lower, which has a better offset correction effect.

[0223] See also Fig.21 , which is a flow chart of an offset voltage correction method according to a second embodiment of the present application. In at least one embodiment of the present application, the offset voltage correction method can be applied to signal receivers 1D to 1G. The signal receivers 1D to 1G may include a ratio Figures 14 to 17 More or less hardware or software, or different component configurations. It is understood that the implementation of the offset voltage correction method is not limited to application to Figures 14 to 17 The signal receivers 1D to 1G shown are illustrated with reference to the drawings for the sake of convenience. The offset voltage calibration method includes the following steps:

[0224] Step S2101 , in the initial stage T0 , the signal receivers 1D to 1G are powered on and perform initialization operations.

[0225] In at least one embodiment of the present application, the initialization operation includes performing initial settings of circuit parameters and making the internal voltage reach a preset level, but is not limited thereto.

[0226] Step S2102 , in the offset correction stage T1 , under the control of the primary correction control module 13 , the primary amplification modules 11A / 11B / 11C / 11D are in a disabled state.

[0227] In at least one embodiment of the present application, the primary amplifying module 11 in the disabled state stops outputting the first primary output signal and the second primary output signal through the first primary output terminal 113 and the second primary output terminal 114 .

[0228] The primary correction control module 13 includes a first primary correction control unit 131 and a second primary correction control unit 132. The first primary correction control unit 131 and the second primary correction control unit 132 are both separated from the high-speed signal path (i.e., the first primary correction control unit 131 and the second primary correction control unit 132 are located outside the high-speed signal path in the signal receiver 1, and are not directly connected to the high-speed signal path). The definition of the high-speed signal path is consistent with that in the signal receiver 1, and is not repeated here.

[0229] In step S2103, in the offset correction stage T1, under the control of the secondary correction control module 16, the secondary bias control module 15 is in an enabled state and establishes a voltage path with the primary amplifier module 11 and provides a secondary bias voltage. The secondary amplifier module 12 generates a secondary amplified output signal according to the secondary bias voltage and a preset compensation current output by the offset correction circuit 30. The comparison circuit 20 generates a comparison signal according to the secondary amplified output signal. The offset correction circuit 30 performs a successive approximation correction operation according to the comparison signal to determine the target compensation current and provides it to the secondary amplifier module 12.

[0230] The secondary bias control module 15 and the second secondary correction control module 16 are both separated from the high-speed signal path (ie, the secondary bias control module 15 and the second secondary correction control module 16 are located outside the high-speed signal path in the signal receiver 1 and are not directly connected to the high-speed signal path).

[0231] The offset correction circuit 30 may be implemented using Figure 5 or Figure 6 The offset correction circuit 30 determines the target compensation current according to the comparison signal of the comparison output node COM_OUT and provides the target compensation current to one of the first secondary correction node N7 and the second secondary correction node N8 in the secondary amplifier module 12. For the specific operation process, please refer to the description in the above signal receiver 1A, which will not be repeated here.

[0232] exist Figures 14 to 17In the illustrated embodiment, the secondary amplifier module 12C / 12D is controlled by the secondary bias control module 15A / 15B and the primary amplifier module 11A / 11B / 11C / 11D. That is, the secondary bias control module 15A and the first load 116 form a conductive path between the operating voltage VDD and the ground voltage GND. Therefore, a divided voltage is generated on the first primary output node N1 and provided to the control end of the third transistor Q3 as a secondary bias voltage. Similarly, the secondary bias control module 15A and the second load 117 form a conductive path between the operating voltage VDD and the ground voltage GND. Therefore, a divided voltage is generated on the second primary output node N2 and provided to the control end of the fourth transistor Q4 as a secondary bias voltage.

[0233] exist Figure 14 to Figure 15 In the illustrated embodiment, the first secondary correction node N7 is a node between the first connection terminal of the third transistor Q3 and the first secondary bias current source 124, and the second secondary correction node N8 is a node between the first connection terminal of the fourth transistor Q4 and the second secondary bias current source 125; Fig.16 as well as Fig.17 In the illustrated embodiment, the second secondary correction node N8 is a node between the first connection terminal of the fourth transistor Q4 and the fourth load 127. The first secondary correction node N7 is multiplexed as the first secondary output node N5, and the second secondary correction node N8 is multiplexed as the second secondary output node N6.

[0234] In this embodiment, reference Fig.14 , and taking the compensation of the second secondary input node N4 by the offset correction circuit 30 as an example, in the offset correction stage T1, the third load 126, the third transistor Q3, the first load 116, the first secondary bias current source 124 and the offset correction circuit 30 form a current path, and the fourth load 127, the fourth transistor Q4, the second secondary bias current source 125 and the offset correction circuit 30 form another current path. The secondary amplification signal generated by the secondary amplifier module 12 includes a first secondary output signal and a second secondary output signal. The first secondary output signal is the voltage of the first secondary output node N5, and the second secondary output signal is the voltage of the second output node N6. Among them, the voltage of the first secondary output node N5 is an internal voltage signal, and its magnitude is related to the third load 126, the third transistor Q3, the second load 117 and the first secondary bias current source 124; the voltage of the second secondary output node N6 is an internal voltage signal, and its magnitude is related to the fourth load 127, the fourth transistor Q4, the second load 117, the second secondary bias current source 125 and the offset correction circuit 30. When the offset correction circuit 30 performs the successive approximation correction operation, the voltage of the second secondary output node N6 varies with the variation of the preset compensation current.

[0235] In step S2104 , in the data transmission phase T2 , under the control of the primary calibration control module 13 , the primary amplification module 11 is in an enabled state.

[0236] The primary amplifier module 11 in the enabled state is used to perform primary amplification processing on the positive input signal TXP and the negative input signal TXN received by the first primary input terminal 111 and the second primary input terminal 112, and then output the first primary output signal and the second primary output signal to the secondary amplifier module 12 through the first primary output terminal 113 and the second primary output terminal 114.

[0237] Step S2105, in the data transmission stage T2, under the control of the secondary correction control module 16, the secondary bias control module 15 is in a disabled state and disconnects the voltage path between the primary amplifier module 11 and stops providing the secondary bias voltage to the secondary amplifier module 12, the offset correction circuit 30 continues to provide the target compensation current to the secondary amplifier module 12, the secondary amplifier module 12 receives the primary amplification signal, the primary amplification signal output by the primary amplifier module 11 and the target compensation current output by the offset correction circuit 30 and generates a secondary amplification signal, and the comparison circuit 20 outputs the secondary amplification signal to the signal processor 3.

[0238] In this embodiment, reference Fig.14 , and taking the compensation of the second secondary input node N4 by the offset correction circuit 30 as an example, in the data transmission stage T2, the first primary output node N1 is electrically connected to the first secondary input node N3, and the second primary output node N2 is electrically connected to the second secondary input node N4, so that the primary amplified signal output by the primary amplifier module 11A is output to the secondary amplifier module 12C. At this time, the voltage of the first secondary output node N5 is the superposition of the first primary output signal and the internal voltage signal, and the voltage of the second secondary output node N6 is the superposition of the second primary output signal, the internal voltage signal and the target compensation current. That is, the magnitude of the voltage of the first secondary output node N5 is related to the first primary amplified signal output by the primary amplifier module 11A, the third load 126, the third transistor Q3, the first load 116 and the first secondary bias current source 124; the magnitude of the voltage of the second secondary output node N6 is related to the second primary amplified signal output by the primary amplifier module 11A, the fourth load 127, the fourth transistor Q4, the second load 117, the second secondary bias current source 125 and the offset correction circuit 30. Since the target compensation current provided by the offset correction circuit 30 remains unchanged, the voltages of the first secondary output node N5 and the second secondary output node N6 will change with the change of the primary amplified signal output by the primary amplification module 11A.

[0239] Fig.21 The offset voltage correction method shown has the same Fig. 20In addition, in the offset correction stage T1 , the secondary amplifier module 12 is controlled by the secondary bias control module 15 and the primary amplifier module 11 , so that the control method of the secondary amplifier module 12 can be optimized.

[0240] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal receiver with an offset voltage correction function, receiving a positive input signal and a negative input signal from a transmitter; the working phase of the signal receiver includes an offset correction phase and a data transmission phase; characterized in that: The signal receiver comprises: an amplifier circuit, configured to receive the positive input signal and the negative input signal, the amplifier circuit comprising: A primary amplification module, electrically connected to the transmitter; A secondary amplification module electrically connected to the primary amplification module; and A primary correction control module, electrically connected to the primary amplification module; A comparison circuit electrically connected to the secondary amplification module; and an offset correction circuit, electrically connected to the comparison circuit and the secondary amplification module; Wherein, there is a high-speed signal path in the signal receiver, and the primary correction control module is separately arranged from the high-speed signal path; in the offset correction stage, the primary correction control module controls the primary amplification module to be in a disabled state, the secondary amplification module generates a secondary amplification signal according to the rated voltage and the preset compensation current output by the offset correction circuit, the comparison circuit generates a comparison signal according to the secondary amplification signal, and the offset correction circuit performs a successive approximation correction operation according to the comparison signal to determine the target compensation current and outputs it to the secondary amplification module; in the data transmission stage, the primary correction control module controls the primary amplification module to be in an enabled state and outputs the primary amplification signal, the offset correction circuit continuously outputs the target compensation current to the secondary amplification module, the secondary amplification module generates the secondary amplification signal according to the rated voltage, the primary amplification signal and the target compensation current, and the comparison circuit outputs the comparison signal.

2. The signal receiver according to claim 1, characterized in that: The high-speed signal path is composed of multiple sections; the signal receiver includes a first signal input terminal and a second signal input terminal; the amplifier circuit includes a first amplifier input terminal, a second amplifier input terminal, a first amplifier output terminal and a second amplifier output terminal; the primary amplifier module includes a first primary input terminal, a second primary input terminal, a first primary output terminal and a second primary output terminal; the secondary amplifier module includes a first secondary input terminal, a second secondary input terminal, a first secondary output terminal and a second secondary output terminal; the comparison circuit has a first comparison input terminal and a second comparison input terminal; the first signal input terminal is electrically connected to the first amplifier input terminal, and a first signal input section is formed between the two; the first amplifier input terminal is directly electrically connected to the first primary input terminal, and a first primary input section is formed between the two; the first primary output terminal is directly electrically connected to the first secondary input terminal, and a The first secondary output terminal is directly electrically connected to the first amplifying output terminal, and a first secondary transmission section is formed between the two. The first amplifying output terminal is directly electrically connected to the first comparison input terminal, and a first signal transmission section is formed between the two. The second signal input terminal is electrically connected to the second amplifying input terminal, and a second signal input section is formed between the two. The second amplifying input terminal is directly electrically connected to the second primary input terminal, and a second primary input section is formed between the two. The second primary output terminal is directly electrically connected to the second secondary input terminal, and a second primary transmission section is formed between the two. The second secondary output terminal is directly electrically connected to the second amplifying output terminal, and a second secondary transmission section is formed between the two. The second amplifying output terminal is directly electrically connected to the second comparison input terminal, and a second signal transmission section is formed between the two.

3. The signal receiver according to claim 1, characterized in that: The primary amplification module includes a first primary bias control unit; the primary correction control module includes a first primary correction control unit; in the offset correction stage, the first primary correction control unit controls the first primary bias control unit to be in a disabled state according to an offset correction control signal, and stops outputting the first primary bias current; in the data transmission stage, the first primary correction control unit controls the first primary bias control unit to be in an enabled state according to the offset correction control signal, and outputs the first primary bias current.

4. The signal receiver according to claim 3, characterized in that: The primary amplification module further includes a first transistor, a second transistor, a first load and a second load; the control end of the first transistor receives the positive input signal, the first connection end of the first transistor is electrically connected to the first primary bias control unit, and the second connection end of the first transistor is grounded through the first load; the control end of the second transistor receives the negative input signal, the first connection end of the second transistor is electrically connected to the first primary bias control unit; the second connection end of the second transistor is grounded through the second load; the first primary bias control unit includes at least one bias control switch; The control end of the at least one bias control switch is electrically connected to the first primary bias control unit, the first connection end of the at least one bias control switch receives an operating voltage, and the second connection end of the at least one bias control switch is electrically connected to the first connection ends of the first transistor and the second transistor.

5. The signal receiver according to claim 3, characterized in that: The primary amplification module further includes a first transistor, a second transistor, a first load and a second load; the control end of the first transistor receives the positive input signal, the first connection end of the first transistor is electrically connected to the first primary bias control unit, and the second connection end of the first transistor receives the working voltage through the first load; the control end of the second transistor receives the negative input signal, the first connection end of the second transistor is electrically connected to the first primary bias control unit; the second connection end of the second transistor receives the working voltage through the second load; the first primary bias control unit includes at least one bias control switch; The control end of the at least one bias control switch is electrically connected to the first primary bias control unit, the first connection end of the at least one bias control switch receives a ground voltage, and the second connection end of the at least one bias control switch is electrically connected to the first connection ends of the first transistor and the second transistor.

6. The signal receiver according to claim 1, characterized in that: The secondary amplification module includes a first secondary bias current source, a second secondary bias current source, a third transistor, a fourth transistor, a third load and a fourth load; the control end of the third transistor receives the rated voltage, the first connection end thereof is electrically connected to the first secondary bias current source through a first secondary correction node, and the second connection end thereof receives the working voltage through a first secondary output node and the third load; the control end of the fourth transistor receives the rated voltage, the first connection end of the fourth transistor is electrically connected to the second secondary bias current source through the second secondary correction node, and the second connection end thereof receives the working voltage through a second secondary output node and the fourth load; one end of the third load is electrically connected to the first secondary output node, and the other end receives the working voltage; the first secondary correction node is also electrically connected to the offset correction circuit, and is multiplexed as a first secondary input node electrically connected to the primary amplification module; the second secondary correction node is electrically connected to the offset correction circuit, and is multiplexed as a second secondary input node electrically connected to the primary amplification module.

7. The signal receiver according to claim 6, characterized in that: The secondary amplification module further includes a resistor and a capacitor; the resistor and the capacitor are connected in parallel between the first secondary correction node and the second secondary correction node.

8. The signal receiver according to claim 1, characterized in that: The offset correction circuit includes a compensation indication module, a successive approximation module and a digital-to-analog conversion module; the compensation indication module outputs a compensation indication signal to the digital-to-analog conversion module according to the initial comparison signal; the compensation indication signal is used to indicate that one of the first secondary correction node and the second secondary correction node in the secondary amplifier module needs to be compensated; the successive approximation module outputs a plurality of offset correction bits to the digital-to-analog conversion module according to the comparison signal output by the comparison circuit and the offset correction clock signal; The digital-to-analog conversion module provides a preset compensation current corresponding to the offset correction bit output by the successive approximation module to a first secondary correction node or a second secondary correction node according to a compensation indication signal.

9. The signal receiver according to claim 8, characterized in that: The digital-to-analog converter is electrically connected between the successive approximation module and the switch unit; the switch unit electrically connects one of the first secondary correction node and the second secondary correction node to the digital-to-analog converter according to the compensation indication signal.

10. An offset voltage correction method, applied to a signal receiver; the signal receiver has a high-speed signal path; the working phase of the signal receiver includes an offset correction phase and a data transmission phase; the signal receiver includes an amplifier circuit, a comparison circuit and an offset correction circuit; the amplifier circuit includes a primary amplifier module, a secondary amplifier module and a primary correction control module; The primary correction control module is separately arranged from the high-speed signal path; the offset voltage correction method comprises: In the offset correction stage, under the control of the primary correction control module, the primary amplification module is in a disabled state; In the offset correction stage, the secondary amplification module generates a secondary amplification signal according to the rated voltage and the preset compensation current output by the offset correction circuit, the comparison circuit obtains a comparison signal according to the secondary amplification signal, and the offset correction circuit performs a successive approximation correction operation according to the comparison signal to determine the target compensation current and provides it to the secondary amplification module; wherein, when performing the successive approximation correction operation, the offset correction circuit outputs a different preset compensation current, and the secondary amplification signal changes with the change of the preset compensation current; In the data transmission stage, under the control of the primary calibration control module, the primary amplification module is in an enabled state; and During the data transmission stage, the offset correction circuit maintains providing the target compensation current to the secondary amplifier module, the secondary amplifier module generates the secondary amplified signal according to the rated voltage, the primary amplified signal output by the primary amplifier module and the target compensation current, and the comparison circuit outputs the secondary amplified signal.

11. The offset voltage calibration method according to claim 10, wherein: The primary amplification module includes a first primary bias control unit; the primary correction control module includes a first primary correction control unit; in the offset correction stage, the first primary correction control unit controls the first primary bias control unit to be in a disabled state according to an offset correction control signal, and stops outputting the first primary bias current; in the data transmission stage, the first primary correction control unit controls the first primary bias control unit to be in an enabled state according to the offset correction control signal, and outputs the first primary bias current.

12. The offset voltage calibration method according to claim 10, wherein: The offset correction circuit includes a compensation indication module, a successive approximation module and a digital-to-analog conversion module; the compensation indication module outputs a compensation indication signal to the digital-to-analog conversion module according to an initial comparison signal output by the comparison circuit; the compensation indication signal is used to indicate that one of the first secondary correction node and the second secondary correction node in the secondary amplifier module needs to be compensated; the successive approximation module outputs a plurality of offset correction bits to the digital-to-analog conversion module according to the comparison signal output by the comparison circuit and an offset correction clock signal; The digital-to-analog conversion module provides a preset compensation current corresponding to the offset correction bit output by the successive approximation module to the first secondary correction node or the second secondary correction node according to a compensation indication signal.

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