Communication broadcast satellite uplink and downlink signal parallel monitoring method

Abstract

The invention belongs to the technical field of signal monitoring, and provides a communication broadcast satellite uplink and downlink signal parallel monitoring method, which adopts a dual-channel receiver design, and receives an uplink transmitting signal and a downlink receiving signal of a communication broadcast satellite in parallel by the same equipment; by adopting the design of the dual-channel receiver, the uplink transmitting signal and the downlink receiving signal of the communication broadcast satellite are received by the same equipment in parallel, so that the number of monitoring equipment is remarkably reduced, the investment demand, the occupied space and the energy cost are reduced, and meanwhile, the maintenance pressure is also reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of signal monitoring, in particular to a method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite. Background Art

[0002] Satellite-based communication and broadcasting systems are the country's most basic and important means of information transmission, especially in border areas, islands, mountainous areas, deserts, forests and other areas. However, the satellite communication and broadcasting system is relatively complex and vulnerable to external interference. In order to ensure the reliability of the system and services, it is necessary to continuously improve the system's technical level and enhance its anti-interference and intrusion capabilities. At the same time, auxiliary maintenance measures for system health management and performance supervision are also needed to improve the system's health management and abnormal emergency response capabilities.

[0003] In existing signal spectrum monitoring systems, different devices are usually used to collect and monitor uplink transmission signals and forward downlink signals to the ground. This method has problems such as a large number of monitoring devices, large investment requirements, large space occupation, high energy costs, and high maintenance pressure.

[0004] To this end, those skilled in the art have proposed a method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite to solve the problems raised by the background technology. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a method for parallel monitoring of uplink and downlink signals of communication broadcast satellites, so as to solve the problem that in the signal spectrum monitoring system in the prior art, different devices are usually used to collect and monitor the uplink transmission signal and forward the downlink signal reaching the ground. This method has the problems of large number of monitoring devices, large investment requirements, large occupied space, high energy cost, and high maintenance pressure.

[0006] A method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite, the method adopts a dual-channel receiver design, and the same device receives the uplink transmission signal and the downlink reception signal of the communication broadcasting satellite in parallel, specifically comprising:

[0007] S1. Use digitally controlled step attenuators to control port impedance matching and provide signal amplitude adjustment capability;

[0008] S2. The signal level is increased by a bypassable low noise amplifier of SiGe Bi-CMOS process or transmitted through an on-chip bypass channel to flexibly adapt to different input signal levels. In the parallel monitoring method of uplink and downlink signals of communication and broadcasting satellites, SiGe Bi-CMOS process is applied to key components such as bypassable low noise amplifier and electronically tunable filter chip, which provides strong support for accurate signal processing and efficient transmission.

[0009] S3, using SiGe Bi-CMOS electronically tunable filter chip to achieve pre-frequency selection function before mixing, reducing parasitic spurious caused by nonlinearity of the mixer;

[0010] S4, using a dual down-conversion integrated circuit that integrates a VCO, a phase-locked loop, a balun, a mixer, a filter, an amplifier, an adjustable amplifier, and a digitally controlled step attenuator to implement RF down-conversion to convert the RF signal into an intermediate frequency signal;

[0011] S5, using a tunable bandpass Σ-Δ type analog-to-digital converter to convert the intermediate frequency signal into a digital baseband signal;

[0012] S6, Process digital baseband signals through fully programmable system-on-chip FPGA integrated circuits to perform spectrum analysis, vector signal processing, automatic monitoring of signal characteristics, etc.;

[0013] S7, storing the original spectrum IQ data in the local device for a long time, and uploading the calculated formatted data and monitoring information to the remote server;

[0014] S8. Real-time data processing, monitoring and response are achieved through the "edge-end-cloud" hybrid computing architecture. The "edge-end-cloud" hybrid computing architecture can process and analyze large amounts of satellite signal data in real time, improve the response speed and accuracy of the monitoring system, and reduce dependence on cloud computing resources, achieving more efficient and reliable data processing.

[0015] Preferably, the dual-channel receiver design combines the high performance of heterodyne design with the high integration of RF-CMOS process integrated circuits, and innovates the design route of heterodyne receivers using SiGe BiCMOS process receiver front-end integrated circuits.

[0016] Preferably, in step S1, an adaptive algorithm is introduced to dynamically adjust the impedance matching of the digitally controlled step attenuator to ensure that the signal loss during the transmission process is minimized.

[0017] Preferably, in the down-conversion process in step S4, a compensation method based on Volterra series is used to reduce the distortion caused by mixer nonlinearity.

[0018] Preferably, during the analog-to-digital conversion process in step S5, an error correction technique is used to reduce the quantization error.

[0019] Preferably, in step S6, a fast Fourier transform (FFT) algorithm is implemented in the FPGA to perform spectrum analysis, and an advanced vector signal processing algorithm is used to improve the accuracy and robustness of signal processing;

[0020] And the neural network algorithm is introduced for signal classification and anomaly detection.

[0021] Preferably, in step S7, the original spectrum IQ data is stored in a high-performance SSD memory local to the device to retain more complete and higher-dimensional information. The high-performance SSD memory uses an efficient data storage and compression algorithm to reduce storage space occupancy and transmission bandwidth requirements.

[0022] Preferably, the fully programmable system-on-chip FPGA integrated circuit is designed with functional modules such as spectrum analysis and processing, vector signal processing, digital persistence and spectrum and other signal statistical characteristics analysis and processing, automatic monitoring of signal characteristics, non-cooperative signal recognition and real-time intrusion response based on machine learning, data management and edge computing for data mining.

[0023] A communication broadcast satellite uplink and downlink signal parallel monitoring system, using the above communication broadcast satellite uplink and downlink signal parallel monitoring method, comprising:

[0024] Impedance matching and signal amplitude adjustment module: uses digitally controlled step attenuators to control port impedance matching and provide signal amplitude adjustment capabilities;

[0025] Signal level boost and transmission module: The signal level is boosted by a bypassable low noise amplifier in SiGe Bi-CMOS process or transmitted via an on-chip bypass channel to flexibly adapt to different input signal levels;

[0026] Pre-mixing frequency selection module: SiGe Bi-CMOS electrically tunable filter chip is used to realize the pre-mixing frequency selection function before mixing, reducing the parasitic spurious caused by the nonlinearity of the mixer;

[0027] RF down-conversion module: RF down-conversion is realized by using a dual down-conversion integrated circuit that integrates VCO, phase-locked loop, balun, mixer, filter, amplifier, adjustable amplifier, and digitally controlled step attenuator to convert RF signals into intermediate frequency signals;

[0028] Analog-to-digital conversion module: uses a tunable bandpass Σ-Δ analog-to-digital converter to convert the intermediate frequency signal into a digital baseband signal;

[0029] Digital baseband signal processing module: Processes digital baseband signals through a fully programmable system-on-chip FPGA integrated circuit to perform spectrum analysis, vector signal processing, automatic monitoring of signal characteristics, etc.

[0030] Data storage and upload module: Stores the original spectrum IQ data in the local high-performance SSD storage of the device for a long time, and uploads the calculated formatted data and monitoring information to the remote server;

[0031] Hybrid computing architecture module: Realize real-time processing, monitoring and response of data through the "edge-end-cloud" hybrid computing architecture.

[0032] A processor is configured to execute the above-mentioned method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite.

[0033] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the above-mentioned method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The present invention adopts a dual-channel receiver design to achieve the parallel reception of uplink transmission signals and downlink reception signals of communication broadcast satellites by the same device, thereby significantly reducing the number of monitoring devices, reducing investment requirements, occupied space and energy costs, and also alleviating maintenance pressure.

[0036] 2. In the process of signal processing, the present invention introduces a variety of advanced technical means, such as a bypassable low-noise amplifier of SiGe Bi-CMOS process, an electrically tunable filter chip, a dual down-conversion integrated circuit, a tunable bandpass Σ-Δ type analog-to-digital converter, etc. The application of the above technologies improves the accuracy and efficiency of signal processing, so that the monitoring system can more accurately identify and monitor satellite signals.

[0037] 3. The present invention processes digital baseband signals through a fully programmable system-on-chip FPGA integrated circuit, realizes multiple functions such as spectrum analysis, vector signal processing, and automatic monitoring of signal characteristics, further improving the performance and intelligence level of the monitoring system; at the same time, through the "edge-end-cloud" hybrid computing architecture, real-time processing, monitoring and response of data are realized, improving the real-time and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flow chart of the method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite of the present invention;

[0039] Figure 2 This is a framework diagram of the communication broadcast satellite uplink and downlink signal parallel monitoring system of the present invention. DETAILED DESCRIPTION

[0040] The following embodiments of the present invention are described in further detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0041] Embodiment: The present invention provides a method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite. The method adopts a dual-channel receiver design, and the same device receives the uplink transmission signal and the downlink reception signal of the communication broadcasting satellite in parallel. Figure 1 As shown, specifically including:

[0042] S1. Use digitally controlled step attenuators to control port impedance matching and provide signal amplitude adjustment capability;

[0043] S2, the signal level is increased by a bypassable low noise amplifier in SiGe Bi-CMOS process or transmitted via an on-chip bypass channel to flexibly adapt to different input signal levels;

[0044] S3, using SiGe Bi-CMOS electronically tunable filter chip to achieve pre-frequency selection function before mixing, reducing parasitic spurious caused by nonlinearity of the mixer;

[0045] S4, using a dual down-conversion integrated circuit that integrates a VCO, a phase-locked loop, a balun, a mixer, a filter, an amplifier, an adjustable amplifier, and a digitally controlled step attenuator to implement RF down-conversion to convert the RF signal into an intermediate frequency signal;

[0046] S5, using a tunable bandpass Σ-Δ type analog-to-digital converter to convert the intermediate frequency signal into a digital baseband signal;

[0047] S6, Process digital baseband signals through fully programmable system-on-chip FPGA integrated circuits to perform spectrum analysis, vector signal processing, automatic monitoring of signal characteristics, etc.;

[0048] S7, storing the original spectrum IQ data in the local device for a long time, and uploading the calculated formatted data and monitoring information to the remote server;

[0049] S8. Realize real-time processing, monitoring and response of data through the "edge-end-cloud" hybrid computing architecture.

[0050] From the above, it can be seen that the dual-channel receiver design can achieve parallel reception of the satellite's uplink transmission signal and downlink reception signal by the same device, which has significant beneficial effects; this method not only reduces the number of monitoring equipment and investment costs, but also improves the accuracy and efficiency of signal processing through advanced technologies such as SiGe Bi-CMOS process, dual down-conversion integrated circuits, and tunable analog-to-digital converters; the application of fully programmable FPGA integrated circuits enables functions such as spectrum analysis and vector signal processing, enhancing the intelligence level of the system; in addition, the introduction of the "edge-end-cloud" hybrid computing architecture ensures real-time processing, monitoring and response of data, further improving the overall performance and reliability of the system.

[0051] Furthermore, the dual-channel receiver design combines the high performance of heterodyne design with the high integration of RF-CMOS process integrated circuits, and innovates the design route of heterodyne receivers using SiGe BiCMOS process receiver front-end integrated circuits.

[0052] As can be seen from the above, the dual-channel receiver design combines the high performance of the heterodyne design with the high integration of the RF-CMOS process integrated circuit, and uses the SiGe BiCMOS process receiver front-end integrated circuit to innovate the design route of the heterodyne receiver. This innovation has brought significant beneficial effects. It can not only achieve high-sensitivity and high-selectivity signal reception, improve the signal capture and processing capabilities, but also reduce the size and power consumption of the receiver through highly integrated circuit design; at the same time, the application of SiGe BiCMOS process enhances the frequency stability and anti-interference ability of the receiver, so that the receiver can operate stably in complex and changeable electromagnetic environments. The innovation of this design route provides a more efficient, reliable and compact solution for the parallel monitoring of uplink and downlink signals of communication and broadcasting satellites.

[0053] Furthermore, in step S1, an adaptive algorithm is introduced to dynamically adjust the impedance matching of the digitally controlled step attenuator to ensure that the signal loss during the transmission process is minimized. The formula of the adaptive algorithm is as follows:

[0054]

[0055] Where T′ represents the adjustment amount, P r represents the reflected power, α is the learning rate, and Q~ represents the impedance.

[0056] From the above, it can be seen that by real-time monitoring of the reflected power and dynamically adjusting the impedance matching of the attenuator according to the adaptive algorithm, the signal loss during transmission can be minimized; this method not only improves the efficiency and quality of signal transmission, but also enhances the adaptability and stability of the system; when faced with complex and changeable signal environments and transmission conditions, the adaptive algorithm can respond quickly and optimize impedance matching, thereby effectively reducing signal distortion and attenuation, and improving the performance and reliability of the overall monitoring system.

[0057] Furthermore, in the down-conversion process in step S4, a compensation method based on Volterra series is used to reduce the distortion caused by the nonlinearity of the mixer, and its algorithm formula is as follows:

[0058]

[0059] Among them, L * represents the compensated signal, l represents the original signal, and h n (x) represents the nth term of the Volterra series.

[0060] From the above, we can see that by accurately modeling the nonlinear characteristics of the mixer through the Volterra series and applying the corresponding compensation algorithm in the signal processing process, the harmonic distortion and intermodulation distortion caused by the nonlinearity of the mixer can be significantly reduced, thereby improving the quality and purity of the signal; this compensation method not only enhances the anti-interference ability of the system, but also improves the accuracy and reliability of signal processing, providing a more accurate and reliable signal basis for subsequent spectrum analysis and vector signal processing.

[0061] Furthermore, in the analog-to-digital conversion process of step S5, an error correction technique is used to reduce the quantization error. The algorithm formula of the error correction technique is as follows:

[0062]

[0063] Among them, H′ represents the corrected value, a k represents the fitting coefficient and h represents the original value.

[0064] From the above, it can be seen that by introducing error correction technology and correcting the original value according to the fitting coefficient, this quantization error can be significantly reduced, thereby improving the precision and accuracy of analog-to-digital conversion; this technology can not only improve the quality of the signal and ensure the reliability of subsequent digital signal processing, but also improve the performance of the entire monitoring system, enabling it to perform better in processing complex and high-precision signals.

[0065] Furthermore, in step S6, a fast Fourier transform (FFT) algorithm is implemented in the FPGA to perform spectrum analysis, and an advanced vector signal processing algorithm is used to improve the accuracy and robustness of signal processing;

[0066] The Fourier transform algorithm formula is as follows:

[0067]

[0068] in, represents the rotation factor;

[0069] The formula of the vector signal processing algorithm is as follows:

[0070] w[n+1]=w[n]+2μe[n]x[n];

[0071] Where w[n] is the filter weight, μ is the learning rate, e[n] is the error signal, and x[n] is the input signal.

[0072] In addition, a neural network algorithm is introduced for signal classification and anomaly detection. The neural network algorithm formula is as follows:

[0073]

[0074] Among them, σ is the activation function, w i is the weight, x i is the input feature and b is the bias.

[0075] From the above, we can see that the comprehensive application of these technical means, such as implementing the fast Fourier transform (FFT) algorithm in FPGA for spectrum analysis, adopting advanced vector signal processing algorithms, and introducing neural network algorithms for signal classification and anomaly detection, has brought significant beneficial effects. First, the efficient implementation of the FFT algorithm makes spectrum analysis faster and more accurate, providing a solid foundation for the in-depth understanding of signal characteristics. The advanced vector signal processing algorithm further improves the accuracy and robustness of signal processing, and effectively copes with complex and changeable signal environments. In addition, the introduction of the neural network algorithm realizes intelligent classification and anomaly detection of signals, greatly enhancing the automation and intelligence level of the system. The combination of the above technologies not only improves the overall performance of signal processing, but also enables the monitoring system to respond to various signal changes more quickly and accurately, thereby ensuring the reliability and efficiency of uplink and downlink signal monitoring of communication and broadcasting satellites.

[0076] Further, in step S7, the original spectrum IQ data is stored in a high-performance SSD memory locally on the device to retain more complete and higher-dimensional information. The high-performance SSD memory uses an efficient data storage and compression algorithm to reduce storage space occupation and transmission bandwidth requirements. The formula of the data storage and compression algorithm is as follows:

[0077]

[0078] in, Indicates the encoding length, the p i is the probability of the symbol, l i is the corresponding encoding length.

[0079] From the above, we can see that, first of all, high-performance SSD storage ensures the fast reading and writing capabilities of data, providing strong support for real-time data processing and subsequent analysis; at the same time, by retaining more complete and higher-dimensional original spectrum IQ data, the system can capture signal characteristics more comprehensively, providing a rich information basis for subsequent signal analysis and anomaly detection; in addition, the use of efficient data storage and compression algorithms can significantly reduce the storage space occupied and transmission bandwidth requirements while ensuring data integrity, thereby reducing the storage and transmission costs of the system; the comprehensive application of this data storage strategy not only improves the data processing efficiency and reliability of the system, but also provides a cost-effective solution for long-term data storage and archive management.

[0080] Furthermore, the fully programmable system-on-chip FPGA integrated circuit is designed with functional modules such as spectrum analysis and processing, vector signal processing, digital persistence and spectrum and other signal statistical characteristics analysis and processing, automatic monitoring of signal characteristics, non-cooperative signal recognition and real-time intrusion response based on machine learning, data management and data mining edge computing.

[0081] From the above, it can be seen that the fully programmable system-on-chip FPGA integrated circuit design integrates functional modules such as spectrum analysis and processing, vector signal processing, digital persistence and spectrum and other signal statistical characteristics analysis and processing, automatic monitoring of signal characteristics, non-cooperative signal recognition and real-time response to intrusion based on machine learning, and edge computing for data management and data mining. This enables the system to efficiently complete complex signal processing and monitoring tasks on a single chip, improving the real-time and accuracy of signal processing; at the same time, through the edge computing function, the system can perform preliminary data processing and analysis locally, reducing data transmission delays and bandwidth occupancy, and enhancing the response speed and flexibility of the system; in addition, the non-cooperative signal recognition and real-time response to intrusion based on machine learning enable the system to intelligently identify abnormal signals and potential threats, thereby improving the security and reliability of communication and broadcasting satellite systems.

[0082] A communication broadcast satellite uplink and downlink signal parallel monitoring system, such as Figure 2 As shown, the method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite described above includes:

[0083] Impedance matching and signal amplitude adjustment module: uses digitally controlled step attenuators to control port impedance matching and provide signal amplitude adjustment capabilities;

[0084] Signal level boost and transmission module: The signal level is boosted by a bypassable low noise amplifier in SiGe Bi-CMOS process or transmitted via an on-chip bypass channel to flexibly adapt to different input signal levels;

[0085] Pre-mixing frequency selection module: SiGe Bi-CMOS electrically tunable filter chip is used to realize the pre-mixing frequency selection function before mixing, reducing the parasitic spurious caused by the nonlinearity of the mixer;

[0086] RF down-conversion module: RF down-conversion is realized by using a dual down-conversion integrated circuit that integrates VCO, phase-locked loop, balun, mixer, filter, amplifier, adjustable amplifier, and digitally controlled step attenuator to convert RF signals into intermediate frequency signals;

[0087] Analog-to-digital conversion module: uses a tunable bandpass Σ-Δ analog-to-digital converter to convert the intermediate frequency signal into a digital baseband signal;

[0088] Digital baseband signal processing module: Processes digital baseband signals through a fully programmable system-on-chip FPGA integrated circuit to perform spectrum analysis, vector signal processing, automatic monitoring of signal characteristics, etc.

[0089] Data storage and upload module: Stores the original spectrum IQ data in the local high-performance SSD storage of the device for a long time, and uploads the calculated formatted data and monitoring information to the remote server;

[0090] Hybrid computing architecture module: Realize real-time processing, monitoring and response of data through the "edge-end-cloud" hybrid computing architecture.

[0091] Working principle: A dual-channel receiver is designed to receive and process the satellite's uplink transmission signal and downlink reception signal in parallel; this method uses a digitally controlled step attenuator to achieve impedance matching and signal amplitude adjustment, and adopts SiGe BiCMOS technology to improve signal level and frequency selectivity. The RF signal is converted into an intermediate frequency signal through a dual down-conversion integrated circuit, and then the intermediate frequency signal is digitized using a tunable bandpass Σ-Δ analog-to-digital converter; in the FPGA, the system implements functions such as spectrum analysis, vector signal processing, and automatic monitoring of signal characteristics, while using a neural network algorithm for signal classification and anomaly detection; the original spectrum IQ data is stored in a high-performance SSD memory for subsequent analysis and processing; the entire system realizes real-time data processing, monitoring and response through the "edge-end-cloud" hybrid computing architecture, ensuring stable transmission and efficient monitoring of communication and broadcasting satellite signals.

[0092] Furthermore, the effect of a communication broadcast satellite uplink and downlink signal parallel monitoring method of the embodiment is compared with the existing signal spectrum monitoring system (comparative example), and the following table is obtained:

[0093]

[0094] It can be seen from the above table that the parallel monitoring method of this embodiment is superior to the existing signal spectrum monitoring system in many aspects; for example, it adopts a dual-channel receiver design, which can simultaneously receive and process uplink transmission signals and downlink reception signals, thereby improving the efficiency of signal processing; it introduces an adaptive algorithm to dynamically adjust impedance matching, as well as advanced technologies such as SiGe BiCMOS process, which improves the sensitivity and selectivity of signal reception; it uses FPGA to integrate multiple functional modules to achieve efficient and intelligent signal processing; it uses high-performance SSD for data storage to improve storage efficiency and data security; and it builds an "edge-end-cloud" hybrid computing architecture to achieve real-time processing, monitoring and response of data.

[0095] These advantages make the parallel monitoring method of the embodiment have better adaptability and stability in complex and changeable signal environments, can complete signal monitoring tasks more efficiently and accurately, and has broad application prospects; at the same time, due to its high integration and good cost-effectiveness, it is also more competitive in the market.

[0096] The embodiment of the present application provides an electronic device, which is applicable to the above-mentioned method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite, including:

[0097] Memory, used to protect computer programs and data;

[0098] Processor, used to run system programs.

[0099] An embodiment of the present application provides a computer storage medium, which is applicable to the above-mentioned method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite, and performs hierarchical confidentiality management on the above-mentioned system and data in accordance with confidentiality management requirements.

[0100] Those skilled in the art will appreciate that the embodiments of the present application may be provided as a system or a computer program product. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0101] The present application is described with reference to the flowcharts and / or block diagrams of the devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0102] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0104] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0105] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0106] Computer readable media include permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0107] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, commodity or device including the elements.

[0108] The embodiments of the present invention are provided for the purpose of illustration and description. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite, characterized in that: The method adopts a dual-channel receiver design to receive the uplink transmission signal and the downlink reception signal of the communication broadcast satellite in parallel with the same device, specifically including: S1. Use digitally controlled step attenuators to control port impedance matching and provide signal amplitude adjustment capability; S2, boost the signal level through a bypassable low noise amplifier in SiGe Bi-CMOS process or transmit through an on-chip bypass channel; S3, using SiGe Bi-CMOS electronically tunable filter chip to achieve pre-frequency selection function before mixing, reducing parasitic spurious caused by nonlinearity of the mixer; S4, using a dual down-conversion integrated circuit that integrates a VCO, a phase-locked loop, a balun, a mixer, a filter, an amplifier, an adjustable amplifier, and a digitally controlled step attenuator to implement RF down-conversion to convert the RF signal into an intermediate frequency signal; S5, converting the intermediate frequency signal into a digital baseband signal using a tunable bandpass Σ-Δ type analog-to-digital converter; S6, Process digital baseband signals through fully programmable system-on-chip FPGA integrated circuits to perform spectrum analysis, vector signal processing, and automatic monitoring of signal characteristics; S7, storing the original spectrum IQ data in the local device for a long time, and uploading the calculated formatted data and monitoring information to the remote server; S8. Realize real-time processing, monitoring and response of data through the "edge-end-cloud" hybrid computing architecture.

2. A method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite as claimed in claim 1, characterized in that: The dual-channel receiver design combines the high performance of heterodyne design with the high integration of RF-CMOS process integrated circuits, and innovates the design route of heterodyne receivers by using SiGe BiCMOS process receiver front-end integrated circuits.

3. A method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite as claimed in claim 1, characterized in that: In step S1, an adaptive algorithm is introduced to dynamically adjust the impedance matching of the digitally controlled step attenuator.

4. A method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite as claimed in claim 1, characterized in that: In the down-conversion process in step S4, a compensation method based on Volterra series is used to reduce the distortion caused by mixer nonlinearity.

5. A method for concurrently monitoring uplink and downlink signals of a communication broadcasting satellite as claimed in claim 1, characterized in that: During the analog-to-digital conversion process in step S5, an error correction technique is used to reduce the quantization error.

6. A method for concurrently monitoring uplink and downlink signals of a communication broadcasting satellite as claimed in claim 1, characterized in that: In step S6, a fast Fourier transform (FFT) algorithm is implemented in the FPGA to perform spectrum analysis, and an advanced vector signal processing algorithm is used; Moreover, neural network algorithms are introduced for signal classification and anomaly detection.

7. A method for concurrently monitoring uplink and downlink signals of a communication broadcasting satellite as claimed in claim 1, characterized in that: In step S7, the original spectrum IQ data is stored in a high-performance SSD memory local to the device, and the high-performance SSD memory adopts an efficient data storage and compression algorithm.

8. A communication broadcast satellite uplink and downlink signal parallel monitoring system, characterized by: A method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite according to any one of claims 1 to 7, comprising: Impedance matching and signal amplitude adjustment module: uses digitally controlled step attenuators to control port impedance matching and provide signal amplitude adjustment capabilities; Signal level boost and transmission module: The signal level is boosted by a bypassable low noise amplifier in SiGe Bi-CMOS process or transmitted via an on-chip bypass channel to flexibly adapt to different input signal levels; Pre-mixing frequency selection module: SiGe Bi-CMOS electrically tunable filter chip is used to realize the pre-mixing frequency selection function before mixing, reducing the parasitic spurious caused by the nonlinearity of the mixer; RF down-conversion module: RF down-conversion is realized by using a dual down-conversion integrated circuit that integrates VCO, phase-locked loop, balun, mixer, filter, amplifier, adjustable amplifier, and digitally controlled step attenuator to convert RF signals into intermediate frequency signals; Analog-to-digital conversion module: uses a tunable bandpass Σ-Δ analog-to-digital converter to convert the intermediate frequency signal into a digital baseband signal; Digital baseband signal processing module: Processes digital baseband signals through a fully programmable system-on-chip FPGA integrated circuit to perform spectrum analysis, vector signal processing, and automatic monitoring of signal characteristics; Data storage and upload module: Stores the original spectrum IQ data in the local high-performance SSD storage of the device for a long time, and uploads the calculated formatted data and monitoring information to the remote server; Hybrid computing architecture module: Realize real-time processing, monitoring and response of data through the "edge-end-cloud" hybrid computing architecture.

9. A processor, characterized in that: The method is configured to execute a method for concurrently monitoring uplink and downlink signals of a communication broadcasting satellite according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, a method for parallel monitoring of uplink and downlink signals of a communication broadcasting satellite as described in any one of claims 1 to 7 is implemented.

Images