Lofic pixel circuit and image sensor
By using a segmented exposure cycle and charge distribution LOFIC pixel circuit design, the problems of dynamic range extension, cost, and area were solved, achieving efficient dynamic range extension and improved image quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2026-03-31
AI Technical Summary
Existing LOFIC pixel structures require larger capacitors when expanding dynamic range, leading to increased pixel area and manufacturing costs, and making miniaturization difficult.
By adopting a segmented exposure cycle design, the LOFIC capacitor is divided into two parts. Through charge distribution and dynamic refresh technology, the charge storage and reset operation are optimized, the number of dynamic refreshes and the capacitance ratio are controlled, and the dynamic range is expanded.
Without increasing capacitor area and complicating processes, it significantly expands dynamic range, reduces manufacturing costs, improves imaging quality, reduces signal loss, and enhances signal stability.
Smart Images
Figure CN119906909B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image sensor circuits, and more particularly to a LOFIC pixel circuit and an image sensor. Background Technology
[0002] Dynamic range is an important indicator for measuring the performance of an image sensor, directly affecting the ability to capture image details and the quality of the image.
[0003] Pixel structures based on lateral overflow integration capacitors (LOFICs) can effectively collect photogenerated charges overflowing from photodiodes (PDs), freeing the pixel's full-well capacity (FWC) from the PD's limitation and effectively expanding the pixel's dynamic range. However, achieving a high dynamic range in LOFIC pixel structures requires a relatively large LOFIC capacitor.
[0004] However, increasing the size of the LOCIC capacitor would occupy a significant amount of pixel area, making pixel miniaturization difficult. Secondly, the three-dimensional capacitor structure within the pixel requires complex multi-step processes, increasing manufacturing costs. Therefore, achieving extended dynamic range without increasing complex processes or pixel area is essential. Summary of the Invention
[0005] This application provides a LOFIC pixel circuit and image sensor that can effectively expand the dynamic range of pixels, thereby improving pixel quality.
[0006] In a first aspect, embodiments of this application provide a pixel structure, the LOFIC pixel circuit including: a photodiode, a transmission transistor, a floating diffusion node, a switching transistor, a first reset transistor, a first power supply, a first overflow charge storage capacitor, a second overflow charge storage capacitor, and a charge sharing transistor;
[0007] In this configuration, the anode of the photodiode is connected to ground; the cathode of the photodiode is connected to the source of the transmission transistor; the drain of the transmission transistor is connected to the floating diffusion node and the source of the switching transistor; the drain of the switching transistor is connected to the upper plate of the first overflow charge storage capacitor; the source of the charge-sharing transistor is connected to the upper plate of the first overflow charge storage capacitor and the source of the first reset transistor; the drain of the charge-sharing transistor is connected to the upper plate of the second overflow charge storage capacitor; the drain of the first reset transistor is connected to the first power supply; and the lower plates of the first and second overflow charge storage capacitors are connected to the first power supply or ground.
[0008] This embodiment proposes a charge-allocation-based LOFIC pixel structure, dividing the traditional LOFIC capacitor into two parts. Through charge allocation and dynamic refresh, the detection limit of saturation signals can be effectively improved. By controlling the number of dynamic refreshes and the capacitance ratio of the two LOFIC parts, different degrees of dynamic range expansion can be achieved; this reduces signal loss due to saturation and improves the image quality of pixels in high-contrast scenes. Furthermore, this pixel circuit does not require additional capacitors, simplifying pixel layout complexity and reducing manufacturing costs.
[0009] In one possible implementation, the LOFIC pixel circuit further includes a first overflow transfer transistor and a second overflow transfer transistor;
[0010] The drain of the switching transistor is connected to the source of the first overflow transfer transistor and the source of the second overflow transfer transistor; the drain of the first overflow transfer transistor is connected to the upper plate of the first overflow charge storage capacitor; and the drain of the second overflow transfer transistor is connected to the upper plate of the second overflow charge storage capacitor.
[0011] In the embodiments of this application, by setting a first overflow transmission transistor and a second overflow transmission transistor, the capacitors storing the two overflow charges are connected in parallel, thereby improving the stability of the overflow signal and enhancing pixel quality.
[0012] In one possible implementation, the LOFIC pixel circuit further includes a direct overflow transistor; wherein the source of the direct overflow transistor is connected to the cathode of the photodiode; and the drain of the direct overflow transistor is the upper plate of a first overflow charge storage capacitor.
[0013] In the embodiments of this application, by setting a direct overflow channel, the saturated photogenerated charge in the photodiode can be directly collected by the first overflow charge storage capacitor and the second overflow charge storage capacitor node, allowing the overflow signal to be processed separately, reducing the loss of saturated photogenerated charge, and obtaining higher signal quality, thereby improving pixel quality.
[0014] In one possible implementation, the LOFIC pixel circuit further includes a second reset transistor; wherein the source of the second reset transistor is connected to the upper plate of the second overflow charge storage capacitor; and the drain of the second reset transistor is connected to a first power supply.
[0015] In the embodiments of this application, the second overflow charge storage capacitor can be reset by additionally setting a reset operation according to actual application needs, thereby adjusting the dynamic refresh mechanism and charge distribution strategy to obtain the corresponding pixel dynamic range, providing developers with greater design freedom.
[0016] In one possible implementation, the dynamic range of the pixel circuit is related to the capacitance ratio, the number of dynamic refreshes, and the effective exposure ratio of the first overflow charge storage capacitor; wherein, the capacitance ratio represents the ratio of the second overflow charge storage capacitor to the sum of the first and second overflow charge storage capacitors; the number of dynamic refreshes represents the number of exposure cycles repeated in the entire exposure cycle; and the effective exposure ratio of the first overflow charge storage capacitor represents the ratio of the total exposure time to the charge collection time of the first overflow charge storage capacitor.
[0017] In the embodiments of this application, the dynamic range can be significantly extended without increasing the metal-insulator-metal capacitance by optimizing the parameter capacitance ratio, the number of dynamic refreshes, and the effective exposure ratio of the first overflow charge storage capacitor.
[0018] In one possible implementation, the dynamic range of the LOFIC pixel circuit is negatively correlated with the value of the second overflow charge storage capacitor. Ideally, the smaller the capacitance value of CS2, the higher the final signal spread ratio.
[0019] In one possible implementation, the dynamic range of a LOFIC pixel circuit is positively correlated with the number of dynamic refreshes. The more refreshes, the more significant the improvement in dynamic range.
[0020] In one possible implementation, the dynamic range of the LOFIC pixel circuit is positively correlated with the effective exposure ratio of the first overflow charge storage capacitor. The higher the effective exposure ratio k value, the greater the improvement in the final dynamic range.
[0021] In one possible implementation, the LOFIC pixel circuit further includes a source follower, a row selection transistor, and a second power supply; wherein the gate of the source follower is connected to a floating diffusion node; the drain of the source follower is connected to the second power supply; the source of the source follower is connected to the drain of the row selection transistor; and the source of the row selection transistor is connected to the column output bus of the LOFIC pixel circuit.
[0022] Secondly, embodiments of this application provide an image sensor, which includes pixel circuitry as described in the first aspect or any possible implementation thereof.
[0023] The technical effects related to the second aspect can be referred to the first aspect or any of the possible technical effects that can be achieved by the first aspect, and will not be repeated here. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of a traditional LOFIC pixel circuit.
[0026] Figure 2 This paper illustrates a schematic diagram of the working process of a LOFIC pixel circuit according to an embodiment of this application.
[0027] Figure 3 This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0028] Figure 4 It shows Figure 3 The timing diagram of the LOFIC pixel circuit shown is shown below.
[0029] Figure 5 This illustration shows a schematic diagram of another LOFIC pixel circuit provided in an embodiment of this application;
[0030] Figure 6 It shows Figure 5 The timing diagram of the LOFIC pixel circuit shown is shown below.
[0031] Figure 7 This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0032] Figure 8 This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0033] Figure 9A This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0034] Figure 9B This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0035] Figure 9C This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0036] Figure 9D This invention provides a schematic diagram of another LOFIC pixel circuit according to an embodiment of the present application.
[0037] Figure 10A simulation diagram of the dynamic range extension of a LOFIC pixel circuit provided in an embodiment of this application is shown. Detailed Implementation
[0038] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.
[0039] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0040] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a direct connection, an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.
[0041] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0042] First, in order to facilitate understanding of the embodiments of this application, the technical problems to be solved by the embodiments of this application are analyzed in detail below.
[0043] Please see Figure 1 , Figure 1 A schematic diagram of a conventional LOFIC pixel circuit is shown.
[0044] like Figure 1 As shown, a traditional LOFIC pixel circuit includes a photodiode (PD), a transfer transistor (TG), a floating diffusion node (FD), a switching transistor (DCG), a reset transistor (RST), an overflow charge storage capacitor (CS), a first power supply (Vddrst), a second power supply (Vddsf), a source follower (SF), a row selection transistor (SEL), and a column output bus (Vpixout). It should be noted that the overflow charge storage capacitor (CS) can also be referred to as a LOFIC capacitor.
[0045] In this configuration, the anode of the photodiode PD is connected to ground; the cathode of the photodiode PD is connected to the source of the transmission transistor TG; the drain of the transmission transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the upper plate of the overflow charge storage capacitor CS; the drain of the reset transistor RST is connected to the first power supply Vddrst; and the lower plate of the overflow charge storage capacitor CS is connected to ground.
[0046] It should be noted that, in Figure 1 In the LOFIC pixel circuit shown, the floating diffusion node FD has an equivalent floating diffusion capacitance Cfd; therefore, in Figure 1 In the circuit topology shown, the drain of the transmission transistor TG is connected to the floating diffusion node FD, which is also represented by the capacitor Cfd of the floating diffusion node FD.
[0047] The gate of the source follower SF is connected to the floating diffusion node FD; the drain of the source follower is connected to the second power supply Vddsf; the source of the source follower SF is connected to the drain of the row selection transistor SEL; the source of the row selection transistor SEL is connected to the column output bus Vpixout of the LOFIC pixel circuit.
[0048] Based on the traditional LOFIC pixel circuit, it is known that the lateral overflow integrated capacitor (LOFIC) pixel structure can effectively collect the photogenerated charge overflowing from the photodiode (PD), so that the full-well capacity (FWC) of the pixel is no longer limited by the PD, effectively expanding the dynamic range of the pixel. However, in the LOFIC pixel structure, the dynamic range (DR) is calculated as follows:
[0049] DR=20*log(Ns+Nfd+Npd) / RN (1)
[0050] Ns=CS*Vadc / q (2)
[0051] Where Ns is the amount of charge in the LOFIC capacitor (capacitor CS); Nfd is the amount of charge in the diffusion node capacitor (capacitor Cfd); Npd is the amount of charge in the photodiode; RN (random noise) is random noise; CS is the LOFIC capacitance value; Vadc is the sampled value of the voltage swing of capacitor CS; and q is the basic charge of a single charge.
[0052] Based on the above calculations of dynamic range, it can be seen that achieving a high dynamic range requires a larger LOFIC capacitor ( Figure 1The capacitor CS is shown in the diagram. In other words, the dynamic range of this design is limited by the capacitance of the LOFIC capacitor, and the capacitor design is constrained by pixel pitch and manufacturing process. However, as pixel size continues to shrink, increasing the capacitance of the LOFIC capacitor becomes increasingly difficult. Traditional methods typically extend the dynamic range by increasing the capacitor area or improving material processing, but these methods are limited by cost and technical complexity.
[0053] Therefore, this application provides an improved LOFIC pixel circuit. This improved LOFIC pixel circuit employs a segmented exposure cycle design, dividing the entire exposure cycle into multiple smaller cycles. See also... Figure 2 , Figure 2 The diagram shows a schematic representation of the working process of the LOFIC pixel circuit in an embodiment of this application.
[0054] In each small cycle: such as Figure 2 As shown, in the first stage, the overflowing charge is transferred from FD to CS1 and CS2, and CS1 and CS2 jointly store the overflowing charge. In the second stage, CS1 and CS2 are separated by a transistor, CS1 is reset, the remaining charge in CS1 is drained and reset, and the charge in CS2 is stored.
[0055] Then, a comprehensive reading of the total charge is performed. At the end of the exposure cycle, the amount of charge stored in CS2 is read. The total charge in CS2 represents the total amount of all overflow charge, including the charge transferred through CS1 and the charge stored in CS2.
[0056] The above scheme utilizes dynamic refresh technology to control the duty cycle of the period during which overflow charge is collected within multiple small cycles, and optimizes charge distribution and reset operations to ensure efficient use of charge storage space and further improve the dynamic range.
[0057] Please see Figure 3 , Figure 3 A schematic diagram of a LOFIC pixel circuit according to an embodiment of this application is shown.
[0058] The LOFIC pixel circuit includes a photodiode PD, a transmission transistor TG, a floating diffusion node FD, a switching transistor DCG, a first reset transistor RST1, a first power supply Vddrst, a first overflow charge storage capacitor CS1, a second overflow charge storage capacitor CS2, and a charge sharing transistor CSG.
[0059] In this configuration, the anode of the photodiode PD is connected to ground; the cathode of the photodiode PD is connected to the source of the transmission transistor TG; the drain of the transmission transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the upper plate of the first overflow charge storage capacitor CS1; the source of the charge sharing transistor CSG is connected to the upper plate of the first overflow charge storage capacitor CS1 and the source of the first reset transistor RST1; the drain of the charge sharing transistor CSG is connected to the upper plate of the second overflow charge storage capacitor CS2; the drain of the first reset transistor RST1 is connected to the first power supply Vddrst; and the lower plates of the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2 are connected to ground.
[0060] It should be noted that, in Figure 3 In the LOFIC pixel circuit shown, the floating diffusion node FD has an equivalent floating diffusion capacitance Cfd; therefore, in Figure 3 In the circuit topology shown, the drain of the transfer transistor TG is connected to the floating diffusion node FD, which means that the drain of the transfer transistor TG is simultaneously connected to the capacitor Cfd of the floating diffusion node FD. Subsequent embodiments will not elaborate further on this.
[0061] In some embodiments, the LOFIC pixel circuit further includes a source follower SF, a row select transistor SEL, a column output bus Vpixout, and a second power supply Vddsf. The gate of the source follower SF is connected to the floating diffusion node FD; the drain of the source follower is connected to the second power supply Vddsf; the source of the source follower SF is connected to the drain of the row select transistor SEL; and the source of the row select transistor SEL is connected to the column output bus Vpixout of the LOFIC pixel circuit.
[0062] It should be noted that in various embodiments of this application, the first power supply Vddrst and the second power supply Vddsf can be the same power supply or different power supplies. This application does not limit this.
[0063] Please see Figure 4 , Figure 4 It shows Figure 3 The diagram shows the timing sequence of the LOFIC pixel circuit.
[0064] Exposure phase: During time period t1, the charge in CS1 is drained and the overflowing charge flows to the power source, and the CSG gate is closed; during time period t2, the charge is collected into CS1 and shared with CS2.
[0065] Reading phase: Before reading at high gain (HR, HS) or medium gain (MS), in time period t3, turn on the first reset transistor RST1 and turn off the charge sharing transistor CSG, and reset CS1 first; in time period t4, turn on the first reset transistor RST1 and the switching transistor DCG, turn off the charge sharing transistor CSG, reset FD and CS1, and then read other gains (MR, LS and LR).
[0066] This pixel circuit divides the LOFIC capacitor into two parts, effectively improving the detection limit of saturation signals through charge distribution and dynamic refresh. By controlling the number of dynamic refreshes and the capacitance ratio of the two LOFIC capacitor parts, different degrees of dynamic range extension can be achieved based on the original capacitor. Simultaneously, this pixel circuit eliminates the need for additional capacitors, simplifying pixel layout complexity and reducing manufacturing costs. Furthermore, this pixel circuit reduces signal loss due to saturation, improving image quality in high-contrast scenes.
[0067] Please see Figure 5 , Figure 5 A schematic diagram of a LOFIC pixel circuit according to an embodiment of this application is shown.
[0068] The LOFIC pixel circuit includes a photodiode PD, a transmission transistor TG, a floating diffusion node FD, a switching transistor DCG, a first reset transistor RST1, a first power supply Vddrst, a first overflow charge storage capacitor CS1, a second overflow charge storage capacitor CS2, a charge sharing transistor CSG, and a direct overflow transistor OF.
[0069] In this configuration, the anode of the photodiode PD is connected to ground; the cathode of the photodiode PD is connected to the source of the transmission transistor TG; the drain of the transmission transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the upper plate of the first overflow charge storage capacitor CS1; the source of the charge sharing transistor CSG is connected to the upper plate of the first overflow charge storage capacitor CS1 and the source of the first reset transistor RST1; the drain of the charge sharing transistor CSG is connected to the upper plate of the second overflow charge storage capacitor CS2; the drain of the first reset transistor RST1 is connected to the first power supply Vddrst; and the lower plates of the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2 are connected to ground.
[0070] The source of the direct overflow transistor OF is connected to the cathode of the photodiode PD; the drain of the direct overflow transistor OF is the upper plate of the first overflow charge storage capacitor CS1.
[0071] In some embodiments, the LOFIC pixel circuit further includes a source follower SF, a row select transistor SEL, a column output bus Vpixout, and a second power supply Vddsf. The gate of the source follower SF is connected to the floating diffusion node FD; the drain of the source follower is connected to the second power supply Vddsf; the source of the source follower SF is connected to the drain of the row select transistor SEL; and the source of the row select transistor SEL is connected to the column output bus Vpixout of the LOFIC pixel circuit.
[0072] Please see Figure 6 , Figure 6 It shows Figure 5 The diagram shows the timing sequence of the LOFIC pixel circuit.
[0073] Exposure Phase: During time period t1', the charge-sharing transistor CSG is turned off, the first reset transistor RST1 is turned on, the charge in the first overflow charge storage capacitor CS1 is drained, and the overflowed charge flows to the power supply. During time period t2', the charge-sharing transistor CSG is turned on, the charge is collected in the first overflow charge storage capacitor CS1 and shared with the second overflow charge storage capacitor CS2. During exposure, the transfer transistor TG remains off, and the direct overflow transistor OF remains at an intermediate level. The charge in the PD overflows through the direct overflow transistor OF into the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2.
[0074] Reading Phase: First, the overflow signal (LS) is read. Then, during time t3', the first reset transistor RST1, the switching transistor DCG, and the charge-sharing transistor CSG are turned on, and FD, the first overflow charge storage capacitor CS1, and the second overflow charge storage capacitor CS2 are reset. Then, the low-gain LR, high-gain HR, HS, and medium-gain MS are read. During time t4', the first reset transistor RST1 and the switching transistor DCG are turned on, the charge-sharing transistor CSG is turned off, FD is reset, and then the medium-gain MR is read.
[0075] This pixel circuit also divides the LOFIC capacitor into two parts, effectively improving the detection limit of the saturation signal through charge distribution and dynamic refresh. By controlling the number of dynamic refreshes and the capacitance ratio of the two LOFIC capacitors, different degrees of dynamic range extension can be achieved based on the original capacitor. At the same time, this pixel circuit does not require additional capacitors, simplifying the complexity of pixel layout and reducing manufacturing costs. In addition, this pixel circuit can reduce signal loss caused by saturation and improve the image quality of pixels in high-contrast scenes. Furthermore, this solution has simpler timing control. By directly overflowing the transistor, the overflow channel can be directly overflowed to ensure that the saturated photogenerated charge in the PD can be directly collected by CS1 and CS2, resulting in low overflow charge loss and higher signal quality.
[0076] Please see Figure 7 , Figure 7 A schematic diagram of a LOFIC pixel circuit according to an embodiment of this application is shown.
[0077] This embodiment is Figure 3 The LOFIC pixel circuit shown or Figure 5 A second reset transistor RST2 is added to the LOFIC pixel circuit shown. The drain of the second reset transistor RST2 is connected to the first power supply Vddrst.
[0078] It should be noted that, Figure 7 The circuit structure of the remaining parts of the LOFIC pixel circuit shown can be found in [reference needed]. Figure 3 The description of the LOFIC pixel circuit in the previous embodiment will not be repeated in this embodiment.
[0079] This LOFIC pixel circuit not only enables dynamic range extension, but also increases the flexibility of pixel timing control through an additional refresh mechanism.
[0080] Please see Figure 8 , Figure 8 A schematic diagram of a LOFIC pixel circuit according to an embodiment of this application is shown.
[0081] The LOFIC pixel circuit includes a photodiode PD, a transfer transistor TG, a floating diffusion node FD, a switching transistor DCG, a first reset transistor RST1, a first power supply Vddrst, a first overflow charge storage capacitor CS1, a second overflow charge storage capacitor CS2, a charge sharing transistor CSG, a first overflow transfer transistor, and a second overflow transfer transistor.
[0082] In this configuration, the anode of the photodiode PD is connected to ground; the cathode of the photodiode PD is connected to the source of the transfer transistor TG; the drain of the transfer transistor TG is connected to the floating diffusion node FD and the source of the switching transistor DCG; the drain of the switching transistor DCG is connected to the source of the first overflow transfer transistor Vg1 and the source of the second overflow transfer transistor Vg2; the drain of the first overflow transfer transistor Vg1 is connected to the upper plate of the first overflow charge storage capacitor CS1; the drain of the second overflow transfer transistor Vg2 is connected to the upper plate of the second overflow charge storage capacitor CS1; the source of the charge-sharing transistor CSG is connected to the upper plate of the first overflow charge storage capacitor CS1 and the source of the first reset transistor RST1; the drain of the charge-sharing transistor CSG is connected to the upper plate of the second overflow charge storage capacitor CS2; the drain of the first reset transistor RST1 is connected to the first power supply Vddrst; and the lower plates of the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2 are connected to ground.
[0083] This LOFIC pixel circuit not only achieves extended dynamic range and reduced manufacturing costs, but also improves pixel quality by setting a first overflow transfer transistor and a second overflow transfer transistor, thus forming a parallel connection between the two split overflow charge storage capacitors.
[0084] Please see Figures 9A-9D , Figures 9A-9D Schematic diagrams of four LOFIC pixel circuits in embodiments of this application are shown.
[0085] The four embodiments corresponding to the 9A-9D are respectively in Figure 3 , Figure 5 , Figure 7 and Figure 8 Based on the LOFIC pixel circuit shown, the lower plates of the first overflow charge storage capacitor CS1 and the second overflow charge storage capacitor CS2 are changed from being grounded to being connected to the first power supply Vddrst.
[0086] It should be noted that, Figures 9A-9D The circuit structure of the remaining parts of the LOFIC pixel circuit shown can be found in [reference needed]. Figure 3 , Figure 5 , Figure 7 and Figure 8 The corresponding description of the LOFIC pixel circuit shown will not be repeated in this embodiment.
[0087] These four LOFIC pixel circuits not only achieve extended dynamic range and reduced manufacturing costs, but also optimize noise and further enhance dynamic range by connecting the lower plate of the overflow storage capacitor to the power supply, thereby changing the voltage difference between the upper and lower plates of the overflow storage capacitor.
[0088] The following analysis examines the expansion of the dynamic range based on the LOFIC pixel circuits provided in the various embodiments of this application.
[0089] If the charge distribution and dynamic refresh rate are set to n, then the entire exposure cycle is divided into n+1 segments.
[0090] Assuming the overflow charge during the first small exposure cycle is Q (accumulated in CS1 and CS2), the charge in CS2 during the first cycle will be:
[0091]
[0092] The same analysis applies to the second cycle, at which point the charge in CS2 will be:
[0093]
[0094] If the total number of small cycles is n+1, and the charge in CS1 is not reset after the nth cycle, then the total charge accumulated in CS1 and CS2 can be expressed as:
[0095]
[0096]
[0097] Among them, fixed It refers to the capacitance ratio.
[0098] Based on the above formula (3), the original total overflow charge during the entire exposure time can be expressed as:
[0099]
[0100] Therefore, the total charge number Qtot can be calculated from the measured charge number Qmeas, using an amplification factor as follows:
[0101]
[0102] Using the exposure ratio k of CS1, the dynamic range extension considering only the increase in full-well charge capacity (FWC) is as follows:
[0103]
[0104] Based on the above formula (4), it can be seen that the capacitance ratio m, the number of dynamic refreshes n, and the exposure ratio k of the first overflow charge storage capacitor CS1 directly affect the dynamic range of the pixel. In other words, the dynamic range extension of the LOFIC pixel circuit is related to the capacitance ratio m, the number of dynamic refreshes n, and the effective exposure ratio k of the first overflow charge storage capacitor CS1. Among them, the dynamic range of the LOFIC pixel circuit is negatively correlated with the capacitance value Cs2 of the second overflow charge storage capacitor CS2; the dynamic range of the LOFIC pixel circuit is positively correlated with the number of dynamic refreshes n; and the dynamic range of the LOFIC pixel circuit is positively correlated with the effective exposure ratio k of the first overflow charge storage capacitor.
[0105] Please see Figure 10 , Figure 10 A simulation diagram of the dynamic range extension of a LOFIC pixel circuit provided in the embodiments of this application is provided.
[0106] In this simulation, k is set to 2; the sum of the capacitance Cs1 of the first overflow charge storage capacitor CS1 and the capacitance Cs2 of the second overflow charge storage capacitor CS2 is 50fF.
[0107] It should be noted that this simulation method is applicable to the pixel circuits mentioned in the embodiments of this application.
[0108] Based on the simulation results, ideally, the smaller the second overflow charge storage capacitor CS2, the higher the final signal spread ratio. Dynamic refresh count n: represents the number of exposure cycles repeated throughout the entire exposure period; the more refreshes, the more significant the improvement in dynamic range. Effective exposure ratio k of the first overflow charge storage capacitor CS1: represents the ratio of total exposure time to the charge collection time of CS1; the higher the value, the greater the improvement in final dynamic range.
[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0110] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A LOFIC pixel circuit, characterized by, The LOFIC pixel circuit comprises a photodiode, a transfer transistor, a floating diffusion node, a switch transistor, a first reset transistor, a first power supply, a first overflow charge storage capacitor, a second overflow charge storage capacitor and a charge sharing transistor; The anode of the photodiode is connected to the ground; the cathode of the photodiode is connected to the source of the transfer transistor; the drain of the transfer transistor is connected to the floating diffusion node and the source of the switch transistor; the drain of the switch transistor is connected to the upper plate of the first overflow charge storage capacitor; the source of the charge sharing transistor is connected to the upper plate of the first overflow charge storage capacitor and the source of the first reset transistor; the drain of the charge sharing transistor is connected to the upper plate of the second overflow charge storage capacitor; the drain of the first reset transistor is connected to the first power supply; the lower plate of the first overflow charge storage capacitor and the lower plate of the second overflow charge storage capacitor are connected to the first power supply. The LOFIC pixel circuit further comprises a first overflow transfer transistor and a second overflow transfer transistor; the drain of the switch transistor is connected to the source of the first overflow transfer transistor and the source of the second overflow transfer transistor; the drain of the first overflow transfer transistor is connected to the upper plate of the first overflow charge storage capacitor; the drain of the second overflow transfer transistor is connected to the upper plate of the second overflow charge storage capacitor. The LOFIC pixel circuit further comprises a direct overflow transistor; 2. The LOFIC pixel circuit of claim 1, wherein: The source of the direct overflow transistor is connected to the cathode of the photodiode; the drain of the direct overflow transistor is connected to the upper plate of the first overflow charge storage capacitor. The LOFIC pixel circuit further comprises a second reset transistor; 3. The LOFIC pixel circuit of claim 2, wherein: The source of the second reset transistor is connected to the upper plate of the second overflow charge storage capacitor; the drain of the second reset transistor is connected to the first power supply. The dynamic range of the pixel circuit is related to a capacitance ratio, a dynamic refresh number and an effective exposure ratio of the first overflow charge storage capacitor; the capacitance ratio represents the ratio of the second overflow charge storage capacitor to the sum of the first overflow charge storage capacitor and the second overflow charge storage capacitor; the dynamic refresh number represents the number of repeated exposure cycles in the entire exposure period; the effective exposure ratio of the first overflow charge storage capacitor represents the ratio of the total exposure time to the time for the first overflow charge storage capacitor to collect charges.
4. The LOFIC pixel circuit of claim 3, wherein: The dynamic range of the LOFIC pixel circuit is negatively related to the value of the second overflow charge storage capacitor.
5. The LOFIC pixel circuit of claim 4, wherein: The dynamic range of the LOFIC pixel circuit is positively related to the dynamic refresh number.
6. The LOFIC pixel circuit of claim 4, wherein: The dynamic range of the LOFIC pixel circuit is positively related to the effective exposure ratio of the first overflow charge storage capacitor.
7. The LOFIC pixel circuit of claim 4, wherein: 8. The LOFIC pixel circuit of claim 1, wherein, The LOFIC pixel circuit further comprises a source follower, a row selection transistor and a second power supply; wherein a gate of the source follower is connected to the floating diffusion node; a drain of the source follower is connected to the second power supply; a source of the source follower is connected to a drain of the row selection transistor; a source of the row selection transistor is connected to a column output bus of the LOFIC pixel circuit.
9. An image sensor, characterized by: The image sensor comprises the LOFIC pixel circuit according to any one of claims 1 to 8.